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author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-05-21 00:09:15 +0000 |
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committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-05-21 00:09:15 +0000 |
commit | 120cdf19c2827a0d4a0dffadcd4d75d671dab739 (patch) | |
tree | c3a4d797b0ae52fc0032629e33abbebb629a3d71 /nuttx/configs/pcblogic-pic32mx/include/board.h | |
parent | d9609492ca56a3138645f1fe5fc1b8de7e9a7d5e (diff) | |
download | px4-nuttx-120cdf19c2827a0d4a0dffadcd4d75d671dab739.tar.gz px4-nuttx-120cdf19c2827a0d4a0dffadcd4d75d671dab739.tar.bz2 px4-nuttx-120cdf19c2827a0d4a0dffadcd4d75d671dab739.zip |
PIC32 Device Configuration Words
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3635 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/configs/pcblogic-pic32mx/include/board.h')
-rwxr-xr-x | nuttx/configs/pcblogic-pic32mx/include/board.h | 34 |
1 files changed, 32 insertions, 2 deletions
diff --git a/nuttx/configs/pcblogic-pic32mx/include/board.h b/nuttx/configs/pcblogic-pic32mx/include/board.h index 00fa2f585..b70bbb80e 100755 --- a/nuttx/configs/pcblogic-pic32mx/include/board.h +++ b/nuttx/configs/pcblogic-pic32mx/include/board.h @@ -49,9 +49,39 @@ /* Configuration ************************************************************/
/* Clocking *****************************************************************/
+/* Crystal frequencies */
-#define BOARD_CPU_CLOCK 80000000
-#define BOARD_PERIPHERAL_CLOCK 40000000
+#define BOARD_POSC_XTAL 8000000 /* Primary OSC XTAL frequency (8MHz) */
+#define BOARD_SOSC_XTAL 32768 /* Secondary OSC XTAL frequency (32.768KHz) */
+
+/* PLL configuration and resulting CPU clock.
+ * CPU_CLOCK = ((POSC_XTAL / IDIV) * MULT) / ODIV
+ */
+
+#define BOARD_PLL_IDIV 2 /* PLL input divider */
+#define BOARD_PLL_MULT 20 /* PLL multiplier */
+#define BOARD_PLL_ODIV 1 /* PLL output divider */
+
+#define BOARD_CPU_CLOCK 80000000 /* CPU clock (80MHz = 8MHz * 20 / 2) */
+
+/* USB PLL configuration.
+ * USB_CLOCK = ((POSC_XTAL / IDIV) * 24) / 2
+ */
+
+#define BOARD_UPLL_IDIV 16 /*2*/ /* USB PLL divider (revisit) */
+#define BOARD_USB_CLOCK 48000000 /* USB clock (8MHz / (2*48MHz/24)) */
+
+/* Peripheral clock is divided down from CPU clock.
+ * PBCLOCK = CPU_CLOCK / PBDIV
+ */
+
+#define BOARD_PBDIV 2 /* Peripheral clock divisor (PBDIV) */
+#define BOARD_PBCLOCK 40000000 /* Peripheral clock (PBCLK = 80MHz/2) */
+
+/* Watchdog pre-scaler (re-visit) */
+
+#define BOARD_WD_ENABLE 0 /* Watchdog is disabled */
+#define BOARD_WD_PRESCALER 8 /* Watchdog pre-scaler */
/* LED definitions **********************************************************/
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