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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-09-22 22:25:21 +0000 |
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| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-09-22 22:25:21 +0000 |
| commit | 5987a3825e81c2338497df61081d294ac4d16ae1 (patch) | |
| tree | a9f257e39b14b18f9f10f76216689736aa81078a /nuttx/configs/shenzhou | |
| parent | cabf873bfd10289dd5a1fd82fd431ec12ed908a8 (diff) | |
| download | px4-nuttx-5987a3825e81c2338497df61081d294ac4d16ae1.tar.gz px4-nuttx-5987a3825e81c2338497df61081d294ac4d16ae1.tar.bz2 px4-nuttx-5987a3825e81c2338497df61081d294ac4d16ae1.zip | |
Add missing STM32 F1 pin remapping definitions
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5180 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/configs/shenzhou')
| -rw-r--r-- | nuttx/configs/shenzhou/src/shenzhou-internal.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/nuttx/configs/shenzhou/src/shenzhou-internal.h b/nuttx/configs/shenzhou/src/shenzhou-internal.h index 48b06e7b0..b5fb4e35c 100644 --- a/nuttx/configs/shenzhou/src/shenzhou-internal.h +++ b/nuttx/configs/shenzhou/src/shenzhou-internal.h @@ -65,6 +65,34 @@ /* Shenzhou GPIO Configuration **********************************************************************/ /* STM3240G-EVAL GPIOs ******************************************************************************/ +/* Ethernet + * + * -- ---- -------------- ---------------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- ---------------------------------------------------------- + * 24 PA1 MII_RX_CLK Ethernet PHY NOTE: Despite the MII labeling of these + * RMII_REF_CLK Ethernet PHY signals, the DM916AEP is actually configured + * 25 PA2 MII_MDIO Ethernet PHY to work in RMII mode. + * 48 PB11 MII_TX_EN Ethernet PHY + * 51 PB12 MII_TXD0 Ethernet PHY + * 52 PB13 MII_TXD1 Ethernet PHY + * 16 PC1 MII_MDC Ethernet PHY + * 34 PC5 MII_INT Ethernet PHY + * 55 PD8 MII_RX_DV Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP + * 55 PD8 RMII_CRSDV Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP + * 56 PD9 MII_RXD0 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP + * 57 PD10 MII_RXD1 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP + * + * The board desdign can support a 50MHz external clock to drive the PHY + * (U9). However, on my board, U9 is not present. + * + * 67 PA8 MCO DM9161AEP + */ + +#ifdef CONFIG_STM32_ETHMAC +# define GPIO_MII_INT (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_EXTI|GPIO_PORTC|GPIO_PIN5) +#endif + /* Wireless * * -- ---- -------------- ------------------------------------------------------------------- |