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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-09-22 19:19:56 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-09-22 19:19:56 +0000 |
| commit | 8f88f77957feaf87be4b7571a420a13682a357b9 (patch) | |
| tree | e81f0bfd6ab73966a0908fe374c3eddb2505ff13 /nuttx/configs/shenzhou | |
| parent | d49fa0f03c72b2fcc29f22ad037bc5c5a8a8d7c9 (diff) | |
| download | px4-nuttx-8f88f77957feaf87be4b7571a420a13682a357b9.tar.gz px4-nuttx-8f88f77957feaf87be4b7571a420a13682a357b9.tar.bz2 px4-nuttx-8f88f77957feaf87be4b7571a420a13682a357b9.zip | |
STM32 Ethernet, Slightly differ register layout for DM9161AEP PHY
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5177 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/configs/shenzhou')
| -rw-r--r-- | nuttx/configs/shenzhou/include/board.h | 13 | ||||
| -rw-r--r-- | nuttx/configs/shenzhou/nsh/defconfig | 14 |
2 files changed, 16 insertions, 11 deletions
diff --git a/nuttx/configs/shenzhou/include/board.h b/nuttx/configs/shenzhou/include/board.h index df4386cf1..d396e2563 100644 --- a/nuttx/configs/shenzhou/include/board.h +++ b/nuttx/configs/shenzhou/include/board.h @@ -50,8 +50,6 @@ * Pre-processor Definitions ************************************************************************************/ -#define BOARD_CFGR_MCO_SOURCE RCC_CFGR_PLL3CLK - /* Clocking *************************************************************************/ /* On-board crystal frequency is 25MHz (HSE) */ @@ -97,10 +95,14 @@ #define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) -/* MCO output */ +/* MCO output driven by PLL3. From above, we already have PLL3 input frequency as: + * + * STM32_PLL_PREDIV2 = 5, 25MHz / 5 => 5MHz + */ #if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO) -# define STM32_PLL_PLL3MUL RCC_CFGR2_PLL3MULx10 +# define BOARD_CFGR_MCO_SOURCE RCC_CFGR_PLL3CLK /* Source: PLL3 */ +# define STM32_PLL_PLL3MUL RCC_CFGR2_PLL3MULx10 /* MCO 5MHz * 10 = 50MHz */ #endif /* LED definitions ******************************************************************/ @@ -179,6 +181,9 @@ * 56 PD9 MII_RXD0 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP * 57 PD10 MII_RXD1 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP * + * The board desdign can support a 50MHz external clock to drive the PHY + * (U9). However, on my board, U9 is not present. + * * 67 PA8 MCO DM9161AEP */ diff --git a/nuttx/configs/shenzhou/nsh/defconfig b/nuttx/configs/shenzhou/nsh/defconfig index 053717470..c4817c2ee 100644 --- a/nuttx/configs/shenzhou/nsh/defconfig +++ b/nuttx/configs/shenzhou/nsh/defconfig @@ -174,14 +174,14 @@ CONFIG_STM32_JTAG_FULL_ENABLE=y # CONFIG_STM32_PHYADDR=1 # CONFIG_STM32_MII is not set -# CONFIG_STM32_MII_MCO is not set -# CONFIG_STM32_MII_EXTCLK is not set CONFIG_STM32_AUTONEG=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR=17 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0xf000 +CONFIG_STM32_PHYSR_10HD=0x1000 +CONFIG_STM32_PHYSR_100HD=0x4000 +CONFIG_STM32_PHYSR_10FD=0x2000 +CONFIG_STM32_PHYSR_100FD=0x8000 # CONFIG_STM32_ETH_PTP is not set CONFIG_STM32_RMII=y CONFIG_STM32_RMII_MCO=y |