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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-07-14 19:30:31 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-07-14 19:30:31 +0000 |
| commit | e135573acc348649e767ca67a1ec189fe4e0fcda (patch) | |
| tree | b34f7d2914cba8aeb9311c5bae3771af40054640 /nuttx/configs/stm3220g-eval/include | |
| parent | d76fa866ad009d65396acf1aa08fcffd3b4b041e (diff) | |
| download | px4-nuttx-e135573acc348649e767ca67a1ec189fe4e0fcda.tar.gz px4-nuttx-e135573acc348649e767ca67a1ec189fe4e0fcda.tar.bz2 px4-nuttx-e135573acc348649e767ca67a1ec189fe4e0fcda.zip | |
Fix STM32 F2/F4 SDIO clocking; Clean-up files in sched/ directory
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4940 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/configs/stm3220g-eval/include')
| -rw-r--r-- | nuttx/configs/stm3220g-eval/include/board.h | 28 |
1 files changed, 15 insertions, 13 deletions
diff --git a/nuttx/configs/stm3220g-eval/include/board.h b/nuttx/configs/stm3220g-eval/include/board.h index bd0a059f7..be9bb886d 100644 --- a/nuttx/configs/stm3220g-eval/include/board.h +++ b/nuttx/configs/stm3220g-eval/include/board.h @@ -34,17 +34,19 @@ * ************************************************************************************/ -#ifndef __ARCH_BOARD_BOARD_H -#define __ARCH_BOARD_BOARD_H +#ifndef __CONFIGS_STM3220G_EVAL_INCLUDE_BOARD_H +#define __CONFIGS_STM3220G_EVAL_INCLUDE_BOARD_H /************************************************************************************ * Included Files ************************************************************************************/ #include <nuttx/config.h> + #ifndef __ASSEMBLY__ # include <stdint.h> #endif + #include "stm32_rcc.h" #include "stm32_sdio.h" #include "stm32_internal.h" @@ -168,29 +170,29 @@ * to service FIFOs in interrupt driven mode. These values have not been * tuned!!! * - * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz */ -#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) +#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz */ #ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) #else -# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) #endif -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(0+2)= 24 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)= 12 MHz */ #ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +# define SDIO_SDXFR_CLKDIV (0 << SDIO_CLKCR_CLKDIV_SHIFT) #else -# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) #endif /* Ethernet *************************************************************************/ @@ -531,4 +533,4 @@ EXTERN void stm3220g_lcdclear(uint16_t color); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_BOARD_BOARD_H */ +#endif /* __CONFIGS_STM3220G_EVAL_INCLUDE_BOARD_H */ |