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author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-12-30 21:12:43 +0000 |
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committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-12-30 21:12:43 +0000 |
commit | fe79bf67bbe7f0c225b3108a1aede600a0df6eaa (patch) | |
tree | 36ce5449d2dea6b534545706953874ea9e8d589b /nuttx/configs/zp214xpa | |
parent | a5a88db827fbaca1058ce3fd6b4784bd9ab03073 (diff) | |
download | px4-nuttx-fe79bf67bbe7f0c225b3108a1aede600a0df6eaa.tar.gz px4-nuttx-fe79bf67bbe7f0c225b3108a1aede600a0df6eaa.tar.bz2 px4-nuttx-fe79bf67bbe7f0c225b3108a1aede600a0df6eaa.zip |
Fix the nxlines configuration for the zp214xpa board
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5467 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/configs/zp214xpa')
-rw-r--r-- | nuttx/configs/zp214xpa/README.txt | 2 | ||||
-rw-r--r-- | nuttx/configs/zp214xpa/src/up_spi1.c | 44 | ||||
-rw-r--r-- | nuttx/configs/zp214xpa/src/up_ug2864ambag01.c | 29 |
3 files changed, 51 insertions, 24 deletions
diff --git a/nuttx/configs/zp214xpa/README.txt b/nuttx/configs/zp214xpa/README.txt index 9f577b98d..58a2242d0 100644 --- a/nuttx/configs/zp214xpa/README.txt +++ b/nuttx/configs/zp214xpa/README.txt @@ -338,3 +338,5 @@ Configurations: CONFIG_HOST_LINUX=y : Linux (Cygwin under Windows okay too). CONFIG_ARM_TOOLCHAIN_GNU_EABI=y : Buildroot (arm-nuttx-elf-gcc) CONFIG_RAW_BINARY=y : Output formats: ELF and raw binary + + 3. Verified as of this writing (2012-12-30). diff --git a/nuttx/configs/zp214xpa/src/up_spi1.c b/nuttx/configs/zp214xpa/src/up_spi1.c index 563d63589..1ee1cac32 100644 --- a/nuttx/configs/zp214xpa/src/up_spi1.c +++ b/nuttx/configs/zp214xpa/src/up_spi1.c @@ -86,20 +86,16 @@ * Definitions ****************************************************************************/ -/* Enables debug output from this file (needs CONFIG_DEBUG too) */ +/* Enables debug output from this file */ -#undef SPI_DEBUG /* Define to enable debug */ -#undef SPI_VERBOSE /* Define to enable verbose debug */ - -#ifdef SPI_DEBUG +#ifdef CONFIG_DEBUG_SPI # define spidbg lldbg -# ifdef SPI_VERBOSE +# ifdef CONFIG_DEBUG_VERBOSE # define spivdbg lldbg # else # define spivdbg(x...) # endif #else -# undef SPI_VERBOSE # define spidbg(x...) # define spivdbg(x...) #endif @@ -112,10 +108,12 @@ /* Use either FIO or legacy GPIO */ #ifdef CONFIG_LPC214x_FIO +# define CS_PIN_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_PIN_OFFSET) # define CS_SET_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_SET_OFFSET) # define CS_CLR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_CLR_OFFSET) # define CS_DIR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_DIR_OFFSET) #else +# define CS_PIN_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_PIN_OFFSET) # define CS_SET_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_SET_OFFSET) # define CS_CLR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_CLR_OFFSET) # define CS_DIR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_DIR_OFFSET) @@ -130,7 +128,7 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock); #endif static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency); -static uint8_t spi_status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +static uint8_t spi_status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); #ifdef CONFIG_SPI_CMDDATA static int spi_cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); #endif @@ -193,7 +191,7 @@ static struct spi_dev_s g_spidev = { &g_spiops }; #ifndef CONFIG_SPI_OWNBUS static int spi_lock(FAR struct spi_dev_s *dev, bool lock) { - /* Not implemented */ + /* Not implemented -- the UG_2864AMBAG01 is the only device on SPI1 */ return -ENOSYS; } @@ -219,25 +217,32 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock) static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { +#ifdef CONFIG_DEBUG_SPI + uint32_t regval; +#endif uint32_t bit = 1 << 20; /* We do not bother to check if devid == SPIDEV_DISPLAY because that is the * only thing on the bus. */ +#ifdef CONFIG_DEBUG_SPI + regval = getreg32(CS_PIN_REGISTER); +#endif + if (selected) { /* Enable slave select (low enables) */ - spidbg("CD asserted\n"); putreg32(bit, CS_CLR_REGISTER); + spidbg("CS asserted: %08x->%08x\n", regval, getreg32(CS_PIN_REGISTER)); } else { /* Disable slave select (low enables) */ - spidbg("CD de-asserted\n"); putreg32(bit, CS_SET_REGISTER); + spidbg("CS de-asserted: %08x->%08x\n", regval, getreg32(CS_PIN_REGISTER)); /* Wait for the TX FIFO not full indication */ @@ -345,6 +350,9 @@ static uint8_t spi_status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) #ifdef CONFIG_SPI_CMDDATA static int spi_cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd) { +#ifdef CONFIG_DEBUG_SPI + uint32_t regval; +#endif uint32_t bit = 1 << 23; /* We do not bother to check if devid == SPIDEV_DISPLAY because that is the @@ -358,19 +366,23 @@ static int spi_cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd * A0 = L: the inputs at D0 to D7 are transferred to the command registers." */ +#ifdef CONFIG_DEBUG_SPI + regval = getreg32(CS_PIN_REGISTER); +#endif + if (cmd) { /* L: the inputs at D0 to D7 are transferred to the command registers */ - spidbg("Command\n"); putreg32(bit, CS_CLR_REGISTER); + spidbg("Command: %08x->%08x\n", regval, getreg32(CS_PIN_REGISTER)); } else { /* H: the inputs at D0 to D7 are treated as display data. */ - spidbg("CD de-asserted\n"); putreg32(bit, CS_SET_REGISTER); + spidbg("Data: %08x->%08x\n", regval, getreg32(CS_PIN_REGISTER)); } return OK; @@ -606,11 +618,15 @@ FAR struct spi_dev_s *up_spiinitialize(int port) * for commands (also low) */ - regval32 = (1 << 20) || (1 << 23); + regval32 = (1 << 20) | (1 << 23); putreg32(regval32, CS_SET_REGISTER); regval32 |= getreg32(CS_DIR_REGISTER); putreg32(regval32, CS_DIR_REGISTER); + spidbg("CS Pin Config: PINSEL1: %08x PIN: %08x DIR: %08x\n", + getreg32(LPC214X_PINSEL1), getreg32(CS_PIN_REGISTER), + getreg32(CS_DIR_REGISTER)); + /* Enable peripheral clocking to SPI1 */ regval32 = getreg32(LPC214X_PCON_PCONP); diff --git a/nuttx/configs/zp214xpa/src/up_ug2864ambag01.c b/nuttx/configs/zp214xpa/src/up_ug2864ambag01.c index 164518db3..236f9fa41 100644 --- a/nuttx/configs/zp214xpa/src/up_ug2864ambag01.c +++ b/nuttx/configs/zp214xpa/src/up_ug2864ambag01.c @@ -85,13 +85,15 @@ /* Use either FIO or legacy GPIO */ #ifdef CONFIG_LPC214x_FIO -# define CS_SET_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_SET_OFFSET) -# define CS_CLR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_CLR_OFFSET) -# define CS_DIR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_DIR_OFFSET) +# define RESET_PIN_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_PIN_OFFSET) +# define RESET_SET_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_SET_OFFSET) +# define RESET_CLR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_CLR_OFFSET) +# define RESET_DIR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_DIR_OFFSET) #else -# define CS_SET_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_SET_OFFSET) -# define CS_CLR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_CLR_OFFSET) -# define CS_DIR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_DIR_OFFSET) +# define RESET_PIN_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_PIN_OFFSET) +# define RESET_SET_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_SET_OFFSET) +# define RESET_CLR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_CLR_OFFSET) +# define RESET_DIR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_DIR_OFFSET) #endif /* Debug ********************************************************************/ @@ -136,14 +138,21 @@ FAR struct lcd_dev_s *up_nxdrvinit(unsigned int devno) /* Set the RESET line low, putting the OLED into the reset state. */ bits32 = (1 << 18); - putreg32(bits32, CS_CLR_REGISTER); - regval32 = getreg32(CS_DIR_REGISTER); - putreg32(regval32 | bits32, CS_DIR_REGISTER); + putreg32(bits32, RESET_CLR_REGISTER); + regval32 = getreg32(RESET_DIR_REGISTER); + putreg32(regval32 | bits32, RESET_DIR_REGISTER); + + lcdvdbg("RESET Pin Config: PINSEL1: %08x PIN: %08x DIR: %08x\n", + getreg32(LPC214X_PINSEL1), getreg32(RESET_PIN_REGISTER), + getreg32(RESET_DIR_REGISTER)); /* Wait a bit then release the OLED from the reset state */ up_mdelay(20); - putreg32(bits32, CS_SET_REGISTER); + putreg32(bits32, RESET_SET_REGISTER); + + lcdvdbg("RESET release: PIN: %08x DIR: %08x\n", + getreg32(RESET_PIN_REGISTER), getreg32(RESET_DIR_REGISTER)); /* Get the SPI1 port interface */ |