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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-12-22 00:31:47 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-12-22 00:31:47 +0000 |
| commit | 0ef224f0edcdc24a123dd2f229256dac3a38c277 (patch) | |
| tree | d0dc01b41249de6a68c5631669aa60b514cee23f /nuttx/configs | |
| parent | 80f67779e93a19f4ead282f5fff0bd070ba93de8 (diff) | |
| download | px4-nuttx-0ef224f0edcdc24a123dd2f229256dac3a38c277.tar.gz px4-nuttx-0ef224f0edcdc24a123dd2f229256dac3a38c277.tar.bz2 px4-nuttx-0ef224f0edcdc24a123dd2f229256dac3a38c277.zip | |
STM32 ADC driver update
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4211 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/configs')
| -rwxr-xr-x | nuttx/configs/hymini-stm32v/include/board.h | 4 | ||||
| -rwxr-xr-x | nuttx/configs/stm3210e-eval/include/board.h | 4 | ||||
| -rw-r--r-- | nuttx/configs/stm3210e-eval/src/up_adc.c | 10 | ||||
| -rwxr-xr-x | nuttx/configs/stm3240g-eval/include/board.h | 2 | ||||
| -rw-r--r-- | nuttx/configs/vsn/include/board.h | 4 |
5 files changed, 11 insertions, 13 deletions
diff --git a/nuttx/configs/hymini-stm32v/include/board.h b/nuttx/configs/hymini-stm32v/include/board.h index 719ad1c74..333f83b89 100755 --- a/nuttx/configs/hymini-stm32v/include/board.h +++ b/nuttx/configs/hymini-stm32v/include/board.h @@ -90,8 +90,8 @@ /* APB2 timers 1 and 8 will receive PCLK2. */ -#define STM32_APB1_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ diff --git a/nuttx/configs/stm3210e-eval/include/board.h b/nuttx/configs/stm3210e-eval/include/board.h index 653ec8999..8e2e88612 100755 --- a/nuttx/configs/stm3210e-eval/include/board.h +++ b/nuttx/configs/stm3210e-eval/include/board.h @@ -86,8 +86,8 @@ /* APB2 timers 1 and 8 will receive PCLK2. */ -#define STM32_APB1_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ diff --git a/nuttx/configs/stm3210e-eval/src/up_adc.c b/nuttx/configs/stm3210e-eval/src/up_adc.c index 8f2cfbd38..f84a88d58 100644 --- a/nuttx/configs/stm3210e-eval/src/up_adc.c +++ b/nuttx/configs/stm3210e-eval/src/up_adc.c @@ -82,13 +82,13 @@ * Private Data ************************************************************************************/ -/* Identifying number of each ADC channel: Variable Resistor , BNC_CN5 and BNC_CN3 */ +/* Identifying number of each ADC channel: Variable Resistor and BNC_CN5 */ -static const uint8_t g_chanlist[ADC_NCHANNELS] = {14, 10}; +static const uint8_t g_chanlist[ADC_NCHANNELS] = {14, 11}; /* Configurations of pins used byte each ADC channels */ -static const uint32_t g_pinlist[ADC_NCHANNELS] = {GPIO_ADC1_IN14 , GPIO_ADC1_IN10}; +static const uint32_t g_pinlist[ADC_NCHANNELS] = {GPIO_ADC1_IN14 , GPIO_ADC1_IN11}; /************************************************************************************ * Private Functions @@ -114,13 +114,11 @@ int adc_devinit(void) int ret; int i; - avdbg("Entry\n"); - /* Configure the pins as analog inputs for the selected channels */ for(i = 0; i < ADC_NCHANNELS; i++) { - stm32_configgpio(g_chanlist[i]); + stm32_configgpio(g_pinlist[i]); } /* Call stm32_adcinitialize() to get an instance of the ADC interface */ diff --git a/nuttx/configs/stm3240g-eval/include/board.h b/nuttx/configs/stm3240g-eval/include/board.h index caf93e54f..6c3b32497 100755 --- a/nuttx/configs/stm3240g-eval/include/board.h +++ b/nuttx/configs/stm3240g-eval/include/board.h @@ -146,7 +146,7 @@ #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) -/* Timers driven from APB12will be twice PCLK2 */ +/* Timers driven from APB2 will be twice PCLK2 */ #define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) #define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK1_FREQUENCY) diff --git a/nuttx/configs/vsn/include/board.h b/nuttx/configs/vsn/include/board.h index b47df4d6e..9fa58de00 100644 --- a/nuttx/configs/vsn/include/board.h +++ b/nuttx/configs/vsn/include/board.h @@ -99,8 +99,8 @@ /* APB2 timers 1 and 8 will receive PCLK2. */ -#define STM32_APB1_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 clock (PCLK1) is HCLK (36MHz) */ |