Finishes the PWM driver for the STM32

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4206 42af7a65-404d-4744-a932-0658087f49c3

6 files changed, 89 insertions, 4 deletions

diff --git a/nuttx/configs/README.txt b/nuttx/configs/README.txt
index aa9d00cf3..a85348bab 100644
--- a/nuttx/configs/README.txt
+++ b/nuttx/configs/README.txt
@@ -1237,7 +1237,8 @@ configs/ez80f0910200zco
 	tools.  The development environment is Cygwin under WinXP.
 
 configs/hymini-stm32v
-	A configuration for the HY-Mini STM32v board.
+	A configuration for the HY-Mini STM32v board.  This board is based on the
+	STM32F103VCT chip.
 
 configs/kwikstik-k40.
     Kinetis K40 Cortex-M4 MCU.  This port uses the FreeScale KwikStik-K40
@@ -1249,7 +1250,7 @@ configs/lm3s6965-ek
 	arm-elf toolchain*.  STATUS:  This port is complete and mature.
 
 configs/lm3s8962-ek
-	Stellaris LMS38962 Evaluation Kit
+	Stellaris LMS38962 Evaluation Kit.
 
 configs/lpcxpresso-lpc1768
 	Embedded Artists base board with NXP LPCExpresso LPC1768.  This board
@@ -1380,6 +1381,11 @@ configs/stm3210e-evel
 	microcontroller (ARM Cortex-M3).  This port uses the GNU Cortex-M3
 	toolchain.
 
+configs/stm32140g-eval
+	STMicro STM3210G-EVAL development board based on the STMicro STM32F103ZET6
+	microcontroller (ARM Cortex-M4 with FPU).  This port uses a GNU Cortex-M4
+	toolchain (such as CodeSourcery).
+
 configs/sure-pic32mx
 	The "Advanced USB Storage Demo Board," Model DB-DP11215, from Sure
 	Electronics (http://www.sureelectronics.net/).  This board features
diff --git a/nuttx/configs/hymini-stm32v/include/board.h b/nuttx/configs/hymini-stm32v/include/board.h
index fbecc0b6c..719ad1c74 100755
--- a/nuttx/configs/hymini-stm32v/include/board.h
+++ b/nuttx/configs/hymini-stm32v/include/board.h
@@ -88,11 +88,25 @@
 #define STM32_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLK
 #define STM32_PCLK2_FREQUENCY   STM32_HCLK_FREQUENCY
 
+/* APB2 timers 1 and 8 will receive PCLK2. */
+
+#define STM32_APB1_TIM1_CLKIN   (STM32_PCLK2_FREQUENCY)
+#define STM32_APB1_TIM8_CLKIN   (STM32_PCLK2_FREQUENCY)
+
 /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */
 
 #define STM32_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLKd2
 #define STM32_PCLK1_FREQUENCY   (STM32_HCLK_FREQUENCY/2)
 
+/* APB1 timers 2-4 will be twice PCLK1 (I presume the remaining will receive PCLK1) */
+
+#define STM32_APB1_TIM2_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM3_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM4_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM5_CLKIN   (STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM6_CLKIN   (STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM7_CLKIN   (STM32_PCLK1_FREQUENCY)
+
 /* USB divider -- Divide PLL clock by 1.5 */
 
 #define STM32_CFGR_USBPRE       0
diff --git a/nuttx/configs/stm3210e-eval/include/board.h b/nuttx/configs/stm3210e-eval/include/board.h
index 02db848fe..653ec8999 100755
--- a/nuttx/configs/stm3210e-eval/include/board.h
+++ b/nuttx/configs/stm3210e-eval/include/board.h
@@ -82,12 +82,27 @@
 
 #define STM32_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLK
 #define STM32_PCLK2_FREQUENCY   STM32_HCLK_FREQUENCY
+#define STM32_APB2_CLKIN        (STM32_PCLK2_FREQUENCY)   /* Timers 2-7, 12-14 */
+
+/* APB2 timers 1 and 8 will receive PCLK2. */
+
+#define STM32_APB1_TIM1_CLKIN   (STM32_PCLK2_FREQUENCY)
+#define STM32_APB1_TIM8_CLKIN   (STM32_PCLK2_FREQUENCY)
 
 /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */
 
 #define STM32_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLKd2
 #define STM32_PCLK1_FREQUENCY   (STM32_HCLK_FREQUENCY/2)
 
+/* APB1 timers 2-4 will be twice PCLK1 (I presume the remaining will receive PCLK1) */
+
+#define STM32_APB1_TIM2_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM3_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM4_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM5_CLKIN   (STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM6_CLKIN   (STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM7_CLKIN   (STM32_PCLK1_FREQUENCY)
+
 /* USB divider -- Divide PLL clock by 1.5 */
 
 #define STM32_CFGR_USBPRE       0
diff --git a/nuttx/configs/stm3240g-eval/README.txt b/nuttx/configs/stm3240g-eval/README.txt
index ac3ebb103..746d0e5ec 100755
--- a/nuttx/configs/stm3240g-eval/README.txt
+++ b/nuttx/configs/stm3240g-eval/README.txt
@@ -14,6 +14,7 @@ Contents
   - STM3240G-EVAL-specific Configuration Options
   - LEDs
   - Ethernet
+  - PWM
   - Configurations
 
 Development Environment
@@ -203,6 +204,21 @@ events as follows:
     on a small proportion of the time.
 *** LED2 may also flicker normally if signals are processed.
 
+PWM
+===
+
+The STM3240G-Eval has no real on-board PWM devices, but the board can be configured to output
+a pulse train using TIM4 CH2.  This pin is used by FSMC is connect to CN5 just for this
+purpose:
+
+  PD13 FSMC_A18 / MC_TIM4_CH2 pin 33 (EnB)
+
+FSMC must be disabled in this case!  PD13 is available at:
+
+  Daughterboard Extension Connector, CN3, pin 32 - available
+  TFT LCD Connector, CN19, pin 17 -- not available without removing the LCD.
+  Motor Control Connector CN15, pin 33 -- no available unless to connect SB14.
+
 STM3240G-EVAL-specific Configuration Options
 ============================================
 
diff --git a/nuttx/configs/stm3240g-eval/include/board.h b/nuttx/configs/stm3240g-eval/include/board.h
index 4002f918a..046691dd9 100755
--- a/nuttx/configs/stm3240g-eval/include/board.h
+++ b/nuttx/configs/stm3240g-eval/include/board.h
@@ -126,14 +126,34 @@
 
 /* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
 
-#define STM32_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
+#define STM32_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLKd4     /* PCLK1 = HCLK / 4 */
 #define STM32_PCLK1_FREQUENCY   (STM32_HCLK_FREQUENCY/4)
 
+/* Timers driven from APB1 will be twice PCLK1 */
+
+#define STM32_APB1_TIM2_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM3_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM4_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM5_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM6_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM7_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM12_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM13_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM14_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+
 /* APB2 clock (PCLK2) is HCLK/2 (84MHz) */
 
-#define STM32_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
+#define STM32_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLKd2     /* PCLK2 = HCLK / 2 */
 #define STM32_PCLK2_FREQUENCY   (STM32_HCLK_FREQUENCY/2)
 
+/* Timers driven from APB12will be twice PCLK2 */
+
+#define STM32_APB2_TIM1_CLKIN   (2*STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM8_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB2_TIM9_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB2_TIM10_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB2_TIM11_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+
 /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
  * otherwise frequency is 2xAPBx. 
  * Note: TIM1,8 are on APB2, others on APB1
diff --git a/nuttx/configs/vsn/include/board.h b/nuttx/configs/vsn/include/board.h
index 9f7ec0756..b47df4d6e 100644
--- a/nuttx/configs/vsn/include/board.h
+++ b/nuttx/configs/vsn/include/board.h
@@ -97,11 +97,25 @@
 #define STM32_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLK
 #define STM32_PCLK2_FREQUENCY   STM32_BOARD_HCLK
 
+/* APB2 timers 1 and 8 will receive PCLK2. */
+
+#define STM32_APB1_TIM1_CLKIN   (STM32_PCLK2_FREQUENCY)
+#define STM32_APB1_TIM8_CLKIN   (STM32_PCLK2_FREQUENCY)
+
 /* APB1 clock (PCLK1) is HCLK (36MHz) */
 
 #define STM32_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLK
 #define STM32_PCLK1_FREQUENCY   STM32_BOARD_HCLK
 
+/* APB1 timers 2-4 will receive PCLK1. */
+
+#define STM32_APB1_TIM2_CLKIN   (STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM3_CLKIN   (STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM4_CLKIN   (STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM5_CLKIN   (STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM6_CLKIN   (STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM7_CLKIN   (STM32_PCLK1_FREQUENCY)
+
 /* Timer 1..8 Frequencies */
 
 #define STM32_TIM27_FREQUENCY   (STM32_BOARD_HCLK)