Add BKP, DBGMCU, EXTI, and PWR header files

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2084 42af7a65-404d-4744-a932-0658087f49c3

5 files changed, 551 insertions, 12 deletions

diff --git a/nuttx/arch/arm/src/stm32/chip.h b/nuttx/arch/arm/src/stm32/chip.h
index 5af969b1f..53b02214e 100755
--- a/nuttx/arch/arm/src/stm32/chip.h
+++ b/nuttx/arch/arm/src/stm32/chip.h
@@ -49,18 +49,21 @@
 
 /* Get customizations for each supported chip (only the STM32F103Z right now) */
 
-#ifdef CONFIG_CHIP_STM32F103Z
-#  undef  CONFIG_STM32_CONNECTIVITYLINE
-#  define STM32_NTIM     4 /* TIM1-TIM4 */
-#  define STM32_NSPI     1 /* SPI1 */
-#  define STM32_NUSART   3 /* USART1-3 */
-#  define STM32_NI2C     2 /* I2C1-2 */
-#  define STM32_NCAN     1 /* bxCAN1 */
-#  define STM32_NGPIO    5 /* GPIOA-E */
-#  define STM32_NADC     2 /* ADC 1-2 */
-#  define STM32_NDAC     0 /* No DAC */
-#  define STM32_NCRC     0 /* No CRC */
-#  define STM32_NTHERNET 0 /* No ethernet */
+#ifdef CONFIG_CHIP_STM32F103ZET6
+#  undef CONFIG_STM32_LOWDENSITY          /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
+#  undef  CONFIG_STM32_MEDIUMDENSITY      /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
+#  define CONFIG_STM32_HIGHDENSITY      1 /* STM32F101x  and STM32F103x w/ 256/512 Kbytes */
+#  undef  CONFIG_STM32_CONNECTIVITYLINE   /* STM32F105x and STM32F107x */
+#  define STM32_NTIM                    4 /* TIM1-TIM4 */
+#  define STM32_NSPI                    1 /* SPI1 */
+#  define STM32_NUSART                  3 /* USART1-3 */
+#  define STM32_NI2C                    2 /* I2C1-2 */
+#  define STM32_NCAN                    1 /* bxCAN1 */
+#  define STM32_NGPIO                   5 /* GPIOA-E */
+#  define STM32_NADC                    2 /* ADC 1-2 */
+#  define STM32_NDAC                    0 /* No DAC */
+#  define STM32_NCRC                    0 /* No CRC */
+#  define STM32_NTHERNET                0 /* No ethernet */
 #else
 #  error "Unsupported STM32 chip */
 #endif
diff --git a/nuttx/arch/arm/src/stm32/stm32_bkp.h b/nuttx/arch/arm/src/stm32/stm32_bkp.h
new file mode 100644
index 000000000..299ef48c8
--- /dev/null
+++ b/nuttx/arch/arm/src/stm32/stm32_bkp.h
@@ -0,0 +1,210 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_bkp.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_STM32_BKP_H
+#define __ARCH_ARM_SRC_STM32_STM32_BKP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include "chip.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE)
+#  define CONFIG_STM32_NBKP_BYTES 84
+#  define CONFIG_STM32_NBKP_REGS  42
+#else
+#  define CONFIG_STM32_NBKP_BYTES 20
+#  define CONFIG_STM32_NBKP_REGS  10
+#endif
+
+/* Register Offsets *****************************************************************/
+
+#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE)
+#  define STM32_BKP_DR_OFFSET(n) ((n) > 10 ? 0x0040+4*((n)-10) : 0x0004+4*(n))
+#else
+#  define STM32_BKP_DR_OFFSET(n)  (0x0004+4*(n))
+#endif
+
+#define STM32_BKP_DR1_OFFSET     0x0004  /* Backup data register 1 */
+#define STM32_BKP_DR2_OFFSET     0x0008  /* Backup data register 2 */
+#define STM32_BKP_DR3_OFFSET     0x000c  /* Backup data register 3 */
+#define STM32_BKP_DR4_OFFSET     0x0010  /* Backup data register 4 */
+#define STM32_BKP_DR5_OFFSET     0x0014  /* Backup data register 5 */
+#define STM32_BKP_DR6_OFFSET     0x0018  /* Backup data register 6 */
+#define STM32_BKP_DR7_OFFSET     0x001c  /* Backup data register 7 */
+#define STM32_BKP_DR8_OFFSET     0x0020  /* Backup data register 8 */
+#define STM32_BKP_DR9_OFFSET     0x0024  /* Backup data register 9 */
+#define STM32_BKP_DR10_OFFSET    0x0028  /* Backup data register 10 */
+
+#define STM32_BKP_RTCCR_OFFSET   0x002c  /* RTC clock calibration register */
+#define STM32_BKP_CR_OFFSET      0x0030  /* Backup control register */
+#define STM32_BKP_CSR_OFFSET     0x0034  /* Backup control/status register */
+
+#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE)
+#  define STM32_BKP_DR11_OFFSET  0x0040  /* Backup data register 11 */
+#  define STM32_BKP_DR12_OFFSET  0x0044  /* Backup data register 12 */
+#  define STM32_BKP_DR13_OFFSET  0x0048  /* Backup data register 13 */
+#  define STM32_BKP_DR14_OFFSET  0x004c  /* Backup data register 14 */
+#  define STM32_BKP_DR15_OFFSET  0x0050  /* Backup data register 15 */
+#  define STM32_BKP_DR16_OFFSET  0x0054  /* Backup data register 16 */
+#  define STM32_BKP_DR17_OFFSET  0x0058  /* Backup data register 17 */
+#  define STM32_BKP_DR18_OFFSET  0x005c  /* Backup data register 18 */
+#  define STM32_BKP_DR19_OFFSET  0x0060  /* Backup data register 19 */
+#  define STM32_BKP_DR20_OFFSET  0x0064  /* Backup data register 20 */
+#  define STM32_BKP_DR21_OFFSET  0x0068  /* Backup data register 21 */
+#  define STM32_BKP_DR22_OFFSET  0x006c  /* Backup data register 22 */
+#  define STM32_BKP_DR23_OFFSET  0x0070  /* Backup data register 23 */
+#  define STM32_BKP_DR24_OFFSET  0x0074  /* Backup data register 24 */
+#  define STM32_BKP_DR25_OFFSET  0x0078  /* Backup data register 25 */
+#  define STM32_BKP_DR26_OFFSET  0x007c  /* Backup data register 26 */
+#  define STM32_BKP_DR27_OFFSET  0x0080  /* Backup data register 27 */
+#  define STM32_BKP_DR28_OFFSET  0x0084  /* Backup data register 28 */
+#  define STM32_BKP_DR29_OFFSET  0x0088  /* Backup data register 29 */
+#  define STM32_BKP_DR30_OFFSET  0x008c  /* Backup data register 30 */
+#  define STM32_BKP_DR31_OFFSET  0x0090  /* Backup data register 31 */
+#  define STM32_BKP_DR32_OFFSET  0x0094  /* Backup data register 32 */
+#  define STM32_BKP_DR33_OFFSET  0x0098  /* Backup data register 33 */
+#  define STM32_BKP_DR34_OFFSET  0x009c  /* Backup data register 34 */
+#  define STM32_BKP_DR35_OFFSET  0x00a0  /* Backup data register 35 */
+#  define STM32_BKP_DR36_OFFSET  0x00a4  /* Backup data register 36 */
+#  define STM32_BKP_DR37_OFFSET  0x00a8  /* Backup data register 37 */
+#  define STM32_BKP_DR38_OFFSET  0x00ac  /* Backup data register 38 */
+#  define STM32_BKP_DR39_OFFSET  0x00b0  /* Backup data register 39 */
+#  define STM32_BKP_DR40_OFFSET  0x00b4  /* Backup data register 40 */
+#  define STM32_BKP_DR41_OFFSET  0x00b8  /* Backup data register 41 */
+#  define STM32_BKP_DR42_OFFSET  0x00bc  /* Backup data register 42 */
+#endif
+
+/* Register Addresses ***************************************************************/
+
+#define STM32_BKP_RTCCR          (STM32_BKP_BASE+STM32_BKP_RTCCR_OFFSET)
+#define STM32_BKP_CR             (STM32_BKP_BASE+STM32_BKP_CR_OFFSET)
+#define STM32_BKP_CSR            (STM32_BKP_BASE+STM32_BKP_CSR_OFFSET)
+
+#define STM32_BKP_DR(n)          (STM32_BKP_BASE+STM32_BKP_DR_OFFSET(n))
+#define STM32_BKP_DR1            (STM32_BKP_BASE+STM32_BKP_DR1_OFFSET)
+#define STM32_BKP_DR2            (STM32_BKP_BASE+STM32_BKP_DR2_OFFSET)
+#define STM32_BKP_DR3            (STM32_BKP_BASE+STM32_BKP_DR3_OFFSET)
+#define STM32_BKP_DR4            (STM32_BKP_BASE+STM32_BKP_DR4_OFFSET)
+#define STM32_BKP_DR5            (STM32_BKP_BASE+STM32_BKP_DR5_OFFSET)
+#define STM32_BKP_DR6            (STM32_BKP_BASE+STM32_BKP_DR6_OFFSET)
+#define STM32_BKP_DR7            (STM32_BKP_BASE+STM32_BKP_DR7_OFFSET)
+#define STM32_BKP_DR8            (STM32_BKP_BASE+STM32_BKP_DR8_OFFSET)
+#define STM32_BKP_DR9            (STM32_BKP_BASE+STM32_BKP_DR9_OFFSET)
+#define STM32_BKP_DR10           (STM32_BKP_BASE+STM32_BKP_DR10_OFFSET)
+
+#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE)
+#  define STM32_BKP_DR11         (STM32_BKP_BASE+STM32_BKP_DR11_OFFSET)
+#  define STM32_BKP_DR12         (STM32_BKP_BASE+STM32_BKP_DR12_OFFSET)
+#  define STM32_BKP_DR13         (STM32_BKP_BASE+STM32_BKP_DR13_OFFSET)
+#  define STM32_BKP_DR14         (STM32_BKP_BASE+STM32_BKP_DR14_OFFSET)
+#  define STM32_BKP_DR15         (STM32_BKP_BASE+STM32_BKP_DR15_OFFSET)
+#  define STM32_BKP_DR16         (STM32_BKP_BASE+STM32_BKP_DR16_OFFSET)
+#  define STM32_BKP_DR17         (STM32_BKP_BASE+STM32_BKP_DR17_OFFSET)
+#  define STM32_BKP_DR18         (STM32_BKP_BASE+STM32_BKP_DR18_OFFSET)
+#  define STM32_BKP_DR19         (STM32_BKP_BASE+STM32_BKP_DR19_OFFSET)
+#  define STM32_BKP_DR20         (STM32_BKP_BASE+STM32_BKP_DR20_OFFSET)
+#  define STM32_BKP_DR21         (STM32_BKP_BASE+STM32_BKP_DR21_OFFSET)
+#  define STM32_BKP_DR22         (STM32_BKP_BASE+STM32_BKP_DR22_OFFSET)
+#  define STM32_BKP_DR23         (STM32_BKP_BASE+STM32_BKP_DR23_OFFSET)
+#  define STM32_BKP_DR24         (STM32_BKP_BASE+STM32_BKP_DR24_OFFSET)
+#  define STM32_BKP_DR25         (STM32_BKP_BASE+STM32_BKP_DR25_OFFSET)
+#  define STM32_BKP_DR26         (STM32_BKP_BASE+STM32_BKP_DR26_OFFSET)
+#  define STM32_BKP_DR27         (STM32_BKP_BASE+STM32_BKP_DR27_OFFSET)
+#  define STM32_BKP_DR28         (STM32_BKP_BASE+STM32_BKP_DR28_OFFSET)
+#  define STM32_BKP_DR29         (STM32_BKP_BASE+STM32_BKP_DR29_OFFSET)
+#  define STM32_BKP_DR30         (STM32_BKP_BASE+STM32_BKP_DR30_OFFSET)
+#  define STM32_BKP_DR31         (STM32_BKP_BASE+STM32_BKP_DR31_OFFSET)
+#  define STM32_BKP_DR32         (STM32_BKP_BASE+STM32_BKP_DR32_OFFSET)
+#  define STM32_BKP_DR33         (STM32_BKP_BASE+STM32_BKP_DR33_OFFSET)
+#  define STM32_BKP_DR34         (STM32_BKP_BASE+STM32_BKP_DR34_OFFSET)
+#  define STM32_BKP_DR35         (STM32_BKP_BASE+STM32_BKP_DR35_OFFSET)
+#  define STM32_BKP_DR36         (STM32_BKP_BASE+STM32_BKP_DR36_OFFSET)
+#  define STM32_BKP_DR37         (STM32_BKP_BASE+STM32_BKP_DR37_OFFSET)
+#  define STM32_BKP_DR38         (STM32_BKP_BASE+STM32_BKP_DR38_OFFSET)
+#  define STM32_BKP_DR39         (STM32_BKP_BASE+STM32_BKP_DR39_OFFSET)
+#  define STM32_BKP_DR40         (STM32_BKP_BASE+STM32_BKP_DR40_OFFSET)
+#  define STM32_BKP_DR41         (STM32_BKP_BASE+STM32_BKP_DR41_OFFSET)
+#  define STM32_BKP_DR42         (STM32_BKP_BASE+STM32_BKP_DR42_OFFSET)
+#endif
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* RTC clock calibration register */
+
+#define BKP_RTCCR_CAL_SHIFT      (0)       /* Bits 6-0: Calibration value */
+#define BKP_RTCCR_CAL_MASK       (0x7f << BKP_RTCCR_CAL_SHIFT)
+#define BKP_RTCCR_CCO            (1 << 7)  /* Bit 7: Calibration Clock Output */
+#define BKP_RTCCR_ASOE           (1 << 8)  /* Bit 8: Alarm or Second Output Enable */
+#define BKP_RTCCR_ASOS           (1 << 9)  /* Bit 9: Alarm or Second Output Selection */
+
+/* Backup control register */
+
+#define BKP_CR_TPE               (1 << 0)  /* Bit 0: TAMPER pin enable */
+#define BKP_CR_TPAL              (1 << 1)  /* Bit 1: TAMPER pin active level */
+
+/* Backup control/status register */
+
+#define BKP_CSR_CTE              (1 << 0)  /* Bit 0: Clear Tamper event */
+#define BKP_CSR_CTI              (1 << 1)  /* Bit 1: Clear Tamper Interrupt */
+#define BKP_CSR_TPIE             (1 << 2)  /* Bit 2: TAMPER Pin interrupt enable */
+#define BKP_CSR_TEF              (1 << 8)  /* Bit 8: Tamper Event Flag */
+#define BKP_CSR_TIF              (1 << 9)  /* Bit 9: Tamper Interrupt Flag */
+
+/* Backup data register */
+
+#define BKP_DR_SHIFT             (0)       /* Bits 1510: Backup data */
+#define BKP_DR_MASK              (0xffff << BKP_DR_SHIFT)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32_STM32_BKP_H */
diff --git a/nuttx/arch/arm/src/stm32/stm32_dgbmcu.h b/nuttx/arch/arm/src/stm32/stm32_dgbmcu.h
new file mode 100644
index 000000000..77657fcf0
--- /dev/null
+++ b/nuttx/arch/arm/src/stm32/stm32_dgbmcu.h
@@ -0,0 +1,104 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_dbgmcu.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_STM32_DBGMCU_H
+#define __ARCH_ARM_SRC_STM32_STM32_DBGMCU_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include "chip.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Register Addresses ***************************************************************/
+
+#define STM32_DBGMCU_IDCODE       0xe0042000  /* MCU identifier */
+#define STM32_DBGMCU_CR_OFFSET    0xe0042004  /* MCU debug */
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* MCU identifier */
+
+#define DBGMCU_IDCODE_DEVID_SHIFT (0) /* Bits 11-0: Device Identifier */
+#define DBGMCU_IDCODE_DEVID_MASK  (0x0fff << DBGMCU_IDCODE_DEVID_SHIFT)
+#define DBGMCU_IDCODE_REVID_SHIFT (16) /* Bits 31-16:  Revision Identifier */
+#define DBGMCU_IDCODE_REVID_MASK  (0xffff << DBGMCU_IDCODE_REVID_SHIFT)
+
+/* MCU debug */
+
+#define DBGMCU_CR_SLEEP           (1 << 0)  /* Bit 0: Debug Sleep Mode */
+#define DBGMCU_CR_STOP            (1 << 1)  /* Bit 1: Debug Stop Mode */
+#define DBGMCU_CR_STANDBY         (1 << 2)  /* Bit 2: Debug Standby mode */
+#define DBGMCU_CR_TRACEIOEN       (1 << 5)  /* Bit 5: Trace enabled */
+#define DBGMCU_CR_TRACEMODE_SHIFT (6)        /* Bits 7-6: Trace mode pin assignement */
+#define DBGMCU_CR_TRACEMODE_MASK  (3 << DBGMCU_CR_TRACEMODE_SHIFT)
+#  define DBGMCU_CR_ASYNCH        (0 <<  DBGMCU_CR_TRACEMODE_SHIFT) /* Asynchronous Mode */
+#  define DBGMCU_CR_SYNCH1        (1 <<  DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=1 */
+#  define DBGMCU_CR_SYNCH2        (2 <<  DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=2 */
+#  define DBGMCU_CR_SYNCH4        (3 <<  DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=4 */
+#define DBGMCU_CR_IWDGSTOP        (1 << 8)   /* Bit 8: Independent Watchdog stopped when core is halted */
+#define DBGMCU_CR_WWDGSTOP        (1 << 9)   /* Bit 9: Window Watchdog stopped when core is halted */
+#define DBGMCU_CR_TIM1STOP        (1 << 10)  /* Bit 10: TIM1 stopped when core is halted */
+#define DBGMCU_CR_TIM2STOP        (1 << 11)  /* Bit 11: TIM2 stopped when core is halted */
+#define DBGMCU_CR_TIM3STOP        (1 << 12)  /* Bit 12: TIM3 stopped when core is halted */
+#define DBGMCU_CR_TIM4STOP        (1 << 13)  /* Bit 13: TIM4 stopped when core is halted */
+#define DBGMCU_CR_CAN1STOP        (1 << 14)  /* Bit 14: CAN1 stopped when core is halted */
+#define DBGMCU_CR_SMBUS1STOP      (1 << 15)  /* Bit 15: I2C1 SMBUS timeout mode stopped when core is halted */
+#define DBGMCU_CR_SMBUS2STOP      (1 << 16)  /* Bit 16: I2C2 SMBUS timeout mode stopped when core is halted */
+#define DBGMCU_CR_TIM8STOP        (1 << 17)  /* Bit 17: TIM8 stopped when core is halted */
+#define DBGMCU_CR_TIM5STOP        (1 << 18)  /* Bit 18: TIM5 stopped when core is halted */
+#define DBGMCU_CR_TIM6STOP        (1 << 19)  /* Bit 19: TIM6 stopped when core is halted */
+#define DBGMCU_CR_TIM7STOP        (1 << 20)  /* Bit 20: TIM7 stopped when core is halted */
+#define DBGMCU_CR_CAN2STOP        (1 << 21)  /* Bit 21: CAN2 stopped when core is halted */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32_STM32_DBGMCU_H */
diff --git a/nuttx/arch/arm/src/stm32/stm32_exti.h b/nuttx/arch/arm/src/stm32/stm32_exti.h
new file mode 100644
index 000000000..c4e7947c1
--- /dev/null
+++ b/nuttx/arch/arm/src/stm32/stm32_exti.h
@@ -0,0 +1,123 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_exti.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_STM32_EXTI_H
+#define __ARCH_ARM_SRC_STM32_STM32_EXTI_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include "chip.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+#ifdef CONFIG_STM32_CONNECTIVITYLINE
+#  define STM32_NEXTI            20
+#  define STM32_EXTI_MASK        0x000fffff
+#else
+#  define STM32_NEXTI            19
+#  define STM32_EXTI_MASK        0x0007ffff
+#endif
+
+#define STM32_EXTI_BIT(n)        (1 << (n))
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_EXTI_IMR_OFFSET    0x0000  /* Interrupt mask register */
+#define STM32_EXTI_EMR_OFFSET    0x0004  /* Event mask register */
+#define STM32_EXTI_RTSR_OFFSET   0x0008  /* Rising Trigger selection register */
+#define STM32_EXTI_FTSR_OFFSET   0x000c  /* Falling Trigger selection register */
+#define STM32_EXTI_SWIER_OFFSET  0x0010  /* Software interrupt event register */
+#define STM32_EXTI_PR_OFFSET     0x0014  /* Pending register */
+
+/* Register Addresses ***************************************************************/
+
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* Interrupt mask register */
+
+#define EXTI_IMR_BIT(n)          STM32_EXTI_BIT(n)
+#define EXTI_IMR_SHIFT           (0)     /* Bits 18/19-0: Interrupt Mask on line n */
+#define EXTI_IMR_MASK            STM32_EXTI_MASK
+
+/* Event mask register */
+
+#define EXTI_EMR_BIT(n)          STM32_EXTI_BIT(n)
+#define EXTI_EMR_SHIFT           (0)     /* Bits 18/19-0:  Event Mask on line n */
+#define EXTI_EMR_MASK            STM32_EXTI_MASK
+
+/* Rising Trigger selection register */
+
+#define EXTI_RTSR_BIT(n)         STM32_EXTI_BIT(n)
+#define EXTI_RTSR_SHIFT          (0)     /* Bits 18/19-0: Rising trigger event configuration bit of line n */
+#define EXTI_RTSR_MASK           STM32_EXTI_MASK
+
+/* Falling Trigger selection register */
+
+#define EXTI_FTSR_BIT(n)         STM32_EXTI_BIT(n)
+#define EXTI_FTSR_SHIFT          (0)     /* Bits 18/19-0: Falling trigger event configuration bit of line n */
+#define EXTI_FTSR_MASK           STM32_EXTI_MASK
+
+/* Software interrupt event register  */
+
+#define EXTI_SWIER_BIT(n)        STM32_EXTI_BIT(n)
+#define EXTI_SWIER_SHIFT         (0)     /*  Bits 18/19-0: Software Interrupt on line n */
+#define EXTI_SWIER_MASK          STM32_EXTI_MASK
+
+/* Pending register */
+
+#define EXTI_IMR_BIT(n)          STM32_EXTI_BIT(n)
+#define EXTI_IMR_SHIFT           (0)     /* Bits 18/19-0: Pending bit on line x */
+#define EXTI_IMR_MASK            STM32_EXTI_MASK
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32_STM32_EXTI_H */
diff --git a/nuttx/arch/arm/src/stm32/stm32_pwr.h b/nuttx/arch/arm/src/stm32/stm32_pwr.h
new file mode 100644
index 000000000..4b9964b09
--- /dev/null
+++ b/nuttx/arch/arm/src/stm32/stm32_pwr.h
@@ -0,0 +1,99 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_pwr.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_STM32_PWR_H
+#define __ARCH_ARM_SRC_STM32_STM32_PWR_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include "chip.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_PWR_CR_OFFSET    000x00  /* Power control register */
+#define STM32_PWR_CSR_OFFSET   0x0004  /* Power control/status register */
+
+/* Register Addresses ***************************************************************/
+
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* Power control register */
+
+#define PWR_CR_LPDS            (1 << 0)  /* Bit 0: Low-Power Deepsleep */
+#define PWR_CR_PDDS            (1 << 1)  /* Bit 1: Power Down Deepsleep */
+#define PWR_CR_CWUF            (1 << 2)  /* Bit 2: Clear Wakeup Flag */
+#define PWR_CR_CSBF            (1 << 3)  /* Bit 3: Clear Standby Flag */
+#define PWR_CR_PVDE            (1 << 4)  /* Bit 4: Power Voltage Detector Enable */
+#define PWR_CR_PLS_SHIFT       (5)       /* Bits 7-5: PVD Level Selection */
+#define PWR_CR_PLS_MASK        (7 << PWR_CR_PLS_SHIFT)
+#  define PWR_CR_2p2V          (0 << PWR_CR_PLS_SHIFT) /* 000: 2.2V */
+#  define PWR_CR_2p3V          (1 << PWR_CR_PLS_SHIFT) /* 001: 2.3V */
+#  define PWR_CR_2p4V          (2 << PWR_CR_PLS_SHIFT) /* 010: 2.4V */
+#  define PWR_CR_2p5V          (3 << PWR_CR_PLS_SHIFT) /* 011: 2.5V */
+#  define PWR_CR_2p6V          (4 << PWR_CR_PLS_SHIFT) /* 100: 2.6V */
+#  define PWR_CR_2p7V          (5 << PWR_CR_PLS_SHIFT) /* 101: 2.7V */
+#  define PWR_CR_2p8V          (6 << PWR_CR_PLS_SHIFT) /* 110: 2.8V */
+#  define PWR_CR_2p9V          (7 << PWR_CR_PLS_SHIFT) /* 111: 2.9V */
+#define PWR_CR_DBP             (1 << 8)  /* Bit 8: Disable Backup Domain write protection */
+
+/* Power control/status register */
+
+#define PWR_CSR_WUF            (1 << 0)  /* Bit 0: Wakeup Flag */
+#define PWR_CSR_SBF            (1 << 1)  /* Bit 1: Standby Flag */
+#define PWR_CSR_PVDO           (1 << 2)  /* Bit 2: PVD Output */
+#define PWR_CSR_EWUP           (1 << 8)  /* Bit 8: Enable WKUP pin */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32_STM32_PWR_H */