SAMV7: Add basic clock and timer ISR configuration logic

12 files changed, 1153 insertions, 28 deletions

diff --git a/nuttx/arch/arm/src/samv7/Make.defs b/nuttx/arch/arm/src/samv7/Make.defs
index 3d59c7fd4..ad37a9e6d 100644
--- a/nuttx/arch/arm/src/samv7/Make.defs
+++ b/nuttx/arch/arm/src/samv7/Make.defs
@@ -1,7 +1,7 @@
 ############################################################################
 # arch/arm/src/samv7/Make.defs
 #
-#   Copyright (C) 2009-2011, 2013-2015 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2015 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -91,6 +91,10 @@ endif
 # Required SAM3/4 files
 
 CHIP_ASRCS  =
-CHIP_CSRCS  =  sam_start.c
+CHIP_CSRCS  =  sam_start.c sam_clockconfig.c
 
 # Configuration-dependent SAM3/4 files
+
+ifneq ($(CONFIG_SCHED_TICKLESS),y)
+CHIP_CSRCS += sam_timerisr.c
+endif
diff --git a/nuttx/arch/arm/src/samv7/chip/sam_eefc.h b/nuttx/arch/arm/src/samv7/chip/sam_eefc.h
index 2b31f6766..aee93614a 100644
--- a/nuttx/arch/arm/src/samv7/chip/sam_eefc.h
+++ b/nuttx/arch/arm/src/samv7/chip/sam_eefc.h
@@ -60,11 +60,11 @@
 
 /* EEFC register addresses **************************************************************/
 
-#define SAM_EEFC_FMR                (SAM_EEFC0_BASE+SAM_EEFC_FMR_OFFSET)
-#define SAM_EEFC_FCR                (SAM_EEFC0_BASE+SAM_EEFC_FCR_OFFSET)
-#define SAM_EEFC_FSR                (SAM_EEFC0_BASE+SAM_EEFC_FSR_OFFSET)
-#define SAM_EEFC_FRR                (SAM_EEFC0_BASE+SAM_EEFC_FRR_OFFSET)
-#define SAM_EEFC_WPMR               (SAM_EEFC0_BASE+SAM_EEFC_WPMR_OFFSET)
+#define SAM_EEFC_FMR                (SAM_EEFC_BASE+SAM_EEFC_FMR_OFFSET)
+#define SAM_EEFC_FCR                (SAM_EEFC_BASE+SAM_EEFC_FCR_OFFSET)
+#define SAM_EEFC_FSR                (SAM_EEFC_BASE+SAM_EEFC_FSR_OFFSET)
+#define SAM_EEFC_FRR                (SAM_EEFC_BASE+SAM_EEFC_FRR_OFFSET)
+#define SAM_EEFC_WPMR               (SAM_EEFC_BASE+SAM_EEFC_WPMR_OFFSET)
 
 /* EEFC register bit definitions ********************************************************/
 /* EEFC Flash Mode Register */
diff --git a/nuttx/arch/arm/src/samv7/chip/sam_matrix.h b/nuttx/arch/arm/src/samv7/chip/sam_matrix.h
new file mode 100644
index 000000000..567e900a4
--- /dev/null
+++ b/nuttx/arch/arm/src/samv7/chip/sam_matrix.h
@@ -0,0 +1,334 @@
+/****************************************************************************************
+ * arch/arm/src/samv7/chip/sam_matrix.h
+ * Bux matrix definitions for the SAMV71
+ *
+ *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_MATRIX_H
+#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_MATRIX_H
+
+/****************************************************************************************
+ * Included Files
+ ****************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+#include "chip/sam_memorymap.h"
+
+/****************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************/
+
+/* MATRIX register offsets **************************************************************/
+
+#define SAM_MATRIX_MCFG_OFFSET(n)        ((n)<<2)
+#  define SAM_MATRIX_MCFG0_OFFSET        0x0000 /* Master Configuration Register 0 */
+#  define SAM_MATRIX_MCFG1_OFFSET        0x0004 /* Master Configuration Register 1 */
+#  define SAM_MATRIX_MCFG2_OFFSET        0x0008 /* Master Configuration Register 2 */
+#  define SAM_MATRIX_MCFG3_OFFSET        0x000c /* Master Configuration Register 3 */
+#  define SAM_MATRIX_MCFG4_OFFSET        0x0010 /* Master Configuration Register 4 */
+#  define SAM_MATRIX_MCFG5_OFFSET        0x0014 /* Master Configuration Register 5 */
+#  define SAM_MATRIX_MCFG6_OFFSET        0x0018 /* Master Configuration Register 6 */
+#  define SAM_MATRIX_MCFG7_OFFSET        0x001c /* Master Configuration Register 7 */
+#  define SAM_MATRIX_MCFG8_OFFSET        0x0020 /* Master Configuration Register 8 */
+#  define SAM_MATRIX_MCFG9_OFFSET        0x0024 /* Master Configuration Register 9 */
+#  define SAM_MATRIX_MCFG10_OFFSET       0x0028 /* Master Configuration Register 10 */
+#  define SAM_MATRIX_MCFG11_OFFSET       0x002c /* Master Configuration Register 11 */
+                                                /* 0x0030-0x003c: Reserved */
+#define SAM_MATRIX_SCFG_OFFSET(n)        (0x0040+((n)<<2))
+# define SAM_MATRIX_SCFG0_OFFSET         0x0040 /* Slave Configuration Register 0 */
+#  define SAM_MATRIX_SCFG1_OFFSET        0x0044 /* Slave Configuration Register 1 */
+#  define SAM_MATRIX_SCFG2_OFFSET        0x0048 /* Slave Configuration Register 2 */
+#  define SAM_MATRIX_SCFG3_OFFSET        0x004c /* Slave Configuration Register 3 */
+#  define SAM_MATRIX_SCFG4_OFFSET        0x0050 /* Slave Configuration Register 4 */
+#  define SAM_MATRIX_SCFG5_OFFSET        0x0054 /* Slave Configuration Register 5 */
+#  define SAM_MATRIX_SCFG6_OFFSET        0x0058 /* Slave Configuration Register 6 */
+#  define SAM_MATRIX_SCFG7_OFFSET        0x005c /* Slave Configuration Register 7 */
+#  define SAM_MATRIX_SCFG8_OFFSET        0x0060 /* Slave Configuration Register 8 */
+                                                /* 0x0064-0x007c: Reserved */
+#define SAM_MATRIX_PRAS_OFFSET(n)        (0x0080+((n)<<3))
+#  define SAM_MATRIX_PRAS0_OFFSET        0x0080 /* Priority Register A for Slave 0 */
+#  define SAM_MATRIX_PRAS1_OFFSET        0x0088 /* Priority Register A for Slave 1 */
+#  define SAM_MATRIX_PRAS2_OFFSET        0x0090 /* Priority Register A for Slave 2 */
+#  define SAM_MATRIX_PRAS3_OFFSET        0x0098 /* Priority Register A for Slave 3 */
+#  define SAM_MATRIX_PRAS4_OFFSET        0x00a0 /* Priority Register A for Slave 4 */
+#  define SAM_MATRIX_PRAS5_OFFSET        0x00a8 /* Priority Register A for Slave 5 */
+#  define SAM_MATRIX_PRAS6_OFFSET        0x00b0 /* Priority Register A for Slave 6 */
+#  define SAM_MATRIX_PRAS7_OFFSET        0x00b8 /* Priority Register A for Slave 7 */
+#  define SAM_MATRIX_PRAS8_OFFSET        0x00c0 /* Priority Register A for Slave 8 */
+
+#define SAM_MATRIX_PRBS_OFFSET(n)        (0x0084+((n)<<3))
+#  define SAM_MATRIX_PRBS0_OFFSET        0x0084 /* Priority Register B for Slave 0 */
+#  define SAM_MATRIX_PRBS1_OFFSET        0x008c /* Priority Register B for Slave 1 */
+#  define SAM_MATRIX_PRBS2_OFFSET        0x0094 /* Priority Register B for Slave 2 */
+#  define SAM_MATRIX_PRBS3_OFFSET        0x009c /* Priority Register B for Slave 3 */
+#  define SAM_MATRIX_PRBS4_OFFSET        0x00a4 /* Priority Register B for Slave 4 */
+#  define SAM_MATRIX_PRBS5_OFFSET        0x00ac /* Priority Register B for Slave 5 */
+#  define SAM_MATRIX_PRBS6_OFFSET        0x00b4 /* Priority Register B for Slave 6 */
+#  define SAM_MATRIX_PRBS7_OFFSET        0x00bc /* Priority Register B for Slave 7 */
+#  define SAM_MATRIX_PRBS8_OFFSET        0x00c4 /* Priority Register B for Slave 8 */
+                                                /* 0x006c8-0x00fc: Reserved */
+#define SAM_MATRIX_MRCR_OFFSET           0x0100 /* Master Remap Control Register */
+                                                /* 0x0104-0x010c: Reserved */
+#define SAM_MATRIX_CAN0_OFFSET           0x0100 /* Master Remap Control Register */
+#define SAM_MATRIX_CCFG_SYSIO_OFFSET     0x0114 /* System I/O Configuration Register */
+                                                /* 0x0118-0x0120: Reserved */
+#define SAM_MATRIX_CCFG_SMCNFCS_OFFSET   0x0124 /* SMC Chip Select NAND Flash Assignment Register */
+                                                /* 0x0128-0x01e0: Reserved */
+#define SAM_MATRIX_WPMR_OFFSET           0x01e4 /* Write Protect Mode Register */
+#define SAM_MATRIX_WPSR_OFFSET           0x01e8 /* Write Protect Status Register */
+                                                /* 0x0110-0x01fc: Reserved */
+
+/* MATRIX register addresses ************************************************************/
+
+#define SAM_MATRIX_MCFG(n))              (SAM_MATRIX_BASE+SAM_MATRIX_MCFG_OFFSET(n))
+#  define SAM_MATRIX_MCFG0               (SAM_MATRIX_BASE+SAM_MATRIX_MCFG0_OFFSET)
+#  define SAM_MATRIX_MCFG1               (SAM_MATRIX_BASE+SAM_MATRIX_MCFG1_OFFSET)
+#  define SAM_MATRIX_MCFG2               (SAM_MATRIX_BASE+SAM_MATRIX_MCFG2_OFFSET)
+#  define SAM_MATRIX_MCFG3               (SAM_MATRIX_BASE+SAM_MATRIX_MCFG3_OFFSET)
+#  define SAM_MATRIX_MCFG4               (SAM_MATRIX_BASE+SAM_MATRIX_MCFG4_OFFSET)
+#  define SAM_MATRIX_MCFG5               (SAM_MATRIX_BASE+SAM_MATRIX_MCFG5_OFFSET)
+#  define SAM_MATRIX_MCFG6               (SAM_MATRIX_BASE+SAM_MATRIX_MCFG6_OFFSET)
+#  define SAM_MATRIX_MCFG7               (SAM_MATRIX_BASE+SAM_MATRIX_MCFG7_OFFSET)
+#  define SAM_MATRIX_MCFG8               (SAM_MATRIX_BASE+SAM_MATRIX_MCFG8_OFFSET)
+#  define SAM_MATRIX_MCFG9               (SAM_MATRIX_BASE+SAM_MATRIX_MCFG9_OFFSET)
+#  define SAM_MATRIX_MCFG10              (SAM_MATRIX_BASE+SAM_MATRIX_MCFG10_OFFSET)
+#  define SAM_MATRIX_MCFG11              (SAM_MATRIX_BASE+SAM_MATRIX_MCFG11_OFFSET)
+
+#define SAM_MATRIX_SCFG(n)               (SAM_MATRIX_BASE+SAM_MATRIX_SCFG_OFFSET(n))
+#  define SAM_MATRIX_SCFG0               (SAM_MATRIX_BASE+SAM_MATRIX_SCFG0_OFFSET)
+#  define SAM_MATRIX_SCFG1               (SAM_MATRIX_BASE+SAM_MATRIX_SCFG1_OFFSET)
+#  define SAM_MATRIX_SCFG2               (SAM_MATRIX_BASE+SAM_MATRIX_SCFG2_OFFSET)
+#  define SAM_MATRIX_SCFG3               (SAM_MATRIX_BASE+SAM_MATRIX_SCFG3_OFFSET)
+#  define SAM_MATRIX_SCFG4               (SAM_MATRIX_BASE+SAM_MATRIX_SCFG4_OFFSET)
+#  define SAM_MATRIX_SCFG5               (SAM_MATRIX_BASE+SAM_MATRIX_SCFG5_OFFSET)
+#  define SAM_MATRIX_SCFG6               (SAM_MATRIX_BASE+SAM_MATRIX_SCFG6_OFFSET)
+#  define SAM_MATRIX_SCFG7               (SAM_MATRIX_BASE+SAM_MATRIX_SCFG7_OFFSET)
+#  define SAM_MATRIX_SCFG8               (SAM_MATRIX_BASE+SAM_MATRIX_SCFG8_OFFSET)
+
+#define SAM_MATRIX_PRAS(n)               (SAM_MATRIX_BASE+SAM_MATRIX_PRAS_OFFSET(n))
+#  define SAM_MATRIX_PRAS0               (SAM_MATRIX_BASE+SAM_MATRIX_PRAS0_OFFSET)
+#  define SAM_MATRIX_PRAS1               (SAM_MATRIX_BASE+SAM_MATRIX_PRAS1_OFFSET)
+#  define SAM_MATRIX_PRAS2               (SAM_MATRIX_BASE+SAM_MATRIX_PRAS2_OFFSET)
+#  define SAM_MATRIX_PRAS3               (SAM_MATRIX_BASE+SAM_MATRIX_PRAS3_OFFSET)
+#  define SAM_MATRIX_PRAS4               (SAM_MATRIX_BASE+SAM_MATRIX_PRAS4_OFFSET)
+#  define SAM_MATRIX_PRAS5               (SAM_MATRIX_BASE+SAM_MATRIX_PRAS5_OFFSET)
+#  define SAM_MATRIX_PRAS6               (SAM_MATRIX_BASE+SAM_MATRIX_PRAS6_OFFSET)
+#  define SAM_MATRIX_PRAS7               (SAM_MATRIX_BASE+SAM_MATRIX_PRAS7_OFFSET)
+#  define SAM_MATRIX_PRAS8               (SAM_MATRIX_BASE+SAM_MATRIX_PRAS8_OFFSET)
+
+#define SAM_MATRIX_PRBS(n)               (SAM_MATRIX_BASE+SAM_MATRIX_PRBS_OFFSET(n))
+#  define SAM_MATRIX_PRBS0               (SAM_MATRIX_BASE+SAM_MATRIX_PRBS0_OFFSET)
+#  define SAM_MATRIX_PRBS1               (SAM_MATRIX_BASE+SAM_MATRIX_PRBS1_OFFSET)
+#  define SAM_MATRIX_PRBS2               (SAM_MATRIX_BASE+SAM_MATRIX_PRBS2_OFFSET)
+#  define SAM_MATRIX_PRBS3               (SAM_MATRIX_BASE+SAM_MATRIX_PRBS3_OFFSET)
+#  define SAM_MATRIX_PRBS4               (SAM_MATRIX_BASE+SAM_MATRIX_PRBS4_OFFSET)
+#  define SAM_MATRIX_PRBS5               (SAM_MATRIX_BASE+SAM_MATRIX_PRBS5_OFFSET)
+#  define SAM_MATRIX_PRBS6               (SAM_MATRIX_BASE+SAM_MATRIX_PRBS6_OFFSET)
+#  define SAM_MATRIX_PRBS7               (SAM_MATRIX_BASE+SAM_MATRIX_PRBS7_OFFSET)
+#  define SAM_MATRIX_PRBS8               (SAM_MATRIX_BASE+SAM_MATRIX_PRBS8_OFFSET)
+
+#define SAM_MATRIX_MRCR                  (SAM_MATRIX_BASE+SAM_MATRIX_MRCR_OFFSET)
+#define SAM_MATRIX_CAN0                  (SAM_MATRIX_BASE+SAM_MATRIX_CAN0_OFFSET)
+#define SAM_MATRIX_CCFG_SYSIO            (SAM_MATRIX_BASE+SAM_MATRIX_CCFG_SYSIO_OFFSET)
+#define SAM_MATRIX_CCFG_SMCNFCS         (SAM_MATRIX_BASE+SAM_MATRIX_CCFG_SMCNFCS_OFFSET)
+#define SAM_MATRIX_WPMR                  (SAM_MATRIX_BASE+SAM_MATRIX_WPMR_OFFSET)
+#define SAM_MATRIX_WPSR                  (SAM_MATRIX_BASE+SAM_MATRIX_WPSR_OFFSET)
+
+/* MATRIX register bit definitions ******************************************************/
+/* Master Configuration Registers */
+
+#define MATRIX_MCFG_ULBT_SHIFT           (0)       /* Bits 0-2:  Undefined Length Burst Type */
+#define MATRIX_MCFG_ULBT_MASK            (7 << MATRIX_MCFG_ULBT_SHIFT)
+#  define MATRIX_MCFG_ULBT_INF           (0 << MATRIX_MCFG_ULBT_SHIFT) /* Infinite Length Burst */
+#  define MATRIX_MCFG_ULBT_SINGLE        (1 << MATRIX_MCFG_ULBT_SHIFT) /* Single Access */
+#  define MATRIX_MCFG_ULBT_4BEAT         (2 << MATRIX_MCFG_ULBT_SHIFT) /* 4-beat Burst */
+#  define MATRIX_MCFG_ULBT_8BEAT         (3 << MATRIX_MCFG_ULBT_SHIFT) /* 8-beat Burst */
+#  define MATRIX_MCFG_ULBT_16BEAT        (4 << MATRIX_MCFG_ULBT_SHIFT) /* 16-beat Burst */
+#  define MATRIX_MCFG_ULBT_32BEAT        (5 << MATRIX_MCFG_ULBT_SHIFT) /* 32-beat Burst */
+#  define MATRIX_MCFG_ULBT_64BEAT        (6 << MATRIX_MCFG_ULBT_SHIFT) /* 64-beat Burst */
+#  define MATRIX_MCFG_ULBT_128BEAT       (7 << MATRIX_MCFG_ULBT_SHIFT) /* 128-beat Burst */
+
+/* Bus Matrix Slave Configuration Registers */
+
+#define MATRIX_SCFG_SLOTCYCLE_SHIFT      (0)       /* Bits 0-8:  Maximum Number of Allowed Cycles for a Burst */
+#define MATRIX_SCFG_SLOTCYCLE_MASK       (0x1ff << MATRIX_SCFG_SLOTCYCLE_SHIFT)
+#  define MATRIX_SCFG_SLOTCYCLE(n)       ((uint32_t)(n) << MATRIX_SCFG_SLOTCYCLE_SHIFT)
+#define MATRIX_SCFG_DEFMSTRTYPE_SHIFT    (16)      /* Bits 16-17:  Default Master Type */
+#define MATRIX_SCFG_DEFMSTRTYPE_MASK     (3 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT)
+#  define MATRIX_SCFG_DEFMSTRTYPE_NONE   (0 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT)
+#  define MATRIX_SCFG_DEFMSTRTYPE_LAST   (1 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT)
+#  define MATRIX_SCFG_DEFMSTRTYPE_FIXED  (2 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT)
+#define MATRIX_SCFG_FIXEDDEFMSTR_SHIFT   (18)      /* Bits 18-21:   Fixed Default Master */
+#define MATRIX_SCFG_FIXEDDEFMSTR_MASK    (15 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
+#  define MATRIX_SCFG0_FIXEDDEFMSTR(n)   ((uint32_t)(n) << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
+
+/* Bus Matrix Priority Registers A For Slaves */
+
+#define MATRIX_PRAS_MPR_SHIFT(x)         ((n)<<2)  /* n=0-7 */
+#define MATRIX_PRAS_MPR_MASK(x)          (3 << MATRIX_PRAS_MPR_SHIFT(x))
+#  define MATRIX_PRAS_M0PR_SHIFT         (0)       /* Bits 0-1:  Master 0 Priority */
+#  define MATRIX_PRAS_M0PR_MASK          (3 << MATRIX_PRAS_M0PR_SHIFT)
+#    define MATRIX_PRAS_M0PR(n)          ((uint32_t)(n) << MATRIX_PRAS_M0PR_SHIFT)
+#  define MATRIX_PRAS_M1PR_SHIFT         (4)       /* Bits 4-5:   Master 1 Priority */
+#  define MATRIX_PRAS_M1PR_MASK          (3 << MATRIX_PRAS_M1PR_SHIFT)
+#    define MATRIX_PRAS_M1PR(n)          ((uint32_t)(n) << MATRIX_PRAS_M1PR_SHIFT)
+#  define MATRIX_PRAS_M2PR_SHIFT         (8)       /* Bits 8-9:  Master 2 Priority */
+#  define MATRIX_PRAS_M2PR_MASK          (3 << MATRIX_PRAS_M2PR_SHIFT)
+#    define MATRIX_PRAS_M2PR(n)          ((uint32_t)(n) << MATRIX_PRAS_M2PR_SHIFT)
+#  define MATRIX_PRAS_M3PR_SHIFT         (12)      /* Bits 12-13: Master 3 Priority */
+#  define MATRIX_PRAS_M3PR_MASK          (3 << MATRIX_PRAS_M3PR_SHIFT)
+#    define MATRIX_PRAS_M3PR(n)          ((uint32_t)(n) << MATRIX_PRAS_M3PR_SHIFT)
+#  define MATRIX_PRAS_M4PR_SHIFT         (16)      /* Bits 16-17: Master 4 Priority */
+#  define MATRIX_PRAS_M4PR_MASK          (3 << MATRIX_PRAS_M4PR_SHIFT)
+#    define MATRIX_PRAS_M4PR(n)          ((uint32_t)(n) << MATRIX_PRAS_M4PR_SHIFT)
+#  define MATRIX_PRAS_M5PR_SHIFT         (20)      /* Bits 20-21: Master 5 Priority */
+#  define MATRIX_PRAS_M5PR_MASK          (3 << MATRIX_PRAS_M5PR_SHIFT)
+#    define MATRIX_PRAS_M5PR(n)          ((uint32_t)(n) << MATRIX_PRAS_M5PR_SHIFT)
+#  define MATRIX_PRAS_M6PR_SHIFT         (24)      /* Bits 24-25: Master 6 Priority */
+#  define MATRIX_PRAS_M6PR_MASK          (3 << MATRIX_PRAS_M6PR_SHIFT)
+#    define MATRIX_PRAS_M6PR(n)          ((uint32_t)(n) << MATRIX_PRAS_M6PR_SHIFT)
+#  define MATRIX_PRAS_M7PR_SHIFT         (28)      /* Bits 28-29: Master 7 Priority */
+#  define MATRIX_PRAS_M7PR_MASK          (3 << MATRIX_PRAS_M7PR_SHIFT)
+#    define MATRIX_PRAS_M7PR(n)          ((uint32_t)(n) << MATRIX_PRAS_M7PR_SHIFT)
+
+/* Bus Matrix Priority Registers B For Slaves */
+
+#define MATRIX_PRBS_MPR_SHIFT(x)         (((n)-8) << 2) /* n = 8-11 */
+#define MATRIX_PRBS_MPR_MASK(x)          (3 << MATRIX_PRBS_MPR_SHIFT(x))
+#  define MATRIX_PRBS_M8PR_SHIFT         (0)       /* Bits 0-1:  Master 8 Priority */
+#  define MATRIX_PRBS_M8PR_MASK          (3 << MATRIX_PRBS_M8PR_SHIFT)
+#    define MATRIX_PRBS_M8PR(n)          ((uint32_t)(n) << MATRIX_PRBS_M8PR_SHIFT)
+#  define MATRIX_PRBS_M9PR_SHIFT         (4)       /* Bits 4-5:   Master 9 Priority */
+#  define MATRIX_PRBS_M9PR_MASK          (3 << MATRIX_PRBS_M9PR_SHIFT)
+#    define MATRIX_PRBS_M9PR(n)          ((uint32_t)(n) << MATRIX_PRBS_M9PR_SHIFT)
+#  define MATRIX_PRBS_M10PR_SHIFT         (8)       /* Bits 8-9:  Master 10 Priority */
+#  define MATRIX_PRBS_M10PR_MASK          (3 << MATRIX_PRBS_M10PR_SHIFT)
+#    define MATRIX_PRBS_M10PR(n)          ((uint32_t)(n) << MATRIX_PRBS_M10PR_SHIFT)
+#  define MATRIX_PRBS_M11PR_SHIFT         (12)      /* Bits 12-13: Master 11 Priority */
+#  define MATRIX_PRBS_M11PR_MASK          (3 << MATRIX_PRBS_M11PR_SHIFT)
+#    define MATRIX_PRBS_M11PR(n)          ((uint32_t)(n) << MATRIX_PRBS_M11PR_SHIFT)
+
+/* Master Remap Control Register */
+
+#define MATRIX_MRCR_RCB(n)               (1 << (n)) /* n=0-11 */
+#  define MATRIX_MRCR_RCB0               (1 << 0)  /* Bit 0:  Remap Command Bit for AHB Master 0 */
+#  define MATRIX_MRCR_RCB1               (1 << 1)  /* Bit 1:  Remap Command Bit for AHB Master 1 */
+#  define MATRIX_MRCR_RCB2               (1 << 2)  /* Bit 2:  Remap Command Bit for AHB Master 2 */
+#  define MATRIX_MRCR_RCB3               (1 << 3)  /* Bit 3:  Remap Command Bit for AHB Master 3 */
+#  define MATRIX_MRCR_RCB4               (1 << 4)  /* Bit 4:  Remap Command Bit for AHB Master 4 */
+#  define MATRIX_MRCR_RCB5               (1 << 5)  /* Bit 5:  Remap Command Bit for AHB Master 5 */
+#  define MATRIX_MRCR_RCB6               (1 << 6)  /* Bit 6:  Remap Command Bit for AHB Master 6 */
+#  define MATRIX_MRCR_RCB7               (1 << 7)  /* Bit 7:  Remap Command Bit for AHB Master 7 */
+#  define MATRIX_MRCR_RCB8               (1 << 8)  /* Bit 8:  Remap Command Bit for AHB Master 8 */
+#  define MATRIX_MRCR_RCB9               (1 << 9)  /* Bit 9:  Remap Command Bit for AHB Master 9 */
+#  define MATRIX_MRCR_RCB10              (1 << 10) /* Bit 10: Remap Command Bit for AHB Master 10 */
+#  define MATRIX_MRCR_RCB11              (1 << 11) /* Bit 11: Remap Command Bit for AHB Master 11 */
+
+/* CAN0 Configuration Register */
+
+#define MATRIX_CAN0_CAN0DMABA_MASK       0xffff0000 /* Bits 16-31: CAN0 DMA Base Address */
+
+/* System I/O and CAN1 Configuration Register */
+
+#define MATRIX_CCFG_SYSIO_SYSIO(n)       (1<<(n))  /* n=4-7, 12 */
+#  define MATRIX_CCFG_SYSIO_SYSIO4       (1 << 4)  /* Bit 4:  PB4 or TDI Assignment */
+#  define MATRIX_CCFG_SYSIO_SYSIO5       (1 << 5)  /* Bit 5:  PB5 or TDO/TRACESWO Assignment */
+#  define MATRIX_CCFG_SYSIO_SYSIO6       (1 << 6)  /* Bit 6:  PB6 or TMS/SWDIO Assignment */
+#  define MATRIX_CCFG_SYSIO_SYSIO7       (1 << 7)  /* Bit 7:  PB7 or TCK/SWCLK Assignment */
+#  define MATRIX_CCFG_SYSIO_SYSIO12      (1 << 12) /* Bit 12: PB12 or ERASE Assignment */
+#define MATRIX_CAN0_CAN1DMABA_MASK       0xffff0000 /* Bits 16-31: CAN1 DMA Base Address */
+
+/* SMC Chip Select NAND Flash Assignment Register */
+
+#define MATRIX_CCFG_SMCNFCS_SMC_NFCS(n)  (1<<(n))  /* Bit n:  SMC NAND Flash Chip Select n Assignment */
+#  define MATRIX_CCFG_SMCNFCS_SMC_NFCS0  (1 << 0)  /* Bit 0:  SMC NAND Flash Chip Select 0 Assignment */
+#  define MATRIX_CCFG_SMCNFCS_SMC_NFCS1  (1 << 1)  /* Bit 1:  SMC NAND Flash Chip Select 2 Assignment */
+#  define MATRIX_CCFG_SMCNFCS_SMC_NFCS2  (1 << 2)  /* Bit 2:  SMC NAND Flash Chip Select 2 Assignment */
+#  define MATRIX_CCFG_SMCNFCS_SMC_NFCS3  (1 << 3)  /* Bit 3:  SMC NAND Flash Chip Select 3 Assignment */
+#define MATRIX_CCFG_SMCNFCS_SDRAMEN      (1 << 4)  /* Bit 4:  SDRAM Enable */
+
+/* Write Protect Mode Register */
+
+#define MATRIX_WPMR_WPEN                 (1 << 0)  /* Bit 0:  Write Protect Enable */
+#define MATRIX_WPMR_WPKEY_SHIFT          (8)       /* Bits 8-31:   Write Protect KEY (Write-only) */
+#define MATRIX_WPMR_WPKEY_MASK           (0x00ffffff << MATRIX_WPMR_WPKEY_SHIFT)
+#  define MATRIX_WPMR_WPKEY              (0x004d4154 << MATRIX_WPMR_WPKEY_SHIFT)
+
+/* Write Protect Status Register */
+
+#define MATRIX_WPSR_WPVS                 (1 << 0)  /* Bit 0:  Enable Write Protect */
+#define MATRIX_WPSR_WPVSRC_SHIFT         (8)       /* Bits 8-23:  Write Protect Violation Source */
+#define MATRIX_WPSR_WPVSRC_MASK          (0xffff << MATRIX_WPSR_WPVSRC_SHIFT)
+
+/* Masters ******************************************************************************/
+
+#define MATRIX_MSTR_CORTEXM7_1           0         /* Cortex-M7 */
+#define MATRIX_MSTR_CORTEXM7_2           1         /* Cortex-M7 */
+#define MATRIX_MSTR_CORTEXM7_P           2         /* Cortex-M7 Peripheral Port */
+#define MATRIX_MSTR_ICM                  3         /* Integrated Check Monitor */
+#define MATRIX_MSTR_XDMAC_1              4         /* XDMAC */
+#define MATRIX_MSTR_XDMAC_2              5         /* XDMAC */
+#define MATRIX_MSTR_ISI                  6         /* ISI DMA */
+#define MATRIX_MSTR_MLB                  7         /* Media LB */
+#define MATRIX_MSTR_USB                  8         /* USB DMA */
+#define MATRIX_MSTR_EMAC                 9         /* Ethernet MAC DMA */
+#define MATRIX_MSTR_CAN0                 10        /* CAN0 DMA */
+#define MATRIX_MSTR_CAN1                 11        /* CAN1 DMA */
+
+/* Slaves *******************************************************************************/
+
+#define MATRIX_SLAVE_ISRAM_1             0         /* Internal SRAM */
+#define MATRIX_SLAVE_ISRAM_2             1         /* Internal SRAM */
+#define MATRIX_SLAVE_IROM                2         /* Internal ROM */
+#define MATRIX_SLAVE_IFLASH              3         /* Internal Flash */
+#define MATRIX_SLAVE_USBRAM              4         /* USB High Speed Dual Port RAM (DPR) */
+#define MATRIX_SLAVE_EBI                 5         /* External Bus Interface */
+#define MATRIX_SLAVE_QSPI                6         /* QSPI */
+#define MATRIX_SLAVE_PB                  7         /* Peripheral Bridge */
+#define MATRIX_SLAVE_AHB                 8         /* AHB Slave */
+
+/****************************************************************************************
+ * Public Types
+ ****************************************************************************************/
+
+/****************************************************************************************
+ * Public Data
+ ****************************************************************************************/
+
+/****************************************************************************************
+ * Public Functions
+ ****************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_MATRIX_H */
diff --git a/nuttx/arch/arm/src/samv7/chip/sam_pmc.h b/nuttx/arch/arm/src/samv7/chip/sam_pmc.h
index 994037a86..49b8aef7f 100644
--- a/nuttx/arch/arm/src/samv7/chip/sam_pmc.h
+++ b/nuttx/arch/arm/src/samv7/chip/sam_pmc.h
@@ -208,6 +208,8 @@
 #define PMC_CKGR_UCKR_UPLLEN           (1 << 16) /* Bit 16: UTMI PLL Enable */
 #define PMC_CKGR_UCKR_UPLLCOUNT_SHIFT  (20)      /* Bits 20-23: UTMI PLL Start-up Time */
 #define PMC_CKGR_UCKR_UPLLCOUNT_MASK   (15 << PMC_CKGR_UCKR_UPLLCOUNT_SHIFT)
+#  define PMC_CKGR_UCKR_UPLLCOUNT(n)   ((uint32_t)(n) << PMC_CKGR_UCKR_UPLLCOUNT_SHIFT)
+
 
 /* PMC Clock Generator Main Oscillator Register */
 
@@ -252,6 +254,7 @@
 #define PMC_CKGR_PLLAR_COUNT_MASK      (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
 #define PMC_CKGR_PLLAR_MUL_SHIFT       (16)      /* Bits 16-26: PLLA Multiplier */
 #define PMC_CKGR_PLLAR_MUL_MASK        (0x7ff << PMC_CKGR_PLLAR_MUL_SHIFT)
+#  define PMC_CKGR_PLLAR_MUL(n)        ((uint32_t)(n) << PMC_CKGR_PLLAR_MUL_SHIFT)
 #define PMC_CKGR_PLLAR_ONE             (1 << 29) /* Bit 29: Always one */
 
 /* PMC Master Clock Register */
diff --git a/nuttx/arch/arm/src/samv7/chip/sam_supc.h b/nuttx/arch/arm/src/samv7/chip/sam_supc.h
index d6f5dd92a..878d3e464 100644
--- a/nuttx/arch/arm/src/samv7/chip/sam_supc.h
+++ b/nuttx/arch/arm/src/samv7/chip/sam_supc.h
@@ -52,7 +52,7 @@
 
 /* SUPC register offsets ****************************************************************/
 
-#define SAM_SUPC_CR_OFFSET              000x00 /* Supply Controller Control Register */
+#define SAM_SUPC_CR_OFFSET              0x0000 /* Supply Controller Control Register */
 #define SAM_SUPC_SMMR_OFFSET            0x0004 /* Supply Controller Supply Monitor Mode Register */
 #define SAM_SUPC_MR_OFFSET              0x0008 /* Supply Controller Mode Register */
 #define SAM_SUPC_WUMR_OFFSET            0x000c /* Supply Controller Wake Up Mode Register */
@@ -82,16 +82,16 @@
 #define SUPC_SMMR_SMTH_SHIFT            (0)       /* Bits 0-3:  Supply Monitor Threshold */
 #define SUPC_SMMR_SMTH_MASK             (15 << SUPC_SMMR_SMTH_SHIFT)
 #  define SUPC_SMMR_SMTH(n)             ((uint32_t)(n) << SUPC_SMMR_SMTH_SHIFT)
-#  define SUPC_SMMR_SMTH_1p6V           (0  << SUPC_SMMR_SMTH_SHIFT) /* 1.58 < 1.60 < 1.62 */
-#  define SUPC_SMMR_SMTH_1p7V           (1  << SUPC_SMMR_SMTH_SHIFT) /* 1.70 < 1.72 < 1.74 */
-#  define SUPC_SMMR_SMTH_1p8V           (2  << SUPC_SMMR_SMTH_SHIFT) /* 1.82 < 1.84 < 1.86 */
-#  define SUPC_SMMR_SMTH_2p0V           (3  << SUPC_SMMR_SMTH_SHIFT) /* 1.94 < 1.96 < 1.98 */
-#  define SUPC_SMMR_SMTH_2p2V           (4  << SUPC_SMMR_SMTH_SHIFT) /* 2.05 < 2.08 < 2.11 */
-#  define SUPC_SMMR_SMTH_2p6V           (5  << SUPC_SMMR_SMTH_SHIFT) /* 2.17 < 2.20 < 2.23 */
-#  define SUPC_SMMR_SMTH_2p3V           (6  << SUPC_SMMR_SMTH_SHIFT) /* 2.29 < 2.32 < 2.35 */
-#  define SUPC_SMMR_SMTH_2p4V           (7  << SUPC_SMMR_SMTH_SHIFT) /* 2.41 < 2.44 < 2.47 */
-#  define SUPC_SMMR_SMTH_2p6V           (8  << SUPC_SMMR_SMTH_SHIFT) /* 2.53 < 2.56 < 2.59 */
-#  define SUPC_SMMR_SMTH_2p7V           (9  << SUPC_SMMR_SMTH_SHIFT) /* 2.65 < 2.68 < 2.71 */
+#  define SUPC_SMMR_SMTH_1p6V           (0  << SUPC_SMMR_SMTH_SHIFT)  /* 1.58 < 1.60 < 1.62 */
+#  define SUPC_SMMR_SMTH_1p7V           (1  << SUPC_SMMR_SMTH_SHIFT)  /* 1.70 < 1.72 < 1.74 */
+#  define SUPC_SMMR_SMTH_1p8V           (2  << SUPC_SMMR_SMTH_SHIFT)  /* 1.82 < 1.84 < 1.86 */
+#  define SUPC_SMMR_SMTH_2p0V           (3  << SUPC_SMMR_SMTH_SHIFT)  /* 1.94 < 1.96 < 1.98 */
+#  define SUPC_SMMR_SMTH_2p1V           (4  << SUPC_SMMR_SMTH_SHIFT)  /* 2.05 < 2.08 < 2.11 */
+#  define SUPC_SMMR_SMTH_2p2V           (5  << SUPC_SMMR_SMTH_SHIFT)  /* 2.17 < 2.20 < 2.23 */
+#  define SUPC_SMMR_SMTH_2p3V           (6  << SUPC_SMMR_SMTH_SHIFT)  /* 2.29 < 2.32 < 2.35 */
+#  define SUPC_SMMR_SMTH_2p4V           (7  << SUPC_SMMR_SMTH_SHIFT)  /* 2.41 < 2.44 < 2.47 */
+#  define SUPC_SMMR_SMTH_2p6V           (8  << SUPC_SMMR_SMTH_SHIFT)  /* 2.53 < 2.56 < 2.59 */
+#  define SUPC_SMMR_SMTH_2p7V           (9  << SUPC_SMMR_SMTH_SHIFT)  /* 2.65 < 2.68 < 2.71 */
 #  define SUPC_SMMR_SMTH_2p8V           (10  << SUPC_SMMR_SMTH_SHIFT) /* 2.77 < 2.80 < 2.83 */
 #  define SUPC_SMMR_SMTH_2p9V           (11  << SUPC_SMMR_SMTH_SHIFT) /* 2.90 < 2.92 < 2.95 */
 #  define SUPC_SMMR_SMTH_3p0V           (12  << SUPC_SMMR_SMTH_SHIFT) /* 3.00 < 3.04 < 3.07 */
diff --git a/nuttx/arch/arm/src/samv7/chip/sam_wdt.h b/nuttx/arch/arm/src/samv7/chip/sam_wdt.h
new file mode 100644
index 000000000..f657545a9
--- /dev/null
+++ b/nuttx/arch/arm/src/samv7/chip/sam_wdt.h
@@ -0,0 +1,117 @@
+/****************************************************************************************
+ * arch/arm/src/samv7/chip/sam_wdt.h
+ * Watchdog Timer (WDT) definitions for the SAMV71
+ *
+ *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_WDT_H
+#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_WDT_H
+
+/****************************************************************************************
+ * Included Files
+ ****************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+#include "chip/sam_memorymap.h"
+
+/****************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************/
+
+/* WDT register offsets *****************************************************************/
+
+#define SAM_WDT_CR_OFFSET         0x00 /* Control Register */
+#define SAM_WDT_MR_OFFSET         0x04 /* Mode Register */
+#define SAM_WDT_SR_OFFSET         0x08 /* Status Register */
+
+/* WDT register addresses ***************************************************************/
+
+/* WDT9: Legacy Watchdog Timer */
+
+#define SAM_WDT0_CR               (SAM_WDT0_BASE+SAM_WDT_CR_OFFSET)
+#define SAM_WDT0_MR               (SAM_WDT0_BASE+SAM_WDT_MR_OFFSET)
+#define SAM_WDT0_SR               (SAM_WDT0_BASE+SAM_WDT_SR_OFFSET)
+
+/* WDT1: Reinforced Safety Watchdog Timer */
+
+#define SAM_WDT1_CR               (SAM_WDT1_BASE+SAM_WDT_CR_OFFSET)
+#define SAM_WDT1_MR               (SAM_WDT1_BASE+SAM_WDT_MR_OFFSET)
+#define SAM_WDT1_SR               (SAM_WDT1_BASE+SAM_WDT_SR_OFFSET)
+
+/* WDT register bit definitions *********************************************************/
+/* Watchdog Timer Control Register */
+
+#define WDT_CR_WDRSTT             (1 << 0)   /* Bit 0:  Watchdog Rest */
+#define WDT_CR_KEY_SHIFT          (24)       /* Bits 24-31:  Password */
+#define WDT_CR_KEY_MASK           (0xff << WDT_CR_KEY_SHIFT)
+#  define WDT0_CR_KEY             (0xa5 << WDT_CR_KEY_SHIFT)
+#  define WDT1_CR_KEY             (0xc4 << WDT_CR_KEY_SHIFT)
+
+/* Watchdog Timer Mode Register */
+
+#define WDT_MR_WDV_SHIFT          (0)       /* Bits 0-11:  Watchdog Counter Value */
+#define WDT_MR_WDV_MAX            0xfff
+#define WDT_MR_WDV_MASK           (WDT_MR_WDV_MAX << WDT_MR_WDV_SHIFT)
+#  define WDT_MR_WDV(n)           ((uint32_t)(n) << WDT_MR_WDV_SHIFT)
+#define WDT_MR_WDFIEN             (1 << 12) /* Bit 12: Watchdog Fault Interrupt Enable */
+#define WDT_MR_WDRSTEN            (1 << 13) /* Bit 13: Watchdog Reset Enable */
+#define WDT1_MR_WDRPROC           (1 << 14) /* Bit 14: Watchdog Reset Processor (WDT1 only) */
+#define WDT_MR_WDDIS              (1 << 15) /* Bit 15: Watchdog Disable */
+#define WDT_MR_WDD_SHIFT          (16)      /* Bits 16-27:  Watchdog Delta Value (WDT0 only) */
+#define WDT_MR_WDD_MAX            0xfff
+#define WDT_MR_WDD_MASK           (WDT_MR_WDD_MAX << WDT_MR_WDD_SHIFT)
+#  define WDT0_MR_WDD(n)          ((uint32_t)(n) << WDT_MR_WDD_SHIFT)
+#  define WDT1_MR_WDD_ALLONES     (0xfff << WDT_MR_WDD_SHIFT)
+#define WDT_MR_WDDBGHLT           (1 << 28) /* Bit 28: Watchdog Debug Halt */
+#define WDT_MR_WDIDLEHLT          (1 << 29) /* Bit 29: Watchdog Idle Halt */
+
+/* Watchdog Timer Status Register */
+
+#define WDT_SR_WDUNF              (1 << 0)  /* Bit 0:  Watchdog Underflow */
+#define WDT0_SR_WDERR             (1 << 1)  /* Bit 1:  Watchdog Error (WDT0 only) */
+
+/****************************************************************************************
+ * Public Types
+ ****************************************************************************************/
+
+/****************************************************************************************
+ * Public Data
+ ****************************************************************************************/
+
+/****************************************************************************************
+ * Public Functions
+ ****************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_WDT_H */
diff --git a/nuttx/arch/arm/src/samv7/chip/samv71_memorymap.h b/nuttx/arch/arm/src/samv7/chip/samv71_memorymap.h
index db318bc0f..8663320ec 100644
--- a/nuttx/arch/arm/src/samv7/chip/samv71_memorymap.h
+++ b/nuttx/arch/arm/src/samv7/chip/samv71_memorymap.h
@@ -128,14 +128,14 @@
 #define SAM_UART0_BASE         0x400e0800 /* 0x400e0800-0x400e093f: UART 0 */
 #define SAM_CHIPID_BASE        0x400e0940 /* 0x400e0940-0x400e09ff: CHIP ID */
 #define SAM_UART1_BASE         0x400e0a00 /* 0x400e0a00-0x400e0bff: UART 1 */
-#define SAM_EFC_BASE           0x400e0c00 /* 0x400e0c00-0x400e0dff: Embedded Flash Controller (EFC) */
+#define SAM_EEFC_BASE          0x400e0c00 /* 0x400e0c00-0x400e0dff: Embedded Flash Controller (EEFC) */
 #define SAM_PIO_BASE           0x400e0e00 /* 0x400e0e00-0x400e13ff: Parallel I/O Controllers */
 #  define SAM_PION_BASE(n)     (0x400e0e00 + ((n) << 9))
 #  define SAM_PIOA_BASE        0x400e0e00 /* 0x400e0e00-0x400e0fff:   Parallel I/O Controller A */
 #  define SAM_PIOB_BASE        0x400e1000 /* 0x400e1000-0x400e11ff:   Parallel I/O Controller B */
 #  define SAM_PIOC_BASE        0x400e1200 /* 0x400e1200-0x400e13ff:   Parallel I/O Controller C */
-#  define SAM_PIOD_BASE        0x400e1400 /* 0x400e1400-0x400e15ff:   Parallel I/O Controller C */
-#  define SAM_PIOE_BASE        0x400e1600 /* 0x400e1600-0x400e17ff:   Parallel I/O Controller C */
+#  define SAM_PIOD_BASE        0x400e1400 /* 0x400e1400-0x400e15ff:   Parallel I/O Controller D */
+#  define SAM_PIOE_BASE        0x400e1600 /* 0x400e1600-0x400e17ff:   Parallel I/O Controller E */
 #define SAM_SYSCTRLR_BASE      0x400e0000 /* 0x400e0000-0x400e1bff: System Controller */
 #  define SAM_RSTC_BASE        0x400e1800 /* 0x400e1800-0x400e180f: Reset Controller (RSTC) */
 #  define SAM_SUPC_BASE        0x400e1810 /* 0x400e1810-0x400e182f: Supply Controller (SUPC) */
@@ -144,7 +144,7 @@
 #  define SAM_RTC_BASE         0x400e1860 /* 0x400e1860-0x400e188f: Real Time Clock (RTC) */
 #  define SAM_GPBR_BASE        0x400e1890 /* 0x400e1890-0x400e18ff: GPBR */
 #  define SAM_SYSC_BASE        0x400e18e0 /* 0x400e1890-0x400e18ff: System Controller Common */
-#  define SAM_WDT1_BASE        0x400e1900 /* 0x400e1850-0x400e19ff: Watchdog Timer 1 (WDT1) */
+#  define SAM_WDT1_BASE        0x400e1900 /* 0x400e1900-0x400e19ff: Watchdog Timer 1 (WDT1) */
 #define SAM_UART2_BASE         0x400e1a00 /* 0x400e1a00-0x400e1bff: UART 2 */
 #define SAM_UART3_BASE         0x400e1c00 /* 0x400e1c00-0x400e1dff: UART 3 */
 #define SAM_UART4_BASE         0x400e1e00 /* 0x400e1e00-0x400e1fff: UART 4 */
diff --git a/nuttx/arch/arm/src/samv7/sam_clockconfig.c b/nuttx/arch/arm/src/samv7/sam_clockconfig.c
new file mode 100644
index 000000000..554d9344f
--- /dev/null
+++ b/nuttx/arch/arm/src/samv7/sam_clockconfig.c
@@ -0,0 +1,342 @@
+/****************************************************************************
+ * arch/arm/src/samv7/sam_clockconfig.c
+ *
+ *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "up_internal.h"
+
+#include "sam_clockconfig.h"
+#include "chip/sam_pmc.h"
+#include "chip/sam_eefc.h"
+#include "chip/sam_wdt.h"
+#include "chip/sam_supc.h"
+#include "chip/sam_matrix.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* PMC register settings based on the board configuration values defined
+ * in board.h
+ */
+
+#define BOARD_CKGR_MOR      (PMC_CKGR_MOR_MOSCXTEN | PMC_CKGR_MOR_MOSCRCEN | \
+                             BOARD_CKGR_MOR_MOSCXTST | PMC_CKGR_MOR_KEY)
+#define BOARD_CKGR_PLLAR    (BOARD_CKGR_PLLAR_DIV | BOARD_CKGR_PLLAR_COUNT | \
+                             BOARD_CKGR_PLLAR_MUL | PMC_CKGR_PLLAR_ONE)
+                             
+#define BOARD_PMC_MCKR_FAST (PMC_MCKR_CSS_MAIN | BOARD_PMC_MCKR_PRES | \
+                             BOARD_PMC_MCKR_MDIV | BOARD_PMC_MCKR_UPLLDIV2)
+#define BOARD_PMC_MCKR      (BOARD_PMC_MCKR_CSS | BOARD_PMC_MCKR_PRES | \
+                             BOARD_PMC_MCKR_MDIV | BOARD_PMC_MCKR_UPLLDIV2)
+#define BOARD_CKGR_UCKR     (BOARD_CKGR_UCKR_UPLLCOUNT | PMC_CKGR_UCKR_UPLLEN)
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_efcsetup
+ *
+ * Description:
+ *   Configure wait states for embedded flash access
+ *
+ ****************************************************************************/
+
+static inline void sam_efcsetup(void)
+{
+  uint32_t regval = EEFC_FMR_FWS(BOARD_FWS) | EEFC_FMR_CLOE;
+  putreg32(regval, SAM_EEFC_FMR);
+}
+
+/****************************************************************************
+ * Name: sam_wdtsetup
+ *
+ * Description:
+ *   Disable the watchdog timer
+ *
+ ****************************************************************************/
+
+static inline void sam_wdtsetup(void)
+{
+#if !defined(CONFIG_SAMV7_WDT0) || \
+    (defined(CONFIG_WDT0_ENABLED_ON_RESET) && defined(CONFIG_WDT0_DISABLE_ON_RESET))
+  putreg32(WDT_MR_WDDIS, SAM_WDT0_MR);
+#endif
+
+#if !defined(CONFIG_SAMV7_WDT1) || \
+    (defined(CONFIG_WDT1_ENABLED_ON_RESET) && defined(CONFIG_WDT1_DISABLE_ON_RESET))
+  putreg32(WDT_MR_WDDIS, SAM_WDT1_MR);
+#endif
+}
+
+/****************************************************************************
+ * Name: sam_supcsetup
+ *
+ * Description:
+ *   Select the external slow clock
+ *
+ ****************************************************************************/
+
+static inline void sam_supcsetup(void)
+{
+  /* Check if the 32-kHz is already selected */
+
+  if ((getreg32(SAM_SUPC_SR) & SUPC_SR_OSCSEL) == 0)
+    {
+      uint32_t delay;
+
+      putreg32((SUPC_CR_XTALSEL|SUPR_CR_KEY), SAM_SUPC_CR);
+      for (delay = 0;
+           (getreg32(SAM_SUPC_SR) & SUPC_SR_OSCSEL) == 0 && delay < UINT32_MAX;
+           delay++);
+    }
+}
+
+/****************************************************************************
+ * Name: sam_pmcwait
+ *
+ * Description:
+ *   Wait for the specified PMC status bit to become "1"
+ *
+ ****************************************************************************/
+
+static void sam_pmcwait(uint32_t bit)
+{
+  volatile uint32_t delay;
+
+  for (delay = 0;
+       (getreg32(SAM_PMC_SR) & bit) == 0 && delay < UINT32_MAX;
+       delay++);
+}
+
+/****************************************************************************
+ * Name: sam_pmcsetup
+ *
+ * Description:
+ *   Initialize clocking
+ *
+ ****************************************************************************/
+
+static inline void sam_pmcsetup(void)
+{
+  uint32_t regval;
+
+  /* Enable main oscillator (if it has not already been selected) */
+
+  if ((getreg32(SAM_PMC_CKGR_MOR) & PMC_CKGR_MOR_MOSCSEL) == 0)
+    {
+      /* "When the MOSCXTEN bit and the MOSCXTCNT are written in CKGR_MOR to
+       *  enable the main oscillator, the MOSCXTS bit in the Power Management
+       *  Controller Status Register (PMC_SR) is cleared and the counter starts
+       *  counting down on the slow clock divided by 8 from the MOSCXTCNT
+       *  value. ... When the counter reaches 0, the MOSCXTS bit is set,
+       *  indicating that the main clock is valid."
+       */
+
+      putreg32(BOARD_CKGR_MOR, SAM_PMC_CKGR_MOR);
+      sam_pmcwait(PMC_INT_MOSCXTS);
+    }
+
+  /* "Switch to the main oscillator.  The selection is made by writing the
+   *  MOSCSEL bit in the Main Oscillator Register (CKGR_MOR). The switch of
+   *  the Main Clock source is glitch free, so there is no need to run out
+   *  of SLCK, PLLACK or UPLLCK in order to change the selection. The MOSCSELS
+   *  bit of the power Management Controller Status Register (PMC_SR) allows
+   *  knowing when the switch sequence is done."
+   *
+   *   MOSCSELS: Main Oscillator Selection Status
+   *             0 = Selection is done
+   *             1 = Selection is in progress
+   */
+
+  putreg32((BOARD_CKGR_MOR | PMC_CKGR_MOR_MOSCSEL), SAM_PMC_CKGR_MOR);
+  sam_pmcwait(PMC_INT_MOSCSELS);
+
+  /* "Select the master clock. "The Master Clock selection is made by writing
+   *  the CSS field (Clock Source Selection) in PMC_MCKR (Master Clock Register).
+   *  The prescaler supports the division by a power of 2 of the selected clock
+   *  between 1 and 64, and the division by 3. The PRES field in PMC_MCKR programs
+   *  the prescaler. Each time PMC_MCKR is written to define a new Master Clock,
+   *  the MCKRDY bit is cleared in PMC_SR. It reads 0 until the Master Clock is
+   *  established.
+   */
+
+  regval  = getreg32(SAM_PMC_MCKR);
+  regval &= ~PMC_MCKR_CSS_MASK;
+  regval |= PMC_MCKR_CSS_MAIN;
+  putreg32(regval, SAM_PMC_MCKR);
+  sam_pmcwait(PMC_INT_MCKRDY);
+
+  /* Setup PLLA and wait for LOCKA */
+
+  putreg32(BOARD_CKGR_PLLAR, SAM_PMC_CKGR_PLLAR);
+  sam_pmcwait(PMC_INT_LOCKA);
+
+#ifdef CONFIG_USBDEV
+  /* Setup UTMI for USB and wait for LOCKU */
+
+  regval = getreg32(SAM_PMC_CKGR_UCKR);
+  regval |= BOARD_CKGR_UCKR;
+  putreg32(regval, SAM_PMC_CKGR_UCKR);
+  sam_pmcwait(PMC_INT_LOCKU);
+#endif
+
+  /* Switch to the fast clock and wait for MCKRDY */
+
+  putreg32(BOARD_PMC_MCKR_FAST, SAM_PMC_MCKR);
+  sam_pmcwait(PMC_INT_MCKRDY);
+
+  putreg32(BOARD_PMC_MCKR, SAM_PMC_MCKR);
+  sam_pmcwait(PMC_INT_MCKRDY);
+}
+
+/****************************************************************************
+ * Name: sam_enabledefaultmaster and sam_disabledefaultmaster
+ *
+ * Description:
+ *   Enable/disable default master access
+ *
+ ****************************************************************************/
+
+static inline void sam_enabledefaultmaster(void)
+{
+#warning REVISIT
+#if 0 /* REVISIT -- this is stuff left over from SAM3/4 */
+  uint32_t regval;
+
+  /* Set default master: SRAM0 -> Cortex-M7 System */
+
+  regval  = getreg32(SAM_MATRIX_SCFG0);
+  regval |= (MATRIX_SCFG0_FIXEDDEFMSTR_ARMS|MATRIX_SCFG_DEFMSTRTYPE_FIXED);
+  putreg32(regval, SAM_MATRIX_SCFG0);
+
+  /* Set default master: SRAM1 -> Cortex-M7 System */
+
+  regval  = getreg32(SAM_MATRIX_SCFG1);
+  regval |= (MATRIX_SCFG1_FIXEDDEFMSTR_ARMS|MATRIX_SCFG_DEFMSTRTYPE_FIXED);
+  putreg32(regval, SAM_MATRIX_SCFG1);
+
+  /* Set default master: Internal flash0 -> Cortex-M7 Instruction/Data */
+
+  regval  = getreg32(SAM_MATRIX_SCFG3);
+  regval |= (MATRIX_SCFG3_FIXEDDEFMSTR_ARMC|MATRIX_SCFG_DEFMSTRTYPE_FIXED);
+  putreg32(regval, SAM_MATRIX_SCFG3);
+#endif
+}
+
+#if 0 /* Not used -- this is stuff left over from SAM3/4 */
+static inline void sam_disabledefaultmaster(void)
+{
+  uint32_t regval;
+
+  /* Clear default master: SRAM0 -> Cortex-M7 System */
+
+  regval  = getreg32(SAM_MATRIX_SCFG0);
+  regval &= ~MATRIX_SCFG_DEFMSTRTYPE_MASK;
+  putreg32(regval, SAM_MATRIX_SCFG0);
+
+  /* Clear default master: SRAM1 -> Cortex-M7 System */
+
+  regval  = getreg32(SAM_MATRIX_SCFG1);
+  regval &= ~MATRIX_SCFG_DEFMSTRTYPE_MASK;
+  putreg32(regval, SAM_MATRIX_SCFG1);
+
+  /* Clear default master: Internal flash0 -> Cortex-M7 Instruction/Data */
+
+  regval  = getreg32(SAM_MATRIX_SCFG3);
+  regval &= ~MATRIX_SCFG_DEFMSTRTYPE_MASK;
+  putreg32(regval, SAM_MATRIX_SCFG3);
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_clockconfig
+ *
+ * Description:
+ *   Called to initialize the SAM3/4.  This does whatever setup is needed
+ *   to put the SoC in a usable state.  This includes the initialization of
+ *   clocking using the settings in board.h.  (After power-on reset, the
+ *   SAMV7 is initially running on a 4MHz internal RC clock).  This function
+ *   also performs other low-level chip initialization of the chip including
+ *   EFC, master clock, IRQ & watchdog configuration.
+ *
+ ****************************************************************************/
+
+void sam_clockconfig(void)
+{
+  /* Configure embedded flash access */
+
+  sam_efcsetup();
+
+  /* Configure the watchdog timer */
+
+  sam_wdtsetup();
+
+  /* Setup the supply controller to use the external slow clock */
+
+  sam_supcsetup();
+
+  /* Initialize clocking */
+
+  sam_pmcsetup();
+
+  /* Optimize CPU setting for speed */
+
+  sam_enabledefaultmaster();
+}
diff --git a/nuttx/arch/arm/src/samv7/sam_start.c b/nuttx/arch/arm/src/samv7/sam_start.c
index 525399d06..d633fccef 100644
--- a/nuttx/arch/arm/src/samv7/sam_start.c
+++ b/nuttx/arch/arm/src/samv7/sam_start.c
@@ -324,6 +324,9 @@ void __start(void)
   sam_lowsetup();
   showprogress('A');
 
+  /* Enable I- and D-Caches */
+#warning Missing Logic
+
   /* Perform early serial initialization */
 
 #ifdef USE_EARLYSERIALINIT
diff --git a/nuttx/arch/arm/src/samv7/sam_timerisr.c b/nuttx/arch/arm/src/samv7/sam_timerisr.c
new file mode 100644
index 000000000..825be35e3
--- /dev/null
+++ b/nuttx/arch/arm/src/samv7/sam_timerisr.c
@@ -0,0 +1,148 @@
+/****************************************************************************
+ * arch/arm/src/samv7/sam_timerisr.c
+ *
+ *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <time.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+#include <arch/board/board.h>
+
+#include "nvic.h"
+#include "clock/clock.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+ /* Select MCU-specific settings
+ *
+ * The SysTick timer is driven by the output of the Mast Clock Controller
+ * prescaler output (i.e., the MDIV output divider is not applied so that
+ * the driving frequency is the same as the CPU frequency).
+ *
+ * The SysTick calibration value is fixed to 37500 which allows the generation
+ * of a time base of 1 ms with SysTick clock to the maximum frequency on
+ * MCK divided by 8. (?)
+ */
+
+#define SAM_SYSTICK_CLOCK  BOARD_CPU_FREQUENCY
+
+/* The desired timer interrupt frequency is provided by the definition
+ * CLK_TCK (see include/time.h).  CLK_TCK defines the desired number of
+ * system clock ticks per second.  That value is a user configurable setting
+ * that defaults to 100 (100 ticks per second = 10 MS interval).
+ */
+
+#define SYSTICK_RELOAD ((SAM_SYSTICK_CLOCK / CLK_TCK) - 1)
+
+/* The size of the reload field is 24 bits.  Verify that the reload value
+ * will fit in the reload register.
+ */
+
+#if SYSTICK_RELOAD > 0x00ffffff
+#  error SYSTICK_RELOAD exceeds the range of the RELOAD register
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Global Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function:  up_timerisr
+ *
+ * Description:
+ *   The timer ISR will perform a variety of services for various portions
+ *   of the systems.
+ *
+ ****************************************************************************/
+
+int up_timerisr(int irq, uint32_t *regs)
+{
+   /* Process timer interrupt */
+
+   sched_process_timer();
+   return 0;
+}
+
+/****************************************************************************
+ * Function:  up_timer_initialize
+ *
+ * Description:
+ *   This function is called during start-up to initialize the timer
+ *   interrupt.
+ *
+ ****************************************************************************/
+
+void up_timer_initialize(void)
+{
+  uint32_t regval;
+
+  /* Configure SysTick to interrupt at the requested rate */
+
+  putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
+  putreg32(0, NVIC_SYSTICK_CURRENT);
+
+  /* Attach the timer interrupt vector */
+
+  (void)irq_attach(SAM_IRQ_SYSTICK, (xcpt_t)up_timerisr);
+
+  /* Enable SysTick interrupts (no divide-by-8) */
+
+  regval = (NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT |
+            NVIC_SYSTICK_CTRL_ENABLE);
+  putreg32(regval, NVIC_SYSTICK_CTRL);
+
+  /* And enable the timer interrupt */
+
+  up_enable_irq(SAM_IRQ_SYSTICK);
+}
diff --git a/nuttx/configs/sam4e-ek/include/board.h b/nuttx/configs/sam4e-ek/include/board.h
index 9bc48258c..2a17c88de 100644
--- a/nuttx/configs/sam4e-ek/include/board.h
+++ b/nuttx/configs/sam4e-ek/include/board.h
@@ -51,7 +51,7 @@
 #endif
 
 /************************************************************************************
- * Definitions
+ * Pre-processor Definitions
  ************************************************************************************/
 
 /* Clocking *************************************************************************/
@@ -82,7 +82,7 @@
 /* PLLA configuration.
  *
  *   Divider = 1
- *   Multipler = 16 or 20
+ *   Multiplier = 16 or 20
  */
 
 #ifdef CONFIG_SAM4EEK_120MHZ
@@ -177,7 +177,7 @@
 
 /* FLASH wait states.
  *
- * SAM4E-EK documetion says:
+ * SAM4E-EK documentation says:
  * VDDCORE: "The voltage ranges from 1.08V to 1.32V."
  * VDDIO:   Looks like it is at 3.3V
  *
@@ -274,7 +274,8 @@
 #undef EXTERN
 #if defined(__cplusplus)
 #define EXTERN extern "C"
-extern "C" {
+extern "C"
+{
 #else
 #define EXTERN extern
 #endif
@@ -311,10 +312,10 @@ void sam_setleds(uint8_t ledset);
 #endif
 
 /************************************************************************************
- * Name:  stm32_lcdclear
+ * Name:  sam_lcdclear
  *
  * Description:
- *   This is a non-standard LCD interface just for the Shenzhou board.  Because
+ *   This is a non-standard LCD interface just for the SAM4e-EK board.  Because
  *   of the various rotations, clearing the display in the normal way by writing a
  *   sequences of runs that covers the entire display can be very slow.  Here the
  *   display is cleared by simply setting all GRAM memory to the specified color.
diff --git a/nuttx/configs/samv71-xult/include/board.h b/nuttx/configs/samv71-xult/include/board.h
index 1273487a5..c56e3278d 100644
--- a/nuttx/configs/samv71-xult/include/board.h
+++ b/nuttx/configs/samv71-xult/include/board.h
@@ -45,6 +45,129 @@
 /************************************************************************************
  * Pre-processor Definitions
  ************************************************************************************/
+/* Clocking *************************************************************************/
+/* After power-on reset, the SAMV71Q device is running out of the Master Clock using
+ * the Fast RC Oscillator running at 4 MHz.
+ *
+ *   MAINOSC:  Frequency = 12MHz (crystal)
+ *
+ * 300MHz Settings:
+ *   PLLA: PLL Divider = 1, Multiplier = 20 to generate PLLACK = 240MHz
+ *   Master Clock (MCK): Source = PLLACK, Prescalar = 1 to generate MCK = 120MHz
+ *   CPU clock: 120MHz
+ *
+ */
+
+/* Main oscillator register settings.
+ *
+ * The main oscillator could be either the embedded 4/8/12 MHz fast RC oscillators
+ * or an external 3-20 MHz crystal or ceramic resonator.  The external clock source
+ * is selected by default in sam_clockconfig.c.  Here we need to specify the main
+ * oscillator start-up time.
+ *
+ * REVISIT... this is old information:
+ * The start up time should be should be:
+ *
+ *   Start Up Time = 8 * MOSCXTST / SLCK = 56 Slow Clock Cycles.
+ */
+
+#define BOARD_CKGR_MOR_MOSCXTST    (62 << PMC_CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */
+
+/* PLLA configuration.
+ *
+ *   Divider = 1
+ *   Multiplier = 25
+ *
+ * Yields:
+ *
+ *   PLLACK = 25 * 12MHz / 1 = 300MHz
+ */
+
+#define BOARD_CKGR_PLLAR_STMODE    PMC_CKGR_PLLAR_STMODE_FAST
+#define BOARD_CKGR_PLLAR_COUNT     (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
+#define BOARD_CKGR_PLLAR_MUL       PMC_CKGR_PLLAR_MUL(25)
+#define BOARD_CKGR_PLLAR_DIV       PMC_CKGR_PLLAR_DIV_BYPASS
+
+/* PMC master clock register settings.
+ *
+ *  BOARD_PMC_MCKR_CSS - The source of main clock input.  This may be one of:
+ *
+ *    PMC_MCKR_CSS_SLOW   Slow Clock
+ *    PMC_MCKR_CSS_MAIN   Main Clock
+ *    PMC_MCKR_CSS_PLLA   PLLA Clock
+ *    MC_MCKR_CSS_UPLL    Divided UPLL Clock
+ *
+ *  BOARD_PMC_MCKR_PRES - Source clock pre-scaler.  May be one of:
+ *
+ *    PMC_MCKR_PRES_DIV1  Selected clock
+ *    PMC_MCKR_PRES_DIV2  Selected clock divided by 2
+ *    PMC_MCKR_PRES_DIV4  Selected clock divided by 4
+ *    PMC_MCKR_PRES_DIV8  Selected clock divided by 8
+ *    PMC_MCKR_PRES_DIV16 Selected clock divided by 16
+ *    MC_MCKR_PRES_DIV32  Selected clock divided by 32
+ *    PMC_MCKR_PRES_DIV64 Selected clock divided by 64
+ *    PMC_MCKR_PRES_DIV3  Selected clock divided by 3
+ *
+ *  The prescaler determines (1) the CPU clock and (2) the input into the
+ *  second divider that then generates the Master Clock (MCK).  MCK is the
+ *  source clock of the peripheral clocks.
+ *
+ *  BOARD_PMC_MCKR_MDIV - MCK divider.  May be one of:
+ *
+ *    PMC_MCKR_MDIV_DIV1  Master Clock is Prescaler Output Clock / 1
+ *    PMC_MCKR_MDIV_DIV2  Master Clock = Prescaler Output Clock / 2
+ *    PMC_MCKR_MDIV_DIV4  Master Clock = Prescaler Output Clock / 4
+ *    PMC_MCKR_MDIV_DIV3  Master Clock = Prescaler Output Clock / 3
+ */
+
+#define BOARD_PMC_MCKR_CSS         PMC_MCKR_CSS_PLLA   /* Source = PLLA */
+#define BOARD_PMC_MCKR_PRES        PMC_MCKR_PRES_DIV1  /* Prescaler = /1 */
+#define BOARD_PMC_MCKR_MDIV        PMC_MCKR_MDIV_DIV2  /* MCK divider = /2 */
+
+/* USB clocking
+ * To be provided
+ */
+
+#define BOARD_PMC_MCKR_UPLLDIV2    0           /* UPLL clock not divided by 2 */
+
+/* Resulting frequencies */
+
+#define BOARD_MAINOSC_FREQUENCY    (12000000)  /* MAINOSC: 12MHz crystal on-board */
+#define BOARD_PLLA_FREQUENCY       (300000000) /* PLLACK:  25 * 12Mhz / 1 */
+#define BOARD_CPU_FREQUENCY        (300000000) /* CPU:     PLLACK / 1 */
+#define BOARD_MCK_FREQUENCY        (150000000) /* MCK:     PLLACK / 1 / 2 */
+
+/* HSMCI clocking
+ *
+ * Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)
+ * divided by (2*(CLKDIV+1)).
+ *
+ *   MCI_SPEED = MCK / (2*(CLKDIV+1))
+ *   CLKDIV = MCK / MCI_SPEED / 2 - 1
+ *
+ * Where CLKDIV has a range of 0-255.
+ */
+
+/* FLASH wait states.
+ *
+ * Wait states Max frequency at 105 centigrade (STH conditions)
+ *
+ *           VDDIO
+ *       1.62V     2.7V
+ * --- -------  -------
+ *  0   26 MHz   30 MHz
+ *  1   52 MHz   62 MHz
+ *  2   78 MHz   93 MHz
+ *  3  104 MHz  124 MHz
+ *  4  131 MHz  150 MHz
+ *  5  150 MHz  --- MHz
+ */
+
+#define BOARD_FWS                  5
+
+/* LED definitions ******************************************************************/
+
+/* Button definitions ***************************************************************/
 
 /************************************************************************************
  * Public Types
@@ -54,8 +177,58 @@
  * Public Data
  ************************************************************************************/
 
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
 /************************************************************************************
  * Public Functions
  ************************************************************************************/
 
+ /************************************************************************************
+ * Name:  sam_ledinit, sam_setled, and sam_setleds
+ *
+ * Description:
+ *   If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board LEDs.  If
+ *   CONFIG_ARCH_LEDS is not defined, then the following interfacesare available to
+ *   control the LEDs from user applications.
+ *
+ ************************************************************************************/
+
+#ifndef CONFIG_ARCH_LEDS
+void sam_ledinit(void);
+void sam_setled(int led, bool ledon);
+void sam_setleds(uint8_t ledset);
+#endif
+
+/************************************************************************************
+ * Name:  sam_lcdclear
+ *
+ * Description:
+ *   This is a non-standard LCD interface just for the SAM4e-EK board.  Because
+ *   of the various rotations, clearing the display in the normal way by writing a
+ *   sequences of runs that covers the entire display can be very slow.  Here the
+ *   display is cleared by simply setting all GRAM memory to the specified color.
+ *
+ ************************************************************************************/
+
+#if defined(CONFIG_SAM4EEK_LCD_RGB565)
+void sam_lcdclear(uint16_t color);
+#else /* if defined(CONFIG_SAM4EEK_LCD_RGB24) defined(CONFIG_SAM4EEK_LCD_RGB32) */
+void sam_lcdclear(uint32_t color);
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
 #endif /* __CONFIGS_SAMV71_XULT_INCLUDE_BOARD_H */