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authorpatacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>2012-04-16 21:13:54 +0000
committerpatacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>2012-04-16 21:13:54 +0000
commit4182100cbbfd9439071369ae2cbdb36d4679cc2e (patch)
tree5abb85a3671a4848e95a6a07a3fe4e8886c7632f /nuttx
parent2652ddc81dd82bdcd788beffd73455802134c6b8 (diff)
downloadpx4-nuttx-4182100cbbfd9439071369ae2cbdb36d4679cc2e.tar.gz
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STM32 IWDG watchdog works
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4619 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx')
-rw-r--r--nuttx/arch/arm/src/stm32/stm32_iwdg.c214
-rw-r--r--nuttx/arch/arm/src/stm32/stm32_lsi.c10
-rw-r--r--nuttx/arch/arm/src/stm32/stm32_wwdg.c18
-rwxr-xr-xnuttx/configs/stm32f4discovery/README.txt10
4 files changed, 197 insertions, 55 deletions
diff --git a/nuttx/arch/arm/src/stm32/stm32_iwdg.c b/nuttx/arch/arm/src/stm32/stm32_iwdg.c
index e2d08cfec..908851302 100644
--- a/nuttx/arch/arm/src/stm32/stm32_iwdg.c
+++ b/nuttx/arch/arm/src/stm32/stm32_iwdg.c
@@ -42,8 +42,10 @@
#include <stdint.h>
#include <errno.h>
+#include <debug.h>
#include <nuttx/watchdog.h>
+#include <arch/board/board.h>
#include "up_arch.h"
#include "stm32_rcc.h"
@@ -55,12 +57,39 @@
/****************************************************************************
* Pre-Processor Definitions
****************************************************************************/
+/* Clocking *****************************************************************/
+/* The minimum frequency of the IWDG clock is:
+ *
+ * Fmin = Flsi / 256
+ *
+ * So the maximum delay (in milliseconds) is then:
+ *
+ * 1000 * IWDG_RLR_MAX / Fmin
+ *
+ * For example, if Flsi = 30Khz (the nominal, uncalibrathed value), then the
+ * maximum delay is:
+ *
+ * Fmin = 117.1875
+ * 1000 * 4095 / Fmin = 34,944 MSec
+ */
+
+#define IWDG_FMIN (STM32_LSI_FREQUENCY / 256)
+#define IWDG_MAXTIMEOUT (1000 * IWDG_RLR_MAX / IWDG_FMIN)
+
/* Configuration ************************************************************/
#ifndef CONFIG_STM32_IWDG_DEFTIMOUT
-# define CONFIG_STM32_IWDG_DEFTIMOUT 3000 /* Three seconds */
+# define CONFIG_STM32_IWDG_DEFTIMOUT IWDG_MAXTIMEOUT
#endif
+/* REVISIT: It appears that you can only setup the prescaler and reload
+ * registers once. After that, the SR register's PVU and RVU bits never go
+ * to zero. So we defer setting up these registers until the watchdog
+ * is started, then refuse any further attempts to change timeout.
+ */
+
+#define CONFIG_STM32_IWDG_ONETIMESETUP 1
+
/* Debug ********************************************************************/
/* Non-standard debug that may be enabled just for testing the watchdog
* driver. NOTE: that only lldbg types are used so that the output is
@@ -99,13 +128,15 @@ struct stm32_lowerhalf_s
/* Register operations ******************************************************/
#if defined(CONFIG_STM32_IWDG_REGDEBUG) && defined(CONFIG_DEBUG)
-static uint32_t stm32_getreg(uint32_t addr);
-static void stm32_putreg(uint32_t val, uint32_t addr);
+static uint16_t stm32_getreg(uint32_t addr);
+static void stm32_putreg(uint16_t val, uint32_t addr);
#else
# define stm32_getreg(addr) getreg16(addr)
# define stm32_putreg(val,addr) putreg16(val,addr)
#endif
+static inline void stm32_setprescaler(FAR struct stm32_lowerhalf_s *priv);
+
/* "Lower half" driver methods **********************************************/
static int stm32_start(FAR struct watchdog_lowerhalf_s *lower);
@@ -224,13 +255,58 @@ static void stm32_putreg(uint16_t val, uint32_t addr)
#endif
/****************************************************************************
+ * Name: stm32_setprescaler
+ *
+ * Description:
+ * Set up the prescaler and reload values. This seems to be something
+ * that can only be done one time.
+ *
+ * Input Parameters:
+ * priv - A pointer the internal representation of the "lower-half"
+ * driver state structure.
+ * timeout - The new timeout value in millisecnds.
+ *
+ * Returned Values:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static inline void stm32_setprescaler(FAR struct stm32_lowerhalf_s *priv)
+{
+ /* Enable write access to IWDG_PR and IWDG_RLR registers */
+
+ stm32_putreg(IWDG_KR_KEY_ENABLE, STM32_IWDG_KR);
+
+ /* Wait for the PVU anrd RVU bit to be reset be hardware. These bits
+ * were set the last time that the PR register was written and may not
+ * yet be cleared.
+ */
+
+#ifndef CONFIG_STM32_IWDG_ONETIMESETUP
+ while ((stm32_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU|IWDG_SR_RVU)) != 0);
+#endif
+
+ /* Set the prescaler */
+
+ stm32_putreg((uint16_t)priv->prescaler << IWDG_PR_SHIFT, STM32_IWDG_PR);
+
+ /* Set the reload value */
+
+ stm32_putreg((uint16_t)priv->reload, STM32_IWDG_RLR);
+
+ /* Reload the counter (and disable write access) */
+
+ stm32_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR);
+}
+
+/****************************************************************************
* Name: stm32_start
*
* Description:
* Start the watchdog timer, resetting the time to the current timeout,
*
* Input Parameters:
- * lower - A pointer the publicly visible representation of the "lower
+ * lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
* Returned Values:
@@ -242,19 +318,33 @@ static int stm32_start(FAR struct watchdog_lowerhalf_s *lower)
{
FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)lower;
+ wdvdbg("Entry: started=%d\n");
DEBUGASSERT(priv);
- /* Reload IWDG counter */
+ /* Have we already been started? */
- stm32_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR);
+ if (!priv->started)
+ {
+ /* REVISIT: It appears that you can only setup the prescaler and reload
+ * registers once. After that, the SR register's PVU and RVU bits never go
+ * to zero. So we defer setting up these registers until the watchdog
+ * is started, then refuse any further attempts to change timeout.
+ */
- /* Enable IWDG (the LSI oscillator will be enabled by hardware). NOTE:
- * If the "Hardware watchdog" feature is enabled through the device option
- * bits, the watchdog is automatically enabled at power-on.
- */
+ /* Set up prescaler and reload value for the selected timeout */
+
+#ifdef CONFIG_STM32_IWDG_ONETIMESETUP
+ stm32_setprescaler(priv);
+#endif
+
+ /* Enable IWDG (the LSI oscillator will be enabled by hardware). NOTE:
+ * If the "Hardware watchdog" feature is enabled through the device option
+ * bits, the watchdog is automatically enabled at power-on.
+ */
- stm32_putreg(IWDG_KR_KEY_START, STM32_IWDG_KR);
- priv->started = true;
+ stm32_putreg(IWDG_KR_KEY_START, STM32_IWDG_KR);
+ priv->started = true;
+ }
return OK;
}
@@ -265,7 +355,7 @@ static int stm32_start(FAR struct watchdog_lowerhalf_s *lower)
* Stop the watchdog timer
*
* Input Parameters:
- * lower - A pointer the publicly visible representation of the "lower
+ * lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
* Returned Values:
@@ -277,6 +367,7 @@ static int stm32_stop(FAR struct watchdog_lowerhalf_s *lower)
{
/* There is no way to disable the IDWG timer once it has been started */
+ wdvdbg("Entry\n");
return -ENOSYS;
}
@@ -289,7 +380,7 @@ static int stm32_stop(FAR struct watchdog_lowerhalf_s *lower)
* the atchdog timer or "petting the dog".
*
* Input Parameters:
- * lower - A pointer the publicly visible representation of the "lower
+ * lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
* Returned Values:
@@ -301,6 +392,7 @@ static int stm32_keepalive(FAR struct watchdog_lowerhalf_s *lower)
{
/* Reload the IWDG timer */
+ wdvdbg("Entry\n");
stm32_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR);
return OK;
}
@@ -312,7 +404,7 @@ static int stm32_keepalive(FAR struct watchdog_lowerhalf_s *lower)
* Get the current watchdog timer status
*
* Input Parameters:
- * lower - A pointer the publicly visible representation of the "lower
+ * lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
* stawtus - The location to return the watchdog status information.
*
@@ -328,6 +420,7 @@ static int stm32_getstatus(FAR struct watchdog_lowerhalf_s *lower,
uint32_t elapsed;
uint16_t reload;
+ wdvdbg("Entry\n");
DEBUGASSERT(priv);
/* Return the status bit */
@@ -350,6 +443,11 @@ static int stm32_getstatus(FAR struct watchdog_lowerhalf_s *lower,
reload = stm32_getreg(STM32_IWDG_RLR);
elapsed = priv->reload - reload;
status->timeleft = (priv->timeout * elapsed) / priv->reload;
+
+ wdvdbg("Status :\n");
+ wdvdbg(" flags : %08x\n", status->flags);
+ wdvdbg(" timeout : %d\n", status->timeout);
+ wdvdbg(" timeleft : %d\n", status->flags);
return OK;
}
@@ -360,7 +458,7 @@ static int stm32_getstatus(FAR struct watchdog_lowerhalf_s *lower,
* Set a new timeout value (and reset the watchdog timer)
*
* Input Parameters:
- * lower - A pointer the publicly visible representation of the "lower
+ * lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
* timeout - The new timeout value in millisecnds.
*
@@ -373,18 +471,41 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
uint32_t timeout)
{
FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)lower;
- uint32_t frequency;
+ uint32_t fiwdg;
uint64_t reload;
- int pr;
+ int prescaler;
int shift;
+ wdvdbg("Entry: timeout=%d\n", timeout);
DEBUGASSERT(priv);
+ /* Can this timeout be represented? */
+
+ if (timeout < 1 || timeout > IWDG_MAXTIMEOUT)
+ {
+ wddbg("Cannot represent timeout=%d > %d\n",
+ timeout, IWDG_MAXTIMEOUT);
+ return -ERANGE;
+ }
+
+ /* REVISIT: It appears that you can only setup the prescaler and reload
+ * registers once. After that, the SR register's PVU and RVU bits never go
+ * to zero.
+ */
+
+#ifdef CONFIG_STM32_IWDG_ONETIMESETUP
+ if (priv->started)
+ {
+ wddbg("Timer is already started\n");
+ return -EBUSY;
+ }
+#endif
+
/* Select the smallest prescaler that will result in a reload value that is
* less than the maximum.
*/
- for (pr = 0; ; pr++)
+ for (prescaler = 0; ; prescaler++)
{
/* PR = 0 -> Divider = 4 = 1 << 2
* PR = 1 -> Divider = 8 = 1 << 3
@@ -396,32 +517,32 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
* PR = n -> Divider = 1 << (n+2)
*/
- shift = pr + 2;
+ shift = prescaler + 2;
/* Get the IWDG counter frequency in Hz. For a nominal 32Khz LSI clock,
* this is value in the range of 7500 and 125.
*/
- frequency = priv->lsifreq >> shift;
+ fiwdg = priv->lsifreq >> shift;
/* We want:
- * 1000 * reload / frequency = timeout
+ * 1000 * reload / Fiwdg = timeout
* Or:
- * reload = frequency * timeout / 1000
+ * reload = Fiwdg * timeout / 1000
*/
- reload = (uint64_t)frequency * (uint64_t)timeout / 1000;
+ reload = (uint64_t)fiwdg * (uint64_t)timeout / 1000;
/* If this reload valid is less than the maximum or we are not ready
* at the prescaler value, then break out of the loop to use these
* settings.
*/
- if (reload <= IWDG_RLR_MAX || pr == 6)
+ if (reload <= IWDG_RLR_MAX || prescaler == 6)
{
/* Note that we explicity break out of the loop rather than using
* the 'for' loop termination logic because we do not want the
- * value of pr to be incremented.
+ * value of prescaler to be incremented.
*/
break;
@@ -435,33 +556,35 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
reload = IWDG_RLR_MAX;
}
- /* Enable write access to IWDG_PR and IWDG_RLR registers */
-
- stm32_putreg(IWDG_KR_KEY_ENABLE, STM32_IWDG_KR);
-
- /* Set the prescaler */
-
- stm32_putreg((uint16_t)pr << IWDG_PR_SHIFT, STM32_IWDG_PR);
-
- /* Set the reload value */
-
- stm32_putreg((uint16_t)reload, STM32_IWDG_RLR);
-
/* Get the actual timeout value in milliseconds.
*
* We have:
- * reload = frequency * timeout / 1000
+ * reload = Fiwdg * timeout / 1000
* So we want:
- * timeout = 1000 * reload / frequency
+ * timeout = 1000 * reload / Fiwdg
*/
- priv->timeout = (1000 * reload) / frequency;
+ priv->timeout = (1000 * (uint32_t)reload) / fiwdg;
/* Save setup values for later use */
- priv->prescaler = pr; /* Not needed */
+ priv->prescaler = prescaler;
priv->reload = reload;
+ /* Write the prescaler and reload values to the IWDG registers.
+ *
+ * REVISIT: It appears that you can only setup the prescaler and reload
+ * registers once. After that, the SR register's PVU and RVU bits never go
+ * to zero.
+ */
+
+#ifndef CONFIG_STM32_IWDG_ONETIMESETUP
+ stm32_setprescaler(priv);
+#endif
+
+ wdvdbg("prescaler=%d fiwdg=%d reload=%d timeout=%d\n",
+ prescaler, fiwdg, reload, priv->timeout);
+
return OK;
}
@@ -491,15 +614,17 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
{
FAR struct stm32_lowerhalf_s *priv = &g_wdgdev;
+ wdvdbg("Entry: devpath=%s lsifreq=%d\n", devpath, lsifreq);
+
/* NOTE we assume that clocking to the IWDG has already been provided by
* the RCC initialization logic.
*/
/* Initialize the driver state structure. */
- priv->ops = &g_wdgops;
+ priv->ops = &g_wdgops;
priv->lsifreq = lsifreq;
- priv->lsifreq = false;
+ priv->started = false;
/* Make sure that the LSI ocsillator is enabled. NOTE: The LSI oscillator
* is enabled here but is not disabled by this file (because this file does
@@ -509,6 +634,7 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
*/
stm32_rcc_enablelsi();
+ wdvdbg("RCC CSR: %08x\n", getreg32(STM32_RCC_CSR));
/* Select an arbitrary initial timeout value. But don't start the watchdog
* yet. NOTE: If the "Hardware watchdog" feature is enabled through the
diff --git a/nuttx/arch/arm/src/stm32/stm32_lsi.c b/nuttx/arch/arm/src/stm32/stm32_lsi.c
index fe7dd0194..e365fbf06 100644
--- a/nuttx/arch/arm/src/stm32/stm32_lsi.c
+++ b/nuttx/arch/arm/src/stm32/stm32_lsi.c
@@ -73,7 +73,11 @@ void stm32_rcc_enablelsi(void)
* the RCC CSR register.
*/
- modifyreg16(STM32_RCC_CSR, 0, RCC_CSR_LSION);
+ modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION);
+
+ /* Wait for the internal RC 40 kHz oscillator to be stable. */
+
+ while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0);
}
/****************************************************************************
@@ -90,5 +94,7 @@ void stm32_rcc_disablelsi(void)
* the RCC CSR register.
*/
- modifyreg16(STM32_RCC_CSR, RCC_CSR_LSION, 0);
+ modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0);
+
+ /* LSIRDY should go low after 3 LSI clock cycles */
}
diff --git a/nuttx/arch/arm/src/stm32/stm32_wwdg.c b/nuttx/arch/arm/src/stm32/stm32_wwdg.c
index 3272d569a..4506fa4e0 100644
--- a/nuttx/arch/arm/src/stm32/stm32_wwdg.c
+++ b/nuttx/arch/arm/src/stm32/stm32_wwdg.c
@@ -57,7 +57,7 @@
* Pre-Processor Definitions
****************************************************************************/
/* Clocking *****************************************************************/
-/* The minimum frequency of the WWD clock is:
+/* The minimum frequency of the WWDG clock is:
*
* Fmin = PCLK1 / 4096 / 8
*
@@ -334,7 +334,7 @@ static int stm32_interrupt(int irq, FAR void *context)
* Start the watchdog timer, resetting the time to the current timeout,
*
* Input Parameters:
- * lower - A pointer the publicly visible representation of the "lower
+ * lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
* Returned Values:
@@ -366,7 +366,7 @@ static int stm32_start(FAR struct watchdog_lowerhalf_s *lower)
* Stop the watchdog timer
*
* Input Parameters:
- * lower - A pointer the publicly visible representation of the "lower
+ * lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
* Returned Values:
@@ -400,7 +400,7 @@ static int stm32_stop(FAR struct watchdog_lowerhalf_s *lower)
* 0xff and 0xC0:
*
* Input Parameters:
- * lower - A pointer the publicly visible representation of the "lower
+ * lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
* Returned Values:
@@ -430,7 +430,7 @@ static int stm32_keepalive(FAR struct watchdog_lowerhalf_s *lower)
* Get the current watchdog timer status
*
* Input Parameters:
- * lower - A pointer the publicly visible representation of the "lower
+ * lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
* stawtus - The location to return the watchdog status information.
*
@@ -486,7 +486,7 @@ static int stm32_getstatus(FAR struct watchdog_lowerhalf_s *lower,
* Set a new timeout value (and reset the watchdog timer)
*
* Input Parameters:
- * lower - A pointer the publicly visible representation of the "lower
+ * lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
* timeout - The new timeout value in millisecnds.
*
@@ -583,7 +583,7 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
/* Calculate and save the actual timeout value in milliseconds:
*
- * timeout = 1000 * (reload + 1) / Fwwdg, OR
+ * timeout = 1000 * (reload + 1) / Fwwdg
*/
priv->timeout = 1000 * (reload + 1) / fwwdg;
@@ -620,7 +620,7 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
* behavior.
*
* Input Parameters:
- * lower - A pointer the publicly visible representation of the "lower
+ * lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
* newhandler - The new watchdog expiration function pointer. If this
* function pointer is NULL, then the the reset-on-expiration
@@ -687,7 +687,7 @@ static xcpt_t stm32_capture(FAR struct watchdog_lowerhalf_s *lower,
* are forwarded to the lower half driver through this method.
*
* Input Parameters:
- * lower - A pointer the publicly visible representation of the "lower
+ * lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
* cmd - The ioctol command value
* arg - The optional argument that accompanies the 'cmd'. The
diff --git a/nuttx/configs/stm32f4discovery/README.txt b/nuttx/configs/stm32f4discovery/README.txt
index 1ad1a2e0b..e4a676f44 100755
--- a/nuttx/configs/stm32f4discovery/README.txt
+++ b/nuttx/configs/stm32f4discovery/README.txt
@@ -843,3 +843,13 @@ Where <subdir> is one of the following:
CONFIG_WATCHDOG=y : Enables watchdog timer driver support
CONFIG_STM32_WWDG=y : Enables the WWDG timer facility, OR
CONFIG_STM32_IWDG=y : Enables the IWDG timer facility (but not both)
+
+ The WWDG watchdog is driven off the (fast) 42MHz PCLK1 and, as result,
+ has a maximum timout value of 49 milliseconds. for WWDG watchdog, you
+ should also add the fillowing to the configuration file:
+
+ CONFIG_EXAMPLES_WATCHDOG_PINGDELAY=20
+ CONFIG_EXAMPLES_WATCHDOG_TIMEOUT=49
+
+ The IWDG timer has a range of about 35 seconds and should not be an issue.
+