Add Nuvoton chip selection logic

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5656 42af7a65-404d-4744-a932-0658087f49c3

5 files changed, 641 insertions, 6 deletions

diff --git a/nuttx/arch/arm/Kconfig b/nuttx/arch/arm/Kconfig
index d47218ef6..f25b68981 100644
--- a/nuttx/arch/arm/Kconfig
+++ b/nuttx/arch/arm/Kconfig
@@ -96,8 +96,8 @@ config ARCH_CHIP_LPC43XX
 	---help---
 		NPX LPC43XX architectures (ARM Cortex-M4).
 
-config ARCH_CHIP_NUC120
-	bool "Nuvoton NUC120"
+config ARCH_CHIP_NUC1XX
+	bool "Nuvoton NUC100/120"
 	select ARCH_CORTEXM0
 	select ARCH_HAVE_CMNVECTOR
 	---help---
@@ -167,7 +167,7 @@ config ARCH_CHIP
 	default "lpc2378"	if ARCH_CHIP_LPC2378
 	default "lpc31xx"	if ARCH_CHIP_LPC31XX
 	default "lpc43xx"	if ARCH_CHIP_LPC43XX
-	default "nuc1xx"	if ARCH_CHIP_NUC120
+	default "nuc1xx"	if ARCH_CHIP_NUC1XX
 	default "sam3u"		if ARCH_CHIP_SAM3U
 	default "stm32"		if ARCH_CHIP_STM32
 	default "str71x"	if ARCH_CHIP_STR71X
@@ -318,7 +318,7 @@ endif
 if ARCH_CHIP_LPC43XX
 source arch/arm/src/lpc43xx/Kconfig
 endif
-if ARCH_CHIP_NUC120
+if ARCH_CHIP_NUC1XX
 source arch/arm/src/nuc1xx/Kconfig
 endif
 if ARCH_CHIP_SAM3U
diff --git a/nuttx/arch/arm/include/nuc1xx/chip.h b/nuttx/arch/arm/include/nuc1xx/chip.h
index 3c4b29f1d..0cf2c89b8 100644
--- a/nuttx/arch/arm/include/nuc1xx/chip.h
+++ b/nuttx/arch/arm/include/nuc1xx/chip.h
@@ -46,6 +46,490 @@
 /************************************************************************************
  * Pre-processor Definitions
  ************************************************************************************/
+/* Chip capabilities ****************************************************************/
+/* NUC100 Advanced Line (Low Density) */
+
+#if defined(CONFIG_ARCH_CHIP_NUC100LC1BN) /* Flash 32K SRAM 4K, LQFP48 package */
+#  define NUC_FLASH  (32*1024)  /* 32K FLASH */
+#  define NUC_SRAM   (4*1024)   /* 4K SRAM */
+#  define NUC_NIO     35        /* (35) GPIO */
+#  define NUC_NTIMERS 4         /* 4x32-bit Timers */
+#  define NUC_NPDMA   1         /* 1 PDMA channels */
+#  define NUC_NUARTS  2         /* (2) UARTs */
+#  define NUC_NSPI    1         /* (1) SPI */
+#  define NUC_NI2C    2         /* (2) I2C */
+#  define NUC_NUSB    0         /* No USB */
+#  define NUC_NLIN    0         /* No LIN */
+#  define NUC_NCAN    0         /* No CAN */
+#  define NUC_NI2S    1         /* (1) I2S */
+#  define NUC_NCOMP   1         /* (1) Analog Comparator */
+#  define NUC_NPWM    4         /* (4) PWM */
+#  define NUC_NADC    8         /* 8x12-bit ADC */
+#  define NUC_RTC     1         /* RTC */
+#  undef  NUC_EBI               /* No EBI */
+#elif defined(CONFIG_ARCH_CHIP_NUC100LD1BN) /* Flash 64K SRAM 4K, LQFP48 package */
+#  define NUC_FLASH  (64*1024)  /* 64K FLASH */
+#  define NUC_SRAM   (4*1024)   /* 4K SRAM */
+#  define NUC_NIO     31        /* (35) GPIO */
+#  define NUC_NTIMERS 4         /* 4x32-bit Timers */
+#  define NUC_NPDMA   1         /* 1 PDMA channels */
+#  define NUC_NUARTS  2         /* (2) UARTs */
+#  define NUC_NSPI    1         /* (1) SPI */
+#  define NUC_NI2C    2         /* (2) I2C */
+#  define NUC_NUSB    0         /* No USB */
+#  define NUC_NLIN    0         /* No LIN */
+#  define NUC_NCAN    0         /* No CAN */
+#  define NUC_NI2S    1         /* (1) I2S */
+#  define NUC_NCOMP   1         /* (1) Analog Comparator */
+#  define NUC_NPWM    4         /* (4) PWM */
+#  define NUC_NADC    8         /* 8x12-bit ADC */
+#  define NUC_RTC     1         /* RTC */
+#  undef  NUC_EBI               /* No EBI */
+#elif defined(CONFIG_ARCH_CHIP_NUC100LD2BN) /* Flash 64K SRAM 8K, LQFP48 package */
+#  define NUC_FLASH  (64*1024)  /* 64K FLASH */
+#  define NUC_SRAM   (8*1024)   /* 8K SRAM */
+#  define NUC_NIO     31        /* (35) GPIO */
+#  define NUC_NTIMERS 4         /* 4x32-bit Timers */
+#  define NUC_NPDMA   1         /* 1 PDMA channels */
+#  define NUC_NUARTS  2         /* (2) UARTs */
+#  define NUC_NSPI    1         /* (1) SPI */
+#  define NUC_NI2C    2         /* (2) I2C */
+#  define NUC_NUSB    0         /* No USB */
+#  define NUC_NLIN    0         /* No LIN */
+#  define NUC_NCAN    0         /* No CAN */
+#  define NUC_NI2S    1         /* (1) I2S */
+#  define NUC_NCOMP   1         /* (1) Analog Comparator */
+#  define NUC_NPWM    4         /* (4) PWM */
+#  define NUC_NADC    8         /* 8x12-bit ADC */
+#  define NUC_RTC     1         /* RTC */
+#  undef  NUC_EBI               /* No EBI */
+#elif defined(CONFIG_ARCH_CHIP_NUC100RC1BN) /* Flash 32K SRAM 4K, LQFP64 package */
+#  define NUC_FLASH  (32*1024)  /* 32K FLASH */
+#  define NUC_SRAM   (4*1024)   /* 4K SRAM */
+#  define NUC_NIO     49        /* (49) GPIO */
+#  define NUC_NTIMERS 4         /* 4x32-bit Timers */
+#  define NUC_NPDMA   1         /* 1 PDMA channels */
+#  define NUC_NUARTS  2         /* (2) UARTs */
+#  define NUC_NSPI    2         /* (2) SPI */
+#  define NUC_NI2C    2         /* (2) I2C */
+#  define NUC_NUSB    0         /* No USB */
+#  define NUC_NLIN    0         /* No LIN */
+#  define NUC_NCAN    0         /* No CAN */
+#  define NUC_NI2S    1         /* (1) I2S */
+#  define NUC_NCOMP   2         /* (2) Analog Comparators */
+#  define NUC_NPWM    4         /* (4) PWM */
+#  define NUC_NADC    8         /* 8x12-bit ADC */
+#  define NUC_RTC     1         /* RTC */
+#  define NUC_EBI     1         /* Supports EBI */
+#elif defined(CONFIG_ARCH_CHIP_NUC100RD1BN) /* Flash 64K SRAM 4K, LQFP64 package */
+#  define NUC_FLASH  (64*1024)  /* 64K FLASH */
+#  define NUC_SRAM   (4*1024)   /* 4K SRAM */
+#  define NUC_NIO     49        /* (49) GPIO */
+#  define NUC_NTIMERS 4         /* 4x32-bit Timers */
+#  define NUC_NPDMA   1         /* 1 PDMA channels */
+#  define NUC_NUARTS  2         /* (2) UARTs */
+#  define NUC_NSPI    2         /* (2) SPI */
+#  define NUC_NI2C    2         /* (2) I2C */
+#  define NUC_NUSB    0         /* No USB */
+#  define NUC_NLIN    0         /* No LIN */
+#  define NUC_NCAN    0         /* No CAN */
+#  define NUC_NI2S    1         /* (1) I2S */
+#  define NUC_NCOMP   2         /* (2) Analog Comparators */
+#  define NUC_NPWM    4         /* (4) PWM */
+#  define NUC_NADC    8         /* 8x12-bit ADC */
+#  define NUC_RTC     1         /* RTC */
+#  define NUC_EBI     1         /* Supports EBI */
+#elif defined(CONFIG_ARCH_CHIP_NUC100RD2BN) /* Flash 64K SRAM 8K, LQFP64 package */
+#  define NUC_FLASH  (64*1024)  /* 64K FLASH */
+#  define NUC_SRAM   (8*1024)   /* 4K SRAM */
+#  define NUC_NIO     49        /* (49) GPIO */
+#  define NUC_NTIMERS 4         /* 4x32-bit Timers */
+#  define NUC_NPDMA   1         /* 1 PDMA channels */
+#  define NUC_NUARTS  2         /* (2) UARTs */
+#  define NUC_NSPI    2         /* (2) SPI */
+#  define NUC_NI2C    2         /* (2) I2C */
+#  define NUC_NUSB    0         /* No USB */
+#  define NUC_NLIN    0         /* No LIN */
+#  define NUC_NCAN    0         /* No CAN */
+#  define NUC_NI2S    1         /* (1) I2S */
+#  define NUC_NCOMP   2         /* (2) Analog Comparators */
+#  define NUC_NPWM    4         /* (4) PWM */
+#  define NUC_NADC    8         /* 8x12-bit ADC */
+#  define NUC_RTC     1         /* RTC */
+#  define NUC_EBI     1         /* Supports EBI */
+
+/* NUC100 Advanced Line (Medium Density) */
+
+#elif defined(CONFIG_ARCH_CHIP_NUC100LD3AN) /* Flash 64K SRAM 16K, LQFP48 package */
+#  define NUC_FLASH  (64*1024)  /* 64K FLASH */
+#  define NUC_SRAM   (16*1024)  /* 16K SRAM */
+#  define NUC_NIO     35        /* (35) GPIO */
+#  define NUC_NTIMERS 4         /* 4x32-bit Timers */
+#  define NUC_NPDMA   9         /* 9 PDMA channels */
+#  define NUC_NUARTS  2         /* (2) UARTs */
+#  define NUC_NSPI    1         /* (1) SPI */
+#  define NUC_NI2C    2         /* (2) I2C */
+#  define NUC_NUSB    0         /* No USB */
+#  define NUC_NLIN    0         /* No LIN */
+#  define NUC_NCAN    0         /* No CAN */
+#  define NUC_NI2S    1         /* (1) I2S */
+#  define NUC_NCOMP   1         /* (1) Analog Comparator */
+#  define NUC_NPWM    6         /* (6) PWM */
+#  define NUC_NADC    8         /* 8x12-bit ADC */
+#  define NUC_RTC     1         /* RTC */
+#  undef  NUC_EBI               /* No EBI */
+#elif defined(CONFIG_ARCH_CHIP_NUC100LE3AN) /* Flash 128K SRAM 16K, LQFP48 package */
+#  define NUC_FLASH  (128*1024) /* 64K FLASH */
+#  define NUC_SRAM   (16*1024)  /* 16K SRAM */
+#  define NUC_NIO     35        /* (35) GPIO */
+#  define NUC_NTIMERS 4         /* 4x32-bit Timers */
+#  define NUC_NPDMA   9         /* 9 PDMA channels */
+#  define NUC_NUARTS  2         /* (2) UARTs */
+#  define NUC_NSPI    1         /* (1) SPI */
+#  define NUC_NI2C    2         /* (2) I2C */
+#  define NUC_NUSB    0         /* No USB */
+#  define NUC_NLIN    0         /* No LIN */
+#  define NUC_NCAN    0         /* No CAN */
+#  define NUC_NI2S    1         /* (1) I2S */
+#  define NUC_NCOMP   1         /* (1) Analog Comparator */
+#  define NUC_NPWM    6         /* (6) PWM */
+#  define NUC_NADC    8         /* 8x12-bit ADC */
+#  define NUC_RTC     1         /* RTC */
+#  undef  NUC_EBI               /* No EBI */
+#elif defined(CONFIG_ARCH_CHIP_NUC100RD3AN) /* Flash 64K SRAM 16K, LQFP64 package */
+#  define NUC_FLASH  (64*1024)  /* 64K FLASH */
+#  define NUC_SRAM   (16*1024)  /* 16K SRAM */
+#  define NUC_NIO     49        /* (49) GPIO */
+#  define NUC_NTIMERS 4         /* 4x32-bit Timers */
+#  define NUC_NPDMA   9         /* 9 PDMA channels */
+#  define NUC_NUARTS  3         /* (3) UARTs */
+#  define NUC_NSPI    2         /* (2) SPI */
+#  define NUC_NI2C    2         /* (2) I2C */
+#  define NUC_NUSB    0         /* No USB */
+#  define NUC_NLIN    0         /* No LIN */
+#  define NUC_NCAN    0         /* No CAN */
+#  define NUC_NI2S    1         /* (1) I2S */
+#  define NUC_NCOMP   2         /* (2) Analog Comparator */
+#  define NUC_NPWM    6         /* (6) PWM */
+#  define NUC_NADC    8         /* 8x12-bit ADC */
+#  define NUC_RTC     1         /* RTC */
+#  undef  NUC_EBI               /* No EBI */
+#elif defined(CONFIG_ARCH_CHIP_NUC100RE3AN) /* Flash 128K SRAM 16K, LQFP64 package */
+#  define NUC_FLASH  (128*1024) /* 128K FLASH */
+#  define NUC_SRAM   (16*1024)  /* 16K SRAM */
+#  define NUC_NIO     49        /* (49) GPIO */
+#  define NUC_NTIMERS 4         /* 4x32-bit Timers */
+#  define NUC_NPDMA   9         /* 9 PDMA channels */
+#  define NUC_NUARTS  3         /* (3) UARTs */
+#  define NUC_NSPI    2         /* (2) SPI */
+#  define NUC_NI2C    2         /* (2) I2C */
+#  define NUC_NUSB    0         /* No USB */
+#  define NUC_NLIN    0         /* No LIN */
+#  define NUC_NCAN    0         /* No CAN */
+#  define NUC_NI2S    1         /* (1) I2S */
+#  define NUC_NCOMP   2         /* (2) Analog Comparator */
+#  define NUC_NPWM    6         /* (6) PWM */
+#  define NUC_NADC    8         /* 8x12-bit ADC */
+#  define NUC_RTC     1         /* RTC */
+#  undef  NUC_EBI               /* No EBI */
+#elif defined(CONFIG_ARCH_CHIP_NUC100VD2AN) /* Flash 64K SRAM 8K, LQFP100 package */
+#  define NUC_FLASH  (64*1024)  /* 64K FLASH */
+#  define NUC_SRAM   (8*1024)   /* 8K SRAM */
+#  define NUC_NIO     80        /* (80) GPIO */
+#  define NUC_NTIMERS 4         /* 4x32-bit Timers */
+#  define NUC_NPDMA   9         /* 9 PDMA channels */
+#  define NUC_NUARTS  3         /* (3) UARTs */
+#  define NUC_NSPI    4         /* (4) SPI */
+#  define NUC_NI2C    2         /* (2) I2C */
+#  define NUC_NUSB    0         /* No USB */
+#  define NUC_NLIN    0         /* No LIN */
+#  define NUC_NCAN    0         /* No CAN */
+#  define NUC_NI2S    1         /* (1) I2S */
+#  define NUC_NCOMP   2         /* (2) Analog Comparator */
+#  define NUC_NPWM    8         /* (8) PWM */
+#  define NUC_NADC    8         /* 8x12-bit ADC */
+#  define NUC_RTC     1         /* RTC */
+#  undef  NUC_EBI               /* No EBI */
+#elif defined(CONFIG_ARCH_CHIP_NUC100VD3AN) /* Flash 64K SRAM 16K, LQFP100 package */
+#  define NUC_FLASH  (64*1024)  /* 64K FLASH */
+#  define NUC_SRAM   (16*1024)  /* 16K SRAM */
+#  define NUC_NIO     80        /* (80) GPIO */
+#  define NUC_NTIMERS 4         /* 4x32-bit Timers */
+#  define NUC_NPDMA   9         /* 9 PDMA channels */
+#  define NUC_NUARTS  3         /* (3) UARTs */
+#  define NUC_NSPI    4         /* (4) SPI */
+#  define NUC_NI2C    2         /* (2) I2C */
+#  define NUC_NUSB    0         /* No USB */
+#  define NUC_NLIN    0         /* No LIN */
+#  define NUC_NCAN    0         /* No CAN */
+#  define NUC_NI2S    1         /* (1) I2S */
+#  define NUC_NCOMP   2         /* (2) Analog Comparator */
+#  define NUC_NPWM    8         /* (8) PWM */
+#  define NUC_NADC    8         /* 8x12-bit ADC */
+#  define NUC_RTC     1         /* RTC */
+#  undef  NUC_EBI               /* No EBI */
+#elif defined(CONFIG_ARCH_CHIP_NUC100VE3AN) /* Flash 128K SRAM 8K, LQFP100 package */
+#  define NUC_FLASH  (128*1024) /* 128K FLASH */
+#  define NUC_SRAM   (16*1024)  /* 16K SRAM */
+#  define NUC_NIO     80        /* (80) GPIO */
+#  define NUC_NTIMERS 4         /* 4x32-bit Timers */
+#  define NUC_NPDMA   9         /* 9 PDMA channels */
+#  define NUC_NUARTS  3         /* (3) UARTs */
+#  define NUC_NSPI    4         /* (4) SPI */
+#  define NUC_NI2C    2         /* (2) I2C */
+#  define NUC_NUSB    0         /* No USB */
+#  define NUC_NLIN    0         /* No LIN */
+#  define NUC_NCAN    0         /* No CAN */
+#  define NUC_NI2S    1         /* (1) I2S */
+#  define NUC_NCOMP   2         /* (2) Analog Comparator */
+#  define NUC_NPWM    8         /* (8) PWM */
+#  define NUC_NADC    8         /* 8x12-bit ADC */
+#  define NUC_RTC     1         /* RTC */
+#  undef  NUC_EBI               /* No EBI */
+
+/* NUC120 USB Line (Low Density) */
+
+#elif defined(CONFIG_ARCH_CHIP_NUC120LC1BN) /* Flash 32K SRAM 4K, LQFP48 package */
+#  define NUC_FLASH  (32*1024)  /* 32K FLASH */
+#  define NUC_SRAM   (4*1024)   /* 4K SRAM */
+#  define NUC_NIO     31        /* (31) GPIO */
+#  define NUC_NTIMERS 4         /* 4x32-bit Timers */
+#  define NUC_NPDMA   1         /* 1 PDMA channels */
+#  define NUC_NUARTS  2         /* (2) UARTs */
+#  define NUC_NSPI    1         /* (1) SPI */
+#  define NUC_NI2C    2         /* (2) I2C */
+#  define NUC_NUSB    1         /* (1) USB 2.0 full speed */
+#  define NUC_NLIN    0         /* No LIN */
+#  define NUC_NCAN    0         /* No CAN */
+#  define NUC_NI2S    1         /* (1) I2S */
+#  define NUC_NCOMP   1         /* (1) Analog Comparator */
+#  define NUC_NPWM    4         /* (4) PWM */
+#  define NUC_NADC    8         /* 8x12-bit ADC */
+#  define NUC_RTC     1         /* RTC */
+#  undef  NUC_EBI               /* No EBI */
+#elif defined(CONFIG_ARCH_CHIP_NUC120LD1BN) /* Flash 64K SRAM 4K, LQFP48 package */
+#  define NUC_FLASH  (64*1024)  /* 64K FLASH */
+#  define NUC_SRAM   (4*1024)   /* 4K SRAM */
+#  define NUC_NIO     31        /* (31) GPIO */
+#  define NUC_NTIMERS 4         /* 4x32-bit Timers */
+#  define NUC_NPDMA   1         /* 1 PDMA channels */
+#  define NUC_NUARTS  2         /* (2) UARTs */
+#  define NUC_NSPI    1         /* (1) SPI */
+#  define NUC_NI2C    2         /* (2) I2C */
+#  define NUC_NUSB    1         /* (1) USB 2.0 full speed */
+#  define NUC_NLIN    0         /* No LIN */
+#  define NUC_NCAN    0         /* No CAN */
+#  define NUC_NI2S    1         /* (1) I2S */
+#  define NUC_NCOMP   1         /* (1) Analog Comparator */
+#  define NUC_NPWM    4         /* (4) PWM */
+#  define NUC_NADC    8         /* 8x12-bit ADC */
+#  define NUC_RTC     1         /* RTC */
+#  undef  NUC_EBI               /* No EBI */
+#elif defined(CONFIG_ARCH_CHIP_NUC120LD2BN) /* Flash 64K SRAM 8K, LQFP48 package */
+#  define NUC_FLASH  (64*1024)  /* 64K FLASH */
+#  define NUC_SRAM   (8*1024)   /* 8K SRAM */
+#  define NUC_NIO     31        /* (31) GPIO */
+#  define NUC_NTIMERS 4         /* 4x32-bit Timers */
+#  define NUC_NPDMA   1         /* 1 PDMA channels */
+#  define NUC_NUARTS  2         /* (2) UARTs */
+#  define NUC_NSPI    1         /* (1) SPI */
+#  define NUC_NI2C    2         /* (2) I2C */
+#  define NUC_NUSB    1         /* (1) USB 2.0 full speed */
+#  define NUC_NLIN    0         /* No LIN */
+#  define NUC_NCAN    0         /* No CAN */
+#  define NUC_NI2S    1         /* (1) I2S */
+#  define NUC_NCOMP   1         /* (1) Analog Comparator */
+#  define NUC_NPWM    4         /* (4) PWM */
+#  define NUC_NADC    8         /* 8x12-bit ADC */
+#  define NUC_RTC     1         /* RTC */
+#  undef  NUC_EBI               /* No EBI */
+#elif defined(CONFIG_ARCH_CHIP_NUC120RC1BN) /* Flash 32K SRAM 4K, LQFP64 package */
+#  define NUC_FLASH  (32*1024)  /* 32K FLASH */
+#  define NUC_SRAM   (4*1024)   /* 4K SRAM */
+#  define NUC_NIO     45        /* (45) GPIO */
+#  define NUC_NTIMERS 4         /* 4x32-bit Timers */
+#  define NUC_NPDMA   1         /* 1 PDMA channels */
+#  define NUC_NUARTS  2         /* (2) UARTs */
+#  define NUC_NSPI    2         /* (2) SPI */
+#  define NUC_NI2C    2         /* (2) I2C */
+#  define NUC_NUSB    1         /* (1) USB 2.0 full speed */
+#  define NUC_NLIN    0         /* No LIN */
+#  define NUC_NCAN    0         /* No CAN */
+#  define NUC_NI2S    1         /* (1) I2S */
+#  define NUC_NCOMP   2         /* (2) Analog Comparators */
+#  define NUC_NPWM    4         /* (4) PWM */
+#  define NUC_NADC    8         /* 8x12-bit ADC */
+#  define NUC_RTC     1         /* RTC */
+#  define NUC_EBI     1         /* Have EBI */
+#elif defined(CONFIG_ARCH_CHIP_NUC120RD1BN) /* Flash 64K SRAM 4K, LQFP64 package */
+#  define NUC_FLASH  (64*1024)  /* 64K FLASH */
+#  define NUC_SRAM   (4*1024)   /* 4K SRAM */
+#  define NUC_NIO     45        /* (45) GPIO */
+#  define NUC_NTIMERS 4         /* 4x32-bit Timers */
+#  define NUC_NPDMA   1         /* 1 PDMA channels */
+#  define NUC_NUARTS  2         /* (2) UARTs */
+#  define NUC_NSPI    2         /* (2) SPI */
+#  define NUC_NI2C    2         /* (2) I2C */
+#  define NUC_NUSB    1         /* (1) USB 2.0 full speed */
+#  define NUC_NLIN    0         /* No LIN */
+#  define NUC_NCAN    0         /* No CAN */
+#  define NUC_NI2S    1         /* (1) I2S */
+#  define NUC_NCOMP   2         /* (2) Analog Comparators */
+#  define NUC_NPWM    4         /* (4) PWM */
+#  define NUC_NADC    8         /* 8x12-bit ADC */
+#  define NUC_RTC     1         /* RTC */
+#  define NUC_EBI     1         /* Have EBI */
+#elif defined(CONFIG_ARCH_CHIP_NUC120RD2BN) /* Flash 64K SRAM 8K, LQFP64 package */
+#  define NUC_FLASH  (64*1024)  /* 64K FLASH */
+#  define NUC_SRAM   (8*1024)   /* 8K SRAM */
+#  define NUC_NIO     45        /* (45) GPIO */
+#  define NUC_NTIMERS 4         /* 4x32-bit Timers */
+#  define NUC_NPDMA   1         /* 1 PDMA channels */
+#  define NUC_NUARTS  2         /* (2) UARTs */
+#  define NUC_NSPI    2         /* (2) SPI */
+#  define NUC_NI2C    2         /* (2) I2C */
+#  define NUC_NUSB    1         /* (1) USB 2.0 full speed */
+#  define NUC_NLIN    0         /* No LIN */
+#  define NUC_NCAN    0         /* No CAN */
+#  define NUC_NI2S    1         /* (1) I2S */
+#  define NUC_NCOMP   2         /* (2) Analog Comparators */
+#  define NUC_NPWM    4         /* (4) PWM */
+#  define NUC_NADC    8         /* 8x12-bit ADC */
+#  define NUC_RTC     1         /* RTC */
+#  define NUC_EBI     1         /* Have EBI */
+
+/* NUC120 USB Line (Medium Density) */
+
+#elif defined(CONFIG_ARCH_CHIP_NUC120LD3AN) /* Flash 64K SRAM 16K, LQFP48 package */
+#  define NUC_FLASH  (64*1024)  /* 64K FLASH */
+#  define NUC_SRAM   (16*1024)  /* 16K SRAM */
+#  define NUC_NIO     31        /* (31) GPIO */
+#  define NUC_NTIMERS 4         /* 4x32-bit Timers */
+#  define NUC_NPDMA   9         /* 9 PDMA channels */
+#  define NUC_NUARTS  2         /* (2) UARTs */
+#  define NUC_NSPI    1         /* (1) SPI */
+#  define NUC_NI2C    2         /* (2) I2C */
+#  define NUC_NUSB    1         /* (1) USB 2.0 full speed */
+#  define NUC_NLIN    0         /* No LIN */
+#  define NUC_NCAN    0         /* No CAN */
+#  define NUC_NI2S    1         /* (1) I2S */
+#  define NUC_NCOMP   1         /* (1) Analog Comparator */
+#  define NUC_NPWM    4         /* (4) PWM */
+#  define NUC_NADC    8         /* 8x12-bit ADC */
+#  define NUC_RTC     1         /* RTC */
+#  undef  NUC_EBI               /* No EBI */
+#elif defined(CONFIG_ARCH_CHIP_NUC120LE3AN) /* Flash 128K SRAM 16K, LQFP48 package */
+#  define NUC_FLASH  (128*1024) /* 128K FLASH */
+#  define NUC_SRAM   (16*1024)  /* 16K SRAM */
+#  define NUC_NIO     31        /* (31) GPIO */
+#  define NUC_NTIMERS 4         /* 4x32-bit Timers */
+#  define NUC_NPDMA   9         /* 9 PDMA channels */
+#  define NUC_NUARTS  2         /* (2) UARTs */
+#  define NUC_NSPI    1         /* (1) SPI */
+#  define NUC_NI2C    2         /* (2) I2C */
+#  define NUC_NUSB    1         /* (1) USB 2.0 full speed */
+#  define NUC_NLIN    0         /* No LIN */
+#  define NUC_NCAN    0         /* No CAN */
+#  define NUC_NI2S    1         /* (1) I2S */
+#  define NUC_NCOMP   1         /* (1) Analog Comparator */
+#  define NUC_NPWM    4         /* (4) PWM */
+#  define NUC_NADC    8         /* 8x12-bit ADC */
+#  define NUC_RTC     1         /* RTC */
+#  undef  NUC_EBI               /* No EBI */
+#elif defined(CONFIG_ARCH_CHIP_NUC120RD3AN) /* Flash 64K SRAM 16K, LQFP64 package */
+#  define NUC_FLASH  (64*1024)  /* 64K FLASH */
+#  define NUC_SRAM   (16*1024)  /* 16K SRAM */
+#  define NUC_NIO     45        /* (45) GPIO */
+#  define NUC_NTIMERS 4         /* 4x32-bit Timers */
+#  define NUC_NPDMA   9         /* 9 PDMA channels */
+#  define NUC_NUARTS  2         /* (2) UARTs */
+#  define NUC_NSPI    2         /* (2) SPI */
+#  define NUC_NI2C    2         /* (2) I2C */
+#  define NUC_NUSB    1         /* (1) USB 2.0 full speed */
+#  define NUC_NLIN    0         /* No LIN */
+#  define NUC_NCAN    0         /* No CAN */
+#  define NUC_NI2S    1         /* (1) I2S */
+#  define NUC_NCOMP   2         /* (2) Analog Comparators */
+#  define NUC_NPWM    6         /* (6) PWM */
+#  define NUC_NADC    8         /* 8x12-bit ADC */
+#  define NUC_RTC     1         /* RTC */
+#  undef  NUC_EBI               /* No EBI */
+#elif defined(CONFIG_ARCH_CHIP_NUC120RE3AN) /* Flash 128K SRAM 16K, LQFP64 package */
+#  define NUC_FLASH  (128*1024) /* 128K FLASH */
+#  define NUC_SRAM   (16*1024)  /* 16K SRAM */
+#  define NUC_NIO     45        /* (45) GPIO */
+#  define NUC_NTIMERS 4         /* 4x32-bit Timers */
+#  define NUC_NPDMA   9         /* 9 PDMA channels */
+#  define NUC_NUARTS  2         /* (2) UARTs */
+#  define NUC_NSPI    2         /* (2) SPI */
+#  define NUC_NI2C    2         /* (2) I2C */
+#  define NUC_NUSB    1         /* (1) USB 2.0 full speed */
+#  define NUC_NLIN    0         /* No LIN */
+#  define NUC_NCAN    0         /* No CAN */
+#  define NUC_NI2S    1         /* (1) I2S */
+#  define NUC_NCOMP   2         /* (2) Analog Comparators */
+#  define NUC_NPWM    6         /* (6) PWM */
+#  define NUC_NADC    8         /* 8x12-bit ADC */
+#  define NUC_RTC     1         /* RTC */
+#  undef  NUC_EBI               /* No EBI */
+#elif defined(CONFIG_ARCH_CHIP_NUC120VD2AN) /* Flash 64K SRAM 8K, LQFP100 package */
+#  define NUC_FLASH  (64*1024)  /* 64K FLASH */
+#  define NUC_SRAM   (8*1024)   /* 8K SRAM */
+#  define NUC_NIO     76        /* (76) GPIO */
+#  define NUC_NTIMERS 4         /* 4x32-bit Timers */
+#  define NUC_NPDMA   9         /* 9 PDMA channels */
+#  define NUC_NUARTS  3         /* (3) UARTs */
+#  define NUC_NSPI    4         /* (4) SPI */
+#  define NUC_NI2C    2         /* (2) I2C */
+#  define NUC_NUSB    1         /* (1) USB 2.0 full speed */
+#  define NUC_NLIN    0         /* No LIN */
+#  define NUC_NCAN    0         /* No CAN */
+#  define NUC_NI2S    1         /* (1) I2S */
+#  define NUC_NCOMP   2         /* (2) Analog Comparators */
+#  define NUC_NPWM    8         /* (8) PWM */
+#  define NUC_NADC    8         /* 8x12-bit ADC */
+#  define NUC_RTC     1         /* RTC */
+#  undef  NUC_EBI               /* No EBI */
+#elif defined(CONFIG_ARCH_CHIP_NUC120VD3AN) /* Flash 64K SRAM 16K, LQFP100 package */
+#  define NUC_FLASH  (64*1024)  /* 64K FLASH */
+#  define NUC_SRAM   (16*1024)  /* 16K SRAM */
+#  define NUC_NIO     76        /* (76) GPIO */
+#  define NUC_NTIMERS 4         /* 4x32-bit Timers */
+#  define NUC_NPDMA   9         /* 9 PDMA channels */
+#  define NUC_NUARTS  3         /* (3) UARTs */
+#  define NUC_NSPI    4         /* (4) SPI */
+#  define NUC_NI2C    2         /* (2) I2C */
+#  define NUC_NUSB    1         /* (1) USB 2.0 full speed */
+#  define NUC_NLIN    0         /* No LIN */
+#  define NUC_NCAN    0         /* No CAN */
+#  define NUC_NI2S    1         /* (1) I2S */
+#  define NUC_NCOMP   2         /* (2) Analog Comparators */
+#  define NUC_NPWM    8         /* (8) PWM */
+#  define NUC_NADC    8         /* 8x12-bit ADC */
+#  define NUC_RTC     1         /* RTC */
+#  undef  NUC_EBI               /* No EBI */
+#elif defined(CONFIG_ARCH_CHIP_NUC120VE3AN) /* Flash 128K SRAM 16K, LQFP100 package */
+#  define NUC_FLASH  (128*1024) /* 128K FLASH */
+#  define NUC_SRAM   (16*1024)  /* 16K SRAM */
+#  define NUC_NIO     76        /* (76) GPIO */
+#  define NUC_NTIMERS 4         /* 4x32-bit Timers */
+#  define NUC_NPDMA   9         /* 9 PDMA channels */
+#  define NUC_NUARTS  3         /* (3) UARTs */
+#  define NUC_NSPI    4         /* (4) SPI */
+#  define NUC_NI2C    2         /* (2) I2C */
+#  define NUC_NUSB    1         /* (1) USB 2.0 full speed */
+#  define NUC_NLIN    0         /* No LIN */
+#  define NUC_NCAN    0         /* No CAN */
+#  define NUC_NI2S    1         /* (1) I2S */
+#  define NUC_NCOMP   2         /* (2) Analog Comparators */
+#  define NUC_NPWM    8         /* (8) PWM */
+#  define NUC_NADC    8         /* 8x12-bit ADC */
+#  define NUC_RTC     1         /* RTC */
+#  undef  NUC_EBI               /* No EBI */
+
+#else
+#  error "Unrecognized NUC1XX chip"
+#endif
 
 /* NVIC priority levels *************************************************************/
 /* Each priority field holds a priority value, 0-3. The lower the value, the greater
diff --git a/nuttx/arch/arm/src/nuc1xx/Kconfig b/nuttx/arch/arm/src/nuc1xx/Kconfig
index 9902936da..50f72c355 100644
--- a/nuttx/arch/arm/src/nuc1xx/Kconfig
+++ b/nuttx/arch/arm/src/nuc1xx/Kconfig
@@ -4,3 +4,140 @@
 #
 
 comment "NUC100/120 Configuration Options"
+
+choice
+	prompt "Nuvoton NUC1xx Chip Selection"
+	default ARCH_CHIP_NUC120LE3AN
+	depends on ARCH_CHIP_NUC1XX
+
+config ARCH_CHIP_NUC100LC1BN
+	bool "NUC100LC1BN
+	---help---
+		Nuvoton NUC100 low density chip: Flash 32K SRAM 4K, LQFP48 package
+
+config ARCH_CHIP_NUC100LD1BN
+	bool "NUC100LD1BN
+	---help---
+		Nuvoton NUC100 low density chip: Flash 64K SRAM 4K, LQFP48 package
+
+config ARCH_CHIP_NUC100LD2BN
+	bool "NUC100LD2BN
+	---help---
+		Nuvoton NUC100 low density chip: Flash 64K SRAM 8K, LQFP48 package
+
+config ARCH_CHIP_NUC100RC1BN
+	bool "NUC100RC1BN
+	---help---
+		Nuvoton NUC100 low density chip: Flash 32K SRAM 4K, LQFP64 package
+
+config ARCH_CHIP_NUC100RD1BN
+	bool "NUC100RD1BN
+	---help---
+		Nuvoton NUC100 low density chip: Flash 64K SRAM 4K, LQFP64 package
+
+config ARCH_CHIP_NUC100RD2BN
+	bool "NUC100RD2BN
+	---help---
+		Nuvoton NUC100 low density chip: Flash 64K SRAM 8K, LQFP64 package
+
+config ARCH_CHIP_NUC100LD3AN
+	bool "NUC100LD3AN
+	---help---
+		Nuvoton NUC100 medium density chip: Flash 64K SRAM 16K, LQFP48 package
+
+config ARCH_CHIP_NUC100LE3AN
+	bool "NUC100LE3AN
+	---help---
+		Nuvoton NUC100 medium density chip: Flash 128K SRAM 16K, LQFP48 package
+
+config ARCH_CHIP_NUC100RD3AN
+	bool "NUC100RD3AN
+	---help---
+		Nuvoton NUC100 medium density chip: Flash 64K SRAM 16K, LQFP64 package
+
+config ARCH_CHIP_NUC100RE3AN
+	bool "NUC100RE3AN
+	---help---
+		Nuvoton NUC100 medium density chip: Flash 128K SRAM 16K, LQFP64 package
+
+config ARCH_CHIP_NUC100VD2AN
+	bool "NUC100VD2AN
+	---help---
+		Nuvoton NUC100 medium density chip: Flash 64K SRAM 8K, LQFP100 package
+
+config ARCH_CHIP_NUC100VD3AN
+	bool "NUC100VD3AN
+	---help---
+		Nuvoton NUC100 medium density chip: Flash 64K SRAM 16K, LQFP100 package
+
+config ARCH_CHIP_NUC100VE3AN
+	bool "NUC100VE3AN
+	---help---
+		Nuvoton NUC100 medium density chip: Flash 128K SRAM 8K, LQFP100 package
+
+config ARCH_CHIP_NUC120LC1BN
+	bool "NUC120LC1BN
+	---help---
+		Nuvoton NUC120 low density chip: Flash 32K SRAM 4K, LQFP48 package
+
+config ARCH_CHIP_NUC120LD1BN
+	bool "NUC120LD1BN
+	---help---
+		Nuvoton NUC120 low density chip: Flash 64K SRAM 4K, LQFP48 package
+
+config ARCH_CHIP_NUC120LD2BN
+	bool "NUC120LD2BN
+	---help---
+		Nuvoton NUC120 low density chip: Flash 64K SRAM 8K, LQFP48 package
+
+config ARCH_CHIP_NUC120RC1BN
+	bool "NUC120RC1BN
+	---help---
+		Nuvoton NUC120 low density chip: Flash 32K SRAM 4K, LQFP64 package
+
+config ARCH_CHIP_NUC120RD1BN
+	bool "NUC120RD1BN
+	---help---
+		Nuvoton NUC120 low density chip: Flash 64K SRAM 4K, LQFP64 package
+
+config ARCH_CHIP_NUC120RD2BN
+	bool "NUC120RD2BN
+	---help---
+		Nuvoton NUC120 low density chip: Flash 64K SRAM 8K, LQFP64 package
+
+config ARCH_CHIP_NUC120LD3AN
+	bool "NUC120LD3AN
+	---help---
+		Nuvoton NUC120 medium density chip: Flash 64K SRAM 16K, LQFP48 package
+
+config ARCH_CHIP_NUC120LE3AN
+	bool "NUC120LE3AN
+	---help---
+		Nuvoton NUC120 medium density chip: Flash 128K SRAM 16K, LQFP48 package
+
+config ARCH_CHIP_NUC120RD3AN
+	bool "NUC120RD3AN
+	---help---
+		Nuvoton NUC120 medium density chip: Flash 64K SRAM 16K, LQFP64 package
+
+config ARCH_CHIP_NUC120RE3AN
+	bool "NUC120RE3AN
+	---help---
+		Nuvoton NUC120 medium density chip: Flash 128K SRAM 16K, LQFP64 package
+
+config ARCH_CHIP_NUC120VD2AN
+	bool "NUC120VD2AN
+	---help---
+		Nuvoton NUC120 medium density chip: Flash 64K SRAM 8K, LQFP100 package
+
+config ARCH_CHIP_NUC120VD3AN
+	bool "NUC120VD3AN
+	---help---
+		Nuvoton NUC120 medium density chip: Flash 64K SRAM 16K, LQFP100 package
+
+config ARCH_CHIP_NUC120VE3AN
+	bool "NUC120VE3AN
+	---help---
+		Nuvoton NUC120 medium density chip: Flash 128K SRAM 16K, LQFP100 package
+
+endchoice
diff --git a/nuttx/configs/Kconfig b/nuttx/configs/Kconfig
index 9829a1f63..590e6897a 100644
--- a/nuttx/configs/Kconfig
+++ b/nuttx/configs/Kconfig
@@ -318,6 +318,15 @@ config ARCH_BOARD_MIRTOO
 		This is the port to the DTX1-4000L "Mirtoo" module.  This module uses MicroChip
 		PIC32MX250F128D.  See http://www.dimitech.com/ for further information.
 
+config ARCH_BOARD_NUTINY_NUC120
+	bool "Nuvoton NuTiny NUC120"
+	depends on ARCH_CHIP_NUC120LE3AN
+	select ARCH_HAVE_LEDS
+	---help---
+		This is the port to the Nuvoton NuTiny EVB 120 board.  This board uses a 
+		Nuvoton NUC120 chip, specifically the NUC120LE3AN.  See http://www.nuvoton.com/
+		for further information.
+
 config ARCH_BOARD_OLIMEXLPC2378
 	bool "Olimex-lpc2378 board"
 	depends on ARCH_CHIP_LPC2378
@@ -695,6 +704,7 @@ config ARCH_BOARD
 	default "ne64badge"           if ARCH_BOARD_NE64BADGE
 	default "ntosd-dm320"         if ARCH_BOARD_NTOSD_DM320
 	default "nucleus2g"           if ARCH_BOARD_NUCLEUS2G
+	default "nutiny-nuc120"       if ARCH_BOARD_NUTINY_NUC120
 	default "olimex-lpc1766stk"   if ARCH_BOARD_LPC1766STK
 	default "olimex-lpc2378"      if ARCH_BOARD_OLIMEXLPC2378
 	default "olimex-stm32-p107"   if ARCH_BOARD_OLIMEX_STM32P107
@@ -876,6 +886,9 @@ endif
 if ARCH_BOARD_NUCLEUS2G
 source "configs/nucleus2g/Kconfig"
 endif
+if ARCH_BOARD_NUTINY_NUC120
+source "configs/nutiny-nuc120/Kconfig"
+endif
 if ARCH_BOARD_LPC1766STK
 source "configs/olimex-lpc1766stk/Kconfig"
 endif
diff --git a/nuttx/configs/nutiny-nuc120/ostest/defconfig b/nuttx/configs/nutiny-nuc120/ostest/defconfig
index 202c3453a..e13b47105 100644
--- a/nuttx/configs/nutiny-nuc120/ostest/defconfig
+++ b/nuttx/configs/nutiny-nuc120/ostest/defconfig
@@ -76,7 +76,8 @@ CONFIG_ARCH="arm"
 # CONFIG_ARCH_CHIP_LPC31XX is not set
 # CONFIG_ARCH_CHIP_LPC43XX is not set
 # CONFIG_ARCH_CHIP_SAM3U is not set
-CONFIG_ARCH_CHIP_NUC120=y
+CONFIG_ARCH_CHIP_NUC1XX=y
+CONFIG_ARCH_CHIP_NUC120LE3AN=y
 # CONFIG_ARCH_CHIP_STR71X is not set
 CONFIG_ARCH_CORTEXM0=y
 CONFIG_ARCH_FAMILY="armv6-m"
@@ -244,7 +245,7 @@ CONFIG_BOOT_RUNFROMFLASH=y
 #
 # Board Selection
 #
-CONFIG_ARCH_BOARD_STM32F3_DISCOVERY=y
+CONFIG_ARCH_BOARD_NUTINY_NUC120=y
 # CONFIG_ARCH_BOARD_CUSTOM is not set
 CONFIG_ARCH_BOARD="nutiny-nuc120"