BEV needs to be zero in single-vector mode; Interrupts go to EBASE+0x200

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4153 42af7a65-404d-4744-a932-0658087f49c3

5 files changed, 60 insertions, 7 deletions

diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-head.S b/nuttx/arch/mips/src/pic32mx/pic32mx-head.S
index 611738395..d4613e7de 100644
--- a/nuttx/arch/mips/src/pic32mx/pic32mx-head.S
+++ b/nuttx/arch/mips/src/pic32mx/pic32mx-head.S
@@ -161,8 +161,9 @@ __reset:
  * Name: _gen_exception
  *
  * Description:
- *   General Exception Vector Handler.  Jumps to _exception_handler.  NOTE:
- *   we set the BEV bit in the status register so all interrupt vectors
+ *   General Exception Vector Handler.  Jumps to _exception_handler. This
+ *   vector will be positioned at 0xbfc00180 by the linker script. NOTE:
+ *   If we set the BEV bit in the status register so all interrupt vectors
  *   should go through the _bev_exception.
  *
  * Input Parameters:
@@ -183,10 +184,39 @@ _gen_exception:
 	.end _gen_exception
 
 /****************************************************************************
+ * Name: _ebase_exception
+ *
+ * Description:
+ *   Interrupt Exception Vector Handler.  Jumps to _int_handler.  This
+ *   vector will be positioned at 0xbfc00200 by the linker script. NOTE:
+ *   Several vectors (JTAG, TLB fills, etc.) could come through this vector.
+ *   However, this is intended to serve vectors in PIC32MX single vector
+ *   mode:  The EBASE register will be set to 0xbfc00000 and the vector
+ *   should go to EBASE + 0x0200.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Does not return
+ *
+ ****************************************************************************/
+
+	.section .ebase_excpt,"ax",@progbits
+	.set	noreorder
+	.ent	_ebase_exception
+_ebase_exception:
+	la		k0, _int_handler
+	jr		k0
+	nop
+	.end _ebase_exception
+
+/****************************************************************************
  * Name: _bev_exception
  *
  * Description:
- *   Boot Exception Vector Handler.  Jumps to _exception_handler
+ *   Boot Exception Vector Handler.  Jumps to _exception_handler.  This
+ *   vector will be positioned at 0xbfc00380 by the linker script. 
  *
  * Input Parameters:
  *   None
@@ -209,7 +239,8 @@ _bev_exception:
  * Name: _int_exception
  *
  * Description:
- *   Interrupt Exception Vector Handler.  Jumps to _int_handler
+ *   Interrupt Exception Vector Handler.  Jumps to _int_handler.  This
+ *   vector will be positioned at 0xbfc00400 by the linker script. 
  *
  * Input Parameters:
  *   None
diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-irq.c b/nuttx/arch/mips/src/pic32mx/pic32mx-irq.c
index 54d624559..9d4bcded0 100644
--- a/nuttx/arch/mips/src/pic32mx/pic32mx-irq.c
+++ b/nuttx/arch/mips/src/pic32mx/pic32mx-irq.c
@@ -114,7 +114,9 @@ void up_irqinitialize(void)
   regval |= CP0_STATUS_BEV;
   cp0_putstatus(regval);
 
-  /* Set the EBASE value to the beginning of boot FLASH */
+  /* Set the EBASE value to the beginning of boot FLASH.  In single-vector
+   * mode, interrupt vectors should go to EBASE + 0x0200 0r 0xbfc00200.
+   */
 
   cp0_putebase(0xbfc00000);
 
@@ -128,10 +130,10 @@ void up_irqinitialize(void)
   regval |= CP0_CAUSE_IV; 
   cp0_putcause(regval);
 
-  /* Clear the EXL bit in the STATUS register */
+  /* Clear the EXL and BEV bits in the STATUS register */
 
   regval  = cp0_getstatus();
-  regval &= ~CP0_STATUS_EXL;
+  regval &= ~(CP0_STATUS_EXL | CP0_STATUS_BEV);
   cp0_putstatus(regval);
 
   /* Configure multi- or single- vector interrupts */
diff --git a/nuttx/configs/pcblogic-pic32mx/ostest/ld.script b/nuttx/configs/pcblogic-pic32mx/ostest/ld.script
index 6984d9f41..ff4015be1 100644
--- a/nuttx/configs/pcblogic-pic32mx/ostest/ld.script
+++ b/nuttx/configs/pcblogic-pic32mx/ostest/ld.script
@@ -70,6 +70,7 @@ MEMORY
 
 	kseg1_reset    (rx) : ORIGIN = 0xbfc00000, LENGTH = 384
 	kseg1_genexcpt (rx) : ORIGIN = 0xbfc00180, LENGTH = 128
+	kseg1_ebexcpt  (rx) : ORIGIN = 0xbfc00200, LENGTH = 128
 	kseg1_bevexcpt (rx) : ORIGIN = 0xbfc00380, LENGTH = 128
 	kseg1_intexcpt (rx) : ORIGIN = 0xbfc00400, LENGTH = 128
 	kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16
@@ -125,6 +126,11 @@ SECTIONS
 		KEEP (*(.gen_excpt))
 	} > kseg1_genexcpt
 
+	.ebase_excpt :
+	{
+		KEEP (*(.ebase_excpt))
+	} > kseg1_ebexcpt
+
 	.bev_excpt :
 	{
 		KEEP (*(.bev_excpt))
diff --git a/nuttx/configs/pic32-starterkit/ostest/ld.script b/nuttx/configs/pic32-starterkit/ostest/ld.script
index eb764bd20..d2c1f162b 100644
--- a/nuttx/configs/pic32-starterkit/ostest/ld.script
+++ b/nuttx/configs/pic32-starterkit/ostest/ld.script
@@ -70,6 +70,8 @@ MEMORY
 
 	kseg1_reset    (rx) : ORIGIN = 0xbfc00000, LENGTH = 384
 	kseg1_genexcpt (rx) : ORIGIN = 0xbfc00180, LENGTH = 128
+	kseg1_ebexcpt  (rx) : ORIGIN = 0xbfc00200, LENGTH = 128
+	kseg1_bevexcpt (rx) : ORIGIN = 0xbfc00380, LENGTH = 128
 	kseg1_intexcpt (rx) : ORIGIN = 0xbfc00400, LENGTH = 128
 	kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16
 	kseg0_bootmem  (rx) : ORIGIN = 0x9fc00490, LENGTH = 8192-1168
@@ -124,6 +126,11 @@ SECTIONS
 		KEEP (*(.gen_excpt))
 	} > kseg1_genexcpt
 
+	.ebase_excpt :
+	{
+		KEEP (*(.ebase_excpt))
+	} > kseg1_ebexcpt
+
 	.bev_excpt :
 	{
 		KEEP (*(.bev_excpt))
diff --git a/nuttx/configs/sure-pic32mx/ostest/ld.script b/nuttx/configs/sure-pic32mx/ostest/ld.script
index d5b41f612..08bc50df1 100644
--- a/nuttx/configs/sure-pic32mx/ostest/ld.script
+++ b/nuttx/configs/sure-pic32mx/ostest/ld.script
@@ -70,6 +70,8 @@ MEMORY
 
 	kseg1_reset    (rx) : ORIGIN = 0xbfc00000, LENGTH = 384
 	kseg1_genexcpt (rx) : ORIGIN = 0xbfc00180, LENGTH = 128
+	kseg1_ebexcpt  (rx) : ORIGIN = 0xbfc00200, LENGTH = 128
+	kseg1_bevexcpt (rx) : ORIGIN = 0xbfc00380, LENGTH = 128
 	kseg1_intexcpt (rx) : ORIGIN = 0xbfc00400, LENGTH = 128
 	kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16
 	kseg0_bootmem  (rx) : ORIGIN = 0x9fc00490, LENGTH = 8192-1168
@@ -124,6 +126,11 @@ SECTIONS
 		KEEP (*(.gen_excpt))
 	} > kseg1_genexcpt
 
+	.ebase_excpt :
+	{
+		KEEP (*(.ebase_excpt))
+	} > kseg1_ebexcpt
+
 	.bev_excpt :
 	{
 		KEEP (*(.bev_excpt))