LPC1788 PLL configuration from Rommel Marcelo

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5654 42af7a65-404d-4744-a932-0658087f49c3

6 files changed, 55 insertions, 40 deletions

diff --git a/nuttx/arch/arm/include/irq.h b/nuttx/arch/arm/include/irq.h
index bde751b99..e1763af84 100644
--- a/nuttx/arch/arm/include/irq.h
+++ b/nuttx/arch/arm/include/irq.h
@@ -57,9 +57,11 @@
  */
 
 #if defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4)
-# include <arch/armv7-m/irq.h>
+#  include <arch/armv7-m/irq.h>
+#elif defined(CONFIG_ARCH_CORTEXM0)
+#  include <arch/armv6-m/irq.h>
 #else
-# include <arch/arm/irq.h>
+#  include <arch/arm/irq.h>
 #endif
 
 /****************************************************************************
diff --git a/nuttx/arch/arm/include/syscall.h b/nuttx/arch/arm/include/syscall.h
index 8b438200a..a11fc2ba3 100644
--- a/nuttx/arch/arm/include/syscall.h
+++ b/nuttx/arch/arm/include/syscall.h
@@ -47,9 +47,11 @@
 /* Include ARM architecture-specific syscall macros */
 
 #if defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4)
-# include <arch/armv7-m/syscall.h>
+#  include <arch/armv7-m/syscall.h>
+#elif defined(CONFIG_ARCH_CORTEXM0)
+#  include <arch/armv6-m/syscall.h>
 #else
-# include <arch/arm/syscall.h>
+#  include <arch/arm/syscall.h>
 #endif
 
 /****************************************************************************
diff --git a/nuttx/arch/arm/include/types.h b/nuttx/arch/arm/include/types.h
index 1d2ea4cfe..7e464d48c 100644
--- a/nuttx/arch/arm/include/types.h
+++ b/nuttx/arch/arm/include/types.h
@@ -89,7 +89,7 @@ typedef unsigned int       _uintptr_t;
  */
 
 #ifdef __thumb2__
-#ifdef CONFIG_ARMV7M_USEBASEPRI
+#if defined(CONFIG_ARMV7M_USEBASEPRI) || defined(CONFIG_ARCH_ARMV6M)
 typedef unsigned char      irqstate_t;
 #else
 typedef unsigned short     irqstate_t;
diff --git a/nuttx/arch/arm/src/Makefile b/nuttx/arch/arm/src/Makefile
index e44def30c..010612124 100644
--- a/nuttx/arch/arm/src/Makefile
+++ b/nuttx/arch/arm/src/Makefile
@@ -42,9 +42,13 @@ else
 ifeq ($(CONFIG_ARCH_CORTEXM4),y)   # Cortex-M4 is ARMv7E-M
 ARCH_SUBDIR = armv7-m
 else
+ifeq ($(CONFIG_ARCH_CORTEXM0),y)   # Cortex-M0 is ARMv6-M
+ARCH_SUBDIR = armv6-m
+else
 ARCH_SUBDIR = arm
 endif
 endif
+endif
 
 ifeq ($(CONFIG_WINDOWS_NATIVE),y)
   ARCH_SRCDIR = $(TOPDIR)\arch\$(CONFIG_ARCH)\src
diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_syscon.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_syscon.h
index 8c1b26f6d..7a30794d6 100644
--- a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_syscon.h
+++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_syscon.h
@@ -220,13 +220,13 @@
                                                       /* Bits 0-11:  Reserved */
 #define SYSCON_FLASHCFG_TIM_SHIFT        (12)         /* Bits 12-15: FLASHTIM Flash access time */
 #define SYSCON_FLASHCFG_TIM_MASK         (15 << SYSCON_FLASHCFG_TIM_SHIFT)
-#  define SYSCON_FLASHCFG_TIM_1          (0 << SYSCON_FLASHCFG_TIM_SHIFT) /* 1 CPU clock <= 20 MHz CPU clock */
-#  define SYSCON_FLASHCFG_TIM_2          (1 << SYSCON_FLASHCFG_TIM_SHIFT) /* 2 CPU clock <= 40 MHz CPU clock */
-#  define SYSCON_FLASHCFG_TIM_3          (2 << SYSCON_FLASHCFG_TIM_SHIFT) /* 3 CPU clock <= 60 MHz CPU clock */
-#  define SYSCON_FLASHCFG_TIM_4          (3 << SYSCON_FLASHCFG_TIM_SHIFT) /* 4 CPU clock <= 80 MHz CPU clock */
-#  define SYSCON_FLASHCFG_TIM_5          (4 << SYSCON_FLASHCFG_TIM_SHIFT) /* 5 CPU clock <= 100 MHz CPU clock
+#  define SYSCON_FLASHCFG_TIM_0          (0)                              /* 1 CPU clock <= 20 MHz CPU clock */
+#  define SYSCON_FLASHCFG_TIM_1          (1 << SYSCON_FLASHCFG_TIM_SHIFT) /* 2 CPU clock <= 40 MHz CPU clock */
+#  define SYSCON_FLASHCFG_TIM_2          (2 << SYSCON_FLASHCFG_TIM_SHIFT) /* 3 CPU clock <= 60 MHz CPU clock */
+#  define SYSCON_FLASHCFG_TIM_3          (3 << SYSCON_FLASHCFG_TIM_SHIFT) /* 4 CPU clock <= 80 MHz CPU clock */
+#  define SYSCON_FLASHCFG_TIM_4          (4 << SYSCON_FLASHCFG_TIM_SHIFT) /* 5 CPU clock <= 100 MHz CPU clock
                                                                            * (Up to 120 Mhz for LPC1788x) */
-#  define SYSCON_FLASHCFG_TIM_6          (5 << SYSCON_FLASHCFG_TIM_SHIFT) /* "safe" setting for any conditions */
+#  define SYSCON_FLASHCFG_TIM_5          (5 << SYSCON_FLASHCFG_TIM_SHIFT) /* "safe" setting for any conditions */
                                                    /* Bits 16-31:  Reserved */
 /* Memory Mapping Control register (MEMMAP - 0x400F C040) */
 
@@ -289,16 +289,16 @@
                                                    /* Bits 9-31:  Reserved */
 /* USB Clock Configuration register */
 
-#define SYSCON_USBCLKCFG_USBDIV_SHIFT    (0)       /* Bits 0-4: PLL0/1 divide value USB clock */
-#define SYSCON_USBCLKCFG_USBDIV_MASK     (0x1f << SYSCON_USBCLKCFG_USBDIV_SHIFT)
-#  define SYSCON_USBCLKCFG_USBDIV_DIV1   (1 << SYSCON_USBCLKCFG_USBDIV_SHIFT) /* PLL0/1 output must be 48MHz */
-#  define SYSCON_USBCLKCFG_USBDIV_DIV2   (2 << SYSCON_USBCLKCFG_USBDIV_SHIFT) /* PLL0/1 output must be 96MHz */
-#  define SYSCON_USBCLKCFG_USBDIV_DIV3   (3 << SYSCON_USBCLKCFG_USBDIV_SHIFT) /* PLL0/1 output must be 144MHz */
+#define SYSCON_USBCLKSEL_USBDIV_SHIFT    (0)       /* Bits 0-4: PLL0/1 divide value USB clock */
+#define SYSCON_USBCLKSEL_USBDIV_MASK     (0x1f << SYSCON_USBCLKSEL_USBDIV_SHIFT)
+#  define SYSCON_USBCLKSEL_USBDIV_DIV1   (1 << SYSCON_USBCLKSEL_USBDIV_SHIFT) /* PLL0/1 output must be 48MHz */
+#  define SYSCON_USBCLKSEL_USBDIV_DIV2   (2 << SYSCON_USBCLKSEL_USBDIV_SHIFT) /* PLL0/1 output must be 96MHz */
+#  define SYSCON_USBCLKSEL_USBDIV_DIV3   (3 << SYSCON_USBCLKSEL_USBDIV_SHIFT) /* PLL0/1 output must be 144MHz */
                                                    /* Bits 5-7:  Reserved */
-#define SYSCON_USBCLKCFG_USBSEL_SHIFT    (8)       /* Bits 8-9: Input clock to USBDIV */
-#define SYSCON_USBCLKCFG_USBSEL_MASK     (3 << SYSCON_USBCLKCFG_USBSEL_SHIFT)
-#define SYSCON_USBCLKCFG_USBSEL_MAINPLL  (1 << SYSCON_USBCLKCFG_USBSEL_SHIFT)  /* 01: PLL0 is used as input clock to USBDIV */
-#define SYSCON_USBCLKCFG_USBSEL_ALTPLL   (2 << SYSCON_USBCLKCFG_USBSEL_SHIFT)  /* 10: PLL1 is used as input clock to USBDIV */
+#define SYSCON_USBCLKSEL_USBSEL_SHIFT    (8)       /* Bits 8-9: Input clock to USBDIV */
+#define SYSCON_USBCLKSEL_USBSEL_MASK     (3 << SYSCON_USBCLKSEL_USBSEL_SHIFT)
+#define SYSCON_USBCLKSEL_USBSEL_PLL0     (1 << SYSCON_USBCLKSEL_USBSEL_SHIFT)  /* 01: PLL0 is used as input clock to USBDIV */
+#define SYSCON_USBCLKSEL_USBSEL_PLL1     (2 << SYSCON_USBCLKSEL_USBSEL_SHIFT)  /* 10: PLL1 is used as input clock to USBDIV */
                                                                                /* 11: unused */
                                                    /* Bits 10-31:  Reserved */
 /* CAN0/1 Sleep Clear Register */
@@ -383,7 +383,7 @@
 #define SYSCON_PCONP_PCCAN1              (1 << 13) /* Bit 13: CAN Controller 1 power/clock control */
 #define SYSCON_PCONP_PCCAN2              (1 << 14) /* Bit 14: CAN Controller 2 power/clock control */
 #define SYSCON_PCONP_PCGPIO              (1 << 15) /* Bit 15: GPIOs power/clock enable */
-#define SYSCON_PCONP_PCRIT               (1 << 16) /* Bit 16: Repetitive Interrupt Timer power/clock control */
+#define SYSCON_PCONP_PCSPIFI             (1 << 16) /* Bit 16: SPI Flash Interface power/clock control */
 #define SYSCON_PCONP_PCMCPWM             (1 << 17) /* Bit 17: Motor Control PWM */
 #define SYSCON_PCONP_PCQEI               (1 << 18) /* Bit 18: Quadrature Encoder power/clock control */
 #define SYSCON_PCONP_PCI2C1              (1 << 19) /* Bit 19: I2C1 power/clock control */
diff --git a/nuttx/configs/open1788/include/board.h b/nuttx/configs/open1788/include/board.h
index 258735e34..4f1d83349 100644
--- a/nuttx/configs/open1788/include/board.h
+++ b/nuttx/configs/open1788/include/board.h
@@ -61,15 +61,16 @@
 #define BOARD_OSCCLK_FREQUENCY      BOARD_XTAL_FREQUENCY  /* Main oscillator frequency */
 #define BOARD_RTCCLK_FREQUENCY      (32768)               /* RTC oscillator frequency */
 #define BOARD_INTRCOSC_FREQUENCY    (4000000)             /* Internal RC oscillator frequency */
+#define BOARD_WDTOSC_FREQUENCY      (500000)              /* WDT oscillator frequency */
 
 /* This is the clock setup we configure for:
  *
  *   SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz  -> Select Main oscillator for source
- *   PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> PLL0 multipler=20, pre-divider=1
- *   CCLCK = 480MHz / 6 = 80MHz               -> CCLK divider = 6
+ *   PLL0CLK = (10 * SYSCLK) / 1 = 120MHz -> PLL0 multipler=10, pre-divider=1
+ *   CCLCK = 120MHz  -> CCLK divider = 1
  */
 
-#define LPC17_CCLK                 80000000 /* 80Mhz */
+#define LPC17_CCLK                 120000000 /* 120Mhz */
 
 /* Select the main oscillator as the frequency source.  SYSCLK is then the frequency
  * of the main oscillator.
@@ -89,44 +90,50 @@
 /* PLL0.  PLL0 is used to generate the CPU clock divider input (PLLCLK).
  *
  *  Source clock:               Main oscillator
- *  PLL0 Multiplier value (M):  20 
- *  PLL0 Pre-divider value (N): 1
+ *  PLL0 Multiplier value (M):  10
+ *  PLL0 Pre-divider value (P): 1
  *
- *  PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz
+ *  PLL0CLK = (M * SYSCLK) = 120MHz
  */
 
 #undef CONFIG_LPC17_PLL0
 #define CONFIG_LPC17_PLL0          1
 #define BOARD_CLKSRCSEL_VALUE      SYSCON_CLKSRCSEL_MAIN
 
-#define BOARD_PLL0CFG_MSEL         20
+#define BOARD_PLL0CFG_MSEL         10
 #define BOARD_PLL0CFG_PSEL         1
 #define BOARD_PLL0CFG_VALUE \
   (((BOARD_PLL0CFG_MSEL-1) << SYSCON_PLLCFG_MSEL_SHIFT) | \
    ((BOARD_PLL0CFG_PSEL-1) << SYSCON_PLLCFG_PSEL_SHIFT))
 
-/* PLL1 -- Not used. */
+#ifdef (CONFIG_LPC17_USBHOST || CONFIG_LPC17_USBDEV)
+/* PLL1 : PLL1 is used to generate clock for the USB */
 
-#undef CONFIG_LPC17_PLL1
-#define BOARD_PLL1CFG_MSEL         36
-#define BOARD_PLL1CFG_NSEL         1
-#define BOARD_PLL1CFG_VALUE \
-  (((BOARD_PLL1CFG_MSEL-1) << SYSCON_PLL1CFG_MSEL_SHIFT) | \
-   ((BOARD_PLL1CFG_NSEL-1) << SYSCON_PLL1CFG_NSEL_SHIFT))
+ #undef CONFIG_LPC17_PLL1
+ #define CONFIG_LPC17_PLL1          1
+ #define BOARD_PLL1CFG_MSEL         4
+ #define BOARD_PLL1CFG_PSEL         2
+ #define BOARD_PLL1CFG_VALUE \
+  (((BOARD_PLL1CFG_MSEL-1) << SYSCON_PLLCFG_MSEL_SHIFT) | \
+   ((BOARD_PLL1CFG_NSEL-1) << SYSCON_PLLCFG_PSEL_SHIFT))
 
-/* USB divider.  This divider is used when PLL1 is not enabled to get the
- * USB clock from PLL0:
+ /* USB divider.  The output of the PLL is used as the USB clock
  *
- *  USBCLK = PLL0CLK / 10 = 48MHz
+ *  USBCLK = PLL1CLK = (SYSCLK * 4)  = 48MHz
  */
 
-#define BOARD_USBCLKCFG_VALUE      SYSCON_USBCLKCFG_DIV10
+#define BOARD_USBCLKCFG_VALUE      (SYSCON_USBCLKSEL_USBDIV_DIV1 | \
+                                    SYSCON_USBCLKSEL_USBSEL_PLL1)
+#endif
 
 /* FLASH Configuration */
 
 #undef  CONFIG_LP17_FLASH
 #define CONFIG_LP17_FLASH          1
-#define BOARD_FLASHCFG_VALUE       0x0000303a
+
+/* Flash access use 6 CPU clocks - Safe for any allowed conditions */
+
+#define BOARD_FLASHCFG_VALUE       SYSCON_FLASHCFG_TIM_5
 
 /* Ethernet configuration */