Fix Cortex-M3 nested interrupt hard fault

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3119 42af7a65-404d-4744-a932-0658087f49c3

8 files changed, 53 insertions, 29 deletions

diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog
index c2223cc5f..8876505d6 100644
--- a/nuttx/ChangeLog
+++ b/nuttx/ChangeLog
@@ -1340,5 +1340,11 @@
 	* sched/timer_settime.c - Fix an error in set-up of one-shot timer.  It was
 	  using the repititive timer value (which is zero in the one-shot case,
 	  always resulting in a 10Ms timer!  Found and fixed by Wilton Tong.
+	* arch/arm/src/lpc17xx/lpc17_vector.S, stm32/stm32_vector.S, lm3s/lm3s_vector.S,
+	  sam3u/sam3u_vector.S -- Fixed a hard fault problem that can occur if certain
+	  types of interrupts are pending at the time another interrupt returns
+	  (SYSTICK).  This has not been verified on all plaform, but is a critical
+	  fixed that is needed by all Cortex-M3 NuttX users.
+
 
 
diff --git a/nuttx/Documentation/NuttX.html b/nuttx/Documentation/NuttX.html
index 77473f253..5f5ee193b 100644
--- a/nuttx/Documentation/NuttX.html
+++ b/nuttx/Documentation/NuttX.html
@@ -8,7 +8,7 @@
   <tr align="center" bgcolor="#e4e4e4">
     <td>
       <h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
-      <p>Last Updated: November 17, 2010</p>
+      <p>Last Updated: November 19, 2010</p>
     </td>
   </tr>
 </table>
@@ -1989,6 +1989,11 @@ nuttx-5.14 2010-xx-xx Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;
 	* sched/timer_settime.c - Fix an error in set-up of one-shot timer.  It was
 	  using the repititive timer value (which is zero in the one-shot case,
 	  always resulting in a 10Ms timer!  Found and fixed by Wilton Tong.
+	* arch/arm/src/lpc17xx/lpc17_vector.S, stm32/stm32_vector.S, lm3s/lm3s_vector.S,
+	  sam3u/sam3u_vector.S -- Fixed a hard fault problem that can occur if certain
+	  types of interrupts are pending at the time another interrupt returns
+	  (SYSTICK).  This has not been verified on all plaform, but is a critical
+	  fixed that is needed by all Cortex-M3 NuttX users.
 
 pascal-2.1 2010-xx-xx Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;
 
diff --git a/nuttx/arch/arm/include/cortexm3/irq.h b/nuttx/arch/arm/include/cortexm3/irq.h
index de38585c3..3f731385b 100644
--- a/nuttx/arch/arm/include/cortexm3/irq.h
+++ b/nuttx/arch/arm/include/cortexm3/irq.h
@@ -244,7 +244,7 @@ static inline void setbasepri(uint32_t basepri)
       : "memory");
 }
 
-/* Get IPSR */
+/* Get/set IPSR */
 
 static inline uint32_t getipsr(void)
 {
@@ -258,6 +258,16 @@ static inline uint32_t getipsr(void)
   return ipsr;
 }
 
+static inline void setipsr(uint32_t ipsr)
+{
+  __asm__ __volatile__
+    (
+      "\tmsr ipsr, %0\n"
+      :
+      : "r" (ipsr)
+      : "memory");
+}
+
 /* SVC system call */
 
 static inline void svcall(uint32_t cmd, uint32_t arg)
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_vectors.S b/nuttx/arch/arm/src/lm3s/lm3s_vectors.S
index 5d6f7962e..b88b52c8b 100644
--- a/nuttx/arch/arm/src/lm3s/lm3s_vectors.S
+++ b/nuttx/arch/arm/src/lm3s/lm3s_vectors.S
@@ -607,7 +607,7 @@ lm3s_irqcommon:
 	 * values to the stack.

 	 */

 

-        add	r1, r0, #SW_XCPT_SIZE	/* R1=Address of HW save area in reg array */

+    add	r1, r0, #SW_XCPT_SIZE	/* R1=Address of HW save area in reg array */

 	ldmia	r1, {r4-r11}		/* Fetch eight registers in HW save area */

 	ldr	r1, [r0, #(4*REG_SP)]	/* R1=Value of SP before interrupt */

 	stmdb	r1!, {r4-r11}		/* Store eight registers in HW save area */

@@ -622,17 +622,18 @@ lm3s_irqcommon:
 2:

 	msr	msp, r1			/* Recover the return MSP value */

 

-	/* Do we need to restore interrupts? */

+	/* Restore the interrupt state.  Preload r14 with the special return

+	 * value first (so that the return actually occurs with interrupts

+	 * still disabled).

+	 */

 

-	tst	r3, #1			/* PRIMASK bit 1=1 means that interrupts are masked */

-	bne	3f

-	cpsie	i			/* Restore interrupts */

+	ldr	r14, =EXC_RETURN	/* Load the special value */

+	msr	primask, r3		/* Restore interrupts */

 

 	/* Always return with R14 containing the special value that will: (1)

 	 * return to thread mode, and (2) continue to use the MSP

 	 */

-3:

-	ldr	r14, =EXC_RETURN	/* Load the special value */

+

 	bx	r14			/* And return */

 	.size	handlers, .-handlers

 

diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c b/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c
index dc9c8b2c6..6742b33a2 100644
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c
@@ -1124,7 +1124,6 @@ static int lpc17_interrupt(int irq, void *context)
           lpc17_putreg(ETH_INT_WKUP, LPC17_ETH_INTCLR);
           EMAC_STAT(priv, wol);
 #         warning "Missing logic"
-          goto intexit;
         }
       else
 #endif
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S b/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S
index ae36da345..ed0f10fad 100755
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S
@@ -295,17 +295,18 @@ lpc17_common:
 2:

 	msr		msp, r1					/* Recover the return MSP value */

 

-	/* Do we need to restore interrupts? Why not just: msr primask, r3 */

+	/* Restore the interrupt state.  Preload r14 with the special return

+	 * value first (so that the return actually occurs with interrupts

+	 * still disabled).

+	 */

 

-	tst		r3, #1					/* PRIMASK bit 1=1 means that interrupts are masked */

-	bne		3f

-	cpsie	i						/* Restore interrupts */

+	ldr		r14, =EXC_RETURN		/* Load the special value */

+	msr		primask, r3				/* Restore interrupts */

 

 	/* Always return with R14 containing the special value that will: (1)

 	 * return to thread mode, and (2) continue to use the MSP

 	 */

-3:

-	ldr		r14, =EXC_RETURN		/* Load the special value */

+

 	bx		r14						/* And return */

 	.size	handlers, .-handlers

 

diff --git a/nuttx/arch/arm/src/sam3u/sam3u_vectors.S b/nuttx/arch/arm/src/sam3u/sam3u_vectors.S
index efa7e0a55..4411cc5b5 100755
--- a/nuttx/arch/arm/src/sam3u/sam3u_vectors.S
+++ b/nuttx/arch/arm/src/sam3u/sam3u_vectors.S
@@ -284,19 +284,20 @@ sam3u_common:
 1:

 	ldmia	r1!, {r2-r11}			/* Recover R4-R11 + 2 temp values */

 2:

-	msr		msp, r1					/* Recover the return MSP value */

+	msr	msp, r1					/* Recover the return MSP value */

 

-	/* Do we need to restore interrupts? */

+	/* Restore the interrupt state.  Preload r14 with the special return

+	 * value first (so that the return actually occurs with interrupts

+	 * still disabled).

+	 */

 

-	tst		r3, #1					/* PRIMASK bit 1=1 means that interrupts are masked */

-	bne		3f

-	cpsie	i						/* Restore interrupts */

+	ldr		r14, =EXC_RETURN		/* Load the special value */

+	msr		primask, r3				/* Restore interrupts */

 

 	/* Always return with R14 containing the special value that will: (1)

 	 * return to thread mode, and (2) continue to use the MSP

 	 */

-3:

-	ldr		r14, =EXC_RETURN		/* Load the special value */

+

 	bx		r14						/* And return */

 	.size	handlers, .-handlers

 

diff --git a/nuttx/arch/arm/src/stm32/stm32_vectors.S b/nuttx/arch/arm/src/stm32/stm32_vectors.S
index 7d119f326..e0055962e 100644
--- a/nuttx/arch/arm/src/stm32/stm32_vectors.S
+++ b/nuttx/arch/arm/src/stm32/stm32_vectors.S
@@ -478,17 +478,18 @@ stm32_common:
 2:

 	msr		msp, r1					/* Recover the return MSP value */

 

-	/* Do we need to restore interrupts? */

+	/* Restore the interrupt state.  Preload r14 with the special return

+	 * value first (so that the return actually occurs with interrupts

+	 * still disabled).

+	 */

 

-	tst		r3, #1					/* PRIMASK bit 1=1 means that interrupts are masked */

-	bne		3f

-	cpsie	i						/* Restore interrupts */

+	ldr		r14, =EXC_RETURN		/* Load the special value */

+	msr		primask, r3				/* Restore interrupts */

 

 	/* Always return with R14 containing the special value that will: (1)

 	 * return to thread mode, and (2) continue to use the MSP

 	 */

-3:

-	ldr		r14, =EXC_RETURN		/* Load the special value */

+

 	bx		r14						/* And return */

 	.size	handlers, .-handlers