PIC32, need to clear SW interrupt bit in CAUSE register

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4218 42af7a65-404d-4744-a932-0658087f49c3

1 files changed, 12 insertions, 3 deletions

diff --git a/nuttx/arch/mips/src/mips32/up_swint0.c b/nuttx/arch/mips/src/mips32/up_swint0.c
index 443f81cfc..6929d0b12 100644
--- a/nuttx/arch/mips/src/mips32/up_swint0.c
+++ b/nuttx/arch/mips/src/mips32/up_swint0.c
@@ -45,9 +45,11 @@
 #include <assert.h>
 #include <debug.h>
 
-#include <arch/irq.h>
 #include <nuttx/sched.h>
 
+#include <arch/irq.h>
+#include <arch/mips32/cp0.h>
+
 #include "up_internal.h"
 
 /****************************************************************************
@@ -268,6 +270,7 @@ static inline void dispatch_syscall(uint32_t *regs)
 int up_swint0(int irq, FAR void *context)
 {
   uint32_t *regs = (uint32_t*)context;
+  uint32_t cause;
 
   DEBUGASSERT(regs && regs == current_regs);
 
@@ -359,9 +362,15 @@ int up_swint0(int irq, FAR void *context)
     }
 #endif
 
-  /* Clear the pending software interrupt 0 */
+  /* Clear the pending software interrupt 0 in the PIC32 interrupt block */
  
   up_clrpend_irq(PIC32MX_IRQSRC_CS0);
-  
+
+  /* And reset the software interrupt bit in the MIPS CAUSE register */
+
+  cause  = cp0_getcause();
+  cause &= ~CP0_CAUSE_IP0;
+  cp0_putcause(cause);
+
   return OK;
 }