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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-09-18 12:34:43 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-09-18 12:34:43 +0000 |
| commit | 7ba198934e41f5283467203549a14bbfdc2e0758 (patch) | |
| tree | bca8ed262f966b491eee096aa19fb4b456378f82 /nuttx | |
| parent | 68e8befbc94818cc60bbfd4fb3f8f556e76ecba2 (diff) | |
| download | px4-nuttx-7ba198934e41f5283467203549a14bbfdc2e0758.tar.gz px4-nuttx-7ba198934e41f5283467203549a14bbfdc2e0758.tar.bz2 px4-nuttx-7ba198934e41f5283467203549a14bbfdc2e0758.zip | |
Fix ording of bytes in ENC28J60 MAC address; Web server refactoring from Kate
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5159 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx')
| -rw-r--r-- | nuttx/drivers/net/enc28j60.c | 23 | ||||
| -rw-r--r-- | nuttx/drivers/net/enc28j60.h | 6 |
2 files changed, 18 insertions, 11 deletions
diff --git a/nuttx/drivers/net/enc28j60.c b/nuttx/drivers/net/enc28j60.c index bf6d89537..3800cd019 100644 --- a/nuttx/drivers/net/enc28j60.c +++ b/nuttx/drivers/net/enc28j60.c @@ -2244,14 +2244,21 @@ static void enc_pwrfull(FAR struct enc_driver_s *priv) static void enc_setmacaddr(FAR struct enc_driver_s *priv) { - /* Program the hardware with it's MAC address (for filtering) */ - - enc_wrbreg(priv, ENC_MAADR1, priv->dev.d_mac.ether_addr_octet[5]); - enc_wrbreg(priv, ENC_MAADR2, priv->dev.d_mac.ether_addr_octet[4]); - enc_wrbreg(priv, ENC_MAADR3, priv->dev.d_mac.ether_addr_octet[3]); - enc_wrbreg(priv, ENC_MAADR4, priv->dev.d_mac.ether_addr_octet[2]); - enc_wrbreg(priv, ENC_MAADR5, priv->dev.d_mac.ether_addr_octet[1]); - enc_wrbreg(priv, ENC_MAADR6, priv->dev.d_mac.ether_addr_octet[0]); + /* Program the hardware with it's MAC address (for filtering). + * MAADR1 MAC Address Byte 1 (MAADR<47:40>), OUI Byte 1 + * MAADR2 MAC Address Byte 2 (MAADR<39:32>), OUI Byte 2 + * MAADR3 MAC Address Byte 3 (MAADR<31:24>), OUI Byte 3 + * MAADR4 MAC Address Byte 4 (MAADR<23:16>) + * MAADR5 MAC Address Byte 5 (MAADR<15:8>) + * MAADR6 MAC Address Byte 6 (MAADR<7:0>) + */ + + enc_wrbreg(priv, ENC_MAADR1, priv->dev.d_mac.ether_addr_octet[0]); + enc_wrbreg(priv, ENC_MAADR2, priv->dev.d_mac.ether_addr_octet[1]); + enc_wrbreg(priv, ENC_MAADR3, priv->dev.d_mac.ether_addr_octet[2]); + enc_wrbreg(priv, ENC_MAADR4, priv->dev.d_mac.ether_addr_octet[3]); + enc_wrbreg(priv, ENC_MAADR5, priv->dev.d_mac.ether_addr_octet[4]); + enc_wrbreg(priv, ENC_MAADR6, priv->dev.d_mac.ether_addr_octet[5]); } /**************************************************************************** diff --git a/nuttx/drivers/net/enc28j60.h b/nuttx/drivers/net/enc28j60.h index dab9cc5cf..446ca8e3e 100644 --- a/nuttx/drivers/net/enc28j60.h +++ b/nuttx/drivers/net/enc28j60.h @@ -304,7 +304,7 @@ #define ENC_MAADR3 REGADDR(0x02, 3, 1) /* MAC Address Byte 3 (MAADR<31:24>), OUI Byte 3 */ #define ENC_MAADR4 REGADDR(0x03, 3, 1) /* MAC Address Byte 4 (MAADR<23:16>) */ #define ENC_MAADR1 REGADDR(0x04, 3, 1) /* MAC Address Byte 1 (MAADR<47:40>), OUI Byte 1 */ -#define ENC_MAADR2 REGADDR(0x05, 3, 1) /* MAC Address Byte 2 (MAADR<39:32>), OUI Byte */ +#define ENC_MAADR2 REGADDR(0x05, 3, 1) /* MAC Address Byte 2 (MAADR<39:32>), OUI Byte 2 */ #define ENC_EBSTSD REGADDR(0x06, 3, 0) /* Built-in Self-Test Fill Seed (EBSTSD<7:0>) */ #define ENC_EBSTCON REGADDR(0x07, 3, 0) /* Built-in Self-Test Control */ #define ENC_EBSTCSL REGADDR(0x08, 3, 0) /* Built-in Self-Test Checksum Low Byte (EBSTCS<7:0>) */ @@ -361,11 +361,11 @@ /* PHY Control Register 1 Register Bit Definitions */ #define PHCON1_PDPXMD (1 << 8) /* Bit 8: PHY Power-Down */ -#define PHCON1_PPWRSV (1 << 11) /* Bit 11: PHY Power-Down */ +#define PHCON1_PPWRSV (1 << 11) /* Bit 11: PHY Power Save */ #define PHCON1_PLOOPBK (1 << 14) /* Bit 14: PHY Loopback */ #define PHCON1_PRST (1 << 15) /* Bit 15: PHY Software Reset */ -/* HY Status 1 Register Bit Definitions */ +/* PHY Status 1 Register Bit Definitions */ #define PHSTAT1_JBSTAT (1 << 1) /* Bit 1: PHY Latching Jabber Status */ #define PHSTAT1_LLSTAT (1 << 2) /* Bit 2: PHY Latching Link Status */ |