Adding support of PIC32MX5xx/6xx/7xx families

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4035 42af7a65-404d-4744-a932-0658087f49c3
author: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> 2011-10-10 18:42:36 +0000
committer: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> 2011-10-10 18:42:36 +0000
commit: 825cd6c478c17dc00135182595c796fcd023854e (patch)
tree: b84f2666b201df856d825d7e2444c0df24c463be /nuttx
parent: ff641f36093e5a01fed6f896ba0b6a1f7969144f (diff)
download: px4-nuttx-825cd6c478c17dc00135182595c796fcd023854e.tar.gz
px4-nuttx-825cd6c478c17dc00135182595c796fcd023854e.tar.bz2
px4-nuttx-825cd6c478c17dc00135182595c796fcd023854e.zip
14 files changed, 619 insertions, 255 deletions
diff --git a/nuttx/arch/mips/include/pic32mx/chip.h b/nuttx/arch/mips/include/pic32mx/chip.h
index 07ba3c69a..f29f10512 100644
--- a/nuttx/arch/mips/include/pic32mx/chip.h
+++ b/nuttx/arch/mips/include/pic32mx/chip.h
@@ -63,7 +63,8 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       0   /* No programmable DMA channels */
 #  define CHIP_NUSBDMACHAN  0
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  undef  CHIP_VRFSEL           /* No comparator voltage reference selection */
+
 #  undef  CHIP_TRACE            /* No trace capability */
 #  define CHIP_NUARTS       2   /* 2 UARTS */
 #  define CHIP_UARTFIFOD    4
@@ -92,7 +93,8 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       0   /* No programmable DMA channels */
 #  define CHIP_NUSBDMACHAN  0
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  undef  CHIP_VRFSEL           /* No comparator voltage reference selection */
+
 #  undef  CHIP_TRACE            /* No trace capability */
 #  define CHIP_NUARTS       2   /* 2 UARTS */
 #  define CHIP_UARTFIFOD    4
@@ -121,7 +123,8 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       0   /* No programmable DMA channels */
 #  define CHIP_NUSBDMACHAN  0
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  undef  CHIP_VRFSEL           /* No comparator voltage reference selection */
+
 #  undef  CHIP_TRACE            /* No trace capability */
 #  define CHIP_NUARTS         2   /* 2 UARTS */
 #  define CHIP_UARTFIFOD    4
@@ -150,7 +153,8 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       4   /* 4 programmable DMA channels */
 #  define CHIP_NUSBDMACHAN  0
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  undef  CHIP_VRFSEL           /* No comparator voltage reference selection */
+
 #  undef  CHIP_TRACE            /* No trace capability */
 #  define CHIP_NUARTS         2   /* 2 UARTS */
 #  define CHIP_UARTFIFOD    4
@@ -179,7 +183,8 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       4   /* 4 programmable DMA channels */
 #  define CHIP_NUSBDMACHAN  0
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  undef  CHIP_VRFSEL           /* No comparator voltage reference selection */
+
 #  undef  CHIP_TRACE            /* No trace capability */
 #  define CHIP_NUARTS         2   /* 2 UARTS */
 #  define CHIP_UARTFIFOD    4
@@ -208,7 +213,8 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       4   /* 4 programmable DMA channels */
 #  define CHIP_NUSBDMACHAN  0
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  undef  CHIP_VRFSEL           /* No comparator voltage reference selection */
+
 #  undef  CHIP_TRACE            /* No trace capability */
 #  define CHIP_NUARTS         2   /* 2 UARTS */
 #  define CHIP_UARTFIFOD    4
@@ -237,7 +243,8 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       0   /* No programmable DMA channels */
 #  define CHIP_NUSBDMACHAN  0
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  undef  CHIP_VRFSEL           /* No comparator voltage reference selection */
+
 #  undef  CHIP_TRACE            /* No trace capability */
 #  define CHIP_NUARTS         2   /* 2 UARTS */
 #  define CHIP_UARTFIFOD    4
@@ -266,7 +273,8 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       4   /* 4 programmable DMA channels */
 #  define CHIP_NUSBDMACHAN  0
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  undef  CHIP_VRFSEL           /* No comparator voltage reference selection */
+
 #  undef  CHIP_TRACE            /* No trace capability */
 #  define CHIP_NUARTS       2   /* 2 UARTS */
 #  define CHIP_UARTFIFOD    4
@@ -295,7 +303,8 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       4   /* 4 programmable DMA channels */
 #  define CHIP_NUSBDMACHAN  0
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  undef  CHIP_VRFSEL           /* No comparator voltage reference selection */
+
 #  define CHIP_TRACE        1   /* Have trace capability */
 #  define CHIP_NUARTS       2   /* 2 UARTS */
 #  define CHIP_UARTFIFOD    4
@@ -324,7 +333,8 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       4   /* 4 programmable DMA channels */
 #  define CHIP_NUSBDMACHAN  0
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  undef  CHIP_VRFSEL           /* No comparator voltage reference selection */
+
 #  define CHIP_TRACE        1   /* Have trace capability */
 #  define CHIP_NUARTS       2   /* 2 UARTS */
 #  define CHIP_UARTFIFOD    4
@@ -353,7 +363,8 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       0   /* No programmable DMA channels */
 #  define CHIP_NUSBDMACHAN  2
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  undef  CHIP_VRFSEL           /* No comparator voltage reference selection */
+
 #  undef  CHIP_TRACE            /* No trace capability */
 #  define CHIP_NUARTS       2   /* 2 UARTS */
 #  define CHIP_UARTFIFOD    4
@@ -382,7 +393,8 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       4   /* 4 programmable DMA channels */
 #  define CHIP_NUSBDMACHAN  2
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  undef  CHIP_VRFSEL           /* No comparator voltage reference selection */
+
 #  undef  CHIP_TRACE            /* No trace capability */
 #  define CHIP_NUARTS       2   /* 2 UARTS */
 #  define CHIP_UARTFIFOD    4
@@ -411,7 +423,8 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       4   /* 4 programmable DMA channels */
 #  define CHIP_NUSBDMACHAN  2
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  undef  CHIP_VRFSEL           /* No comparator voltage reference selection */
+
 #  undef  CHIP_TRACE            /* No trace capability */
 #  define CHIP_NUARTS       2   /* 2 UARTS */
 #  define CHIP_UARTFIFOD    4
@@ -440,7 +453,8 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       4   /* 4 programmable DMA channels */
 #  define CHIP_NUSBDMACHAN  2
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  undef  CHIP_VRFSEL           /* No comparator voltage reference selection */
+
 #  undef  CHIP_TRACE            /* No trace capability */
 #  define CHIP_NUARTS       2   /* 2 UARTS */
 #  define CHIP_UARTFIFOD    4
@@ -469,7 +483,8 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       4   /* 4 programmable DMA channels */
 #  define CHIP_NUSBDMACHAN  2
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  undef  CHIP_VRFSEL           /* No comparator voltage reference selection */
+
 #  undef  CHIP_TRACE            /* No trace capability */
 #  define CHIP_NUARTS       2   /* 2 UARTS */
 #  define CHIP_UARTFIFOD    4
@@ -498,7 +513,8 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       4   /* 4 programmable DMA channels */
 #  define CHIP_NUSBDMACHAN  2
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  undef  CHIP_VRFSEL           /* No comparator voltage reference selection */
+
 #  define CHIP_TRACE        1   /* Have trace capability */
 #  define CHIP_NUARTS       2   /* 2 UARTS */
 #  define CHIP_UARTFIFOD    4
@@ -527,7 +543,8 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       4   /* 4 programmable DMA channels */
 #  define CHIP_NUSBDMACHAN  2
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  undef  CHIP_VRFSEL           /* No comparator voltage reference selection */
+
 #  define CHIP_TRACE        1   /* Have trace capability */
 #  define CHIP_NUARTS       2   /* 2 UARTS */
 #  define CHIP_UARTFIFOD    4
@@ -556,7 +573,7 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       4   /* 4 programmable DMA channels (4 dedicated) */
 #  define CHIP_NUSBDMACHAN  tbd
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  define CHIP_VRFSEL       1   /* Have comparator voltage reference selection */
 #  undef  CHIP_TRACE            /* No trace capability */
 #  define CHIP_NUARTS       6   /* 6 UARTS */
 #  define CHIP_UARTFIFOD    tbd
@@ -585,7 +602,7 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       4   /* 4 programmable DMA channels (4 dedicated) */
 #  define CHIP_NUSBDMACHAN  tbd
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  define CHIP_VRFSEL       1   /* Have comparator voltage reference selection */
 #  undef  CHIP_TRACE            /* No trace capability */
 #  define CHIP_NUARTS       6   /* 6 UARTS */
 #  define CHIP_UARTFIFOD    tbd
@@ -614,7 +631,7 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       4   /* 4 programmable DMA channels (4 dedicated) */
 #  define CHIP_NUSBDMACHAN  tbd
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  define CHIP_VRFSEL       1   /* Have comparator voltage reference selection */
 #  undef  CHIP_TRACE            /* No trace capability */
 #  define CHIP_NUARTS       6   /* 6 UARTS */
 #  define CHIP_UARTFIFOD    tbd
@@ -643,7 +660,7 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       8   /* 8 programmable DMA channels (4 dedicated) */
 #  define CHIP_NUSBDMACHAN  tbd
-#  undef  CHIP_CVR              /* No comparator voltage reference */
+#  undef  CHIP_VRFSEL           /* No comparator voltage reference selection */
 #  undef  CHIP_TRACE            /* No trace capability */
 #  define CHIP_NUARTS       6   /* 6 UARTS */
 #  define CHIP_UARTFIFOD    tbd
@@ -672,7 +689,7 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       8   /* 8 programmable DMA channels (4 dedicated) */
 #  define CHIP_NUSBDMACHAN  tbd
-#  undef  CHIP_CVR              /* No comparator voltage reference */
+#  undef  CHIP_VRFSEL           /* No comparator voltage reference selection */
 #  undef  CHIP_TRACE            /* No trace capability */
 #  define CHIP_NUARTS       6   /* 6 UARTS */
 #  define CHIP_UARTFIFOD    tbd
@@ -701,7 +718,7 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       4   /* 4 programmable DMA channels (4 dedicated) */
 #  define CHIP_NUSBDMACHAN  tbd
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  define CHIP_VRFSEL       1   /* Have comparator voltage reference selection */
 #  define CHIP_TRACE        1   /* Have trace capability */
 #  define CHIP_NUARTS       6   /* 6 UARTS */
 #  define CHIP_UARTFIFOD    tbd
@@ -730,7 +747,7 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       4   /* 4 programmable DMA channels (4 dedicated) */
 #  define CHIP_NUSBDMACHAN  tbd
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  define CHIP_VRFSEL       1   /* Have comparator voltage reference selection */
 #  define CHIP_TRACE        1   /* Have trace capability */
 #  define CHIP_NUARTS       6   /* 6 UARTS */
 #  define CHIP_UARTFIFOD    tbd
@@ -759,7 +776,7 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       4   /* 4 programmable DMA channels (4 dedicated) */
 #  define CHIP_NUSBDMACHAN  tbd
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  define CHIP_VRFSEL       1   /* Have comparator voltage reference selection */
 #  define CHIP_TRACE        1   /* Have trace capability */
 #  define CHIP_NUARTS       6   /* 6 UARTS */
 #  define CHIP_UARTFIFOD    tbd
@@ -788,7 +805,7 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       8   /* 8 programmable DMA channels (4 dedicated) */
 #  define CHIP_NUSBDMACHAN  tbd
-#  undef  CHIP_CVR              /* No comparator voltage reference */
+#  undef  CHIP_VRFSEL           /* No comparator voltage reference selection */
 #  define CHIP_TRACE        1   /* Have trace capability */
 #  define CHIP_NUARTS       6   /* 6 UARTS */
 #  define CHIP_UARTFIFOD    tbd
@@ -817,7 +834,7 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       8   /* 8 programmable DMA channels (4 dedicated) */
 #  define CHIP_NUSBDMACHAN  tbd
-#  undef  CHIP_CVR              /* No comparator voltage reference */
+#  undef  CHIP_VRFSEL           /* No comparator voltage reference selection */
 #  define CHIP_TRACE        1   /* Have trace capability */
 #  define CHIP_NUARTS       6   /* 6 UARTS */
 #  define CHIP_UARTFIFOD    tbd
@@ -846,7 +863,7 @@
 #  define CHIP_NOC          5   /* 5 output compare */   /* 5 output compare */
 #  define CHIP_NDMACH       4   /* 4 programmable DMA channels (4 dedicated) */
 #  define CHIP_NUSBDMACHAN  tbd
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  define CHIP_VRFSEL       1   /* Have comparator voltage reference selection */
 #  undef  CHIP_TRACE            /* No trace capability */
 #  define CHIP_NUARTS       6   /* 6 UARTS */
 #  define CHIP_UARTFIFOD    tbd
@@ -857,7 +874,7 @@
 #  define CHIP_NCM          2   /* 2 Comparators */
 #  define CHIP_PMP          1   /* Have parallel master port */
 #  define CHIP_PSP          1   /* Have parallel slave port */
-#  define CHIP_NETHERNET    1   /* 1 Ethernett interface */
+#  define CHIP_NETHERNET    1   /* 1 Ethernet interface */
 #  define CHIP_JTAG
 #elif defined(CONFIG_ARCH_CHIP_PIC32MX664F128H)
 #  undef  CHIP_PIC32MX3
@@ -875,7 +892,7 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       4   /* 4 programmable DMA channels (4 dedicated) */
 #  define CHIP_NUSBDMACHAN  tbd
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  define CHIP_VRFSEL       1   /* Have comparator voltage reference selection */
 #  undef  CHIP_TRACE            /* No trace capability */
 #  define CHIP_NUARTS       6   /* 6 UARTS */
 #  define CHIP_UARTFIFOD    tbd
@@ -886,7 +903,7 @@
 #  define CHIP_NCM          2   /* 2 Comparators */
 #  define CHIP_PMP          1   /* Have parallel master port */
 #  define CHIP_PSP          1   /* Have parallel slave port */
-#  define CHIP_NETHERNET    1   /* 1 Ethernett interface */
+#  define CHIP_NETHERNET    1   /* 1 Ethernet interface */
 #  define CHIP_JTAG
 #elif defined(CONFIG_ARCH_CHIP_PIC32MX675F256H)
 #  undef  CHIP_PIC32MX3
@@ -904,7 +921,7 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       8   /* 8 programmable DMA channels (4 dedicated) */
 #  define CHIP_NUSBDMACHAN  tbd
-#  undef  CHIP_CVR              /* No comparator voltage reference */
+#  undef  CHIP_VRFSEL           /* No comparator voltage reference selection */
 #  undef  CHIP_TRACE            /* No trace capability */
 #  define CHIP_NUARTS       6   /* 6 UARTS */
 #  define CHIP_UARTFIFOD    tbd
@@ -915,7 +932,7 @@
 #  define CHIP_NCM          2   /* 2 Comparators */
 #  define CHIP_PMP          1   /* Have parallel master port */
 #  define CHIP_PSP          1   /* Have parallel slave port */
-#  define CHIP_NETHERNET    1   /* 1 Ethernett interface */
+#  define CHIP_NETHERNET    1   /* 1 Ethernet interface */
 #  define CHIP_JTAG
 #elif defined(CONFIG_ARCH_CHIP_PIC32MX675F512H)
 #  undef  CHIP_PIC32MX3
@@ -933,7 +950,7 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       8   /* 8 programmable DMA channels (4 dedicated) */
 #  define CHIP_NUSBDMACHAN  tbd
-#  undef  CHIP_CVR              /* No comparator voltage reference */
+#  undef  CHIP_VRFSEL           /* No comparator voltage reference selection */
 #  undef  CHIP_TRACE            /* No trace capability */
 #  define CHIP_NUARTS       6   /* 6 UARTS */
 #  define CHIP_UARTFIFOD    tbd
@@ -944,7 +961,7 @@
 #  define CHIP_NCM          2   /* 2 Comparators */
 #  define CHIP_PMP          1   /* Have parallel master port */
 #  define CHIP_PSP          1   /* Have parallel slave port */
-#  define CHIP_NETHERNET    1   /* 1 Ethernett interface */
+#  define CHIP_NETHERNET    1   /* 1 Ethernet interface */
 #  define CHIP_JTAG
 #elif defined(CONFIG_ARCH_CHIP_PIC32MX695F512H)
 #  undef  CHIP_PIC32MX3
@@ -962,7 +979,7 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       8   /* 8 programmable DMA channels (4 dedicated) */
 #  define CHIP_NUSBDMACHAN  tbd
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  define CHIP_VRFSEL       1   /* Have comparator voltage reference selection */
 #  undef  CHIP_TRACE            /* No trace capability */
 #  define CHIP_NUARTS       6   /* 6 UARTS */
 #  define CHIP_UARTFIFOD    tbd
@@ -973,7 +990,7 @@
 #  define CHIP_NCM          2   /* 2 Comparators */
 #  define CHIP_PMP          1   /* Have parallel master port */
 #  define CHIP_PSP          1   /* Have parallel slave port */
-#  define CHIP_NETHERNET    1   /* 1 Ethernett interface */
+#  define CHIP_NETHERNET    1   /* 1 Ethernet interface */
 #  define CHIP_JTAG
 #elif defined(CONFIG_ARCH_CHIP_PIC32MX664F064L)
 #  undef  CHIP_PIC32MX3
@@ -991,7 +1008,7 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       4   /* 4 programmable DMA channels (4 dedicated) */
 #  define CHIP_NUSBDMACHAN  tbd
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  define CHIP_VRFSEL       1   /* Have comparator voltage reference selection */
 #  define CHIP_TRACE        1   /* Have trace capability */
 #  define CHIP_NUARTS       6   /* 6 UARTS */
 #  define CHIP_UARTFIFOD    tbd
@@ -1002,7 +1019,7 @@
 #  define CHIP_NCM          2   /* 2 Comparators */
 #  define CHIP_PMP          1   /* Have parallel master port */
 #  define CHIP_PSP          1   /* Have parallel slave port */
-#  define CHIP_NETHERNET    1   /* 1 Ethernett interface */
+#  define CHIP_NETHERNET    1   /* 1 Ethernet interface */
 #  define CHIP_JTAG
 #elif defined(CONFIG_ARCH_CHIP_PIC32MX664F128L)
 #  undef  CHIP_PIC32MX3
@@ -1020,7 +1037,7 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       4   /* 4 programmable DMA channels (4 dedicated) */
 #  define CHIP_NUSBDMACHAN  tbd
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  define CHIP_VRFSEL       1   /* Have comparator voltage reference selection */
 #  define CHIP_TRACE        1   /* Have trace capability */
 #  define CHIP_NUARTS       6   /* 6 UARTS */
 #  define CHIP_UARTFIFOD    tbd
@@ -1031,7 +1048,7 @@
 #  define CHIP_NCM          2   /* 2 Comparators */
 #  define CHIP_PMP          1   /* Have parallel master port */
 #  define CHIP_PSP          1   /* Have parallel slave port */
-#  define CHIP_NETHERNET    1   /* 1 Ethernett interface */
+#  define CHIP_NETHERNET    1   /* 1 Ethernet interface */
 #  define CHIP_JTAG
 #elif defined(CONFIG_ARCH_CHIP_PIC32MX675F256L)
 #  undef  CHIP_PIC32MX3
@@ -1049,7 +1066,7 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       8   /* 8 programmable DMA channels (4 dedicated) */
 #  define CHIP_NUSBDMACHAN  tbd
-#  undef  CHIP_CVR              /* No comparator voltage reference */
+#  undef  CHIP_VRFSEL           /* No comparator voltage reference selection */
 #  define CHIP_TRACE        1   /* Have trace capability */
 #  define CHIP_NUARTS       6   /* 6 UARTS */
 #  define CHIP_UARTFIFOD    tbd
@@ -1060,7 +1077,7 @@
 #  define CHIP_NCM          2   /* 2 Comparators */
 #  define CHIP_PMP          1   /* Have parallel master port */
 #  define CHIP_PSP          1   /* Have parallel slave port */
-#  define CHIP_NETHERNET    1   /* 1 Ethernett interface */
+#  define CHIP_NETHERNET    1   /* 1 Ethernet interface */
 #  define CHIP_JTAG
 #elif defined(CONFIG_ARCH_CHIP_PIC32MX675F512L)
 #  undef  CHIP_PIC32MX3
@@ -1078,7 +1095,7 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       8   /* 8 programmable DMA channels (4 dedicated) */
 #  define CHIP_NUSBDMACHAN  tbd
-#  undef  CHIP_CVR              /* No comparator voltage reference */
+#  undef  CHIP_VRFSEL           /* No comparator voltage reference selection */
 #  define CHIP_TRACE        1   /* Have trace capability */
 #  define CHIP_NUARTS       6   /* 6 UARTS */
 #  define CHIP_UARTFIFOD    tbd
@@ -1089,7 +1106,7 @@
 #  define CHIP_NCM          2   /* 2 Comparators */
 #  define CHIP_PMP          1   /* Have parallel master port */
 #  define CHIP_PSP          1   /* Have parallel slave port */
-#  define CHIP_NETHERNET    1   /* 1 Ethernett interface */
+#  define CHIP_NETHERNET    1   /* 1 Ethernet interface */
 #  define CHIP_JTAG
 #elif defined(CONFIG_ARCH_CHIP_PIC32MX695F512L)
 #  undef  CHIP_PIC32MX3
@@ -1107,7 +1124,7 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       8   /* xx programmable DMA channels (4 dedicated) */
 #  define CHIP_NUSBDMACHAN  tbd
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  define CHIP_VRFSEL       1   /* Have comparator voltage reference selection */
 #  define CHIP_TRACE        1   /* Have trace capability */
 #  define CHIP_NUARTS       6   /* 6 UARTS */
 #  define CHIP_UARTFIFOD    tbd
@@ -1118,7 +1135,7 @@
 #  define CHIP_NCM          2   /* 2 Comparators */
 #  define CHIP_PMP          1   /* Have parallel master port */
 #  define CHIP_PSP          1   /* Have parallel slave port */
-#  define CHIP_NETHERNET    1   /* 1 Ethernett interface */
+#  define CHIP_NETHERNET    1   /* 1 Ethernet interface */
 #  define CHIP_JTAG
 #elif defined(CONFIG_ARCH_CHIP_PIC32MX764F128H)
 #  undef  CHIP_PIC32MX3
@@ -1136,7 +1153,7 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       4   /* 4 programmable DMA channels (6 dedicated) */
 #  define CHIP_NUSBDMACHAN  tbd
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  define CHIP_VRFSEL       1   /* Have comparator voltage reference selection */
 #  undef  CHIP_TRACE            /* No trace capability */
 #  define CHIP_NUARTS       6   /* 6 UARTS */
 #  define CHIP_UARTFIFOD    tbd
@@ -1147,7 +1164,7 @@
 #  define CHIP_NCM          2   /* 2 Comparators */
 #  define CHIP_PMP          1   /* Have parallel master port */
 #  define CHIP_PSP          1   /* Have parallel slave port */
-#  define CHIP_NETHERNET    1   /* 1 Ethernett interface */
+#  define CHIP_NETHERNET    1   /* 1 Ethernet interface */
 #  define CHIP_JTAG
 #elif defined(CONFIG_ARCH_CHIP_PIC32MX775F256H)
 #  undef  CHIP_PIC32MX3
@@ -1165,7 +1182,7 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       8   /* 8 programmable DMA channels (8 dedicated) */
 #  define CHIP_NUSBDMACHAN  tbd
-#  undef  CHIP_CVR              /* No comparator voltage reference */
+#  undef  CHIP_VRFSEL           /* No comparator voltage reference selection */
 #  undef  CHIP_TRACE            /* No trace capability */
 #  define CHIP_NUARTS       6   /* 6 UARTS */
 #  define CHIP_UARTFIFOD    tbd
@@ -1194,7 +1211,7 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       8   /* 8 programmable DMA channels (8 dedicated) */
 #  define CHIP_NUSBDMACHAN  tbd
-#  undef  CHIP_CVR              /* No comparator voltage reference */
+#  undef  CHIP_VRFSEL           /* No comparator voltage reference selection */
 #  undef  CHIP_TRACE            /* No trace capability */
 #  define CHIP_NUARTS       6   /* 6 UARTS */
 #  define CHIP_UARTFIFOD    tbd
@@ -1223,7 +1240,7 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       8   /* 8 programmable DMA channels (8 dedicated) */
 #  define CHIP_NUSBDMACHAN  tbd
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  define CHIP_VRFSEL       1   /* Have comparator voltage reference selection */
 #  undef  CHIP_TRACE            /* No trace capability */
 #  define CHIP_NUARTS       6   /* 6 UARTS */
 #  define CHIP_UARTFIFOD    tbd
@@ -1252,7 +1269,7 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       4   /* 4 programmable DMA channels (6 dedicated) */
 #  define CHIP_NUSBDMACHAN  tbd
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  define CHIP_VRFSEL       1   /* Have comparator voltage reference selection */
 #  define CHIP_TRACE        1   /* Have trace capability */
 #  define CHIP_NUARTS       6   /* 6 UARTS */
 #  define CHIP_UARTFIFOD    tbd
@@ -1281,7 +1298,7 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       8   /* 8 programmable DMA channels (8 dedicated) */
 #  define CHIP_NUSBDMACHAN  tbd
-#  undef  CHIP_CVR              /* No comparator voltage reference */
+#  undef  CHIP_VRFSEL           /* No comparator voltage reference selection */
 #  define CHIP_TRACE        1   /* Have trace capability */
 #  define CHIP_NUARTS       6   /* 6 UARTS */
 #  define CHIP_UARTFIFOD    tbd
@@ -1310,7 +1327,7 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       8   /* 8 programmable DMA channels (8 dedicated) */
 #  define CHIP_NUSBDMACHAN  tbd
-#  undef  CHIP_CVR              /* No comparator voltage reference */
+#  undef  CHIP_VRFSEL           /* No comparator voltage reference selection */
 #  define CHIP_TRACE        1   /* Have trace capability */
 #  define CHIP_NUARTS       6   /* 6 UARTS */
 #  define CHIP_UARTFIFOD    tbd
@@ -1339,7 +1356,7 @@
 #  define CHIP_NOC          5   /* 5 output compare */
 #  define CHIP_NDMACH       8   /* 8 programmable DMA channels (8 dedicated) */
 #  define CHIP_NUSBDMACHAN  tbd
-#  define CHIP_CVR          1   /* Have comparator voltage reference */
+#  define CHIP_VRFSEL       1   /* Have comparator voltage reference selection */
 #  define CHIP_TRACE        1   /* Have trace capability */
 #  define CHIP_NUARTS       6   /* 6 UARTS */
 #  define CHIP_UARTFIFOD    tbd
diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-adc.h b/nuttx/arch/mips/src/pic32mx/pic32mx-adc.h
index e5ebc97fb..5a14b3095 100644
--- a/nuttx/arch/mips/src/pic32mx/pic32mx-adc.h
+++ b/nuttx/arch/mips/src/pic32mx/pic32mx-adc.h
@@ -2,7 +2,7 @@
  * arch/mips/src/pic32mx/pic32mx-adc.h
  *
  *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_ADc_H
-#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_ADc_H
+#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_ADC_H
+#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_ADC_H
 
 /************************************************************************************
  * Included Files
@@ -240,4 +240,4 @@ extern "C" {
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_ADc_H */
+#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_ADC_H */
diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-can.h b/nuttx/arch/mips/src/pic32mx/pic32mx-can.h
new file mode 100644
index 000000000..e644ef69e
--- /dev/null
+++ b/nuttx/arch/mips/src/pic32mx/pic32mx-can.h
@@ -0,0 +1,89 @@
+/****************************************************************************
+ * arch/mips/src/pic32mx/pic32mx-can.h
+ *
+ *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CAN_H
+#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CAN_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "pic32mx-memorymap.h"
+
+/****************************************************************************
+ * Pre-Processor Definitions
+ ****************************************************************************/
+/* Register Offsets *********************************************************/
+
+#warning "To be provided"
+
+/* Register Addresses *******************************************************/
+
+#warning "To be provided"
+
+/* Register Bit-Field Definitions *******************************************/
+
+#warning "To be provided"
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CAN_H */
diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-cvr.h b/nuttx/arch/mips/src/pic32mx/pic32mx-cvr.h
index 1383bfece..f41ea89fb 100644
--- a/nuttx/arch/mips/src/pic32mx/pic32mx-cvr.h
+++ b/nuttx/arch/mips/src/pic32mx/pic32mx-cvr.h
@@ -2,7 +2,7 @@
  * arch/mips/src/pic32mx/pic32mx-cvr.h
  *
  *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -45,8 +45,6 @@
 #include "chip.h"
 #include "pic32mx-memorymap.h"
 
-#ifdef CHIP_CVR
-
 /************************************************************************************
  * Pre-Processor Definitions
  ************************************************************************************/
@@ -74,13 +72,15 @@
 #define CVR_CON_CVRSS             (1 << 4)  /* Bit 4:  CVREF source selection */
 #define CVR_CON_CVRR              (1 << 5)  /* Bit 5:  CVREF range selection */
 #define CVR_CON_CVROE             (1 << 6)  /* Bit 6:  CVREFOUT enable */
-#define CVR_CON_BGSEL_SHIFT       (8)       /* Bits 8-9: Band gap reference source */
-#define CVR_CON_BGSEL_MASK        (3 << CVR_CON_CVR_SHIFT)
-#  define CVR_CON_BGSEL_1p2V      (0 << CVR_CON_CVR_SHIFT) /* IVREF = 1.2V (nominal) */
-#  define CVR_CON_BGSEL_0p6V      (1 << CVR_CON_CVR_SHIFT) /* IVREF = 0.6V (nominal) */
-#  define CVR_CON_BGSEL_0p2V      (2 << CVR_CON_CVR_SHIFT) /* IVREF = 0.2V (nominal) */
-#  define CVR_CON_BGSEL_VREF      (3 << CVR_CON_CVR_SHIFT) /* VREF = VREF+ */
-#define CVR_CON_VREFSEL           (1 << 10) /* Bit 10:  Voltage reference select */
+#ifdef CHIP_VRFSEL
+#  define CVR_CON_BGSEL_SHIFT     (8)       /* Bits 8-9: Band gap reference source */
+#  define CVR_CON_BGSEL_MASK      (3 << CVR_CON_CVR_SHIFT)
+#    define CVR_CON_BGSEL_1p2V    (0 << CVR_CON_CVR_SHIFT) /* IVREF = 1.2V (nominal) */
+#    define CVR_CON_BGSEL_0p6V    (1 << CVR_CON_CVR_SHIFT) /* IVREF = 0.6V (nominal) */
+#    define CVR_CON_BGSEL_0p2V    (2 << CVR_CON_CVR_SHIFT) /* IVREF = 0.2V (nominal) */
+#    define CVR_CON_BGSEL_VREF    (3 << CVR_CON_CVR_SHIFT) /* VREF = VREF+ */
+#  define CVR_CON_VREFSEL         (1 << 10) /* Bit 10:  Voltage reference select */
+#endif
 #define CVR_CON_ON                (1 << 15) /* Bit 15: Comparator voltage reference on */
 
 /************************************************************************************
@@ -110,5 +110,4 @@ extern "C" {
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* CHIP_CVR */
 #endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CVR_H */
diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-devcfg.h b/nuttx/arch/mips/src/pic32mx/pic32mx-devcfg.h
index 03c5acad4..73e761292 100644
--- a/nuttx/arch/mips/src/pic32mx/pic32mx-devcfg.h
+++ b/nuttx/arch/mips/src/pic32mx/pic32mx-devcfg.h
@@ -2,7 +2,7 @@
  * arch/mips/src/pic32mx/pic32mx-devcfg.h
  *
  *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -68,14 +68,23 @@
 #define DEVCFG3_USERID_SHIFT      (0)       /* Bits 0-15: User-defined, readable via ICSP� and JTAG */
 #define DEVCFG3_USERID_MASK       (0xffff << DEVCFG3_USERID_SHIFT)
 #define DEVCFG3_FSRSSEL_SHIFT     (16)      /* Bits 16-18: SRS select */
-#define DEVCFG3_FSRSSEL_MASK      (7 << DEVCFG3_FSRSSEL_SHIFT)
-#define DEVCFG3_FMIIEN            (1 << 24) /* Bit 24: Ethernet MII enable */
-#define DEVCFG3_FETHIO            (1 << 25) /* Bit 25: Ethernet I/O pin selection */
-#define DEVCFG3_FCANIO            (1 << 26) /* Bit 26: CAN I/O pin selection */
-#define DEVCFG3_FSCM1IO           (1 << 29) /* Bit 29: SCM1 pin C selection */
-#define DEVCFG3_FUSBIDIO          (1 << 30) /* Bit 30: USB USBID selection */
-#define DEVCFG3_FVBUSIO           (1 << 31) /* Bit 31: USB VBUSON selection */
-#define DEVCFG3_UNUSED            0x18f80000 /* Bits 19-23, 27-28 */
+
+#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4)
+
+#  define DEVCFG3_UNUSED          0xffff0000 /* Bits 16-31 */
+
+#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
+
+#  define DEVCFG3_FSRSSEL_MASK    (7 << DEVCFG3_FSRSSEL_SHIFT)
+#  define DEVCFG3_FMIIEN          (1 << 24) /* Bit 24: Ethernet MII enable */
+#  define DEVCFG3_FETHIO          (1 << 25) /* Bit 25: Ethernet I/O pin selection */
+#  define DEVCFG3_FCANIO          (1 << 26) /* Bit 26: CAN I/O pin selection */
+#  define DEVCFG3_FSCM1IO         (1 << 29) /* Bit 29: SCM1 pin C selection */
+#  define DEVCFG3_FUSBIDIO        (1 << 30) /* Bit 30: USB USBID selection */
+#  define DEVCFG3_FVBUSIO         (1 << 31) /* Bit 31: USB VBUSON selection */
+#  define DEVCFG3_UNUSED          0x18f80000 /* Bits 19-23, 27-28 */
+
+#endif
 
 /* Device configuration word 2 */
 
diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-dma.h b/nuttx/arch/mips/src/pic32mx/pic32mx-dma.h
index cbe6c6ffe..fd8af3087 100644
--- a/nuttx/arch/mips/src/pic32mx/pic32mx-dma.h
+++ b/nuttx/arch/mips/src/pic32mx/pic32mx-dma.h
@@ -2,7 +2,7 @@
  * arch/mips/src/pic32mx/pic32mx-dma.h
  *
  *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -178,45 +178,47 @@
 #define PIC32MX_DMACH_DATSET(n)       (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_DATSET_OFFSET)
 #define PIC32MX_DMACH_DATINV(n)       (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_DATINV_OFFSET)
 
-#define PIC32MX_DMACH0_CON            (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CON_OFFSET)
-#define PIC32MX_DMACH0_CONCLR         (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CONCLR_OFFSET)
-#define PIC32MX_DMACH0_CONSET         (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CONSET_OFFSET)
-#define PIC32MX_DMACH0_CONINV         (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CONINV_OFFSET)
-#define PIC32MX_DMACH0_ECON           (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_ECON_OFFSET)
-#define PIC32MX_DMACH0_ECONCLR        (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_ECONCLR_OFFSET)
-#define PIC32MX_DMACH0_ECONSET        (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_ECONSET_OFFSET)
-#define PIC32MX_DMACH0_ECONINV        (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_ECONINV_OFFSET)
-#define PIC32MX_DMACH0_INT            (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_INT_OFFSET)
-#define PIC32MX_DMACH0_INTCLR         (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_INTCLR_OFFSET)
-#define PIC32MX_DMACH0_INTSET         (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_INTSET_OFFSET)
-#define PIC32MX_DMACH0_INTINV         (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_INTINV_OFFSET)
-#define PIC32MX_DMACH0_SSA            (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSA_OFFSET)
-#define PIC32MX_DMACH0_SSACLR         (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSACLR_OFFSET)
-#define PIC32MX_DMACH0_SSASET         (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSASET_OFFSET)
-#define PIC32MX_DMACH0_SSAINV         (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSAINV_OFFSET)
-#define PIC32MX_DMACH0_DSA            (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSA_OFFSET)
-#define PIC32MX_DMACH0_DSACLR         (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSACLR_OFFSET)
-#define PIC32MX_DMACH0_DSASET         (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSASET_OFFSET)
-#define PIC32MX_DMACH0_DSAINV         (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSAINV_OFFSET)
-#define PIC32MX_DMACH0_SSIZ           (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSIZ_OFFSET)
-#define PIC32MX_DMACH0_SSIZCLR        (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSIZCLR_OFFSET)
-#define PIC32MX_DMACH0_SSIZSET        (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSIZSET_OFFSET)
-#define PIC32MX_DMACH0_SSIZINV        (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSIZINV_OFFSET)
-#define PIC32MX_DMACH0_DSIZ           (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSIZ_OFFSET)
-#define PIC32MX_DMACH0_DSIZCLR        (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSIZCLR_OFFSET)
-#define PIC32MX_DMACH0_DSIZSET        (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSIZSET_OFFSET)
-#define PIC32MX_DMACH0_DSIZINV        (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSIZINV_OFFSET)
-#define PIC32MX_DMACH0_SPTR           (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SPTR_OFFSET)
-#define PIC32MX_DMACH0_DPTR           (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DPTR_OFFSET)
-#define PIC32MX_DMACH0_CSIZ           (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CSIZ_OFFSET)
-#define PIC32MX_DMACH0_CSIZCLR        (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CSIZCLR_OFFSET)
-#define PIC32MX_DMACH0_CSIZSET        (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CSIZSET_OFFSET)
-#define PIC32MX_DMACH0_CSIZINV        (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CSIZINV_OFFSET)
-#define PIC32MX_DMACH0_CPTR           (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CPTR_OFFSET)
-#define PIC32MX_DMACH0_DAT            (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DAT_OFFSET)
-#define PIC32MX_DMACH0_DATCLR         (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DATCLR_OFFSET)
-#define PIC32MX_DMACH0_DATSET         (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DATSET_OFFSET)
-#define PIC32MX_DMACH0_DATINV         (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DATINV_OFFSET)
+#if CHIP_NDMACH > 0
+#  define PIC32MX_DMACH0_CON          (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CON_OFFSET)
+#  define PIC32MX_DMACH0_CONCLR       (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CONCLR_OFFSET)
+#  define PIC32MX_DMACH0_CONSET       (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CONSET_OFFSET)
+#  define PIC32MX_DMACH0_CONINV       (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CONINV_OFFSET)
+#  define PIC32MX_DMACH0_ECON         (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_ECON_OFFSET)
+#  define PIC32MX_DMACH0_ECONCLR      (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_ECONCLR_OFFSET)
+#  define PIC32MX_DMACH0_ECONSET      (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_ECONSET_OFFSET)
+#  define PIC32MX_DMACH0_ECONINV      (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_ECONINV_OFFSET)
+#  define PIC32MX_DMACH0_INT          (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_INT_OFFSET)
+#  define PIC32MX_DMACH0_INTCLR       (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_INTCLR_OFFSET)
+#  define PIC32MX_DMACH0_INTSET       (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_INTSET_OFFSET)
+#  define PIC32MX_DMACH0_INTINV       (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_INTINV_OFFSET)
+#  define PIC32MX_DMACH0_SSA          (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSA_OFFSET)
+#  define PIC32MX_DMACH0_SSACLR       (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSACLR_OFFSET)
+#  define PIC32MX_DMACH0_SSASET       (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSASET_OFFSET)
+#  define PIC32MX_DMACH0_SSAINV       (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSAINV_OFFSET)
+#  define PIC32MX_DMACH0_DSA          (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSA_OFFSET)
+#  define PIC32MX_DMACH0_DSACLR       (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSACLR_OFFSET)
+#  define PIC32MX_DMACH0_DSASET       (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSASET_OFFSET)
+#  define PIC32MX_DMACH0_DSAINV       (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSAINV_OFFSET)
+#  define PIC32MX_DMACH0_SSIZ         (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSIZ_OFFSET)
+#  define PIC32MX_DMACH0_SSIZCLR      (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSIZCLR_OFFSET)
+#  define PIC32MX_DMACH0_SSIZSET      (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSIZSET_OFFSET)
+#  define PIC32MX_DMACH0_SSIZINV      (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSIZINV_OFFSET)
+#  define PIC32MX_DMACH0_DSIZ         (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSIZ_OFFSET)
+#  define PIC32MX_DMACH0_DSIZCLR      (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSIZCLR_OFFSET)
+#  define PIC32MX_DMACH0_DSIZSET      (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSIZSET_OFFSET)
+#  define PIC32MX_DMACH0_DSIZINV      (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSIZINV_OFFSET)
+#  define PIC32MX_DMACH0_SPTR         (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SPTR_OFFSET)
+#  define PIC32MX_DMACH0_DPTR         (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DPTR_OFFSET)
+#  define PIC32MX_DMACH0_CSIZ         (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CSIZ_OFFSET)
+#  define PIC32MX_DMACH0_CSIZCLR      (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CSIZCLR_OFFSET)
+#  define PIC32MX_DMACH0_CSIZSET      (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CSIZSET_OFFSET)
+#  define PIC32MX_DMACH0_CSIZINV      (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CSIZINV_OFFSET)
+#  define PIC32MX_DMACH0_CPTR         (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CPTR_OFFSET)
+#  define PIC32MX_DMACH0_DAT          (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DAT_OFFSET)
+#  define PIC32MX_DMACH0_DATCLR       (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DATCLR_OFFSET)
+#  define PIC32MX_DMACH0_DATSET       (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DATSET_OFFSET)
+#  define PIC32MX_DMACH0_DATINV       (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DATINV_OFFSET)
+#endif
 
 #if CHIP_NDMACH > 1
 #  define PIC32MX_DMACH1_CON          (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_CON_OFFSET)
@@ -343,41 +345,242 @@
 #  define PIC32MX_DMACH3_DATINV       (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_DATINV_OFFSET)
 #endif
 
+#if CHIP_NDMACH > 4
+#  define PIC32MX_DMACH4_CON          (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_CON_OFFSET)
+#  define PIC32MX_DMACH4_CONCLR       (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_CONCLR_OFFSET)
+#  define PIC32MX_DMACH4_CONSET       (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_CONSET_OFFSET)
+#  define PIC32MX_DMACH4_CONINV       (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_CONINV_OFFSET)
+#  define PIC32MX_DMACH4_ECON         (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_ECON_OFFSET)
+#  define PIC32MX_DMACH4_ECONCLR      (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_ECONCLR_OFFSET)
+#  define PIC32MX_DMACH4_ECONSET      (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_ECONSET_OFFSET)
+#  define PIC32MX_DMACH4_ECONINV      (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_ECONINV_OFFSET)
+#  define PIC32MX_DMACH4_INT          (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_INT_OFFSET)
+#  define PIC32MX_DMACH4_INTCLR       (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_INTCLR_OFFSET)
+#  define PIC32MX_DMACH4_INTSET       (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_INTSET_OFFSET)
+#  define PIC32MX_DMACH4_INTINV       (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_INTINV_OFFSET)
+#  define PIC32MX_DMACH4_SSA          (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_SSA_OFFSET)
+#  define PIC32MX_DMACH4_SSACLR       (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_SSACLR_OFFSET)
+#  define PIC32MX_DMACH4_SSASET       (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_SSASET_OFFSET)
+#  define PIC32MX_DMACH4_SSAINV       (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_SSAINV_OFFSET)
+#  define PIC32MX_DMACH4_DSA          (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DSA_OFFSET)
+#  define PIC32MX_DMACH4_DSACLR       (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DSACLR_OFFSET)
+#  define PIC32MX_DMACH4_DSASET       (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DSASET_OFFSET)
+#  define PIC32MX_DMACH4_DSAINV       (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DSAINV_OFFSET)
+#  define PIC32MX_DMACH4_SSIZ         (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_SSIZ_OFFSET)
+#  define PIC32MX_DMACH4_SSIZCLR      (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_SSIZCLR_OFFSET)
+#  define PIC32MX_DMACH4_SSIZSET      (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_SSIZSET_OFFSET)
+#  define PIC32MX_DMACH4_SSIZINV      (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_SSIZINV_OFFSET)
+#  define PIC32MX_DMACH4_DSIZ         (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DSIZ_OFFSET)
+#  define PIC32MX_DMACH4_DSIZCLR      (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DSIZCLR_OFFSET)
+#  define PIC32MX_DMACH4_DSIZSET      (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DSIZSET_OFFSET)
+#  define PIC32MX_DMACH4_DSIZINV      (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DSIZINV_OFFSET)
+#  define PIC32MX_DMACH4_SPTR         (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_SPTR_OFFSET)
+#  define PIC32MX_DMACH4_DPTR         (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DPTR_OFFSET)
+#  define PIC32MX_DMACH4_CSIZ         (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_CSIZ_OFFSET)
+#  define PIC32MX_DMACH4_CSIZCLR      (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_CSIZCLR_OFFSET)
+#  define PIC32MX_DMACH4_CSIZSET      (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_CSIZSET_OFFSET)
+#  define PIC32MX_DMACH4_CSIZINV      (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_CSIZINV_OFFSET)
+#  define PIC32MX_DMACH4_CPTR         (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_CPTR_OFFSET)
+#  define PIC32MX_DMACH4_DAT          (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DAT_OFFSET)
+#  define PIC32MX_DMACH4_DATCLR       (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DATCLR_OFFSET)
+#  define PIC32MX_DMACH4_DATSET       (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DATSET_OFFSET)
+#  define PIC32MX_DMACH4_DATINV       (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DATINV_OFFSET)
+#endif
+
+#if CHIP_NDMACH > 5
+#  define PIC32MX_DMACH5_CON          (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_CON_OFFSET)
+#  define PIC32MX_DMACH5_CONCLR       (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_CONCLR_OFFSET)
+#  define PIC32MX_DMACH5_CONSET       (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_CONSET_OFFSET)
+#  define PIC32MX_DMACH5_CONINV       (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_CONINV_OFFSET)
+#  define PIC32MX_DMACH5_ECON         (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_ECON_OFFSET)
+#  define PIC32MX_DMACH5_ECONCLR      (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_ECONCLR_OFFSET)
+#  define PIC32MX_DMACH5_ECONSET      (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_ECONSET_OFFSET)
+#  define PIC32MX_DMACH5_ECONINV      (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_ECONINV_OFFSET)
+#  define PIC32MX_DMACH5_INT          (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_INT_OFFSET)
+#  define PIC32MX_DMACH5_INTCLR       (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_INTCLR_OFFSET)
+#  define PIC32MX_DMACH5_INTSET       (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_INTSET_OFFSET)
+#  define PIC32MX_DMACH5_INTINV       (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_INTINV_OFFSET)
+#  define PIC32MX_DMACH5_SSA          (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_SSA_OFFSET)
+#  define PIC32MX_DMACH5_SSACLR       (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_SSACLR_OFFSET)
+#  define PIC32MX_DMACH5_SSASET       (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_SSASET_OFFSET)
+#  define PIC32MX_DMACH5_SSAINV       (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_SSAINV_OFFSET)
+#  define PIC32MX_DMACH5_DSA          (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DSA_OFFSET)
+#  define PIC32MX_DMACH5_DSACLR       (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DSACLR_OFFSET)
+#  define PIC32MX_DMACH5_DSASET       (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DSASET_OFFSET)
+#  define PIC32MX_DMACH5_DSAINV       (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DSAINV_OFFSET)
+#  define PIC32MX_DMACH5_SSIZ         (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_SSIZ_OFFSET)
+#  define PIC32MX_DMACH5_SSIZCLR      (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_SSIZCLR_OFFSET)
+#  define PIC32MX_DMACH5_SSIZSET      (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_SSIZSET_OFFSET)
+#  define PIC32MX_DMACH5_SSIZINV      (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_SSIZINV_OFFSET)
+#  define PIC32MX_DMACH5_DSIZ         (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DSIZ_OFFSET)
+#  define PIC32MX_DMACH5_DSIZCLR      (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DSIZCLR_OFFSET)
+#  define PIC32MX_DMACH5_DSIZSET      (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DSIZSET_OFFSET)
+#  define PIC32MX_DMACH5_DSIZINV      (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DSIZINV_OFFSET)
+#  define PIC32MX_DMACH5_SPTR         (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_SPTR_OFFSET)
+#  define PIC32MX_DMACH5_DPTR         (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DPTR_OFFSET)
+#  define PIC32MX_DMACH5_CSIZ         (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_CSIZ_OFFSET)
+#  define PIC32MX_DMACH5_CSIZCLR      (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_CSIZCLR_OFFSET)
+#  define PIC32MX_DMACH5_CSIZSET      (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_CSIZSET_OFFSET)
+#  define PIC32MX_DMACH5_CSIZINV      (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_CSIZINV_OFFSET)
+#  define PIC32MX_DMACH5_CPTR         (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_CPTR_OFFSET)
+#  define PIC32MX_DMACH5_DAT          (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DAT_OFFSET)
+#  define PIC32MX_DMACH5_DATCLR       (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DATCLR_OFFSET)
+#  define PIC32MX_DMACH5_DATSET       (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DATSET_OFFSET)
+#  define PIC32MX_DMACH5_DATINV       (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DATINV_OFFSET)
+#endif
+
+#if CHIP_NDMACH > 6
+#  define PIC32MX_DMACH6_CON          (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_CON_OFFSET)
+#  define PIC32MX_DMACH6_CONCLR       (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_CONCLR_OFFSET)
+#  define PIC32MX_DMACH6_CONSET       (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_CONSET_OFFSET)
+#  define PIC32MX_DMACH6_CONINV       (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_CONINV_OFFSET)
+#  define PIC32MX_DMACH6_ECON         (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_ECON_OFFSET)
+#  define PIC32MX_DMACH6_ECONCLR      (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_ECONCLR_OFFSET)
+#  define PIC32MX_DMACH6_ECONSET      (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_ECONSET_OFFSET)
+#  define PIC32MX_DMACH6_ECONINV      (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_ECONINV_OFFSET)
+#  define PIC32MX_DMACH6_INT          (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_INT_OFFSET)
+#  define PIC32MX_DMACH6_INTCLR       (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_INTCLR_OFFSET)
+#  define PIC32MX_DMACH6_INTSET       (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_INTSET_OFFSET)
+#  define PIC32MX_DMACH6_INTINV       (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_INTINV_OFFSET)
+#  define PIC32MX_DMACH6_SSA          (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_SSA_OFFSET)
+#  define PIC32MX_DMACH6_SSACLR       (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_SSACLR_OFFSET)
+#  define PIC32MX_DMACH6_SSASET       (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_SSASET_OFFSET)
+#  define PIC32MX_DMACH6_SSAINV       (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_SSAINV_OFFSET)
+#  define PIC32MX_DMACH6_DSA          (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DSA_OFFSET)
+#  define PIC32MX_DMACH6_DSACLR       (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DSACLR_OFFSET)
+#  define PIC32MX_DMACH6_DSASET       (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DSASET_OFFSET)
+#  define PIC32MX_DMACH6_DSAINV       (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DSAINV_OFFSET)
+#  define PIC32MX_DMACH6_SSIZ         (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_SSIZ_OFFSET)
+#  define PIC32MX_DMACH6_SSIZCLR      (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_SSIZCLR_OFFSET)
+#  define PIC32MX_DMACH6_SSIZSET      (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_SSIZSET_OFFSET)
+#  define PIC32MX_DMACH6_SSIZINV      (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_SSIZINV_OFFSET)
+#  define PIC32MX_DMACH6_DSIZ         (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DSIZ_OFFSET)
+#  define PIC32MX_DMACH6_DSIZCLR      (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DSIZCLR_OFFSET)
+#  define PIC32MX_DMACH6_DSIZSET      (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DSIZSET_OFFSET)
+#  define PIC32MX_DMACH6_DSIZINV      (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DSIZINV_OFFSET)
+#  define PIC32MX_DMACH6_SPTR         (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_SPTR_OFFSET)
+#  define PIC32MX_DMACH6_DPTR         (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DPTR_OFFSET)
+#  define PIC32MX_DMACH6_CSIZ         (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_CSIZ_OFFSET)
+#  define PIC32MX_DMACH6_CSIZCLR      (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_CSIZCLR_OFFSET)
+#  define PIC32MX_DMACH6_CSIZSET      (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_CSIZSET_OFFSET)
+#  define PIC32MX_DMACH6_CSIZINV      (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_CSIZINV_OFFSET)
+#  define PIC32MX_DMACH6_CPTR         (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_CPTR_OFFSET)
+#  define PIC32MX_DMACH6_DAT          (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DAT_OFFSET)
+#  define PIC32MX_DMACH6_DATCLR       (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DATCLR_OFFSET)
+#  define PIC32MX_DMACH6_DATSET       (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DATSET_OFFSET)
+#  define PIC32MX_DMACH6_DATINV       (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DATINV_OFFSET)
+#endif
+
+#if CHIP_NDMACH > 7
+#  define PIC32MX_DMACH7_CON          (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_CON_OFFSET)
+#  define PIC32MX_DMACH7_CONCLR       (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_CONCLR_OFFSET)
+#  define PIC32MX_DMACH7_CONSET       (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_CONSET_OFFSET)
+#  define PIC32MX_DMACH7_CONINV       (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_CONINV_OFFSET)
+#  define PIC32MX_DMACH7_ECON         (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_ECON_OFFSET)
+#  define PIC32MX_DMACH7_ECONCLR      (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_ECONCLR_OFFSET)
+#  define PIC32MX_DMACH7_ECONSET      (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_ECONSET_OFFSET)
+#  define PIC32MX_DMACH7_ECONINV      (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_ECONINV_OFFSET)
+#  define PIC32MX_DMACH7_INT          (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_INT_OFFSET)
+#  define PIC32MX_DMACH7_INTCLR       (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_INTCLR_OFFSET)
+#  define PIC32MX_DMACH7_INTSET       (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_INTSET_OFFSET)
+#  define PIC32MX_DMACH7_INTINV       (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_INTINV_OFFSET)
+#  define PIC32MX_DMACH7_SSA          (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_SSA_OFFSET)
+#  define PIC32MX_DMACH7_SSACLR       (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_SSACLR_OFFSET)
+#  define PIC32MX_DMACH7_SSASET       (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_SSASET_OFFSET)
+#  define PIC32MX_DMACH7_SSAINV       (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_SSAINV_OFFSET)
+#  define PIC32MX_DMACH7_DSA          (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DSA_OFFSET)
+#  define PIC32MX_DMACH7_DSACLR       (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DSACLR_OFFSET)
+#  define PIC32MX_DMACH7_DSASET       (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DSASET_OFFSET)
+#  define PIC32MX_DMACH7_DSAINV       (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DSAINV_OFFSET)
+#  define PIC32MX_DMACH7_SSIZ         (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_SSIZ_OFFSET)
+#  define PIC32MX_DMACH7_SSIZCLR      (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_SSIZCLR_OFFSET)
+#  define PIC32MX_DMACH7_SSIZSET      (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_SSIZSET_OFFSET)
+#  define PIC32MX_DMACH7_SSIZINV      (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_SSIZINV_OFFSET)
+#  define PIC32MX_DMACH7_DSIZ         (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DSIZ_OFFSET)
+#  define PIC32MX_DMACH7_DSIZCLR      (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DSIZCLR_OFFSET)
+#  define PIC32MX_DMACH7_DSIZSET      (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DSIZSET_OFFSET)
+#  define PIC32MX_DMACH7_DSIZINV      (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DSIZINV_OFFSET)
+#  define PIC32MX_DMACH7_SPTR         (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_SPTR_OFFSET)
+#  define PIC32MX_DMACH7_DPTR         (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DPTR_OFFSET)
+#  define PIC32MX_DMACH7_CSIZ         (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_CSIZ_OFFSET)
+#  define PIC32MX_DMACH7_CSIZCLR      (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_CSIZCLR_OFFSET)
+#  define PIC32MX_DMACH7_CSIZSET      (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_CSIZSET_OFFSET)
+#  define PIC32MX_DMACH7_CSIZINV      (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_CSIZINV_OFFSET)
+#  define PIC32MX_DMACH7_CPTR         (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_CPTR_OFFSET)
+#  define PIC32MX_DMACH7_DAT          (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DAT_OFFSET)
+#  define PIC32MX_DMACH7_DATCLR       (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DATCLR_OFFSET)
+#  define PIC32MX_DMACH7_DATSET       (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DATSET_OFFSET)
+#  define PIC32MX_DMACH7_DATINV       (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DATINV_OFFSET)
+#endif
+
 /* Register Bit-Field Definitions ***********************************************************/
 /* Global DMA Registers */
 /* DMA Controller Control Register */
 
-#define DMA_CON_DMABUSY               (1 << 11) /* Bit 15: DMA module busy */
-#define DMA_CON_SUSPEND               (1 << 12) /* Bit 12: DMA suspend */
-#define DMA_CON_SIDL                  (1 << 13) /* Bit 13: Stop in idle mode */
-#define DMA_CON_FRZ                   (1 << 14) /* Bit 14: DMA freeze */
-#define DMA_CON_ON                    (1 << 15) /* Bit 15: DMA on */
+#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4)
+
+#  define DMA_CON_SUSPEND             (1 << 12) /* Bit 12: DMA suspend */
+#  define DMA_CON_SIDL                (1 << 13) /* Bit 13: Stop in idle mode */
+#  define DMA_CON_FRZ                 (1 << 14) /* Bit 14: DMA freeze */
+#  define DMA_CON_ON                  (1 << 15) /* Bit 15: DMA on */
+
+#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
+
+#  define DMA_CON_DMABUSY             (1 << 11) /* Bit 15: DMA module busy */
+#  define DMA_CON_SUSPEND             (1 << 12) /* Bit 12: DMA suspend */
+#  define DMA_CON_FRZ                 (1 << 14) /* Bit 14: DMA freeze */
+#  define DMA_CON_ON                  (1 << 15) /* Bit 15: DMA on */
+
+#endif
 
 /* DMA Status Register */
 
-#define DMA_STAT_DMACH_SHIFT          (0)       /* Bits 0-1: DMA channel */
-#define DMA_STAT_DMACH_MASK           (3 << DMA_STAT_DMACH_SHIFT)
-#define DMA_STAT_RDWR                 (1 << 3)  /* Bit 3:  Read/write status */
+#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4)
+
+#  define DMA_STAT_DMACH_SHIFT        (0)       /* Bits 0-1: DMA channel */
+#  define DMA_STAT_DMACH_MASK         (3 << DMA_STAT_DMACH_SHIFT)
+#  define DMA_STAT_RDWR               (1 << 3)  /* Bit 3:  Read/write status */
+
+#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
+
+#  define DMA_STAT_DMACH_SHIFT        (0)       /* Bits 0-2: DMA channel */
+#  define DMA_STAT_DMACH_MASK         (7 << DMA_STAT_DMACH_SHIFT)
+#  define DMA_STAT_RDWR               (1 << 3)  /* Bit 3:  Read/write status */
+
+#endif
 
 /* DMA Address Register -- This register contains a 32-bit address value */
 
 /* DMA CRC Control Register */
 
-#define DMA_CRCCON_CRCCH_SHIFT        (0)       /* Bits 0-1: CRC channel select */
-#define DMA_CRCCON_CRCCH_MASK         (3 << DMA_CRCCON_CRCCH_SHIFT)
-#define DMA_CRCCON_CRCTYP             (1 << 5)  /* Bit 5:  CRC type selection */
-#define DMA_CRCCON_CRCAPP             (1 << 6)  /* Bit 6:  CRC append mode */
-#define DMA_CRCCON_CRCEN              (1 << 7)  /* Bit 7:  CRC enable */
-#define DMA_CRCCON_PLEN_SHIFT         (8)       /* Bits 8-11: Polynomial length */
-#define DMA_CRCCON_PLEN_MASK          (15 << DMA_CRCCON_PLEN_SHIFT)
-#define DMA_CRCCON_BITO               (1 << 24) /* Bit 24: CRC bit order selection */
-#define DMA_CRCCON_WBO                (1 << 27) /* Bit 27: CRC write byte order selection */
-#define DMA_CRCCON_BYTO_SHIFT         (28)      /* Bits 28-29: CRC byte order selection */
-#define DMA_CRCCON_BYTO_MASK          (3 << DMA_CRCCON_BYTO_SHIFT)
-#  define DMA_CRCCON_BYTO_SRCORDER    (0 << DMA_CRCCON_BYTO_SHIFT) /* No swapping (i.e., source byte order) */ */
-#  define DMA_CRCCON_BYTO_SWAP32      (1 << DMA_CRCCON_BYTO_SHIFT) /* Endian byte swap on word boundaries */
-#  define DMA_CRCCON_BYTO_SWAP32H     (2 << DMA_CRCCON_BYTO_SHIFT) /* Swap half-words on word boundaries */
-#  define DMA_CRCCON_BYTO_SWAP16      (3 << DMA_CRCCON_BYTO_SHIFT) /* Endian byte swap on half-word boundaries */
+#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4)
+
+#  define DMA_CRCCON_CRCCH_SHIFT      (0)       /* Bits 0-1: CRC channel select */
+#  define DMA_CRCCON_CRCCH_MASK       (3 << DMA_CRCCON_CRCCH_SHIFT)
+#  define DMA_CRCCON_CRCAPP           (1 << 6)  /* Bit 6:  CRC append mode */
+#  define DMA_CRCCON_CRCEN            (1 << 7)  /* Bit 7:  CRC enable */
+#  define DMA_CRCCON_PLEN_SHIFT       (8)       /* Bits 8-11: Polynomial length */
+#  define DMA_CRCCON_PLEN_MASK        (15 << DMA_CRCCON_PLEN_SHIFT)
+
+#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
+
+#  define DMA_CRCCON_CRCCH_SHIFT      (0)       /* Bits 0-1: CRC channel select */
+#  define DMA_CRCCON_CRCCH_MASK       (3 << DMA_CRCCON_CRCCH_SHIFT)
+#  define DMA_CRCCON_CRCTYP           (1 << 5)  /* Bit 5:  CRC type selection */
+#  define DMA_CRCCON_CRCAPP           (1 << 6)  /* Bit 6:  CRC append mode */
+#  define DMA_CRCCON_CRCEN            (1 << 7)  /* Bit 7:  CRC enable */
+#  define DMA_CRCCON_PLEN_SHIFT       (8)       /* Bits 8-11: Polynomial length */
+#  define DMA_CRCCON_PLEN_MASK        (15 << DMA_CRCCON_PLEN_SHIFT)
+#  define DMA_CRCCON_BITO             (1 << 24) /* Bit 24: CRC bit order selection */
+#  define DMA_CRCCON_WBO              (1 << 27) /* Bit 27: CRC write byte order selection */
+#  define DMA_CRCCON_BYTO_SHIFT       (28)      /* Bits 28-29: CRC byte order selection */
+#  define DMA_CRCCON_BYTO_MASK        (3 << DMA_CRCCON_BYTO_SHIFT)
+#    define DMA_CRCCON_BYTO_SRCORDER  (0 << DMA_CRCCON_BYTO_SHIFT) /* No swapping (i.e., source byte order) */
+#    define DMA_CRCCON_BYTO_SWAP32    (1 << DMA_CRCCON_BYTO_SHIFT) /* Endian byte swap on word boundaries */
+#    define DMA_CRCCON_BYTO_SWAP32H   (2 << DMA_CRCCON_BYTO_SHIFT) /* Swap half-words on word boundaries */
+#    define DMA_CRCCON_BYTO_SWAP16    (3 << DMA_CRCCON_BYTO_SHIFT) /* Endian byte swap on half-word boundaries */
+
+#endif
 
 /* DMA CRC Data Register -- 16 or 32-bits of data */
 
@@ -395,7 +598,10 @@
 #define DMACH_CON_CHAED               (1 << 6)  /* Bit 6:  Channel allow events if disabled */
 #define DMACH_CON_CHEN                (1 << 7)  /* Bit 7:  Channel enable */
 #define DMACH_CON_CHCHNS              (1 << 8)  /* Bit 8:  Chain channel selection */
-#define DMACH_CON_CHBUSY              (1 << 15) /* Bit 15: Channel busy */
+
+#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
+#  define DMACH_CON_CHBUSY            (1 << 15) /* Bit 15: Channel busy */
+#endif
 
 /* DMA Channel Event Control Register */
 
diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-ethernet.h b/nuttx/arch/mips/src/pic32mx/pic32mx-ethernet.h
new file mode 100644
index 000000000..9df46f21b
--- /dev/null
+++ b/nuttx/arch/mips/src/pic32mx/pic32mx-ethernet.h
@@ -0,0 +1,89 @@
+/****************************************************************************
+ * arch/mips/src/pic32mx/pic32mx-ethernet.h
+ *
+ *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_ETHERNET_H
+#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_ETHERNET_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "pic32mx-memorymap.h"
+
+/****************************************************************************
+ * Pre-Processor Definitions
+ ****************************************************************************/
+/* Register Offsets *********************************************************/
+
+#warning "To be provided"
+
+/* Register Addresses *******************************************************/
+
+#warning "To be provided"
+
+/* Register Bit-Field Definitions *******************************************/
+
+#warning "To be provided"
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_ETHERNET_H */
diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-internal.h b/nuttx/arch/mips/src/pic32mx/pic32mx-internal.h
index 0c3392b30..96d8114f7 100644
--- a/nuttx/arch/mips/src/pic32mx/pic32mx-internal.h
+++ b/nuttx/arch/mips/src/pic32mx/pic32mx-internal.h
@@ -55,14 +55,6 @@
  * Definitions
  ************************************************************************************/
 
-/* Configuration ********************************************************************/
-
-/* Bit-encoded input to pic32mx_configgpio() ****************************************/
-/* To be provided */
-
-/* GPIO pin definitions *************************************************************/
-/* To be provided */
-
 /************************************************************************************
  * Public Types
  ************************************************************************************/
@@ -168,20 +160,6 @@ EXTERN void pic32mx_uartconfigure(uintptr_t uart_base, uint32_t baudrate,
 #endif
 
 /************************************************************************************
- * Name: pic32mx_gpioirqinitialize
- *
- * Description:
- *   Initialize logic to support a second level of interrupt decoding for GPIO pins.
- *
- ************************************************************************************/
-
-#ifdef CONFIG_GPIO_IRQ
-EXTERN void pic32mx_gpioirqinitialize(void);
-#else
-#  define pic32mx_gpioirqinitialize()
-#endif
-
-/************************************************************************************
  * Name: pic32mx_boardinitialize
  *
  * Description:
@@ -214,78 +192,6 @@ EXTERN uint32_t *pic32mx_decodeirq(uint32_t *regs);
 EXTERN uint32_t *pic32mx_dobev(uint32_t *regs);
 
 /************************************************************************************
- * Name: pic32mx_configgpio
- *
- * Description:
- *   Configure a GPIO pin based on bit-encoded description of the pin.
- *
- ************************************************************************************/
-
-EXTERN int pic32mx_configgpio(uint16_t cfgset);
-
-/************************************************************************************
- * Name: pic32mx_gpiowrite
- *
- * Description:
- *   Write one or zero to the selected GPIO pin
- *
- ************************************************************************************/
-
-EXTERN void pic32mx_gpiowrite(uint16_t pinset, bool value);
-
-/************************************************************************************
- * Name: pic32mx_gpioread
- *
- * Description:
- *   Read one or zero from the selected GPIO pin
- *
- ************************************************************************************/
-
-EXTERN bool pic32mx_gpioread(uint16_t pinset);
-
-/************************************************************************************
- * Name: pic32mx_gpioirqenable
- *
- * Description:
- *   Enable the interrupt for specified GPIO IRQ
- *
- ************************************************************************************/
-
-#ifdef CONFIG_GPIO_IRQ
-EXTERN void pic32mx_gpioirqenable(int irq);
-#else
-#  define pic32mx_gpioirqenable(irq)
-#endif
-
-/************************************************************************************
- * Name: pic32mx_gpioirqdisable
- *
- * Description:
- *   Disable the interrupt for specified GPIO IRQ
- *
- ************************************************************************************/
-
-#ifdef CONFIG_GPIO_IRQ
-EXTERN void pic32mx_gpioirqdisable(int irq);
-#else
-#  define pic32mx_gpioirqdisable(irq)
-#endif
-
-/************************************************************************************
- * Function:  pic32mx_dumpgpio
- *
- * Description:
- *   Dump all GPIO registers associated with the base address of the provided pinset.
- *
- ************************************************************************************/
-
-#ifdef CONFIG_DEBUG_GPIO
-EXTERN int pic32mx_dumpgpio(uint16_t pinset, const char *msg);
-#else
-#  define pic32mx_dumpgpio(p,m)
-#endif
-
-/************************************************************************************
  * Name:  pic32mx_spiNselect, pic32mx_spiNstatus, and pic32mx_spiNcmddata
  *
  * Description:
diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-ioport.h b/nuttx/arch/mips/src/pic32mx/pic32mx-ioport.h
index c730e8dcf..186136345 100644
--- a/nuttx/arch/mips/src/pic32mx/pic32mx-ioport.h
+++ b/nuttx/arch/mips/src/pic32mx/pic32mx-ioport.h
@@ -2,7 +2,7 @@
  * arch/mips/src/pic32mx/pic32mx-ioport.h
  *
  *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-irq.c b/nuttx/arch/mips/src/pic32mx/pic32mx-irq.c
index dadbcdfe6..75f7367ff 100644
--- a/nuttx/arch/mips/src/pic32mx/pic32mx-irq.c
+++ b/nuttx/arch/mips/src/pic32mx/pic32mx-irq.c
@@ -128,14 +128,6 @@ void up_irqinitialize(void)
 
   current_regs = NULL;
 
-  /* Initialize logic to support a second level of interrupt decoding for
-   * IOPORT pins.
-   */
- 
-#ifdef CONFIG_GPIO_IRQ
-  lpc17_gpioirqinitialize();
-#endif
-
   /* And finally, enable interrupts */
 
 #ifndef CONFIG_SUPPRESS_INTERRUPTS
diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-lowconsole.c b/nuttx/arch/mips/src/pic32mx/pic32mx-lowconsole.c
index 5498e2235..c94d7fd99 100644
--- a/nuttx/arch/mips/src/pic32mx/pic32mx-lowconsole.c
+++ b/nuttx/arch/mips/src/pic32mx/pic32mx-lowconsole.c
@@ -2,7 +2,7 @@
  * arch/mips/src/pic32mx/pic32mx-lowconsole.c
  *
  *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -69,6 +69,30 @@
 #  define PIC32MX_CONSOLE_BITS     CONFIG_UART2_BITS
 #  define PIC32MX_CONSOLE_PARITY   CONFIG_UART2_PARITY
 #  define PIC32MX_CONSOLE_2STOP    CONFIG_UART2_2STOP
+#elif defined(CONFIG_UART3_SERIAL_CONSOLE)
+#  define PIC32MX_CONSOLE_BASE     PIC32MX_UART3_K1BASE
+#  define PIC32MX_CONSOLE_BAUD     CONFIG_UART3_BAUD
+#  define PIC32MX_CONSOLE_BITS     CONFIG_UART3_BITS
+#  define PIC32MX_CONSOLE_PARITY   CONFIG_UART3_PARITY
+#  define PIC32MX_CONSOLE_2STOP    CONFIG_UART3_2STOP
+#elif defined(CONFIG_UART4_SERIAL_CONSOLE)
+#  define PIC32MX_CONSOLE_BASE     PIC32MX_UART4_K1BASE
+#  define PIC32MX_CONSOLE_BAUD     CONFIG_UART4_BAUD
+#  define PIC32MX_CONSOLE_BITS     CONFIG_UART4_BITS
+#  define PIC32MX_CONSOLE_PARITY   CONFIG_UART4_PARITY
+#  define PIC32MX_CONSOLE_2STOP    CONFIG_UART4_2STOP
+#elif defined(CONFIG_UART5_SERIAL_CONSOLE)
+#  define PIC32MX_CONSOLE_BASE     PIC32MX_UART5_K1BASE
+#  define PIC32MX_CONSOLE_BAUD     CONFIG_UART5_BAUD
+#  define PIC32MX_CONSOLE_BITS     CONFIG_UART5_BITS
+#  define PIC32MX_CONSOLE_PARITY   CONFIG_UART5_PARITY
+#  define PIC32MX_CONSOLE_2STOP    CONFIG_UART5_2STOP
+#elif defined(CONFIG_UART6_SERIAL_CONSOLE)
+#  define PIC32MX_CONSOLE_BASE     PIC32MX_UART6_K1BASE
+#  define PIC32MX_CONSOLE_BAUD     CONFIG_UART6_BAUD
+#  define PIC32MX_CONSOLE_BITS     CONFIG_UART6_BITS
+#  define PIC32MX_CONSOLE_PARITY   CONFIG_UART6_PARITY
+#  define PIC32MX_CONSOLE_2STOP    CONFIG_UART6_2STOP
 #else
 #  error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
 #endif
diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-memorymap.h b/nuttx/arch/mips/src/pic32mx/pic32mx-memorymap.h
index f738506c7..472d607d1 100644
--- a/nuttx/arch/mips/src/pic32mx/pic32mx-memorymap.h
+++ b/nuttx/arch/mips/src/pic32mx/pic32mx-memorymap.h
@@ -149,8 +149,6 @@
 /* Comparator Register Base Addresses */
 
 #  define PIC32MX_CM_K1BASE         (PIC32MX_SFR_K1BASE + 0x0000a000)
-#  define PIC32MX_CM1_K1BASE        (PIC32MX_SFR_K1BASE + 0x0000a000)
-#  define PIC32MX_CM2_K1BASE        (PIC32MX_SFR_K1BASE + 0x0000a010)
 
 /* Oscillator Control Register Base Addresses */
 
@@ -264,6 +262,7 @@
 #  define PIC32MX_SPI3_K1BASE       (PIC32MX_SFR_K1BASE + 0x00005800)
 #  define PIC32MX_SPI2_K1BASE       (PIC32MX_SFR_K1BASE + 0x00005a00)
 #  define PIC32MX_SPI4_K1BASE       (PIC32MX_SFR_K1BASE + 0x00005c00)
+#  define PIC32MX_SPI1_K1BASE       (PIC32MX_SFR_K1BASE + 0x00005e00)
 
 /* UART 1-6 Register Base Addresses */
 
@@ -289,8 +288,6 @@
 /* Comparator Register Base Addresses */
 
 #  define PIC32MX_CM_K1BASE         (PIC32MX_SFR_K1BASE + 0x0000a000)
-#  define PIC32MX_CM1_K1BASE        (PIC32MX_SFR_K1BASE + 0x0000a000)
-#  define PIC32MX_CM2_K1BASE        (PIC32MX_SFR_K1BASE + 0x0000a010)
 
 /* Oscillator Control Register Base Addresses */
 
@@ -324,6 +321,10 @@
 #  define PIC32MX_DMACH1_K1BASE     (PIC32MX_SFR_K1BASE + 0x00083120)
 #  define PIC32MX_DMACH2_K1BASE     (PIC32MX_SFR_K1BASE + 0x000831e0)
 #  define PIC32MX_DMACH3_K1BASE     (PIC32MX_SFR_K1BASE + 0x000832a0)
+#  define PIC32MX_DMACH4_K1BASE     (PIC32MX_SFR_K1BASE + 0x00083360)
+#  define PIC32MX_DMACH5_K1BASE     (PIC32MX_SFR_K1BASE + 0x00083420)
+#  define PIC32MX_DMACH6_K1BASE     (PIC32MX_SFR_K1BASE + 0x000834e0)
+#  define PIC32MX_DMACH7_K1BASE     (PIC32MX_SFR_K1BASE + 0x000835a0)
 
 /* Prefetch Cache Register Base Address */
 
diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-usbotg.h b/nuttx/arch/mips/src/pic32mx/pic32mx-usbotg.h
index 022e931ed..d67b2ff02 100644
--- a/nuttx/arch/mips/src/pic32mx/pic32mx-usbotg.h
+++ b/nuttx/arch/mips/src/pic32mx/pic32mx-usbotg.h
@@ -2,7 +2,7 @@
  * arch/mips/src/pic32mx/pic32mx-usbotg.h
  *
  *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -165,7 +165,9 @@
 
 #define USB_PWRC_USBPWR            (1 << 0) /* Bit 0: USB Operation Enable */
 #define USB_PWRC_USUSPEND          (1 << 1) /* Bit 1: USB Suspend Mode */
-#define USB_PWRC_USBBUSY           (1 << 3) /* Bit 3: USB Module Busy */
+#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
+#  define USB_PWRC_USBBUSY         (1 << 3) /* Bit 3: USB Module Busy */
+#endif
 #define USB_PWRC_USLPGRD           (1 << 4) /* Bit 4: USB Sleep Entry Guard */
 #define USB_PWRC_UACTPND           (1 << 7) /* Bit 7: USB Activity Pending */
 
@@ -263,7 +265,9 @@
 
 /* USB Debug and Idle Register */
 
-#define USB_CNFG1_UASUSPND         (1 << 0) /* Bit 0: Automatic Suspend Enable */
+#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
+#  define USB_CNFG1_UASUSPND       (1 << 0) /* Bit 0: Automatic Suspend Enable */
+#endif
 #define USB_CNFG1_USBSIDL          (1 << 4) /* Bit 4: Stop in Idle Mode */
 #define USB_CNFG1_USBFRZ           (1 << 5) /* Bit 5: Freeze in Debug Mode */
 #define USB_CNFG1_UOEMON           (1 << 6) /* Bit 6: USB OE Monitor Enable */
diff --git a/nuttx/configs/pic32-starterkit/ostest/defconfig b/nuttx/configs/pic32-starterkit/ostest/defconfig
index f88505a5c..1f3ca99c1 100644
--- a/nuttx/configs/pic32-starterkit/ostest/defconfig
+++ b/nuttx/configs/pic32-starterkit/ostest/defconfig
@@ -185,24 +185,52 @@ CONFIG_PIC32MX_ICESEL=0
 #
 CONFIG_UART1_SERIAL_CONSOLE=n
 CONFIG_UART2_SERIAL_CONSOLE=y
+CONFIG_UART3_SERIAL_CONSOLE=n
+CONFIG_UART4_SERIAL_CONSOLE=n
+CONFIG_UART5_SERIAL_CONSOLE=n
+CONFIG_UART6_SERIAL_CONSOLE=n
 
 CONFIG_UART1_TXBUFSIZE=256
 CONFIG_UART2_TXBUFSIZE=256
+CONFIG_UART3_TXBUFSIZE=256
+CONFIG_UART4_TXBUFSIZE=256
+CONFIG_UART5_TXBUFSIZE=256
+CONFIG_UART6_TXBUFSIZE=256
 
 CONFIG_UART1_RXBUFSIZE=256
 CONFIG_UART2_RXBUFSIZE=256
+CONFIG_UART3_RXBUFSIZE=256
+CONFIG_UART4_RXBUFSIZE=256
+CONFIG_UART5_RXBUFSIZE=256
+CONFIG_UART6_RXBUFSIZE=256
 
 CONFIG_UART1_BAUD=115200
 CONFIG_UART2_BAUD=115200
+CONFIG_UART3_BAUD=115200
+CONFIG_UART4_BAUD=115200
+CONFIG_UART5_BAUD=115200
+CONFIG_UART6_BAUD=115200
 
 CONFIG_UART1_BITS=8
 CONFIG_UART2_BITS=8
+CONFIG_UART3_BITS=8
+CONFIG_UART4_BITS=8
+CONFIG_UART5_BITS=8
+CONFIG_UART6_BITS=8
 
 CONFIG_UART1_PARITY=0
 CONFIG_UART2_PARITY=0
+CONFIG_UART3_PARITY=0
+CONFIG_UART4_PARITY=0
+CONFIG_UART5_PARITY=0
+CONFIG_UART6_PARITY=0
 
 CONFIG_UART1_2STOP=0
 CONFIG_UART2_2STOP=0
+CONFIG_UART3_2STOP=0
+CONFIG_UART4_2STOP=0
+CONFIG_UART5_2STOP=0
+CONFIG_UART6_2STOP=0
 
 #
 # General build options
author	patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>	2011-10-10 18:42:36 +0000
committer	patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>	2011-10-10 18:42:36 +0000
commit	825cd6c478c17dc00135182595c796fcd023854e (patch)
tree	b84f2666b201df856d825d7e2444c0df24c463be /nuttx
parent	ff641f36093e5a01fed6f896ba0b6a1f7969144f (diff)
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