Shenzhou PHY address should be 0; make sure the F2/F4 bits are not set when using STM32 ethernet driver with F1

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5181 42af7a65-404d-4744-a932-0658087f49c3

4 files changed, 49 insertions, 17 deletions

diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_eth.h b/nuttx/arch/arm/src/stm32/chip/stm32_eth.h
index 431144009..0b5ef18ca 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32_eth.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32_eth.h
@@ -62,7 +62,9 @@
 #define STM32_ETH_MACVLANTR_OFFSET   0x001c /* Ethernet MAC VLAN tag register */
 #define STM32_ETH_MACRWUFFR_OFFSET   0x0028 /* Ethernet MAC remote wakeup frame filter reg */
 #define STM32_ETH_MACPMTCSR_OFFSET   0x002c /* Ethernet MAC PMT control and status register */
-#define STM32_ETH_MACDBGR_OFFSET     0x0034 /* Ethernet MAC debug register */
+#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
+#  define STM32_ETH_MACDBGR_OFFSET   0x0034 /* Ethernet MAC debug register */
+#endif
 #define STM32_ETH_MACSR_OFFSET       0x0038 /* Ethernet MAC interrupt status register */
 #define STM32_ETH_MACIMR_OFFSET      0x003c /* Ethernet MAC interrupt mask register */
 #define STM32_ETH_MACA0HR_OFFSET     0x0040 /* Ethernet MAC address 0 high register */
@@ -132,7 +134,9 @@
 #define STM32_ETH_MACVLANTR          (STM32_ETHERNET_BASE+STM32_ETH_MACVLANTR_OFFSET)
 #define STM32_ETH_MACRWUFFR          (STM32_ETHERNET_BASE+STM32_ETH_MACRWUFFR_OFFSET)
 #define STM32_ETH_MACPMTCSR          (STM32_ETHERNET_BASE+STM32_ETH_MACPMTCSR_OFFSET)
-#define STM32_ETH_MACDBGR            (STM32_ETHERNET_BASE+STM32_ETH_MACDBGR_OFFSET)
+#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
+#  define STM32_ETH_MACDBGR          (STM32_ETHERNET_BASE+STM32_ETH_MACDBGR_OFFSET)
+#endif
 #define STM32_ETH_MACSR              (STM32_ETHERNET_BASE+STM32_ETH_MACSR_OFFSET)
 #define STM32_ETH_MACIMR             (STM32_ETHERNET_BASE+STM32_ETH_MACIMR_OFFSET)
 #define STM32_ETH_MACA0HR            (STM32_ETHERNET_BASE+STM32_ETH_MACA0HR_OFFSET)
@@ -216,7 +220,9 @@
 #  define ETH_MACCR_IFG(n)           ((12-((n) >> 3)) << ETH_MACCR_IFG_SHIFT) /* n bit times, n=40,48,..96 */
 #define ETH_MACCR_JD                 (1 << 22) /* Bit 22: Jabber disable */
 #define ETH_MACCR_WD                 (1 << 23) /* Bit 23: Watchdog disable */
-#define ETH_MACCR_CSTF               (1 << 25) /* Bits 25: CRC stripping for Type frames */
+#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
+#  define ETH_MACCR_CSTF             (1 << 25) /* Bits 25: CRC stripping for Type frames */
+#endif
 
 /* Ethernet MAC frame filter register */
 
@@ -303,6 +309,8 @@
 
 /* Ethernet MAC debug register */
 
+#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
+
 #define ETH_MACDBGR_MMRPEA           (1 << 0)  /* Bit 0: MAC MII receive protocol engine active */
 #define ETH_MACDBGR_MSFRWCS_SHIFT    (1)       /* Bits 1-2: MAC small FIFO read / write controllers status */
 #define ETH_MACDBGR_MSFRWCS_MASK     (3 << ETH_MACDBGR_MSFRWCS_SHIFT)
@@ -337,6 +345,8 @@
 #define ETH_MACDBGR_TFNE             (1 << 24) /* Bit 24: Tx FIFO not empty */
 #define ETH_MACDBGR_TFF              (1 << 25) /* Bit 25: Tx FIFO full */
 
+#endif
+
 /* Ethernet MAC interrupt status register */
 
 #define ETH_MACSR_PMTS               (1 << 3)  /* Bit 3: PMT status */
@@ -419,7 +429,9 @@
 #define ETH_MMCCR_ROR                (1 << 2)  /* Bit 2: Reset on read */
 #define ETH_MMCCR_MCF                (1 << 3)  /* Bit 3: MMC counter freeze */
 #define ETH_MMCCR_MCP                (1 << 4)  /* Bit 4: MMC counter preset */
-#define ETH_MMCCR_MCFHP              (1 << 5)  /* Bit 5: MMC counter Full-Half preset */
+#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
+#  define ETH_MMCCR_MCFHP            (1 << 5)  /* Bit 5: MMC counter Full-Half preset */
+#endif
 
 /* Ethernet MMC receive interrupt and interrupt mask registers */
 
@@ -453,6 +465,8 @@
 #define ETH_PTPTSCR_TSSTU            (1 << 3)  /* Bit 3:  Time stamp system time update */
 #define ETH_PTPTSCR_TSITE            (1 << 4)  /* Bit 4:  Time stamp interrupt trigger enable */
 #define ETH_PTPTSCR_TSARU            (1 << 5)  /* Bit 5:  Time stamp addend register update */
+
+#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
 #define ETH_PTPTSCR_TSSARFE          (1 << 8)  /* Bit 8:  Time stamp snapshot for all received frames enable */
 #define ETH_PTPTSCR_TSSSR            (1 << 9)  /* Bit 9:  Time stamp subsecond rollover: digital or binary rollover control */
 #define ETH_PTPTSCR_TSPTPPSV2E       (1 << 10) /* Bit 10: Time stamp PTP packet snooping for version2 format enable */
@@ -468,6 +482,7 @@
 #  define ETH_PTPTSCR_TSCNT_E2E      (2 << ETH_PTPTSCR_TSCNT_SHIFT) /* 10: End-to-end transparent clock */
 #  define ETH_PTPTSCR_TSCNT_P2P      (3 << ETH_PTPTSCR_TSCNT_SHIFT) /* 11: Peer-to-peer transparent clock */
 #define ETH_PTPTSCR_TSPFFMAE         (1 << 18) /* Bit 18: Time stamp PTP frame filtering MAC address enable */
+#endif
 
 /* Ethernet PTP subsecond increment register */
 
@@ -543,7 +558,9 @@
 #define ETH_DMABMR_USP               (1 << 23) /* Bit 23: Use separate PBL */
 #define ETH_DMABMR_FPM               (1 << 24) /* Bit 24: 4xPBL mode */
 #define ETH_DMABMR_AAB               (1 << 25) /* Bit 25: Address-aligned beats */
-#define ETH_DMABMR_MB                (1 << 26) /* Bit 26: Mixed burst */
+#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
+#  define ETH_DMABMR_MB              (1 << 26) /* Bit 26: Mixed burst */
+#endif
 
 /* Ethernet DMA transmit poll demand register (32-bit) */
 /* Ethernet DMA receive poll demand register (32-bit) */
diff --git a/nuttx/arch/arm/src/stm32/stm32_eth.c b/nuttx/arch/arm/src/stm32/stm32_eth.c
index b3392fa7a..ab9cac209 100644
--- a/nuttx/arch/arm/src/stm32/stm32_eth.c
+++ b/nuttx/arch/arm/src/stm32/stm32_eth.c
@@ -283,14 +283,22 @@
  * ETH_MACCR_IFG   Bits 17-19: Interframe gap
  * ETH_MACCR_JD    Bit 22: Jabber disable
  * ETH_MACCR_WD    Bit 23: Watchdog disable
- * ETH_MACCR_CSTF  Bits 25: CRC stripping for Type frames
+ * ETH_MACCR_CSTF  Bits 25: CRC stripping for Type frames (F2/F4 only)
  */
 
+#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
 #define MACCR_CLEAR_BITS \
- ( ETH_MACCR_RE | ETH_MACCR_TE | ETH_MACCR_DC | ETH_MACCR_BL_MASK | \
+  (ETH_MACCR_RE | ETH_MACCR_TE | ETH_MACCR_DC | ETH_MACCR_BL_MASK | \
    ETH_MACCR_APCS | ETH_MACCR_RD | ETH_MACCR_IPCO | ETH_MACCR_DM | \
    ETH_MACCR_LM | ETH_MACCR_ROD | ETH_MACCR_FES | ETH_MACCR_CSD | \
-   ETH_MACCR_IFG_MASK | ETH_MACCR_JD | ETH_MACCR_WD | ETH_MACCR_CSTF )
+   ETH_MACCR_IFG_MASK | ETH_MACCR_JD | ETH_MACCR_WD | ETH_MACCR_CSTF)
+#else
+#define MACCR_CLEAR_BITS \
+  (ETH_MACCR_RE | ETH_MACCR_TE | ETH_MACCR_DC | ETH_MACCR_BL_MASK | \
+   ETH_MACCR_APCS | ETH_MACCR_RD | ETH_MACCR_IPCO | ETH_MACCR_DM | \
+   ETH_MACCR_LM | ETH_MACCR_ROD | ETH_MACCR_FES | ETH_MACCR_CSD | \
+   ETH_MACCR_IFG_MASK | ETH_MACCR_JD | ETH_MACCR_WD)
+#endif
 
 /* The following bits are set or left zero unconditionally in all modes.
  *
@@ -307,7 +315,7 @@
  * ETH_MACCR_IFG   Interframe gap                 0 (96 bits)
  * ETH_MACCR_JD    Jabber disable                 0 (enabled)
  * ETH_MACCR_WD    Watchdog disable               0 (enabled)
- * ETH_MACCR_CSTF  CRC stripping for Type frames  0 (disabled)
+ * ETH_MACCR_CSTF  CRC stripping for Type frames  0 (disabled, F2/F4 only)
  *
  * The following are set conditioinally based on mode and speed.
  *
@@ -462,13 +470,20 @@
  * ETH_DMABMR_USP   Bit 23: Use separate PBL
  * ETH_DMABMR_FPM   Bit 24: 4xPBL mode
  * ETH_DMABMR_AAB   Bit 25: Address-aligned beats
- * ETH_DMABMR_MB    Bit 26: Mixed burst
+ * ETH_DMABMR_MB    Bit 26: Mixed burst (F2/F4 only)
  */
 
+#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
 #define DMABMR_CLEAR_MASK \
   (ETH_DMABMR_SR | ETH_DMABMR_DA | ETH_DMABMR_DSL_MASK | ETH_DMABMR_EDFE | \
    ETH_DMABMR_PBL_MASK | ETH_DMABMR_RTPR_MASK | ETH_DMABMR_FB | ETH_DMABMR_RDP_MASK | \
    ETH_DMABMR_USP | ETH_DMABMR_FPM | ETH_DMABMR_AAB | ETH_DMABMR_MB)
+#else
+#define DMABMR_CLEAR_MASK \
+  (ETH_DMABMR_SR | ETH_DMABMR_DA | ETH_DMABMR_DSL_MASK | ETH_DMABMR_EDFE | \
+   ETH_DMABMR_PBL_MASK | ETH_DMABMR_RTPR_MASK | ETH_DMABMR_FB | ETH_DMABMR_RDP_MASK | \
+   ETH_DMABMR_USP | ETH_DMABMR_FPM | ETH_DMABMR_AAB)
+#endif
 
 /* The following bits are set or left zero unconditionally in all modes.
  *
@@ -484,7 +499,7 @@
  * ETH_DMABMR_USP   Use separate PBL                   1 (enabled)
  * ETH_DMABMR_FPM   4xPBL mode                         0 (disabled)
  * ETH_DMABMR_AAB   Address-aligned beats              1 (enabled)
- * ETH_DMABMR_MB    Mixed burst                        0 (disabled)
+ * ETH_DMABMR_MB    Mixed burst                        0 (disabled, F2/F4 only)
  */
 
 #ifdef CONFIG_STM32_ETH_ENHANCEDDESC
@@ -2001,7 +2016,7 @@ static int stm32_ifup(struct uip_driver_s *dev)
 
   ndbg("Bringing up: %d.%d.%d.%d\n",
        dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
-       (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 );
+       (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
 
   /* Configure the Ethernet interface for DMA operation. */
 
@@ -2242,7 +2257,7 @@ static void stm32_txdescinit(FAR struct stm32_ethmac_s *priv)
     
       /* Initialize the next descriptor with the Next Descriptor Polling Enable */
 
-      if( i < (CONFIG_STM32_ETH_NTXDESC-1))
+      if (i < (CONFIG_STM32_ETH_NTXDESC-1))
         {
           /* Set next descriptor address register with next descriptor base
            * address
@@ -2321,7 +2336,7 @@ static void stm32_rxdescinit(FAR struct stm32_ethmac_s *priv)
     
       /* Initialize the next descriptor with the Next Descriptor Polling Enable */
 
-      if( i < (CONFIG_STM32_ETH_NRXDESC-1))
+      if (i < (CONFIG_STM32_ETH_NRXDESC-1))
         {
           /* Set next descriptor address register with next descriptor base
            * address
@@ -2524,7 +2539,7 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv)
 
   if (timeout >= PHY_RETRY_TIMEOUT)
     {
-      ndbg("Timed out waiting for link status\n");
+      ndbg("Timed out waiting for link status: %04x\n", phyval);
       return -ETIMEDOUT;
     }
 
diff --git a/nuttx/configs/shenzhou/nsh/defconfig b/nuttx/configs/shenzhou/nsh/defconfig
index c4817c2ee..313f9f57b 100644
--- a/nuttx/configs/shenzhou/nsh/defconfig
+++ b/nuttx/configs/shenzhou/nsh/defconfig
@@ -172,7 +172,7 @@ CONFIG_STM32_JTAG_FULL_ENABLE=y
 #
 # Ethernet MAC configuration
 #
-CONFIG_STM32_PHYADDR=1
+CONFIG_STM32_PHYADDR=0
 # CONFIG_STM32_MII is not set
 CONFIG_STM32_AUTONEG=y
 CONFIG_STM32_PHYSR=17
diff --git a/nuttx/drivers/net/enc28j60.h b/nuttx/drivers/net/enc28j60.h
index 6f7f8f465..6a0553a95 100644
--- a/nuttx/drivers/net/enc28j60.h
+++ b/nuttx/drivers/net/enc28j60.h
@@ -78,7 +78,7 @@
  *
  * The last five locations (0x1b to 0x1f) of all banks point to a common set
  * of registers: EIE, EIR, ESTAT, ECON2 and ECON1. These are key registers
- * usedin controlling and monitoring the operation of the device. Their
+ * used in controlling and monitoring the operation of the device. Their
  * common mapping allows easy access without switching the bank.
  *
  * Control registers for the ENC28J60 are generically grouped as ETH, MAC and