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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-05-26 01:45:37 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-05-26 01:45:37 +0000 |
| commit | c5c0212b8edfc405665c9ac46e2e4dca8b9c34aa (patch) | |
| tree | 0264934a5e12a173199c637b8c8b0193e074c432 /nuttx | |
| parent | 7678a8287c4a198ba6811f45b9bba934b2a5716b (diff) | |
| download | px4-nuttx-c5c0212b8edfc405665c9ac46e2e4dca8b9c34aa.tar.gz px4-nuttx-c5c0212b8edfc405665c9ac46e2e4dca8b9c34aa.tar.bz2 px4-nuttx-c5c0212b8edfc405665c9ac46e2e4dca8b9c34aa.zip | |
Now have to press enter 3 times to start with USB NSH console
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4772 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx')
| -rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32_otgfs.h | 16 | ||||
| -rwxr-xr-x | nuttx/arch/arm/src/stm32/stm32_otgfsdev.c | 12 |
2 files changed, 16 insertions, 12 deletions
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_otgfs.h b/nuttx/arch/arm/src/stm32/chip/stm32_otgfs.h index 57799b6b6..d3bf7eb54 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32_otgfs.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32_otgfs.h @@ -198,17 +198,17 @@ #define STM32_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12)) #define STM32_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12)) -#define STM32_OTGFS_DFIFO_DEP0_OFFSET 0x1000 /* 0x1000–0x1ffc Device IN/OUT Endpoint 0 DFIFO Write/Read Access */ -#define STM32_OTGFS_DFIFO_HCH0_OFFSET 0x1000 /* 0x1000–0x1ffc Host OUT/IN Channel 0 DFIFO Read/Write Access */ +#define STM32_OTGFS_DFIFO_DEP0_OFFSET 0x1000 /* 0x1000-0x1ffc Device IN/OUT Endpoint 0 DFIFO Write/Read Access */ +#define STM32_OTGFS_DFIFO_HCH0_OFFSET 0x1000 /* 0x1000-0x1ffc Host OUT/IN Channel 0 DFIFO Read/Write Access */ -#define STM32_OTGFS_DFIFO_DEP1_OFFSET 0x2000 /* 0x2000–0x2ffc Device IN/OUT Endpoint 0 DFIFO Write/Read Access */ -#define STM32_OTGFS_DFIFO_HCH1_OFFSET 0x2000 /* 0x2000–0x2ffc Host OUT/IN Channel 0 DFIFO Read/Write Access */ +#define STM32_OTGFS_DFIFO_DEP1_OFFSET 0x2000 /* 0x2000-0x2ffc Device IN/OUT Endpoint 1 DFIFO Write/Read Access */ +#define STM32_OTGFS_DFIFO_HCH1_OFFSET 0x2000 /* 0x2000-0x2ffc Host OUT/IN Channel 1 DFIFO Read/Write Access */ -#define STM32_OTGFS_DFIFO_DEP2_OFFSET 0x3000 /* 0x3000–0x3ffc Device IN/OUT Endpoint 0 DFIFO Write/Read Access */ -#define STM32_OTGFS_DFIFO_HCH2_OFFSET 0x3000 /* 0x3000–0x3ffc Host OUT/IN Channel 0 DFIFO Read/Write Access */ +#define STM32_OTGFS_DFIFO_DEP2_OFFSET 0x3000 /* 0x3000-0x3ffc Device IN/OUT Endpoint 1 DFIFO Write/Read Access */ +#define STM32_OTGFS_DFIFO_HCH2_OFFSET 0x3000 /* 0x3000-0x3ffc Host OUT/IN Channel 1 DFIFO Read/Write Access */ -#define STM32_OTGFS_DFIFO_DEP3_OFFSET 0x4000 /* 0x4000–0x4ffc Device IN/OUT Endpoint 0 DFIFO Write/Read Access */ -#define STM32_OTGFS_DFIFO_HCH3_OFFSET 0x4000 /* 0x4000–0x4ffc Host OUT/IN Channel 0 DFIFO Read/Write Access */ +#define STM32_OTGFS_DFIFO_DEP3_OFFSET 0x4000 /* 0x4000-0x4ffc Device IN/OUT Endpoint 1 DFIFO Write/Read Access */ +#define STM32_OTGFS_DFIFO_HCH3_OFFSET 0x4000 /* 0x4000-0x4ffc Host OUT/IN Channel 1 DFIFO Read/Write Access */ /* Power and clock gating registers */ diff --git a/nuttx/arch/arm/src/stm32/stm32_otgfsdev.c b/nuttx/arch/arm/src/stm32/stm32_otgfsdev.c index e36f4e33b..d07d06c79 100755 --- a/nuttx/arch/arm/src/stm32/stm32_otgfsdev.c +++ b/nuttx/arch/arm/src/stm32/stm32_otgfsdev.c @@ -1263,9 +1263,11 @@ static void stm32_rxfifo_read(FAR struct stm32_ep_s *privep, uint32_t regaddr; int i; - /* Get the address of the endpoint FIFO. Note: there is only one RxFIFO. */ + /* Get the address of the RxFIFO. Note: there is only one RxFIFO so + * we might as well use the addess associated with EP0. + */ - regaddr = STM32_OTGFS_DFIFO_DEP(privep->epphy); + regaddr = STM32_OTGFS_DFIFO_DEP(EP0); /* Read 32-bits and write 4 x 8-bits at time (to avoid unaligned accesses) */ @@ -1305,9 +1307,11 @@ static void stm32_rxfifo_discard(FAR struct stm32_ep_s *privep, int len) uint32_t regaddr; int i; - /* Get the address of the endpoint FIFO */ + /* Get the address of the RxFIFO Note: there is only one RxFIFO so + * we might as well use the addess associated with EP0. + */ - regaddr = STM32_OTGFS_DFIFO_DEP(privep->epphy); + regaddr = STM32_OTGFS_DFIFO_DEP(EP0); /* Read 32-bits at time */ |