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authorpatacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>2013-03-28 13:35:50 +0000
committerpatacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>2013-03-28 13:35:50 +0000
commitc942ffd840bb16140db80f04873c875830c31f67 (patch)
tree9b2cdbd9a04deb63e28d9e443c603d0bc1649410 /nuttx
parenta15c952cd525e220d428fbd88ce7de7fc4efec59 (diff)
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Fix Open1788 EMC clocking
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5796 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx')
-rw-r--r--nuttx/configs/open1788/include/board.h9
-rw-r--r--nuttx/configs/open1788/src/lpc17_sdraminitialize.c15
2 files changed, 15 insertions, 9 deletions
diff --git a/nuttx/configs/open1788/include/board.h b/nuttx/configs/open1788/include/board.h
index 369d08eba..bf9918199 100644
--- a/nuttx/configs/open1788/include/board.h
+++ b/nuttx/configs/open1788/include/board.h
@@ -123,11 +123,13 @@
#ifdef CONFIG_LPC17_EMC
/* EMC clock selection.
*
- * The EMC uses the CPU clock undivided.
+ * The EMC clock should not be driven above 80MHz. As a result the EMC
+ * uses the CPU clock divided by two.
*/
-# define BOARD_EMCCLKSEL_VALUE SYSCON_EMCCLKSEL_CCLK_DIV1
-# define LPC17_EMCCLK LPC17_CCLK
+# define BOARD_EMCCLKSEL_DIVIDER 2
+# define BOARD_EMCCLKSEL_VALUE SYSCON_EMCCLKSEL_CCLK_DIV2
+# define LPC17_EMCCLK (LPC17_CCLK / BOARD_EMCCLKSEL_DIVIDER)
#endif
#if defined(CONFIG_LPC17_USBHOST) || (CONFIG_LPC17_USBDEV)
@@ -136,6 +138,7 @@
* USBCLK = PLL1CLK = (SYSCLK * 4) = 48MHz
*/
+# define BOARD_USBCLKSEL_DIVIDER 1
# define BOARD_USBCLKSEL_VALUE (SYSCON_USBCLKSEL_USBDIV_DIV1 | \
SYSCON_USBCLKSEL_USBSEL_PLL1)
#endif
diff --git a/nuttx/configs/open1788/src/lpc17_sdraminitialize.c b/nuttx/configs/open1788/src/lpc17_sdraminitialize.c
index e18643f20..10196b18c 100644
--- a/nuttx/configs/open1788/src/lpc17_sdraminitialize.c
+++ b/nuttx/configs/open1788/src/lpc17_sdraminitialize.c
@@ -62,15 +62,18 @@
*
* For example:
* LPC17_CCLCK = 120,000,000
- * EMCCLKSEL -> use LPC17_CCLK undivided
- * LPC17_EMCCLK = 120,000,000
- * LPC17_EMCCLK_MHZ = 120 (rounded)
- * EMC_NSPERCLK = 8 (rounded)
+ * EMCCLKSEL -> LPC17_CCLK divided by 2
+ * LPC17_EMCCLK = 60,000,000
+ * LPC17_EMCCLK_MHZ = 60 (Rounded to an integer)
+ * EMC_NSPERCLK = 16.667 (Represented with 4 bits of fraction, 267)
+ *
+ * EMC_NS2CLK(63) = ((63 << 4) + 266) / 267 = 4 (actual 3.78)
+ * EMC_NS2CLK(20) = ((20 << 4) + 266) / 267 = 2 (actual 1.20)
*/
#define LPC17_EMCCLK_MHZ ((LPC17_EMCCLK + 500000) / 1000000)
-#define EMC_NSPERCLK ((1000 + (LPC17_EMCCLK_MHZ >> 1)) / LPC17_EMCCLK_MHZ)
-#define EMC_NS2CLK(ns) ((ns + (EMC_NSPERCLK - 1)) / EMC_NSPERCLK)
+#define EMC_NSPERCLK_B4 (((1000 << 4) + (LPC17_EMCCLK_MHZ >> 1)) / LPC17_EMCCLK_MHZ)
+#define EMC_NS2CLK(ns) (((ns << 4) + (EMC_NSPERCLK_B4 - 1)) / EMC_NSPERCLK_B4)
#define MDKCFG_RASCAS0VAL 0x00000303
/* Set up for 32-bit SDRAM at CS0 */