Add reset register control definitions

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2476 42af7a65-404d-4744-a932-0658087f49c3

2 files changed, 117 insertions, 15 deletions

diff --git a/nuttx/arch/arm/src/sam3u/sam3u_memorymap.h b/nuttx/arch/arm/src/sam3u/sam3u_memorymap.h
index 801c4d258..c43c0540a 100755
--- a/nuttx/arch/arm/src/sam3u/sam3u_memorymap.h
+++ b/nuttx/arch/arm/src/sam3u/sam3u_memorymap.h
@@ -101,21 +101,21 @@
 /* System Controller Register Blocks:  0x400e0000-0x4007ffff */

 

 #define SAM3U_SMC_BASE          0x400e0000 /* 0x400e0000-0x400e01ff: Static Memory Controller */

-#define SAM3U_MATRIX_BASE       0x400e0000 /* 0x400e0200-0x400e03ff: MATRIX */

-#define SAM3U_PMC_BASE          0x400e0000 /* 0x400e0400-0x400e05ff: Power Management Controller */

-#define SAM3U_UART_BASE         0x400e0000 /* 0x400e0600-0x400e073f: UART */

-#define SAM3U_CHIPID_BASE       0x400e0000 /* 0x400e0740-0x400e07ff: CHIP ID */

-#define SAM3U_EFC0_BASE         0x400e0000 /* 0x400e0800-0x400e09ff: Enhanced Embedded Flash Controller 0 */

-#define SAM3U_EFC1_BASE         0x400e0000 /* 0x400e0a00-0x400e0bff: Enhanced Embedded Flash Controller 1 */

-#define SAM3U_PIOA_BASE         0x400e0000 /* 0x400e0c00-0x400e0dff: Parallel I/O Controller A */

-#define SAM3U_PIOB_BASE         0x400e0000 /* 0x400e0e00-0x400e0fff: Parallel I/O Controller B */

-#define SAM3U_PIOC_BASE         0x400e0000 /* 0x400e1000-0x400e11ff: Parallel I/O Controller C */

-#define SAM3U_RSTC_BASE         0x400e0000 /* 0x400e1200-0x400e120f: Reset Controller */

-#define SAM3U_SUPC_BASE         0x400e0000 /* 0x400e1210-0x400e122f: Supply Controller */

-#define SAM3U_RTT_BASE          0x400e0000 /* 0x400e1230-0x400e124f: Real Time Timer */

-#define SAM3U_WDT_BASE          0x400e0000 /* 0x400e1250-0x400e125f: Watchdog Timer */

-#define SAM3U_RTC_BASE          0x400e0000 /* 0x400e1260-0x400e128f: Real Time Clock */

-#define SAM3U_GPBR_BASE         0x400e0000 /* 0x400e1290-0x400e13ff: GPBR */

+#define SAM3U_MATRIX_BASE       0x400e0200 /* 0x400e0200-0x400e03ff: MATRIX */

+#define SAM3U_PMC_BASE          0x400e0400 /* 0x400e0400-0x400e05ff: Power Management Controller */

+#define SAM3U_UART_BASE         0x400e0600 /* 0x400e0600-0x400e073f: UART */

+#define SAM3U_CHIPID_BASE       0x400e0740 /* 0x400e0740-0x400e07ff: CHIP ID */

+#define SAM3U_EFC0_BASE         0x400e0800 /* 0x400e0800-0x400e09ff: Enhanced Embedded Flash Controller 0 */

+#define SAM3U_EFC1_BASE         0x400e0a00 /* 0x400e0a00-0x400e0bff: Enhanced Embedded Flash Controller 1 */

+#define SAM3U_PIOA_BASE         0x400e0c00 /* 0x400e0c00-0x400e0dff: Parallel I/O Controller A */

+#define SAM3U_PIOB_BASE         0x400e0e00 /* 0x400e0e00-0x400e0fff: Parallel I/O Controller B */

+#define SAM3U_PIOC_BASE         0x400e1000 /* 0x400e1000-0x400e11ff: Parallel I/O Controller C */

+#define SAM3U_RSTC_BASE         0x400e1200 /* 0x400e1200-0x400e120f: Reset Controller */

+#define SAM3U_SUPC_BASE         0x400e1210 /* 0x400e1210-0x400e122f: Supply Controller */

+#define SAM3U_RTT_BASE          0x400e1230 /* 0x400e1230-0x400e124f: Real Time Timer */

+#define SAM3U_WDT_BASE          0x400e1250 /* 0x400e1250-0x400e125f: Watchdog Timer */

+#define SAM3U_RTC_BASE          0x400e1260 /* 0x400e1260-0x400e128f: Real Time Clock */

+#define SAM3U_GPBR_BASE         0x400e1290 /* 0x400e1290-0x400e13ff: GPBR */

                                            /* 0x490e1400-0x4007ffff: Reserved */

 

 /************************************************************************************************

diff --git a/nuttx/arch/arm/src/sam3u/sam3u_rstc.h b/nuttx/arch/arm/src/sam3u/sam3u_rstc.h
new file mode 100755
index 000000000..4241eeba4
--- /dev/null
+++ b/nuttx/arch/arm/src/sam3u/sam3u_rstc.h
@@ -0,0 +1,102 @@
+/****************************************************************************************

+ * arch/arm/src/sam3u/sam3u_rstc.h

+ *

+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.

+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>

+ *

+ * Redistribution and use in source and binary forms, with or without

+ * modification, are permitted provided that the following conditions

+ * are met:

+ *

+ * 1. Redistributions of source code must retain the above copyright

+ *    notice, this list of conditions and the following disclaimer.

+ * 2. Redistributions in binary form must reproduce the above copyright

+ *    notice, this list of conditions and the following disclaimer in

+ *    the documentation and/or other materials provided with the

+ *    distribution.

+ * 3. Neither the name NuttX nor the names of its contributors may be

+ *    used to endorse or promote products derived from this software

+ *    without specific prior written permission.

+ *

+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS

+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,

+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,

+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS

+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED

+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT

+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN

+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+ * POSSIBILITY OF SUCH DAMAGE.

+ *

+ ****************************************************************************************/

+

+#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_RSTC_H

+#define __ARCH_ARM_SRC_SAM3U_SAM3U_RSTC_H

+

+/****************************************************************************************

+ * Included Files

+ ****************************************************************************************/

+

+#include <nuttx/config.h>

+

+#include "chip.h"

+#include "sam3u_memorymap.h"

+

+/****************************************************************************************

+ * Pre-processor Definitions

+ ****************************************************************************************/

+

+/* RSTC register offsets ****************************************************************/

+

+#define SAM3U_RSTC_CR_OFFSET    0x00 /* Control Register */

+#define SAM3U_RSTC_SR_OFFSET    0x04 /* Status Register */

+#define SAM3U_RSTC_MR_OFFSET    0x08 /* Mode Register  */

+

+/* RSTC register adresses ***************************************************************/

+

+#define SAM3U_RSTC_CR           (SAM3U_RSTC_BASE+SAM3U_RSTC_CR_OFFSET)

+#define SAM3U_RSTC_SR           (SAM3U_RSTC_BASE+SAM3U_RSTC_SR_OFFSET)

+#define SAM3U_RSTC_MR           (SAM3U_RSTC_BASE+SAM3U_RSTC_MR_OFFSET)

+

+/* RSTC register bit definitions ********************************************************/

+

+#define RSTC_CR_PROCRST         (1 << 0)  /* Bit 0:  Processor Reset */

+#define RSTC_CR_PERRST          (1 << 2)  /* Bit 2:  Peripheral Reset */

+#define RSTC_CR_EXTRST          (1 << 3)  /* Bit 3:  External Reset */

+#define RSTC_CR_KEY_SHIFT       (24)      /* Bits 24-31:  Password */

+#define RSTC_CR_KEY_MASK        (0xff << RSTC_CR_KEY_SHIFT)

+

+#define RSTC_SR_URSTS           (1 << 0)  /* Bit 0:  User Reset Status */

+#define RSTC_SR_RSTTYP_SHIFT    (8)       /* Bits 8-10:  Reset Type */

+#define RSTC_SR_RSTTYP_MASK     (7 << RSTC_SR_RSTTYP_SHIFT)

+#  define RSTC_SR_RSTTYP_PWRUP  (0 << RSTC_SR_RSTTYP_SHIFT) /* General Reset */

+#  define RSTC_SR_RSTTYP_BACKUP (1 << RSTC_SR_RSTTYP_SHIFT) /* Backup Reset */

+#  define RSTC_SR_RSTTYP_WDOG   (2 << RSTC_SR_RSTTYP_SHIFT) /* Watchdog Reset */

+#  define RSTC_SR_RSTTYP_SWRST  (3 << RSTC_SR_RSTTYP_SHIFT) /* Software Reset */

+#  define RSTC_SR_RSTTYP_NRST   (4 << RSTC_SR_RSTTYP_SHIFT) /* User Reset NRST pin */

+#define RSTC_SR_NRSTL           (1 << 16) /* Bit 16:  NRST Pin Level */

+#define RSTC_SR_SRCMP           (1 << 17) /* Bit 17:  Software Reset Command in Progress */

+

+#define RSTC_MR_URSTEN          (1 << 0)  /* Bit 0:  User Reset Enable */

+#define RSTC_MR_URSTIEN         (1 << 4)  /* Bit 4:  User Reset Interrupt Enable */

+#define RSTC_MR_ERSTL_SHIFT     (8)       /* Bits 8-11:  External Reset Length */

+#define RSTC_MR_ERSTL_MASK      (15 << RSTC_MR_ERSTL_SHIFT)

+#define RSTC_MR_KEY_SHIFT       (24)      /* Bits 24-31:  Password */

+#define RSTC_MR_KEY_MASK        (0xff << RSTC_CR_KEY_SHIFT)

+

+/****************************************************************************************

+ * Public Types

+ ****************************************************************************************/

+

+/****************************************************************************************

+ * Public Data

+ ****************************************************************************************/

+

+/****************************************************************************************

+ * Public Functions

+ ****************************************************************************************/

+

+#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_RSTC_H */