diff options
4 files changed, 24 insertions, 12 deletions
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h index 80a558095..0eaf2f310 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h @@ -164,7 +164,10 @@ # define RCC_CFGR_PLLMUL_CLKx15 (13 << RCC_CFGR_PLLMUL_SHIFT) /* 1101: PLL input clock x 15 */ # define RCC_CFGR_PLLMUL_CLKx16 (14 << RCC_CFGR_PLLMUL_SHIFT) /* 111x: PLL input clock x 16 */ #ifndef CONFIG_STM32_VALUELINE -# define RCC_CFGR_USBPRE (1 << 22) /* Bit 22: USB/OTG FS prescaler */ +# define RCC_CFGR_USBPRE (1 << 22) /* Bit 22: USB FS prescaler */ +#endif +#ifdef CONFIG_STM32_CONNECTIVITYLINE +# define RCC_CFGR_OTGFSPRE (1 << 22) /* Bit 22: OTG FS prescaler */ #endif #define RCC_CFGR_MCO_SHIFT (24) /* Bits 27-24: Microcontroller Clock Output */ #define RCC_CFGR_MCO_MASK (15 << RCC_CFGR_MCO_SHIFT) diff --git a/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c b/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c index bd660e1b3..f887f8995 100644 --- a/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c +++ b/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c @@ -114,6 +114,18 @@ static inline void rcc_enableahb(void) { uint32_t regval; +#if defined(CONFIG_STM32_CONNECTIVITYLINE) && defined(CONFIG_STM32_OTGFS) + /* USB clock divider for USB OTG FS. This bit must be valid before + * enabling the USB clock in the RCC_AHBENR register. This bit can't be + * reset if the USB clock is enabled. + */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_OTGFSPRE; + regval |= STM32_CFGR_OTGFSPRE; + putreg32(regval, STM32_RCC_CFGR); +#endif + /* Always enable FLITF clock and SRAM clock */ regval = RCC_AHBENR_FLITFEN|RCC_AHBENR_SRAMEN; @@ -176,16 +188,13 @@ static inline void rcc_enableahb(void) static inline void rcc_enableapb1(void) { uint32_t regval; - -#if defined(CONFIG_STM32_USB) || defined(CONFIG_STM32_OTGFS) - /* USB clock divider for USB FD device or USB OTG FS (OTGFS naming for this - * bit is different, but it is the same bit. - * - * This bit must be valid before enabling the either the USB clock in the - * RCC_APB1ENR register ro the OTG FS clock in the AHBENR reigser. This - * bit can’t be reset if the USB clock is enabled. +#ifdef CONFIG_STM32_USB + /* USB clock divider for USB FS device. This bit must be valid before + * enabling the USB clock in the RCC_APB1ENR register. This bit can't be + * reset if the USB clock is enabled. */ + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_USBPRE; regval |= STM32_CFGR_USBPRE; diff --git a/nuttx/configs/viewtool-stm32f107/include/board-stm32f103vct6.h b/nuttx/configs/viewtool-stm32f107/include/board-stm32f103vct6.h index 04d3c0d00..54731ecf7 100644 --- a/nuttx/configs/viewtool-stm32f107/include/board-stm32f103vct6.h +++ b/nuttx/configs/viewtool-stm32f107/include/board-stm32f103vct6.h @@ -110,7 +110,7 @@ #define STM32_CFGR_USBPRE 0 /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. + * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 */ #define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY diff --git a/nuttx/configs/viewtool-stm32f107/include/board-stm32f107vct6.h b/nuttx/configs/viewtool-stm32f107/include/board-stm32f107vct6.h index a25955f1e..1c200a133 100644 --- a/nuttx/configs/viewtool-stm32f107/include/board-stm32f107vct6.h +++ b/nuttx/configs/viewtool-stm32f107/include/board-stm32f107vct6.h @@ -111,7 +111,7 @@ * USB clock = PLLOUT / 1.5 = 72MHz / 1.5 = 48MHz */ -#define STM32_CFGR_USBPRE 0 +#define STM32_CFGR_OTGFSPRE 0 /* MCO output driven by PLL3. From above, we already have PLL3 input frequency as: * @@ -120,7 +120,7 @@ * NOTE: The Viewtool DP83848C module has its on, on-board 50MHz clock. No * MCO clock need be provided on that board. */ - + #if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO) # define BOARD_CFGR_MCO_SOURCE RCC_CFGR_PLL3CLK /* Source: PLL3 */ # define STM32_PLL_PLL3MUL RCC_CFGR2_PLL3MULx10 /* MCO 5MHz * 10 = 50MHz */ |