diff options
| -rw-r--r-- | nuttx/ChangeLog | 5 | ||||
| -rwxr-xr-x | nuttx/arch/arm/src/lpc17xx/lpc17_can.c | 1017 | ||||
| -rwxr-xr-x | nuttx/arch/arm/src/lpc17xx/lpc17_can.h | 1010 | ||||
| -rwxr-xr-x | nuttx/arch/arm/src/stm32/stm32_can.c | 5 | ||||
| -rwxr-xr-x | nuttx/configs/olimex-lpc1766stk/README.txt | 14 | ||||
| -rw-r--r-- | nuttx/configs/olimex-lpc1766stk/nsh/appconfig | 5 | ||||
| -rwxr-xr-x | nuttx/configs/olimex-lpc1766stk/nsh/defconfig | 24 | ||||
| -rwxr-xr-x | nuttx/configs/olimex-lpc1766stk/src/Makefile | 6 | ||||
| -rw-r--r-- | nuttx/configs/stm3240g-eval/src/up_can.c | 2 |
9 files changed, 1323 insertions, 765 deletions
diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index a63f152ee..318adf258 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -2328,4 +2328,9 @@ loopback mode on the STM3240G-EVAL board. * configs/stm3240g-eval/src/up_adc.c: Complete coding of ADC support for the potentiometer on board the STM3240G-EVAL. + * arch/arm/src/lpc17_can.c: Several CAN driver improvements. Adds support for + testing in loopback mode. now uses all three transmit buffers for better + performance. + * confgs/olimex-lpc1766stk/nsh: Now supports the CAN loopback test as an + optional "built-in" application. diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_can.c b/nuttx/arch/arm/src/lpc17xx/lpc17_can.c index dfcd1f0e7..41f823459 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_can.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_can.c @@ -2,9 +2,14 @@ * arch/arm/src/lpc17xx/lpc17_can.c * * Copyright (C) 2011 Li Zhuoyi. All rights reserved. - * Author: Li Zhuoyi <lzyy.cn@gmail.com> - * History: 0.1 2011-07-12 initial version - * 0.2 2011-08-03 support CAN1/CAN2 + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Authors: + * Li Zhuoyi <lzyy.cn@gmail.com> + * Gregory Nutt <gnutt@nuttx.org> + * History: + * 2011-07-12: Initial version (Li Zhuoyi) + * 2011-08-03: Support CAN1/CAN2 (Li Zhuoyi) + * 2012-01-02: Add support for CAN loopback mode (Gregory Nutt) * * This file is a part of NuttX: * @@ -65,17 +70,62 @@ #if defined(CONFIG_LPC17_CAN1) || defined(CONFIG_LPC17_CAN2) /**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Debug ********************************************************************/ +/* Non-standard debug that may be enabled just for testing CAN */ + +#if !defined(CONFIG_DEBUG) || !defined(CONFIG_DEBUG_CAN) +# undef CONFIG_CAN_REGDEBUG +#endif + +#ifdef CONFIG_DEBUG_CAN +# ifdef CONFIG_CAN_REGDEBUG +# define candbg lldbg +# define canvdbg llvdbg +# else +# define candbg dbg +# define canvdbg vdbg +# endif +# define canlldbg lldbg +# define canllvdbg llvdbg +#else +# define candbg(x...) +# define canvdbg(x...) +# define canlldbg(x...) +# define canllvdbg(x...) +#endif + +/**************************************************************************** * Private Types ****************************************************************************/ + struct up_dev_s { - int port; - int baud; /* Configured baud */ + uint8_t port; /* CAN port number */ + uint32_t baud; /* Configured baud */ + uint32_t base; /* CAN register base address */ }; /**************************************************************************** * Private Function Prototypes ****************************************************************************/ +/* CAN Register access */ + +#ifdef CONFIG_CAN_REGDEBUG +static void can_printreg(uint32_t addr, uint32_t value); +#endif + +static uint32_t can_getreg(struct up_dev_s *priv, int offset); +static void can_putreg(struct up_dev_s *priv, int offset, uint32_t value); + +#ifdef CONFIG_CAN_REGDEBUG +static uint32_t can_getcommon(uint32_t addr); +static void can_putcommon(uint32_t addr, uint32_t value); +#else +# define can_getcommon(addr) getreg32(addr) +# define can_putcommon(addr, value) putreg32(value, addr) +#endif /* CAN methods */ @@ -88,7 +138,9 @@ static int can_ioctl(FAR struct can_dev_s *dev, int cmd, unsigned long arg); static int can_remoterequest(FAR struct can_dev_s *dev, uint16_t id); static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg); static bool can_txempty(FAR struct can_dev_s *dev); -static int can_interrupt(int irq, void *context); + +static void can_interrupt(FAR struct can_dev_s *dev); +static int can12_interrupt(int irq, void *context); /**************************************************************************** * Private Data @@ -96,263 +148,704 @@ static int can_interrupt(int irq, void *context); static const struct can_ops_s g_canops = { - .co_reset =can_reset, - .co_setup = can_setup, - .co_shutdown = can_shutdown, - .co_rxint = can_rxint, - .co_txint = can_txint, - .co_ioctl = can_ioctl, - .co_remoterequest = can_remoterequest, - .co_send = can_send, - .co_txempty = can_txempty, + .co_reset = can_reset, + .co_setup = can_setup, + .co_shutdown = can_shutdown, + .co_rxint = can_rxint, + .co_txint = can_txint, + .co_ioctl = can_ioctl, + .co_remoterequest = can_remoterequest, + .co_send = can_send, + .co_txempty = can_txempty, }; #ifdef CONFIG_LPC17_CAN1 static struct up_dev_s g_can1priv = { - .port = 1, - .baud = CONFIG_CAN1_BAUD, + .port = 1, + .baud = CONFIG_CAN1_BAUD, + .base = LPC17_CAN1_BASE, }; static struct can_dev_s g_can1dev = { - .cd_ops = &g_canops, - .cd_priv= &g_can1priv, + .cd_ops = &g_canops, + .cd_priv = &g_can1priv, }; #endif #ifdef CONFIG_LPC17_CAN2 static struct up_dev_s g_can2priv = { - .port = 2, - .baud = CONFIG_CAN2_BAUD, + .port = 2, + .baud = CONFIG_CAN2_BAUD, + .base = LPC17_CAN2_BASE, }; static struct can_dev_s g_can2dev = { - .cd_ops = &g_canops, - .cd_priv= &g_can2priv, + .cd_ops = &g_canops, + .cd_priv = &g_can2priv, }; #endif /**************************************************************************** * Private Functions ****************************************************************************/ -/* Reset the CAN device. Called early to initialize the hardware. This -* is called, before co_setup() and on error conditions. -*/ +/**************************************************************************** + * Name: can_printreg + * + * Description: + * Print the value read from a register. + * + * Input Parameters: + * addr - The register address + * value - The register value + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_CAN_REGDEBUG +static void can_printreg(uint32_t addr, uint32_t value) +{ + static uint32_t prevaddr = 0; + static uint32_t preval = 0; + static uint32_t count = 0; + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && value == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + lldbg("...\n"); + } + return; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + lldbg("[repeats %d more times]\n", count-3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = value; + count = 1; + } + + /* Show the register value read */ + + lldbg("%08x->%08x\n", addr, value); +} +#endif + +/**************************************************************************** + * Name: can_getreg + * + * Description: + * Read the value of an CAN1/2 register. + * + * Input Parameters: + * priv - A reference to the CAN block status + * offset - The offset to the register to read + * + * Returned Value: + * + ****************************************************************************/ + +#ifdef CONFIG_CAN_REGDEBUG +static uint32_t can_getreg(struct up_dev_s *priv, int offset) +{ + uint32_t addr; + uint32_t value; + + /* Read the value from the register */ + + addr = priv->base + offset; + value = getreg32(addr); + can_printreg(addr, value); + return value; +} +#else +static uint32_t can_getreg(struct up_dev_s *priv, int offset) +{ + return getreg32(priv->base + offset); +} +#endif + +/**************************************************************************** + * Name: can_putreg + * + * Description: + * Set the value of an CAN1/2 register. + * + * Input Parameters: + * priv - A reference to the CAN block status + * offset - The offset to the register to write + * value - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_CAN_REGDEBUG +static void can_putreg(struct up_dev_s *priv, int offset, uint32_t value) +{ + uint32_t addr = priv->base + offset; + + /* Show the register value being written */ + + lldbg("%08x<-%08x\n", addr, value); + + /* Write the value */ + + putreg32(value, addr); +} +#else +static void can_putreg(struct up_dev_s *priv, int offset, uint32_t value) +{ + putreg32(value, priv->base + offset); +} +#endif + +/**************************************************************************** + * Name: can_getcommon + * + * Description: + * Get the value of common register. + * + * Input Parameters: + * addr - The address of the register to read + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_CAN_REGDEBUG +static uint32_t can_getcommon(uint32_t addr) +{ + uint32_t value; + + /* Read the value from the register */ + + value = getreg32(addr); + can_printreg(addr, value); + return value; +} +#endif + +/**************************************************************************** + * Name: can_putcommon + * + * Description: + * Set the value of common register. + * + * Input Parameters: + * addr - The address of the register to write + * value - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_CAN_REGDEBUG +static void can_putcommon(uint32_t addr, uint32_t value) +{ + /* Show the register value being written */ + + lldbg("%08x<-%08x\n", addr, value); + + /* Write the value */ + + putreg32(value, addr); +} +#endif + +/**************************************************************************** + * Name: can_reset + * + * Description: + * Reset the CAN device. Called early to initialize the hardware. This + * function is called, before can_setup() and on error conditions. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + static void can_reset(FAR struct can_dev_s *dev) { - irqstate_t flags; - uint32_t regval; - struct up_dev_s *priv=dev->cd_priv; - int baud = priv->baud; - int port = priv->port; - - baud = 0x25c003; - flags = irqsave(); - - if(port==1) - { - putreg32(0x01,LPC17_CAN1_MOD); - putreg32(0x00,LPC17_CAN1_IER); - putreg32(0x00,LPC17_CAN1_GSR); - putreg32(0x02,LPC17_CAN1_CMR); - putreg32(baud,LPC17_CAN1_BTR); - putreg32(0x00,LPC17_CAN1_MOD); - putreg32(0x01,LPC17_CAN1_IER); - putreg32(0x02,LPC17_CANAF_AFMR); - } - else if(port==2) - { - putreg32(0x01,LPC17_CAN2_MOD); - putreg32(0x00,LPC17_CAN2_IER); - putreg32(0x00,LPC17_CAN2_GSR); - putreg32(0x02,LPC17_CAN2_CMR); - putreg32(baud,LPC17_CAN2_BTR); - putreg32(0x00,LPC17_CAN2_MOD); - putreg32(0x01,LPC17_CAN2_IER); - putreg32(0x02,LPC17_CANAF_AFMR); - } - else - { - dbg("Unsupport port %d\n",port); - } - irqrestore(flags); + FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->cd_priv; + uint32_t baud; + irqstate_t flags; + + canvdbg("CAN%d\n", priv->port); + +#warning "BTR setting must be calculated from priv->baud" + baud = 0x25c003; + flags = irqsave(); + + can_putreg(priv, LPC17_CAN_MOD_OFFSET, CAN_MOD_RM); /* Enter Reset Mode */ + can_putreg(priv, LPC17_CAN_IER_OFFSET, 0); /* Disable interrupts */ + can_putreg(priv, LPC17_CAN_GSR_OFFSET, 0); /* Clear status bits */ + can_putreg(priv, LPC17_CAN_CMR_OFFSET, CAN_CMR_AT); /* Abort transmission */ + can_putreg(priv, LPC17_CAN_BTR_OFFSET, baud); /* Set bit timing */ +#ifdef CONFIG_CAN_LOOPBACK + can_putreg(priv, LPC17_CAN_MOD_OFFSET, CAN_MOD_STM); /* Leave Reset Mode, enter Test Mode */ +#else + can_putreg(priv, LPC17_CAN_MOD_OFFSET, 0); /* Leave Reset Mode */ +#endif + can_putcommon(LPC17_CANAF_AFMR, CANAF_AFMR_ACCBP); /* All RX messages accepted */ + irqrestore(flags); } -/* Configure the CAN. This method is called the first time that the CAN -* device is opened. This will occur when the port is first opened. -* This setup includes configuring and attaching CAN interrupts. Interrupts -* are all disabled upon return. -*/ -static int can_setup(FAR struct can_dev_s *dev) +/**************************************************************************** + * Name: can_setup + * + * Description: + * Configure the CAN. This method is called the first time that the CAN + * device is opened. This will occur when the port is first opened. + * This setup includes configuring and attaching CAN interrupts. + * All CAN interrupts are disabled upon return. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int can_setup(FAR struct can_dev_s *dev) { - int ret = irq_attach(LPC17_IRQ_CAN, can_interrupt); - if (ret == OK) +#ifdef CONFIG_DEBUG_CAN + FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->cd_priv; +#endif + int ret; + + canvdbg("CAN%d\n", priv->port); + + ret = irq_attach(LPC17_IRQ_CAN, can12_interrupt); + if (ret == OK) { - up_enable_irq(LPC17_IRQ_CAN); + up_enable_irq(LPC17_IRQ_CAN); } - return ret; + return ret; } -/* Disable the CAN. This method is called when the CAN device is closed. -* This method reverses the operation the setup method. -*/ +/**************************************************************************** + * Name: can_shutdown + * + * Description: + * Disable the CAN. This method is called when the CAN device is closed. + * This method reverses the operation the setup method. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + static void can_shutdown(FAR struct can_dev_s *dev) { - up_disable_irq(LPC17_IRQ_CAN); - irq_detach(LPC17_IRQ_CAN); +#ifdef CONFIG_DEBUG_CAN + FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->cd_priv; + + canvdbg("CAN%d\n", priv->port); +#endif + + up_disable_irq(LPC17_IRQ_CAN); + irq_detach(LPC17_IRQ_CAN); } -/* Call to enable or disable RX interrupts */ +/**************************************************************************** + * Name: can_rxint + * + * Description: + * Call to enable or disable RX interrupts. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + static void can_rxint(FAR struct can_dev_s *dev, bool enable) { - uint32_t regval; - int port = ((struct up_dev_s *)(dev->cd_priv))->port; - - if(port == 1) - regval = getreg32(LPC17_CAN1_IER); - else - regval = getreg32(LPC17_CAN2_IER); - - if (enable) - regval |= CAN_IER_RIE; - else - regval &= ~CAN_IER_RIE; - - if(port == 1) - putreg32(regval, LPC17_CAN1_IER); - else - putreg32(regval, LPC17_CAN2_IER); + FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->cd_priv; + uint32_t regval; + + canvdbg("CAN%d enable: %d\n", priv->port, enable); + + regval = can_getreg(priv, LPC17_CAN_IER_OFFSET); + if (enable) + { + regval |= CAN_IER_RIE; + } + else + { + regval &= ~CAN_IER_RIE; + } + can_putreg(priv, LPC17_CAN_IER_OFFSET, regval); } -/* Call to enable or disable TX interrupts */ +/**************************************************************************** + * Name: can_txint + * + * Description: + * Call to enable or disable TX interrupts. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + static void can_txint(FAR struct can_dev_s *dev, bool enable) { - uint32_t regval; - int port = ((struct up_dev_s *)(dev->cd_priv))->port; - - if(port == 1) - regval = getreg32(LPC17_CAN1_IER); - else - regval = getreg32(LPC17_CAN2_IER); - - if (enable) - regval |= CAN_IER_TIE1; - else - regval &= ~CAN_IER_TIE1; - - if(port == 1) - putreg32(regval, LPC17_CAN1_IER); - else - putreg32(regval, LPC17_CAN2_IER); + FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->cd_priv; + uint32_t regval; + + canvdbg("CAN%d enable: %d\n", priv->port, enable); + + /* Only disabling of the TX interrupt is supported here. The TX interrupt + * is automatically enabled just before a message is sent in order to avoid + * lost TX interrupts. + */ + + if (!enable) + { + regval = can_getreg(priv, LPC17_CAN_IER_OFFSET); + regval &= ~(CAN_IER_TIE1 | CAN_IER_TIE2 | CAN_IER_TIE3); + can_putreg(priv, LPC17_CAN_IER_OFFSET, regval); + } } -/* All ioctl calls will be routed through this method */ -static int can_ioctl(FAR struct can_dev_s *dev, int cmd, unsigned long arg) +/**************************************************************************** + * Name: can_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int can_ioctl(FAR struct can_dev_s *dev, int cmd, unsigned long arg) { - dbg("Fix me:Not Implemented\n"); - return 0; + dbg("Fix me:Not Implemented\n"); + return 0; } -/* Send a remote request */ -static int can_remoterequest(FAR struct can_dev_s *dev, uint16_t id) +/**************************************************************************** + * Name: can_remoterequest + * + * Description: + * Send a remote request + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int can_remoterequest(FAR struct can_dev_s *dev, uint16_t id) { - dbg("Fix me:Not Implemented\n"); - return 0; + dbg("Fix me:Not Implemented\n"); + return 0; } -static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg) +/**************************************************************************** + * Name: can_send + * + * Description: + * Send one can message. + * + * One CAN-message consists of a maximum of 10 bytes. A message is + * composed of at least the first 2 bytes (when there are no data bytes). + * + * Byte 0: Bits 0-7: Bits 3-10 of the 11-bit CAN identifier + * Byte 1: Bits 5-7: Bits 0-2 of the 11-bit CAN identifier + * Bit 4: Remote Tranmission Request (RTR) + * Bits 0-3: Data Length Code (DLC) + * Bytes 2-10: CAN data + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg) { - int port = ((struct up_dev_s *)(dev->cd_priv))->port; - uint32_t tid=CAN_ID(msg->cm_hdr); - uint32_t tfi=CAN_DLC(msg->cm_hdr)<<16; - if (CAN_RTR(msg->cm_hdr)) - tfi|=CAN_TFI_RTR; - if( port == 1) - { - putreg32(tfi,LPC17_CAN1_TFI1); - putreg32(tid,LPC17_CAN1_TID1); - putreg32(*(uint32_t *)&msg->cm_data[0],LPC17_CAN1_TDA1); - putreg32(*(uint32_t *)&msg->cm_data[4],LPC17_CAN1_TDB1); - putreg32(0x21,LPC17_CAN1_CMR); - } - else - { - putreg32(tfi,LPC17_CAN2_TFI1); - putreg32(tid,LPC17_CAN2_TID1); - putreg32(*(uint32_t *)&msg->cm_data[0],LPC17_CAN2_TDA1); - putreg32(*(uint32_t *)&msg->cm_data[4],LPC17_CAN2_TDB1); - putreg32(0x21,LPC17_CAN2_CMR); - } - return 0; + FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->cd_priv; + uint32_t tid = CAN_ID(msg->cm_hdr); + uint32_t tfi = CAN_DLC(msg->cm_hdr) << 16; + uint32_t regval; + irqstate_t flags; + int ret = OK; + + canvdbg("CAN%d ID: %d DLC: %d\n", + priv->port, CAN_ID(msg->cm_hdr), CAN_DLC(msg->cm_hdr)); + + if (CAN_RTR(msg->cm_hdr)) + { + tfi |= CAN_TFI_RTR; + } + + flags = irqsave(); + + /* Pick a transmit buffer */ + + regval = can_getreg(priv, LPC17_CAN_SR_OFFSET); + if ((regval & CAN_SR_TBS1) != 0) + { + /* Set up the transfer */ + + can_putreg(priv, LPC17_CAN_TFI1_OFFSET, tfi); + can_putreg(priv, LPC17_CAN_TID1_OFFSET, tid); + can_putreg(priv, LPC17_CAN_TDA1_OFFSET, *(uint32_t *)&msg->cm_data[0]); + can_putreg(priv, LPC17_CAN_TDB1_OFFSET, *(uint32_t *)&msg->cm_data[4]); + + /* Send the message */ + +#ifdef CONFIG_CAN_LOOPBACK + can_putreg(priv, LPC17_CAN_CMR_OFFSET, CAN_CMR_STB1 | CAN_CMR_SRR); +#else + can_putreg(priv, LPC17_CAN_CMR_OFFSET, CAN_CMR_STB1 | CAN_CMR_TR); +#endif + + /* Tell the caller that the transfer is done. It isn't, but we have + * more transmit buffers and this can speed things up. + */ + + can_txdone(dev); + } + else if ((regval & CAN_SR_TBS2) != 0) + { + /* Set up the transfer */ + + can_putreg(priv, LPC17_CAN_TFI2_OFFSET, tfi); + can_putreg(priv, LPC17_CAN_TID2_OFFSET, tid); + can_putreg(priv, LPC17_CAN_TDA2_OFFSET, *(uint32_t *)&msg->cm_data[0]); + can_putreg(priv, LPC17_CAN_TDB2_OFFSET, *(uint32_t *)&msg->cm_data[4]); + + /* Send the message */ + +#ifdef CONFIG_CAN_LOOPBACK + can_putreg(priv, LPC17_CAN_CMR_OFFSET, CAN_CMR_STB2 | CAN_CMR_SRR); +#else + can_putreg(priv, LPC17_CAN_CMR_OFFSET, CAN_CMR_STB2 | CAN_CMR_TR); +#endif + + /* Tell the caller that the transfer is done. It isn't, but we have + * more transmit buffers and this can speed things up. + */ + + can_txdone(dev); + } + else if ((regval & CAN_SR_TBS3) != 0) + { + /* We have no more buffers. We will make the caller wait. First, make + * sure that the buffer 3 TX interrupt is enabled BEFORE sending the + * message. The TX interrupt is generated TBS3 bit in CANxSR goes from 0 + * to 1 when the TIE3 bit in CANxIER is 1. If we don't enable it now, + * we will miss interrupts. + * + * Hmmm... we could probably do better than this. Buffer 1 or 2 is much + * more likely to complete quicker than buffer 3. + */ + + regval = can_getreg(priv, LPC17_CAN_IER_OFFSET); + regval |= CAN_IER_TIE3; + can_putreg(priv, LPC17_CAN_IER_OFFSET, regval); + + /* Set up the transfer */ + + can_putreg(priv, LPC17_CAN_TFI3_OFFSET, tfi); + can_putreg(priv, LPC17_CAN_TID3_OFFSET, tid); + can_putreg(priv, LPC17_CAN_TDA3_OFFSET, *(uint32_t *)&msg->cm_data[0]); + can_putreg(priv, LPC17_CAN_TDB3_OFFSET, *(uint32_t *)&msg->cm_data[4]); + + /* Send the message */ + +#ifdef CONFIG_CAN_LOOPBACK + can_putreg(priv, LPC17_CAN_CMR_OFFSET, CAN_CMR_STB3 | CAN_CMR_SRR); +#else + can_putreg(priv, LPC17_CAN_CMR_OFFSET, CAN_CMR_STB3 | CAN_CMR_TR); +#endif + } + else + { + candbg("No available transmission buffer, SR: %08x\n", regval); + ret = -EBUSY; + } + + irqrestore(flags); + return ret; } +/**************************************************************************** + * Name: can_txempty + * + * Description: + * Return true if all message have been sent. If for example, the CAN + * hardware implements FIFOs, then this would mean the transmit FIFO is + * empty. This method is called when the driver needs to make sure that + * all characters are "drained" from the TX hardware before calling + * co_shutdown(). + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + static bool can_txempty(FAR struct can_dev_s *dev) { - uint32_t regval; - int port = ((struct up_dev_s *)(dev->cd_priv))->port; - if( port == 1) - regval = getreg32(LPC17_CAN1_GSR); - else - regval = getreg32(LPC17_CAN2_GSR); - if ( regval & CAN_GSR_TBS) - return true; - else - return false; + FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->cd_priv; + uint32_t regval = can_getreg(priv, LPC17_CAN_GSR_OFFSET); + return ((regval & CAN_GSR_TBS) != 0); } -static int can_interrupt(int irq, void *context) +/**************************************************************************** + * Name: can_interrupt + * + * Description: + * CAN1/2 RX/TX interrupt handler + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static void can_interrupt(FAR struct can_dev_s *dev) { - uint32_t regval; - -#ifdef CONFIG_LPC17_CAN1 - regval=getreg32(LPC17_CAN1_ICR); - if (regval & CAN_ICR_RI ) //Receive interrupt - { - uint16_t hdr; - uint32_t data[2]; - uint32_t rfs=getreg32(LPC17_CAN1_RFS); - uint32_t rid=getreg32(LPC17_CAN1_RID); - data[0]=getreg32(LPC17_CAN1_RDA); - data[1]=getreg32(LPC17_CAN1_RDB); - putreg32(0x04,LPC17_CAN1_CMR); //release recieve buffer - hdr=((rid<<5)&~0x1f)|((rfs>>16)&0x0f); - if (rfs&CAN_RFS_RTR) - hdr|=0x10; - can_receive(&g_can1dev,hdr,(uint8_t *)data); - } - if ( regval & CAN_ICR_TI1) //Transmit interrupt 1 - can_txdone(&g_can1dev); -#endif + FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->cd_priv; + uint32_t data[2]; + uint32_t rfs; + uint32_t rid; + uint32_t regval; + uint16_t hdr; + uint16_t id; + uint16_t dlc; + uint16_t rtr; + + /* Read the interrupt and capture register (also clearing most status bits) */ + + regval = can_getreg(priv, LPC17_CAN_ICR_OFFSET); + canllvdbg("CAN%d ICR: %08x\n", priv->port, regval); + + /* Check for a receive interrupt */ + + if ((regval & CAN_ICR_RI) != 0) + { + rfs = can_getreg(priv, LPC17_CAN_RFS_OFFSET); + rid = can_getreg(priv, LPC17_CAN_RID_OFFSET); + data[0] = can_getreg(priv, LPC17_CAN_RDA_OFFSET); + data[1] = can_getreg(priv, LPC17_CAN_RDB_OFFSET); + + /* Release the receive buffer */ + + can_putreg(priv, LPC17_CAN_CMR_OFFSET, CAN_CMR_RRB); + + /* Construct the CAN header */ + + id = rid & CAN_RID_ID11_MASK; + dlc = (rfs & CAN_RFS_DLC_MASK) >> CAN_RFS_DLC_SHIFT; + rtr = ((rfs & CAN_RFS_RTR) != 0); + hdr = CAN_HDR(id, rtr, dlc); + + /* Process the received CAN packet */ + + can_receive(dev, hdr, (uint8_t *)data); + } + + /* Check for a transmit interrupt from buffer 3 */ + + if ((regval & CAN_ICR_TI3) != 0) + { + can_txdone(&g_can1dev); + } +} + +/**************************************************************************** + * Name: can12_interrupt + * + * Description: + * CAN interrupt handler. There is a single interrupt for both CAN1 and + * CAN2. + * + * Input Parameters: + * irq - The IRQ number of the interrupt. + * context - The register state save array at the time of the interrupt. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int can12_interrupt(int irq, void *context) +{ + /* Handle CAN1/2 interrupts */ + canllvdbg("irq: %d\n", irq); + +#ifdef CONFIG_LPC17_CAN1 + can_interrupt(&g_can1dev); +#endif #ifdef CONFIG_LPC17_CAN2 - regval=getreg32(LPC17_CAN2_ICR); - if (regval & CAN_ICR_RI ) //Receive interrupt - { - uint16_t hdr; - uint32_t data[2]; - uint32_t rfs=getreg32(LPC17_CAN2_RFS); - uint32_t rid=getreg32(LPC17_CAN2_RID); - data[0]=getreg32(LPC17_CAN2_RDA); - data[1]=getreg32(LPC17_CAN2_RDB); - putreg32(0x04,LPC17_CAN2_CMR); //release recieve buffer - hdr=((rid<<5)&~0x1f)|((rfs>>16)&0x0f); - if (rfs&CAN_RFS_RTR) - hdr|=0x10; - can_receive(&g_can2dev,hdr,data); - } - if ( regval & CAN_ICR_TI1) //Transmit interrupt 1 - can_txdone(&g_can2dev); + can_interrupt(&g_can2dev); #endif - return OK; + + return OK; } /**************************************************************************** * Public Functions ****************************************************************************/ - /**************************************************************************** * Name: lpc17_caninitialize * @@ -369,67 +862,79 @@ static int can_interrupt(int irq, void *context) FAR struct can_dev_s *lpc17_caninitialize(int port) { - uint32_t regval; - irqstate_t flags; - flags = irqsave(); - struct can_dev_s *candev=NULL; - -#ifdef CONFIG_LPC17_CAN1 - if( port == 1 ) - { - regval = getreg32(LPC17_SYSCON_PCONP); - regval |= SYSCON_PCONP_PCCAN1; - putreg32(regval, LPC17_SYSCON_PCONP); - - regval = getreg32(LPC17_SYSCON_PCLKSEL0); - regval &= ~SYSCON_PCLKSEL0_CAN1_MASK; - regval |= (SYSCON_PCLKSEL_CCLK4 << SYSCON_PCLKSEL0_CAN1_SHIFT); - putreg32(regval, LPC17_SYSCON_PCLKSEL0); - - lpc17_configgpio(GPIO_CAN1_RD); - lpc17_configgpio(GPIO_CAN1_TD); - - putreg32(0x01,LPC17_CAN1_MOD); - putreg32(0x00,LPC17_CAN1_IER); - putreg32(0x00,LPC17_CAN1_GSR); - putreg32(0x02,LPC17_CAN1_CMR); - putreg32(0x49c009,LPC17_CAN1_BTR); - putreg32(0x00,LPC17_CAN1_MOD); - putreg32(0x01,LPC17_CAN1_IER); - putreg32(0x02,LPC17_CANAF_AFMR); - - candev = &g_can1dev; - } -#endif -#ifdef CONFIG_LPC17_CAN2 - if ( port ==2 ) - { - regval = getreg32(LPC17_SYSCON_PCONP); - regval |= SYSCON_PCONP_PCCAN2; - putreg32(regval, LPC17_SYSCON_PCONP); - - regval = getreg32(LPC17_SYSCON_PCLKSEL0); - regval &= ~SYSCON_PCLKSEL0_CAN2_MASK; - regval |= (SYSCON_PCLKSEL_CCLK4 << SYSCON_PCLKSEL0_CAN2_SHIFT); - putreg32(regval, LPC17_SYSCON_PCLKSEL0); - - lpc17_configgpio(GPIO_CAN2_RD); - lpc17_configgpio(GPIO_CAN2_TD); - - putreg32(0x01,LPC17_CAN2_MOD); - putreg32(0x00,LPC17_CAN2_IER); - putreg32(0x00,LPC17_CAN2_GSR); - putreg32(0x02,LPC17_CAN2_CMR); - putreg32(0x49c009,LPC17_CAN2_BTR); - putreg32(0x00,LPC17_CAN2_MOD); - putreg32(0x01,LPC17_CAN2_IER); - putreg32(0x02,LPC17_CANAF_AFMR); - - candev = &g_can2dev; - } -#endif - irqrestore(flags); - return candev; + FAR struct can_dev_s *candev; + irqstate_t flags; + uint32_t regval; + + canllvdbg("CAN%d\n", port); + + flags = irqsave(); + +#ifdef CONFIG_LPC17_CAN1 + if (port == 1) + { + /* Enable power to the CAN module */ + + regval = can_getcommon(LPC17_SYSCON_PCONP); + regval |= SYSCON_PCONP_PCCAN1; + can_putcommon(LPC17_SYSCON_PCONP, regval); + + /* Enable clocking to the CAN module (not necessary... already done + * in low level clock configuration logic. + */ + + regval = can_getcommon(LPC17_SYSCON_PCLKSEL0); + regval &= ~SYSCON_PCLKSEL0_CAN1_MASK; + regval |= (SYSCON_PCLKSEL_CCLK4 << SYSCON_PCLKSEL0_CAN1_SHIFT); + can_putcommon(LPC17_SYSCON_PCLKSEL0, regval); + + /* Configure CAN GPIO pins */ + + lpc17_configgpio(GPIO_CAN1_RD); + lpc17_configgpio(GPIO_CAN1_TD); + + candev = &g_can1dev; + } + else +#endif +#ifdef CONFIG_LPC17_CAN2 + if (port == 2) + { + /* Enable power to the CAN module */ + + regval = can_getcommon(LPC17_SYSCON_PCONP); + regval |= SYSCON_PCONP_PCCAN2; + can_putcommon(LPC17_SYSCON_PCONP, regval); + + /* Enable clocking to the CAN module (not necessary... already done + * in low level clock configuration logic. + */ + + regval = can_getcommon(LPC17_SYSCON_PCLKSEL0); + regval &= ~SYSCON_PCLKSEL0_CAN2_MASK; + regval |= (SYSCON_PCLKSEL_CCLK4 << SYSCON_PCLKSEL0_CAN2_SHIFT); + can_putcommon(LPC17_SYSCON_PCLKSEL0, regval); + + /* Configure CAN GPIO pins */ + + lpc17_configgpio(GPIO_CAN2_RD); + lpc17_configgpio(GPIO_CAN2_TD); + + candev = &g_can2dev; + } + else +#endif + { + candbg("Unsupported port: %d\n", port); + irqrestore(flags); + return NULL; + } + + /* Then just perform a CAN reset operation */ + + can_reset(candev); + irqrestore(flags); + return candev; } #endif diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_can.h b/nuttx/arch/arm/src/lpc17xx/lpc17_can.h index f59699121..d743925f8 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_can.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_can.h @@ -1,505 +1,505 @@ -/************************************************************************************
- * arch/arm/src/lpc17xx/lpc17_can.h
- *
- * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_CAN_H
-#define __ARCH_ARM_SRC_LPC17XX_LPC17_CAN_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "lpc17_memorymap.h"
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Register offsets *****************************************************************/
-/* CAN acceptance filter registers */
-
-#define LPC17_CANAF_AFMR_OFFSET 0x0000 /* Acceptance Filter Register */
-#define LPC17_CANAF_SFFSA_OFFSET 0x0004 /* Standard Frame Individual Start Address Register */
-#define LPC17_CANAF_SFFGRPSA_OFFSET 0x0008 /* Standard Frame Group Start Address Register */
-#define LPC17_CANAF_EFFSA_OFFSET 0x000c /* Extended Frame Start Address Register */
-#define LPC17_CANAF_EFFGRPSA_OFFSET 0x0010 /* Extended Frame Group Start Address Register */
-#define LPC17_CANAF_EOT_OFFSET 0x0014 /* End of AF Tables register */
-#define LPC17_CANAF_LUTERRAD_OFFSET 0x0018 /* LUT Error Address register */
-#define LPC17_CANAF_LUTERR_OFFSET 0x001c /* LUT Error Register */
-#define LPC17_CANAF_FCANIE_OFFSET 0x0020 /* FullCAN interrupt enable register */
-#define LPC17_CANAF_FCANIC0_OFFSET 0x0024 /* FullCAN interrupt and capture register 0 */
-#define LPC17_CANAF_FCANIC1_OFFSET 0x0028 /* FullCAN interrupt and capture register 1 */
-
-/* Central CAN registers */
-
-#define LPC17_CAN_TXSR_OFFSET 0x0000 /* CAN Central Transmit Status Register */
-#define LPC17_CAN_RXSR_OFFSET 0x0004 /* CAN Central Receive Status Register */
-#define LPC17_CAN_MSR_OFFSET 0x0008 /* CAN Central Miscellaneous Register */
-
-/* CAN1/2 registers */
-
-#define LPC17_CAN_MOD_OFFSET 0x0000 /* CAN operating mode */
-#define LPC17_CAN_CMR_OFFSET 0x0004 /* Command bits */
-#define LPC17_CAN_GSR_OFFSET 0x0008 /* Controller Status and Error Counters */
-#define LPC17_CAN_ICR_OFFSET 0x000c /* Interrupt and capure register */
-#define LPC17_CAN_IER_OFFSET 0x0010 /* Interrupt Enable */
-#define LPC17_CAN_BTR_OFFSET 0x0014 /* Bus Timing */
-#define LPC17_CAN_EWL_OFFSET 0x0018 /* Error Warning Limit */
-#define LPC17_CAN_SR_OFFSET 0x001c /* Status Register */
-#define LPC17_CAN_RFS_OFFSET 0x0020 /* Receive frame status */
-#define LPC17_CAN_RID_OFFSET 0x0024 /* Received Identifier */
-#define LPC17_CAN_RDA_OFFSET 0x0028 /* Received data bytes 1-4 */
-#define LPC17_CAN_RDB_OFFSET 0x002c /* Received data bytes 5-8 */
-#define LPC17_CAN_TFI1_OFFSET 0x0030 /* Transmit frame info (Tx Buffer 1) */
-#define LPC17_CAN_TID1_OFFSET 0x0034 /* Transmit Identifier (Tx Buffer 1) */
-#define LPC17_CAN_TDA1_OFFSET 0x0038 /* Transmit data bytes 1-4 (Tx Buffer 1) */
-#define LPC17_CAN_TDB1_OFFSET 0x003c /* Transmit data bytes 5-8 (Tx Buffer 1) */
-#define LPC17_CAN_TFI2_OFFSET 0x0040 /* Transmit frame info (Tx Buffer 2) */
-#define LPC17_CAN_TID2_OFFSET 0x0044 /* Transmit Identifier (Tx Buffer 2) */
-#define LPC17_CAN_TDA2_OFFSET 0x0048 /* Transmit data bytes 1-4 (Tx Buffer 2) */
-#define LPC17_CAN_TDB2_OFFSET 0x004c /* Transmit data bytes 5-8 (Tx Buffer 2) */
-#define LPC17_CAN_TFI3_OFFSET 0x0050 /* Transmit frame info (Tx Buffer 3) */
-#define LPC17_CAN_TID3_OFFSET 0x0054 /* Transmit Identifier (Tx Buffer 3) */
-#define LPC17_CAN_TDA3_OFFSET 0x0058 /* Transmit data bytes 1-4 (Tx Buffer 3) */
-#define LPC17_CAN_TDB3_OFFSET 0x005c /* Transmit data bytes 5-8 (Tx Buffer 3) */
-
-/* Register addresses ***************************************************************/
-/* CAN acceptance filter registers */
-
-#define LPC17_CANAF_AFMR (LPC17_CANAF_BASE+LPC17_CANAF_AFMR_OFFSET)
-#define LPC17_CANAF_SFFSA (LPC17_CANAF_BASE+LPC17_CANAF_SFFSA_OFFSET)
-#define LPC17_CANAF_SFFGRPSA (LPC17_CANAF_BASE+LPC17_CANAF_SFFGRPSA_OFFSET)
-#define LPC17_CANAF_EFFSA (LPC17_CANAF_BASE+LPC17_CANAF_EFFSA_OFFSET)
-#define LPC17_CANAF_EFFGRPSA (LPC17_CANAF_BASE+LPC17_CANAF_EFFGRPSA_OFFSET)
-#define LPC17_CANAF_EOT (LPC17_CANAF_BASE+LPC17_CANAF_EOT_OFFSET)
-#define LPC17_CANAF_LUTERRAD (LPC17_CANAF_BASE+LPC17_CANAF_LUTERRAD_OFFSET)
-#define LPC17_CANAF_LUTERR (LPC17_CANAF_BASE+LPC17_CANAF_LUTERR_OFFSET)
-#define LPC17_CANAF_FCANIE (LPC17_CANAF_BASE+LPC17_CANAF_FCANIE_OFFSET)
-#define LPC17_CANAF_FCANIC0 (LPC17_CANAF_BASE+LPC17_CANAF_FCANIC0_OFFSET)
-#define LPC17_CANAF_FCANIC1 (LPC17_CANAF_BASE+LPC17_CANAF_FCANIC1_OFFSET)
-
-/* Central CAN registers */
-
-#define LPC17_CAN_TXSR (LPC17_CAN_BASE+LPC17_CAN_TXSR_OFFSET)
-#define LPC17_CAN_RXSR (LPC17_CAN_BASE+LPC17_CAN_RXSR_OFFSET)
-#define LPC17_CAN_MSR (LPC17_CAN_BASE+LPC17_CAN_MSR_OFFSET)
-
-/* CAN1/2 registers */
-
-#define LPC17_CAN1_MOD (LPC17_CAN1_BASE+LPC17_CAN_MOD_OFFSET)
-#define LPC17_CAN1_CMR (LPC17_CAN1_BASE+LPC17_CAN_CMR_OFFSET)
-#define LPC17_CAN1_GSR (LPC17_CAN1_BASE+LPC17_CAN_GSR_OFFSET)
-#define LPC17_CAN1_ICR (LPC17_CAN1_BASE+LPC17_CAN_ICR_OFFSET)
-#define LPC17_CAN1_IER (LPC17_CAN1_BASE+LPC17_CAN_IER_OFFSET)
-#define LPC17_CAN1_BTR (LPC17_CAN1_BASE+LPC17_CAN_BTR_OFFSET)
-#define LPC17_CAN1_EWL (LPC17_CAN1_BASE+LPC17_CAN_EWL_OFFSET)
-#define LPC17_CAN1_SR (LPC17_CAN1_BASE+LPC17_CAN_SR_OFFSET)
-#define LPC17_CAN1_RFS (LPC17_CAN1_BASE+LPC17_CAN_RFS_OFFSET)
-#define LPC17_CAN1_RID (LPC17_CAN1_BASE+LPC17_CAN_RID_OFFSET)
-#define LPC17_CAN1_RDA (LPC17_CAN1_BASE+LPC17_CAN_RDA_OFFSET)
-#define LPC17_CAN1_RDB (LPC17_CAN1_BASE+LPC17_CAN_RDB_OFFSET)
-#define LPC17_CAN1_TFI1 (LPC17_CAN1_BASE+LPC17_CAN_TFI1_OFFSET)
-#define LPC17_CAN1_TID1 (LPC17_CAN1_BASE+LPC17_CAN_TID1_OFFSET)
-#define LPC17_CAN1_TDA1 (LPC17_CAN1_BASE+LPC17_CAN_TDA1_OFFSET)
-#define LPC17_CAN1_TDB1 (LPC17_CAN1_BASE+LPC17_CAN_TDB1_OFFSET)
-#define LPC17_CAN1_TFI2 (LPC17_CAN1_BASE+LPC17_CAN_TFI2_OFFSET)
-#define LPC17_CAN1_TID2 (LPC17_CAN1_BASE+LPC17_CAN_TID2_OFFSET)
-#define LPC17_CAN1_TDA2 (LPC17_CAN1_BASE+LPC17_CAN_TDA2_OFFSET)
-#define LPC17_CAN1_TDB2 (LPC17_CAN1_BASE+LPC17_CAN_TDB2_OFFSET)
-#define LPC17_CAN1_TFI3 (LPC17_CAN1_BASE+LPC17_CAN_TFI3_OFFSET)
-#define LPC17_CAN1_TID3 (LPC17_CAN1_BASE+LPC17_CAN_TID3_OFFSET)
-#define LPC17_CAN1_TDA3 (LPC17_CAN1_BASE+LPC17_CAN_TDA3_OFFSET)
-#define LPC17_CAN1_TDB3 (LPC17_CAN1_BASE+LPC17_CAN_TDB3_OFFSET)
-
-#define LPC17_CAN2_MOD (LPC17_CAN2_BASE+LPC17_CAN_MOD_OFFSET)
-#define LPC17_CAN2_CMR (LPC17_CAN2_BASE+LPC17_CAN_CMR_OFFSET)
-#define LPC17_CAN2_GSR (LPC17_CAN2_BASE+LPC17_CAN_GSR_OFFSET)
-#define LPC17_CAN2_ICR (LPC17_CAN2_BASE+LPC17_CAN_ICR_OFFSET)
-#define LPC17_CAN2_IER (LPC17_CAN2_BASE+LPC17_CAN_IER_OFFSET)
-#define LPC17_CAN2_BTR (LPC17_CAN2_BASE+LPC17_CAN_BTR_OFFSET)
-#define LPC17_CAN2_EWL (LPC17_CAN2_BASE+LPC17_CAN_EWL_OFFSET)
-#define LPC17_CAN2_SR (LPC17_CAN2_BASE+LPC17_CAN_SR_OFFSET)
-#define LPC17_CAN2_RFS (LPC17_CAN2_BASE+LPC17_CAN_RFS_OFFSET)
-#define LPC17_CAN2_RID (LPC17_CAN2_BASE+LPC17_CAN_RID_OFFSET)
-#define LPC17_CAN2_RDA (LPC17_CAN2_BASE+LPC17_CAN_RDA_OFFSET)
-#define LPC17_CAN2_RDB (LPC17_CAN2_BASE+LPC17_CAN_RDB_OFFSET)
-#define LPC17_CAN2_TFI1 (LPC17_CAN2_BASE+LPC17_CAN_TFI1_OFFSET)
-#define LPC17_CAN2_TID1 (LPC17_CAN2_BASE+LPC17_CAN_TID1_OFFSET)
-#define LPC17_CAN2_TDA1 (LPC17_CAN2_BASE+LPC17_CAN_TDA1_OFFSET)
-#define LPC17_CAN2_TDB1 (LPC17_CAN2_BASE+LPC17_CAN_TDB1_OFFSET)
-#define LPC17_CAN2_TFI2 (LPC17_CAN2_BASE+LPC17_CAN_TFI2_OFFSET)
-#define LPC17_CAN2_TID2 (LPC17_CAN2_BASE+LPC17_CAN_TID2_OFFSET)
-#define LPC17_CAN2_TDA2 (LPC17_CAN2_BASE+LPC17_CAN_TDA2_OFFSET)
-#define LPC17_CAN2_TDB2 (LPC17_CAN2_BASE+LPC17_CAN_TDB2_OFFSET)
-#define LPC17_CAN2_TFI3 (LPC17_CAN2_BASE+LPC17_CAN_TFI3_OFFSET)
-#define LPC17_CAN2_TID3 (LPC17_CAN2_BASE+LPC17_CAN_TID3_OFFSET)
-#define LPC17_CAN2_TDA3 (LPC17_CAN2_BASE+LPC17_CAN_TDA3_OFFSET)
-#define LPC17_CAN2_TDB3 (LPC17_CAN2_BASE+LPC17_CAN_TDB3_OFFSET)
-
-/* Register bit definitions *********************************************************/
-/* CAN acceptance filter registers */
-/* Acceptance Filter Register */
-
-#define CANAF_AFMR_ACCOFF (1 << 0) /* Bit 0: AF non-operational; All RX messages ignored */
-#define CANAF_AFMR_ACCBP (1 << 1) /* Bit 1: AF bypass: All RX messages accepted */
-#define CANAF_AFMR_EFCAN (1 << 2) /* Bit 2: Enable Full CAN mode */
- /* Bits 3-31: Reserved */
-/* Standard Frame Individual Start Address Register */
- /* Bits 0-1: Reserved */
-#define CANAF_SFFSA_SHIFT (2) /* Bits 2-10: Address of Standard Identifiers in AF Lookup RAM */
-#define CANAF_SFFSA_MASK (0x01ff << CANAF_SFFSA_SHIFT)
- /* Bits 11-31: Reserved */
-/* Standard Frame Group Start Address Register */
- /* Bits 0-1: Reserved */
-#define CANAF_SFFGRPSA_SHIFT (2) /* Bits 2-10: Address of grouped Standard Identifiers in AF Lookup RAM */
-#define CANAF_SFFGRPSA_MASK (0x01ff << CANAF_SFFGRPSA_SHIFT)
- /* Bits 11-31: Reserved */
-/* Extended Frame Start Address Register */
- /* Bits 0-1: Reserved */
-#define CANAF_EFFSA_SHIFT (2) /* Bits 2-10: Address of Extended Identifiers in AF Lookup RAM */
-#define CANAF_EFFSA_MASK (0x01ff << CANAF_EFFSA_SHIFT)
- /* Bits 11-31: Reserved */
-/* Extended Frame Group Start Address Register */
- /* Bits 0-1: Reserved */
-#define CANAF_EFFGRPSA_SHIFT (2) /* Bits 2-10: Address of grouped Extended Identifiers in AF Lookup RAM */
-#define CANAF_EFFGRPSA_MASK (0x01ff << CANAF_EFFGRPSA_SHIFT)
- /* Bits 11-31: Reserved */
-/* End of AF Tables register */
- /* Bits 0-1: Reserved */
-#define CANAF_EOT_SHIFT (2) /* Bits 2-10: Last active address in last active AF table */
-#define CANAF_EOT_MASK (0x01ff << CANAF_EOT_SHIFT)
- /* Bits 11-31: Reserved */
-/* LUT Error Address register */
- /* Bits 0-1: Reserved */
-#define CANAF_LUTERRAD_SHIFT (2) /* Bits 2-10: Address in AF Lookup RAM of error */
-#define CANAF_LUTERRAD_MASK (0x01ff << CANAF_EOT_SHIFT)
- /* Bits 11-31: Reserved */
-/* LUT Error Register */
-
-#define CANAF_LUTERR_LUTERR (1 << 0) /* Bit 0: AF error in AF RAM tables */
- /* Bits 1-31: Reserved */
-/* FullCAN interrupt enable register */
-
-#define CANAF_FCANIE_FCANIE (1 << 0) /* Bit 0: Global FullCAN Interrupt Enable */
- /* Bits 1-31: Reserved */
-
-/* FullCAN interrupt and capture register 0 */
-
-#define CANAF_FCANIC0_INTPND(n) (1 << (n)) /* n=0,1,2,... 31 */
-
-/* FullCAN interrupt and capture register 1 */
-
-#define CANAF_FCANIC1_INTPND(n) (1 << ((n)-32)) /* n=32,33,...63 */
-
-/* Central CAN registers */
-/* CAN Central Transmit Status Register */
-
-#define CAN_TXSR_TS1 (1 << 0) /* Bit 0: CAN1 sending */
-#define CAN_TXSR_TS2 (1 << 1) /* Bit 1: CAN2 sending */
- /* Bits 2-7: Reserved */
-#define CAN_TXSR_TBS1 (1 << 8) /* Bit 8: All 3 CAN1 TX buffers available */
-#define CAN_TXSR_TBS2 (1 << 9) /* Bit 9: All 3 CAN2 TX buffers available */
- /* Bits 10-15: Reserved */
-#define CAN_TXSR_TCS1 (1 << 16) /* Bit 16: All CAN1 xmissions completed */
-#define CAN_TXSR_TCS2 (1 << 17) /* Bit 17: All CAN2 xmissions completed */
- /* Bits 18-31: Reserved */
-/* CAN Central Receive Status Register */
-
-#define CAN_RXSR_RS1 (1 << 0) /* Bit 0: CAN1 receiving */
-#define CAN_RXSR_RS2 (1 << 1) /* Bit 1: CAN2 receiving */
- /* Bits 2-7: Reserved */
-#define CAN_RXSR_RB1 (1 << 8) /* Bit 8: CAN1 received message available */
-#define CAN_RXSR_RB2 (1 << 9) /* Bit 9: CAN2 received message available */
- /* Bits 10-15: Reserved */
-#define CAN_RXSR_DOS1 (1 << 16) /* Bit 16: All CAN1 message lost */
-#define CAN_RXSR_DOS2 (1 << 17) /* Bit 17: All CAN2 message lost */
- /* Bits 18-31: Reserved */
-/* CAN Central Miscellaneous Register */
-
-#define CAN_MSR_E1 (1 << 0) /* Bit 0: CAN1 error counters at limit */
-#define CAN_MSR_E2 (1 << 1) /* Bit 1: CAN2 error counters at limit */
- /* Bits 2-7: Reserved */
-#define CAN_MSR_BS1 (1 << 8) /* Bit 8: CAN1 busy */
-#define CAN_MSR_BS2 (1 << 9) /* Bit 7: CAN2 busy */
- /* Bits 10-31: Reserved */
-/* CAN1/2 registers */
-/* CAN operating mode */
-
-#define CAN_MOD_RM (1 << 0) /* Bit 0: Reset Mode */
-#define CAN_MOD_LOM (1 << 1) /* Bit 1: Listen Only Mode */
-#define CAN_MOD_STM (1 << 2) /* Bit 2: Self Test Mode */
-#define CAN_MOD_TPM (1 << 3) /* Bit 3: Transmit Priority Mode */
-#define CAN_MOD_SM (1 << 4) /* Bit 4: Sleep Mode */
-#define CAN_MOD_RPM (1 << 5) /* Bit 5: Receive Polarity Mode */
- /* Bit 6: Reserved */
-#define CAN_MOD_TM (1 << 7) /* Bit 7: Test Mode */
- /* Bits 8-31: Reserved */
-/* Command bits */
-
-#define CAN_CMR_TR (1 << 0) /* Bit 0: Transmission Request */
-#define CAN_CMR_AT (1 << 1) /* Bit 1: Abort Transmission */
-#define CAN_CMR_RRB (1 << 2) /* Bit 2: Release Receive Buffer */
-#define CAN_CMR_CDO (1 << 3) /* Bit 3: Clear Data Overrun */
-#define CAN_CMR_SRR (1 << 4) /* Bit 4: Self Reception Request */
-#define CAN_CMR_STB1 (1 << 5) /* Bit 5: Select Tx Buffer 1 */
-#define CAN_CMR_STB2 (1 << 6) /* Bit 6: Select Tx Buffer 2 */
-#define CAN_CMR_STB3 (1 << 7) /* Bit 7: Select Tx Buffer 3 */
- /* Bits 8-31: Reserved */
-/* Controller Status and Error Counters */
-
-#define CAN_GSR_RBS (1 << 0) /* Bit 0: Receive Buffer Status */
-#define CAN_GSR_DOS (1 << 1) /* Bit 1: Data Overrun Status */
-#define CAN_GSR_TBS (1 << 2) /* Bit 2: Transmit Buffer Status */
-#define CAN_GSR_TCS (1 << 3) /* Bit 3: Transmit Complete Status */
-#define CAN_GSR_RS (1 << 4) /* Bit 4: Receive Status */
-#define CAN_GSR_TS (1 << 5) /* Bit 5: Transmit Status */
-#define CAN_GSR_ES (1 << 6) /* Bit 6: Error Status */
-#define CAN_GSR_BS (1 << 7) /* Bit 7: Bus Status */
- /* Bits 8-15: Reserved */
-#define CAN_GSR_RXERR_SHIFT (16) /* Bits 16-23: Rx Error Counter */
-#define CAN_GSR_RXERR_MASK (0xff << CAN_GSR_RXERR_SHIFT)
-#define CAN_GSR_TXERR_SHIFT (24) /* Bits 24-31: Tx Error Counter */
-#define CAN_GSR_TXERR_MASK (0xff << CAN_GSR_TXERR_SHIFT)
-
-/* Interrupt and capure register */
-
-#define CAN_ICR_RI (1 << 0) /* Bit 0: Receive Interrupt */
-#define CAN_ICR_TI1 (1 << 1) /* Bit 1: Transmit Interrupt 1 */
-#define CAN_ICR_EI (1 << 2) /* Bit 2: Error Warning Interrupt */
-#define CAN_ICR_DOI (1 << 3) /* Bit 3: Data Overrun Interrupt */
-#define CAN_ICR_WUI (1 << 4) /* Bit 4: Wake-Up Interrupt */
-#define CAN_ICR_EPI (1 << 5) /* Bit 5: Error Passive Interrupt */
-#define CAN_ICR_ALI (1 << 6) /* Bit 6: Arbitration Lost Interrupt */
-#define CAN_ICR_BEI (1 << 7) /* Bit 7: Bus Error Interrupt */
-#define CAN_ICR_IDI (1 << 8) /* Bit 8: ID Ready Interrupt */
-#define CAN_ICR_TI2 (1 << 9) /* Bit 9: Transmit Interrupt 2 */
-#define CAN_ICR_TI3 (1 << 10) /* Bit 10: Transmit Interrupt 3 */
- /* Bits 11-15: Reserved */
-#define CAN_ICR_ERRBIT_SHIFT (16) /* Bits 16-20: Error Code Capture */
-#define CAN_ICR_ERRBIT_MASK (0x1f << CAN_ICR_ERRBIT_SHIFT)
-# define CAN_ICR_ERRBIT_SOF (3 << CAN_ICR_ERRBIT_SHIFT) /* Start of Frame */
-# define CAN_ICR_ERRBIT_ID28 (2 << CAN_ICR_ERRBIT_SHIFT) /* ID28 ... ID21 */
-# define CAN_ICR_ERRBIT_SRTR (4 << CAN_ICR_ERRBIT_SHIFT) /* SRTR Bit */
-# define CAN_ICR_ERRBIT_IDE (5 << CAN_ICR_ERRBIT_SHIFT) /* DE bit */
-# define CAN_ICR_ERRBIT_ID20 (6 << CAN_ICR_ERRBIT_SHIFT) /* ID20 ... ID18 */
-# define CAN_ICR_ERRBIT_ID17 (7 << CAN_ICR_ERRBIT_SHIFT) /* ID17 ... 13 */
-# define CAN_ICR_ERRBIT_CRC (8 << CAN_ICR_ERRBIT_SHIFT) /* CRC Sequence */
-# define CAN_ICR_ERRBIT_DATA (10 << CAN_ICR_ERRBIT_SHIFT) /* Data Field */
-# define CAN_ICR_ERRBIT_LEN (11 << CAN_ICR_ERRBIT_SHIFT) /* Data Length Code */
-# define CAN_ICR_ERRBIT_ RTR (12 << CAN_ICR_ERRBIT_SHIFT) /* RTR Bit */
-# define CAN_ICR_ERRBIT_ID4 (14 << CAN_ICR_ERRBIT_SHIFT) /* ID4 ... ID0 */
-# define CAN_ICR_ERRBIT_ID12 (15 << CAN_ICR_ERRBIT_SHIFT) /* ID12 ... ID5 */
-# define CAN_ICR_ERRBIT_AERR (17 << CAN_ICR_ERRBIT_SHIFT) /* Active Error Flag */
-# define CAN_ICR_ERRBIT_INTERMSN (18 << CAN_ICR_ERRBIT_SHIFT) /* Intermission */
-# define CAN_ICR_ERRBIT_DOM (19 << CAN_ICR_ERRBIT_SHIFT) /* Tolerate Dominant Bits */
-# define CAN_ICR_ERRBIT_PERR (22 << CAN_ICR_ERRBIT_SHIFT) /* Passive Error Flag */
-# define CAN_ICR_ERRBIT_ERRDLM (23 << CAN_ICR_ERRBIT_SHIFT) /* Error Delimiter */
-# define CAN_ICR_ERRBIT_CRCDLM (24 << CAN_ICR_ERRBIT_SHIFT) /* CRC Delimiter */
-# define CAN_ICR_ERRBIT_ACKSLT (25 << CAN_ICR_ERRBIT_SHIFT) /* Acknowledge Slot */
-# define CAN_ICR_ERRBIT_EOF (26 << CAN_ICR_ERRBIT_SHIFT) /* End of Frame */
-# define CAN_ICR_ERRBIT_ACKDLM (27 << CAN_ICR_ERRBIT_SHIFT) /* Acknowledge Delimiter */
-# define CAN_ICR_ERRBIT_OVLD (28 << CAN_ICR_ERRBIT_SHIFT) /* Overload flag */
-#define CAN_ICR_ERRDIR (1 << 21) /* Bit 21: Direction bit at time of error */
-#define CAN_ICR_ERRC_SHIFT (22) /* Bits 22-23: Type of error */
-#define CAN_ICR_ERRC_MASK (3 << CAN_ICR_ERRC_SHIFT)
-# define CAN_ICR_ERRC_BIT (0 << CAN_ICR_ERRC_SHIFT)
-# define CAN_ICR_ERRC_FORM (1 << CAN_ICR_ERRC_SHIFT)
-# define CAN_ICR_ERRC_STUFF (2 << CAN_ICR_ERRC_SHIFT)
-# define CAN_ICR_ERRC_OTHER (3 << CAN_ICR_ERRC_SHIFT)
-#define CAN_ICR_ALCBIT_SHIFT (24) /* Bits 24-31: Bit number within frame */
-#define CAN_ICR_ALCBIT_MASK (0xff << CAN_ICR_ALCBIT_SHIFT)
-
-/* Interrupt Enable */
-
-#define CAN_IER_RIE (1 << 0) /* Bit 0: Receiver Interrupt Enable */
-#define CAN_IER_TIE1 (1 << 1) /* Bit 1: Transmit Interrupt Enable for Buffer1 */
-#define CAN_IER_EIE (1 << 2) /* Bit 2: Error Warning Interrupt Enable */
-#define CAN_IER_DOIE (1 << 3) /* Bit 3: Data Overrun Interrupt Enable */
-#define CAN_IER_WUIE (1 << 4) /* Bit 4: Wake-Up Interrupt Enable */
-#define CAN_IER_EPIE (1 << 5) /* Bit 5: Error Passive Interrupt Enable */
-#define CAN_IER_ALIE (1 << 6) /* Bit 6: Arbitration Lost Interrupt Enable */
-#define CAN_IER_BEIE (1 << 7) /* Bit 7: Bus Error Interrupt */
-#define CAN_IER_IDIE (1 << 8) /* Bit 8: ID Ready Interrupt Enable */
-#define CAN_IER_TIE2 (1 << 9) /* Bit 9: Transmit Interrupt Enable for Buffer2 */
-#define CAN_IER_TIE3 (1 << 10) /* Bit 10: Transmit Interrupt Enable for Buffer3 */
- /* Bits 11-31: Reserved */
-/* Bus Timing */
-
-#define CAN_BTR_BRP_SHIFT (0) /* Bits 0-9: Baud Rate Prescaler */
-#define CAN_BTR_BRP_MASK (0x3ff << CAN_BTR_BRP_SHIFT)
- /* Bits 10-13: Reserved */
-#define CAN_BTR_SJW_SHIFT (14) /* Bits 14-15: Synchronization Jump Width */
-#define CAN_BTR_SJW_MASK (3 << CAN_BTR_SJW_SHIFT)
-#define CAN_BTR_TESG1_SHIFT (16) /* Bits 16-19: Sync to sample delay */
-#define CAN_BTR_TESG1_MASK (15 << CAN_BTR_TESG1_SHIFT)
-#define CAN_BTR_TESG2_SHIFT (20) /* Bits 20-22: smaple to next delay */
-#define CAN_BTR_TESG2_MASK (7 << CAN_BTR_TESG2_SHIFT)
-#define CAN_BTR_SAM (1 << 23) /* Bit 23: Sampling */
- /* Bits 24-31: Reserved */
-/* Error Warning Limit */
-
-#define CAN_EWL_SHIFT (0) /* Bits 0-7: Error warning limit */
-#define CAN_EWL_MASK (0xff << CAN_EWL_SHIFT)
- /* Bits 8-31: Reserved */
-/* Status Register */
-
-#define CAN_SR_RBS1 (1 << 0) /* Bit 0: Receive Buffer Status */
-#define CAN_SR_DOS1 (1 << 1) /* Bit 1: Data Overrun Status */
-#define CAN_SR_TBS1 (1 << 2) /* Bit 2: Transmit Buffer Status 1 */
-#define CAN_SR_TCS1 (1 << 3) /* Bit 3: Transmission Complete Status */
-#define CAN_SR_RS1 (1 << 4) /* Bit 4: Receive Status */
-#define CAN_SR_TS1 (1 << 5) /* Bit 5: Transmit Status 1 */
-#define CAN_SR_ES1 (1 << 6) /* Bit 6: Error Status */
-#define CAN_SR_BS1 (1 << 7) /* Bit 7: Bus Status */
-#define CAN_SR_RBS2 (1 << 8) /* Bit 8: Receive Buffer Status */
-#define CAN_SR_DOS2 (1 << 9) /* Bit 9: Data Overrun Status */
-#define CAN_SR_TBS2 (1 << 10) /* Bit 10: Transmit Buffer Status 2 */
-#define CAN_SR_TCS2 (1 << 11) /* Bit 11: Transmission Complete Status */
-#define CAN_SR_RS2 (1 << 12) /* Bit 12: Receive Status */
-#define CAN_SR_TS2 (1 << 13) /* Bit 13: Transmit Status 2 */
-#define CAN_SR_ES2 (1 << 14) /* Bit 14: Error Status */
-#define CAN_SR_BS2 (1 << 15) /* Bit 15: Bus Status */
-#define CAN_SR_RBS3 (1 << 16) /* Bit 16: Receive Buffer Status */
-#define CAN_SR_DOS3 (1 << 17) /* Bit 17: Data Overrun Status */
-#define CAN_SR_TBS3 (1 << 18) /* Bit 18: Transmit Buffer Status 3 */
-#define CAN_SR_TCS3 (1 << 19) /* Bit 19: Transmission Complete Status */
-#define CAN_SR_RS3 (1 << 20) /* Bit 20: Receive Status */
-#define CAN_SR_TS3 (1 << 21) /* Bit 21: Transmit Status 3 */
-#define CAN_SR_ES3 (1 << 22) /* Bit 22: Error Status */
-#define CAN_SR_BS3 (1 << 23) /* Bit 23: Bus Status */
- /* Bits 24-31: Reserved */
-/* Receive frame status */
-
-#define CAN_RFS_ID_SHIFT (0) /* Bits 0-9: ID Index */
-#define CAN_RFS_ID_MASK (0x03ff << CAN_RFS_ID_SHIFT)
-#define CAN_RFS_BP (1 << 10) /* Bit 10: Received in AF Bypass mode */
- /* Bits 11-15: Reserved */
-#define CAN_RFS_DLC_SHIFT (16) /* Bits 16-19: Message Data Length Code (DLC) */
-#define CAN_RFS_DLC_MASK (15 << yy)
- /* Bits 20-29: Reserved */
-#define CAN_RFS_RTR (1 << 30) /* Bit 30: Message Remote Transmission Request */
-#define CAN_RFS_FF (1 << 31) /* Bit 31: Message 29-bit vs 11-bit ID */
-
-/* Received Identifier */
-
-#define CAN_RID_ID11_MASK (0x7ff) /* Bits 0-10: 11-bit Identifier (FF=0) */
- /* Bits 11-31: Reserved */
-#define CAN_RID_ID29_MASK (0x1fffffff) /* Bits 0-28: 29-bit Identifiter (FF=1) */
- /* Bits 29-31: Reserved */
-/* Received data bytes 1-4 */
-
-#define CAN_RDA_DATA1_SHIFT (0) /* Bits 0-7: If CANRFS >= 1 */
-#define CAN_RDA_DATA1_MASK (0x0ff << CAN_RDA_DATA1_SHIFT)
-#define CAN_RDA_DATA2_SHIFT (8) /* Bits 8-15: If CANRFS >= 2 */
-#define CAN_RDA_DATA2_MASK (0x0ff << CAN_RDA_DATA2_SHIFT)
-#define CAN_RDA_DATA3_SHIFT (16) /* Bits 16-23: If CANRFS >= 3 */
-#define CAN_RDA_DATA3_MASK (0x0ff << CAN_RDA_DATA3_SHIFT)
-#define CAN_RDA_DATA4_SHIFT (24) /* Bits 24-31: If CANRFS >= 4 */
-#define CAN_RDA_DATA4_MASK (0x0ff << CAN_RDA_DATA4_SHIFT)
-
-/* Received data bytes 5-8 */
-
-#define CAN_RDB_DATA5_SHIFT (0) /* Bits 0-7: If CANRFS >= 5 */
-#define CAN_RDB_DATA5_MASK (0x0ff << CAN_RDB_DATA5_SHIFT)
-#define CAN_RDB_DATA6_SHIFT (8) /* Bits 8-15: If CANRFS >= 6 */
-#define CAN_RDB_DATA6_MASK (0x0ff << CAN_RDB_DATA6_SHIFT)
-#define CAN_RDB_DATA7_SHIFT (16) /* Bits 16-23: If CANRFS >= 7 */
-#define CAN_RDB_DATA7_MASK (0x0ff << CAN_RDB_DATA7_SHIFT)
-#define CAN_RDB_DATA8_SHIFT (24) /* Bits 24-31: If CANRFS >= 8 */
-#define CAN_RDB_DATA8_MASK (0x0ff << CAN_RDB_DATA8_SHIFT)
-
-/* Transmit frame info (Tx Buffer 1), Transmit frame info (Tx Buffer 2), and
- * Transmit frame info (Tx Buffer 3) common bit field definitions
- */
-
-#define CAN_TFI_PRIO_SHIFT (0) /* Bits 0-7: TX buffer priority */
-#define CAN_TFI_PRIO_MASK (0xff << CAN_TFI_PRIO_SHIFT)
- /* Bits 8-15: Reserved */
-#define CAN_TFI_DLC_SHIFT (16) /* Bits 16-19: TX Data Length Code */
-#define CAN_TFI_DLC_MASK (15 << CAN_TFI_DLC_SHIFT)
- /* Bits 20-29: Reserved */
-#define CAN_TFI_RTR (1 << 30) /* Bit 30: TX RTR bit */
-#define CAN_TFI_FF (1 << 31) /* Bit 31: Message 29-bit vs 11-bit ID */
-
-/* Transmit Identifier (Tx Buffer 1), Transmit Identifier (Tx Buffer 2), and
- * Transmit Identifier (Tx Buffer 3) common bit field definitions.
- */
-
-#define CAN_TID_ID11_MASK (0x7ff) /* Bits 0-10: 11-bit Identifier (FF=0) */
- /* Bits 11-31: Reserved */
-#define CAN_TID_ID29_MASK (0x1fffffff) /* Bits 0-28: 29-bit Identifiter (FF=1) */
- /* Bits 29-31: Reserved */
-
-/* Transmit data bytes 1-4 (Tx Buffer 1), Transmit data bytes 1-4 (Tx Buffer 2), and
- * Transmit data bytes 1-4 (Tx Buffer 3) common bit field definitions.
- */
-
-#define CAN_TDA_DATA1_SHIFT (0) /* Bits 0-7: RTR=0 && DLC >= 1 */
-#define CAN_TDA_DATA1_MASK (0x0ff << CAN_TDA_DATA1_SHIFT)
-#define CAN_TDA_DATA2_SHIFT (8) /* Bits 8-15: RTR=0 && DLC >= 2 */
-#define CAN_TDA_DATA2_MASK (0x0ff << CAN_TDA_DATA2_SHIFT)
-#define CAN_TDA_DATA3_SHIFT (16) /* Bits 16-23: RTR=0 && DLC >= 3 */
-#define CAN_TDA_DATA3_MASK (0x0ff << CAN_TDA_DATA3_SHIFT)
-#define CAN_TDA_DATA4_SHIFT (24) /* Bits 24-31: RTR=0 && DLC >= 4 */
-#define CAN_TDA_DATA4_MASK (0x0ff << CAN_TDA_DATA4_SHIFT)
-
-/* Transmit data bytes 5-8 (Tx Buffer 1), Transmit data bytes 5-8 (Tx Buffer 2), and
- * Transmit data bytes 5-8 (Tx Buffer 3) common bit field definitions.
- */
-
-#define CAN_RDB_DATA5_SHIFT (0) /* Bits 0-7: RTR=0 && DLC >= 5 */
-#define CAN_RDB_DATA5_MASK (0x0ff << CAN_RDB_DATA5_SHIFT)
-#define CAN_RDB_DATA6_SHIFT (8) /* Bits 8-15: RTR=0 && DLC >= 6 */
-#define CAN_RDB_DATA6_MASK (0x0ff << CAN_RDB_DATA6_SHIFT)
-#define CAN_RDB_DATA7_SHIFT (16) /* Bits 16-23: RTR=0 && DLC >= 7 */
-#define CAN_RDB_DATA7_MASK (0x0ff << CAN_RDB_DATA7_SHIFT)
-#define CAN_RDB_DATA8_SHIFT (24) /* Bits 24-31: RTR=0 && DLC >= 8 */
-#define CAN_RDB_DATA8_MASK (0x0ff << CAN_RDB_DATA8_SHIFT)
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_CAN_H */
+/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_can.h + * + * Copyright (C) 2010-2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_CAN_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_CAN_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ +/* CAN acceptance filter registers */ + +#define LPC17_CANAF_AFMR_OFFSET 0x0000 /* Acceptance Filter Register */ +#define LPC17_CANAF_SFFSA_OFFSET 0x0004 /* Standard Frame Individual Start Address Register */ +#define LPC17_CANAF_SFFGRPSA_OFFSET 0x0008 /* Standard Frame Group Start Address Register */ +#define LPC17_CANAF_EFFSA_OFFSET 0x000c /* Extended Frame Start Address Register */ +#define LPC17_CANAF_EFFGRPSA_OFFSET 0x0010 /* Extended Frame Group Start Address Register */ +#define LPC17_CANAF_EOT_OFFSET 0x0014 /* End of AF Tables register */ +#define LPC17_CANAF_LUTERRAD_OFFSET 0x0018 /* LUT Error Address register */ +#define LPC17_CANAF_LUTERR_OFFSET 0x001c /* LUT Error Register */ +#define LPC17_CANAF_FCANIE_OFFSET 0x0020 /* FullCAN interrupt enable register */ +#define LPC17_CANAF_FCANIC0_OFFSET 0x0024 /* FullCAN interrupt and capture register 0 */ +#define LPC17_CANAF_FCANIC1_OFFSET 0x0028 /* FullCAN interrupt and capture register 1 */ + +/* Central CAN registers */ + +#define LPC17_CAN_TXSR_OFFSET 0x0000 /* CAN Central Transmit Status Register */ +#define LPC17_CAN_RXSR_OFFSET 0x0004 /* CAN Central Receive Status Register */ +#define LPC17_CAN_MSR_OFFSET 0x0008 /* CAN Central Miscellaneous Register */ + +/* CAN1/2 registers */ + +#define LPC17_CAN_MOD_OFFSET 0x0000 /* CAN operating mode */ +#define LPC17_CAN_CMR_OFFSET 0x0004 /* Command bits */ +#define LPC17_CAN_GSR_OFFSET 0x0008 /* Controller Status and Error Counters */ +#define LPC17_CAN_ICR_OFFSET 0x000c /* Interrupt and capure register */ +#define LPC17_CAN_IER_OFFSET 0x0010 /* Interrupt Enable */ +#define LPC17_CAN_BTR_OFFSET 0x0014 /* Bus Timing */ +#define LPC17_CAN_EWL_OFFSET 0x0018 /* Error Warning Limit */ +#define LPC17_CAN_SR_OFFSET 0x001c /* Status Register */ +#define LPC17_CAN_RFS_OFFSET 0x0020 /* Receive frame status */ +#define LPC17_CAN_RID_OFFSET 0x0024 /* Received Identifier */ +#define LPC17_CAN_RDA_OFFSET 0x0028 /* Received data bytes 1-4 */ +#define LPC17_CAN_RDB_OFFSET 0x002c /* Received data bytes 5-8 */ +#define LPC17_CAN_TFI1_OFFSET 0x0030 /* Transmit frame info (Tx Buffer 1) */ +#define LPC17_CAN_TID1_OFFSET 0x0034 /* Transmit Identifier (Tx Buffer 1) */ +#define LPC17_CAN_TDA1_OFFSET 0x0038 /* Transmit data bytes 1-4 (Tx Buffer 1) */ +#define LPC17_CAN_TDB1_OFFSET 0x003c /* Transmit data bytes 5-8 (Tx Buffer 1) */ +#define LPC17_CAN_TFI2_OFFSET 0x0040 /* Transmit frame info (Tx Buffer 2) */ +#define LPC17_CAN_TID2_OFFSET 0x0044 /* Transmit Identifier (Tx Buffer 2) */ +#define LPC17_CAN_TDA2_OFFSET 0x0048 /* Transmit data bytes 1-4 (Tx Buffer 2) */ +#define LPC17_CAN_TDB2_OFFSET 0x004c /* Transmit data bytes 5-8 (Tx Buffer 2) */ +#define LPC17_CAN_TFI3_OFFSET 0x0050 /* Transmit frame info (Tx Buffer 3) */ +#define LPC17_CAN_TID3_OFFSET 0x0054 /* Transmit Identifier (Tx Buffer 3) */ +#define LPC17_CAN_TDA3_OFFSET 0x0058 /* Transmit data bytes 1-4 (Tx Buffer 3) */ +#define LPC17_CAN_TDB3_OFFSET 0x005c /* Transmit data bytes 5-8 (Tx Buffer 3) */ + +/* Register addresses ***************************************************************/ +/* CAN acceptance filter registers */ + +#define LPC17_CANAF_AFMR (LPC17_CANAF_BASE+LPC17_CANAF_AFMR_OFFSET) +#define LPC17_CANAF_SFFSA (LPC17_CANAF_BASE+LPC17_CANAF_SFFSA_OFFSET) +#define LPC17_CANAF_SFFGRPSA (LPC17_CANAF_BASE+LPC17_CANAF_SFFGRPSA_OFFSET) +#define LPC17_CANAF_EFFSA (LPC17_CANAF_BASE+LPC17_CANAF_EFFSA_OFFSET) +#define LPC17_CANAF_EFFGRPSA (LPC17_CANAF_BASE+LPC17_CANAF_EFFGRPSA_OFFSET) +#define LPC17_CANAF_EOT (LPC17_CANAF_BASE+LPC17_CANAF_EOT_OFFSET) +#define LPC17_CANAF_LUTERRAD (LPC17_CANAF_BASE+LPC17_CANAF_LUTERRAD_OFFSET) +#define LPC17_CANAF_LUTERR (LPC17_CANAF_BASE+LPC17_CANAF_LUTERR_OFFSET) +#define LPC17_CANAF_FCANIE (LPC17_CANAF_BASE+LPC17_CANAF_FCANIE_OFFSET) +#define LPC17_CANAF_FCANIC0 (LPC17_CANAF_BASE+LPC17_CANAF_FCANIC0_OFFSET) +#define LPC17_CANAF_FCANIC1 (LPC17_CANAF_BASE+LPC17_CANAF_FCANIC1_OFFSET) + +/* Central CAN registers */ + +#define LPC17_CAN_TXSR (LPC17_CAN_BASE+LPC17_CAN_TXSR_OFFSET) +#define LPC17_CAN_RXSR (LPC17_CAN_BASE+LPC17_CAN_RXSR_OFFSET) +#define LPC17_CAN_MSR (LPC17_CAN_BASE+LPC17_CAN_MSR_OFFSET) + +/* CAN1/2 registers */ + +#define LPC17_CAN1_MOD (LPC17_CAN1_BASE+LPC17_CAN_MOD_OFFSET) +#define LPC17_CAN1_CMR (LPC17_CAN1_BASE+LPC17_CAN_CMR_OFFSET) +#define LPC17_CAN1_GSR (LPC17_CAN1_BASE+LPC17_CAN_GSR_OFFSET) +#define LPC17_CAN1_ICR (LPC17_CAN1_BASE+LPC17_CAN_ICR_OFFSET) +#define LPC17_CAN1_IER (LPC17_CAN1_BASE+LPC17_CAN_IER_OFFSET) +#define LPC17_CAN1_BTR (LPC17_CAN1_BASE+LPC17_CAN_BTR_OFFSET) +#define LPC17_CAN1_EWL (LPC17_CAN1_BASE+LPC17_CAN_EWL_OFFSET) +#define LPC17_CAN1_SR (LPC17_CAN1_BASE+LPC17_CAN_SR_OFFSET) +#define LPC17_CAN1_RFS (LPC17_CAN1_BASE+LPC17_CAN_RFS_OFFSET) +#define LPC17_CAN1_RID (LPC17_CAN1_BASE+LPC17_CAN_RID_OFFSET) +#define LPC17_CAN1_RDA (LPC17_CAN1_BASE+LPC17_CAN_RDA_OFFSET) +#define LPC17_CAN1_RDB (LPC17_CAN1_BASE+LPC17_CAN_RDB_OFFSET) +#define LPC17_CAN1_TFI1 (LPC17_CAN1_BASE+LPC17_CAN_TFI1_OFFSET) +#define LPC17_CAN1_TID1 (LPC17_CAN1_BASE+LPC17_CAN_TID1_OFFSET) +#define LPC17_CAN1_TDA1 (LPC17_CAN1_BASE+LPC17_CAN_TDA1_OFFSET) +#define LPC17_CAN1_TDB1 (LPC17_CAN1_BASE+LPC17_CAN_TDB1_OFFSET) +#define LPC17_CAN1_TFI2 (LPC17_CAN1_BASE+LPC17_CAN_TFI2_OFFSET) +#define LPC17_CAN1_TID2 (LPC17_CAN1_BASE+LPC17_CAN_TID2_OFFSET) +#define LPC17_CAN1_TDA2 (LPC17_CAN1_BASE+LPC17_CAN_TDA2_OFFSET) +#define LPC17_CAN1_TDB2 (LPC17_CAN1_BASE+LPC17_CAN_TDB2_OFFSET) +#define LPC17_CAN1_TFI3 (LPC17_CAN1_BASE+LPC17_CAN_TFI3_OFFSET) +#define LPC17_CAN1_TID3 (LPC17_CAN1_BASE+LPC17_CAN_TID3_OFFSET) +#define LPC17_CAN1_TDA3 (LPC17_CAN1_BASE+LPC17_CAN_TDA3_OFFSET) +#define LPC17_CAN1_TDB3 (LPC17_CAN1_BASE+LPC17_CAN_TDB3_OFFSET) + +#define LPC17_CAN2_MOD (LPC17_CAN2_BASE+LPC17_CAN_MOD_OFFSET) +#define LPC17_CAN2_CMR (LPC17_CAN2_BASE+LPC17_CAN_CMR_OFFSET) +#define LPC17_CAN2_GSR (LPC17_CAN2_BASE+LPC17_CAN_GSR_OFFSET) +#define LPC17_CAN2_ICR (LPC17_CAN2_BASE+LPC17_CAN_ICR_OFFSET) +#define LPC17_CAN2_IER (LPC17_CAN2_BASE+LPC17_CAN_IER_OFFSET) +#define LPC17_CAN2_BTR (LPC17_CAN2_BASE+LPC17_CAN_BTR_OFFSET) +#define LPC17_CAN2_EWL (LPC17_CAN2_BASE+LPC17_CAN_EWL_OFFSET) +#define LPC17_CAN2_SR (LPC17_CAN2_BASE+LPC17_CAN_SR_OFFSET) +#define LPC17_CAN2_RFS (LPC17_CAN2_BASE+LPC17_CAN_RFS_OFFSET) +#define LPC17_CAN2_RID (LPC17_CAN2_BASE+LPC17_CAN_RID_OFFSET) +#define LPC17_CAN2_RDA (LPC17_CAN2_BASE+LPC17_CAN_RDA_OFFSET) +#define LPC17_CAN2_RDB (LPC17_CAN2_BASE+LPC17_CAN_RDB_OFFSET) +#define LPC17_CAN2_TFI1 (LPC17_CAN2_BASE+LPC17_CAN_TFI1_OFFSET) +#define LPC17_CAN2_TID1 (LPC17_CAN2_BASE+LPC17_CAN_TID1_OFFSET) +#define LPC17_CAN2_TDA1 (LPC17_CAN2_BASE+LPC17_CAN_TDA1_OFFSET) +#define LPC17_CAN2_TDB1 (LPC17_CAN2_BASE+LPC17_CAN_TDB1_OFFSET) +#define LPC17_CAN2_TFI2 (LPC17_CAN2_BASE+LPC17_CAN_TFI2_OFFSET) +#define LPC17_CAN2_TID2 (LPC17_CAN2_BASE+LPC17_CAN_TID2_OFFSET) +#define LPC17_CAN2_TDA2 (LPC17_CAN2_BASE+LPC17_CAN_TDA2_OFFSET) +#define LPC17_CAN2_TDB2 (LPC17_CAN2_BASE+LPC17_CAN_TDB2_OFFSET) +#define LPC17_CAN2_TFI3 (LPC17_CAN2_BASE+LPC17_CAN_TFI3_OFFSET) +#define LPC17_CAN2_TID3 (LPC17_CAN2_BASE+LPC17_CAN_TID3_OFFSET) +#define LPC17_CAN2_TDA3 (LPC17_CAN2_BASE+LPC17_CAN_TDA3_OFFSET) +#define LPC17_CAN2_TDB3 (LPC17_CAN2_BASE+LPC17_CAN_TDB3_OFFSET) + +/* Register bit definitions *********************************************************/ +/* CAN acceptance filter registers */ +/* Acceptance Filter Register */ + +#define CANAF_AFMR_ACCOFF (1 << 0) /* Bit 0: AF non-operational; All RX messages ignored */ +#define CANAF_AFMR_ACCBP (1 << 1) /* Bit 1: AF bypass: All RX messages accepted */ +#define CANAF_AFMR_EFCAN (1 << 2) /* Bit 2: Enable Full CAN mode */ + /* Bits 3-31: Reserved */ +/* Standard Frame Individual Start Address Register */ + /* Bits 0-1: Reserved */ +#define CANAF_SFFSA_SHIFT (2) /* Bits 2-10: Address of Standard Identifiers in AF Lookup RAM */ +#define CANAF_SFFSA_MASK (0x01ff << CANAF_SFFSA_SHIFT) + /* Bits 11-31: Reserved */ +/* Standard Frame Group Start Address Register */ + /* Bits 0-1: Reserved */ +#define CANAF_SFFGRPSA_SHIFT (2) /* Bits 2-10: Address of grouped Standard Identifiers in AF Lookup RAM */ +#define CANAF_SFFGRPSA_MASK (0x01ff << CANAF_SFFGRPSA_SHIFT) + /* Bits 11-31: Reserved */ +/* Extended Frame Start Address Register */ + /* Bits 0-1: Reserved */ +#define CANAF_EFFSA_SHIFT (2) /* Bits 2-10: Address of Extended Identifiers in AF Lookup RAM */ +#define CANAF_EFFSA_MASK (0x01ff << CANAF_EFFSA_SHIFT) + /* Bits 11-31: Reserved */ +/* Extended Frame Group Start Address Register */ + /* Bits 0-1: Reserved */ +#define CANAF_EFFGRPSA_SHIFT (2) /* Bits 2-10: Address of grouped Extended Identifiers in AF Lookup RAM */ +#define CANAF_EFFGRPSA_MASK (0x01ff << CANAF_EFFGRPSA_SHIFT) + /* Bits 11-31: Reserved */ +/* End of AF Tables register */ + /* Bits 0-1: Reserved */ +#define CANAF_EOT_SHIFT (2) /* Bits 2-10: Last active address in last active AF table */ +#define CANAF_EOT_MASK (0x01ff << CANAF_EOT_SHIFT) + /* Bits 11-31: Reserved */ +/* LUT Error Address register */ + /* Bits 0-1: Reserved */ +#define CANAF_LUTERRAD_SHIFT (2) /* Bits 2-10: Address in AF Lookup RAM of error */ +#define CANAF_LUTERRAD_MASK (0x01ff << CANAF_EOT_SHIFT) + /* Bits 11-31: Reserved */ +/* LUT Error Register */ + +#define CANAF_LUTERR_LUTERR (1 << 0) /* Bit 0: AF error in AF RAM tables */ + /* Bits 1-31: Reserved */ +/* FullCAN interrupt enable register */ + +#define CANAF_FCANIE_FCANIE (1 << 0) /* Bit 0: Global FullCAN Interrupt Enable */ + /* Bits 1-31: Reserved */ + +/* FullCAN interrupt and capture register 0 */ + +#define CANAF_FCANIC0_INTPND(n) (1 << (n)) /* n=0,1,2,... 31 */ + +/* FullCAN interrupt and capture register 1 */ + +#define CANAF_FCANIC1_INTPND(n) (1 << ((n)-32)) /* n=32,33,...63 */ + +/* Central CAN registers */ +/* CAN Central Transmit Status Register */ + +#define CAN_TXSR_TS1 (1 << 0) /* Bit 0: CAN1 sending */ +#define CAN_TXSR_TS2 (1 << 1) /* Bit 1: CAN2 sending */ + /* Bits 2-7: Reserved */ +#define CAN_TXSR_TBS1 (1 << 8) /* Bit 8: All 3 CAN1 TX buffers available */ +#define CAN_TXSR_TBS2 (1 << 9) /* Bit 9: All 3 CAN2 TX buffers available */ + /* Bits 10-15: Reserved */ +#define CAN_TXSR_TCS1 (1 << 16) /* Bit 16: All CAN1 xmissions completed */ +#define CAN_TXSR_TCS2 (1 << 17) /* Bit 17: All CAN2 xmissions completed */ + /* Bits 18-31: Reserved */ +/* CAN Central Receive Status Register */ + +#define CAN_RXSR_RS1 (1 << 0) /* Bit 0: CAN1 receiving */ +#define CAN_RXSR_RS2 (1 << 1) /* Bit 1: CAN2 receiving */ + /* Bits 2-7: Reserved */ +#define CAN_RXSR_RB1 (1 << 8) /* Bit 8: CAN1 received message available */ +#define CAN_RXSR_RB2 (1 << 9) /* Bit 9: CAN2 received message available */ + /* Bits 10-15: Reserved */ +#define CAN_RXSR_DOS1 (1 << 16) /* Bit 16: All CAN1 message lost */ +#define CAN_RXSR_DOS2 (1 << 17) /* Bit 17: All CAN2 message lost */ + /* Bits 18-31: Reserved */ +/* CAN Central Miscellaneous Register */ + +#define CAN_MSR_E1 (1 << 0) /* Bit 0: CAN1 error counters at limit */ +#define CAN_MSR_E2 (1 << 1) /* Bit 1: CAN2 error counters at limit */ + /* Bits 2-7: Reserved */ +#define CAN_MSR_BS1 (1 << 8) /* Bit 8: CAN1 busy */ +#define CAN_MSR_BS2 (1 << 9) /* Bit 7: CAN2 busy */ + /* Bits 10-31: Reserved */ +/* CAN1/2 registers */ +/* CAN operating mode */ + +#define CAN_MOD_RM (1 << 0) /* Bit 0: Reset Mode */ +#define CAN_MOD_LOM (1 << 1) /* Bit 1: Listen Only Mode */ +#define CAN_MOD_STM (1 << 2) /* Bit 2: Self Test Mode */ +#define CAN_MOD_TPM (1 << 3) /* Bit 3: Transmit Priority Mode */ +#define CAN_MOD_SM (1 << 4) /* Bit 4: Sleep Mode */ +#define CAN_MOD_RPM (1 << 5) /* Bit 5: Receive Polarity Mode */ + /* Bit 6: Reserved */ +#define CAN_MOD_TM (1 << 7) /* Bit 7: Test Mode */ + /* Bits 8-31: Reserved */ +/* Command bits */ + +#define CAN_CMR_TR (1 << 0) /* Bit 0: Transmission Request */ +#define CAN_CMR_AT (1 << 1) /* Bit 1: Abort Transmission */ +#define CAN_CMR_RRB (1 << 2) /* Bit 2: Release Receive Buffer */ +#define CAN_CMR_CDO (1 << 3) /* Bit 3: Clear Data Overrun */ +#define CAN_CMR_SRR (1 << 4) /* Bit 4: Self Reception Request */ +#define CAN_CMR_STB1 (1 << 5) /* Bit 5: Select Tx Buffer 1 */ +#define CAN_CMR_STB2 (1 << 6) /* Bit 6: Select Tx Buffer 2 */ +#define CAN_CMR_STB3 (1 << 7) /* Bit 7: Select Tx Buffer 3 */ + /* Bits 8-31: Reserved */ +/* Controller Status and Error Counters */ + +#define CAN_GSR_RBS (1 << 0) /* Bit 0: Receive Buffer Status */ +#define CAN_GSR_DOS (1 << 1) /* Bit 1: Data Overrun Status */ +#define CAN_GSR_TBS (1 << 2) /* Bit 2: Transmit Buffer Status */ +#define CAN_GSR_TCS (1 << 3) /* Bit 3: Transmit Complete Status */ +#define CAN_GSR_RS (1 << 4) /* Bit 4: Receive Status */ +#define CAN_GSR_TS (1 << 5) /* Bit 5: Transmit Status */ +#define CAN_GSR_ES (1 << 6) /* Bit 6: Error Status */ +#define CAN_GSR_BS (1 << 7) /* Bit 7: Bus Status */ + /* Bits 8-15: Reserved */ +#define CAN_GSR_RXERR_SHIFT (16) /* Bits 16-23: Rx Error Counter */ +#define CAN_GSR_RXERR_MASK (0xff << CAN_GSR_RXERR_SHIFT) +#define CAN_GSR_TXERR_SHIFT (24) /* Bits 24-31: Tx Error Counter */ +#define CAN_GSR_TXERR_MASK (0xff << CAN_GSR_TXERR_SHIFT) + +/* Interrupt and capture register */ + +#define CAN_ICR_RI (1 << 0) /* Bit 0: Receive Interrupt */ +#define CAN_ICR_TI1 (1 << 1) /* Bit 1: Transmit Interrupt 1 */ +#define CAN_ICR_EI (1 << 2) /* Bit 2: Error Warning Interrupt */ +#define CAN_ICR_DOI (1 << 3) /* Bit 3: Data Overrun Interrupt */ +#define CAN_ICR_WUI (1 << 4) /* Bit 4: Wake-Up Interrupt */ +#define CAN_ICR_EPI (1 << 5) /* Bit 5: Error Passive Interrupt */ +#define CAN_ICR_ALI (1 << 6) /* Bit 6: Arbitration Lost Interrupt */ +#define CAN_ICR_BEI (1 << 7) /* Bit 7: Bus Error Interrupt */ +#define CAN_ICR_IDI (1 << 8) /* Bit 8: ID Ready Interrupt */ +#define CAN_ICR_TI2 (1 << 9) /* Bit 9: Transmit Interrupt 2 */ +#define CAN_ICR_TI3 (1 << 10) /* Bit 10: Transmit Interrupt 3 */ + /* Bits 11-15: Reserved */ +#define CAN_ICR_ERRBIT_SHIFT (16) /* Bits 16-20: Error Code Capture */ +#define CAN_ICR_ERRBIT_MASK (0x1f << CAN_ICR_ERRBIT_SHIFT) +# define CAN_ICR_ERRBIT_SOF (3 << CAN_ICR_ERRBIT_SHIFT) /* Start of Frame */ +# define CAN_ICR_ERRBIT_ID28 (2 << CAN_ICR_ERRBIT_SHIFT) /* ID28 ... ID21 */ +# define CAN_ICR_ERRBIT_SRTR (4 << CAN_ICR_ERRBIT_SHIFT) /* SRTR Bit */ +# define CAN_ICR_ERRBIT_IDE (5 << CAN_ICR_ERRBIT_SHIFT) /* DE bit */ +# define CAN_ICR_ERRBIT_ID20 (6 << CAN_ICR_ERRBIT_SHIFT) /* ID20 ... ID18 */ +# define CAN_ICR_ERRBIT_ID17 (7 << CAN_ICR_ERRBIT_SHIFT) /* ID17 ... 13 */ +# define CAN_ICR_ERRBIT_CRC (8 << CAN_ICR_ERRBIT_SHIFT) /* CRC Sequence */ +# define CAN_ICR_ERRBIT_DATA (10 << CAN_ICR_ERRBIT_SHIFT) /* Data Field */ +# define CAN_ICR_ERRBIT_LEN (11 << CAN_ICR_ERRBIT_SHIFT) /* Data Length Code */ +# define CAN_ICR_ERRBIT_ RTR (12 << CAN_ICR_ERRBIT_SHIFT) /* RTR Bit */ +# define CAN_ICR_ERRBIT_ID4 (14 << CAN_ICR_ERRBIT_SHIFT) /* ID4 ... ID0 */ +# define CAN_ICR_ERRBIT_ID12 (15 << CAN_ICR_ERRBIT_SHIFT) /* ID12 ... ID5 */ +# define CAN_ICR_ERRBIT_AERR (17 << CAN_ICR_ERRBIT_SHIFT) /* Active Error Flag */ +# define CAN_ICR_ERRBIT_INTERMSN (18 << CAN_ICR_ERRBIT_SHIFT) /* Intermission */ +# define CAN_ICR_ERRBIT_DOM (19 << CAN_ICR_ERRBIT_SHIFT) /* Tolerate Dominant Bits */ +# define CAN_ICR_ERRBIT_PERR (22 << CAN_ICR_ERRBIT_SHIFT) /* Passive Error Flag */ +# define CAN_ICR_ERRBIT_ERRDLM (23 << CAN_ICR_ERRBIT_SHIFT) /* Error Delimiter */ +# define CAN_ICR_ERRBIT_CRCDLM (24 << CAN_ICR_ERRBIT_SHIFT) /* CRC Delimiter */ +# define CAN_ICR_ERRBIT_ACKSLT (25 << CAN_ICR_ERRBIT_SHIFT) /* Acknowledge Slot */ +# define CAN_ICR_ERRBIT_EOF (26 << CAN_ICR_ERRBIT_SHIFT) /* End of Frame */ +# define CAN_ICR_ERRBIT_ACKDLM (27 << CAN_ICR_ERRBIT_SHIFT) /* Acknowledge Delimiter */ +# define CAN_ICR_ERRBIT_OVLD (28 << CAN_ICR_ERRBIT_SHIFT) /* Overload flag */ +#define CAN_ICR_ERRDIR (1 << 21) /* Bit 21: Direction bit at time of error */ +#define CAN_ICR_ERRC_SHIFT (22) /* Bits 22-23: Type of error */ +#define CAN_ICR_ERRC_MASK (3 << CAN_ICR_ERRC_SHIFT) +# define CAN_ICR_ERRC_BIT (0 << CAN_ICR_ERRC_SHIFT) +# define CAN_ICR_ERRC_FORM (1 << CAN_ICR_ERRC_SHIFT) +# define CAN_ICR_ERRC_STUFF (2 << CAN_ICR_ERRC_SHIFT) +# define CAN_ICR_ERRC_OTHER (3 << CAN_ICR_ERRC_SHIFT) +#define CAN_ICR_ALCBIT_SHIFT (24) /* Bits 24-31: Bit number within frame */ +#define CAN_ICR_ALCBIT_MASK (0xff << CAN_ICR_ALCBIT_SHIFT) + +/* Interrupt Enable */ + +#define CAN_IER_RIE (1 << 0) /* Bit 0: Receiver Interrupt Enable */ +#define CAN_IER_TIE1 (1 << 1) /* Bit 1: Transmit Interrupt Enable for Buffer1 */ +#define CAN_IER_EIE (1 << 2) /* Bit 2: Error Warning Interrupt Enable */ +#define CAN_IER_DOIE (1 << 3) /* Bit 3: Data Overrun Interrupt Enable */ +#define CAN_IER_WUIE (1 << 4) /* Bit 4: Wake-Up Interrupt Enable */ +#define CAN_IER_EPIE (1 << 5) /* Bit 5: Error Passive Interrupt Enable */ +#define CAN_IER_ALIE (1 << 6) /* Bit 6: Arbitration Lost Interrupt Enable */ +#define CAN_IER_BEIE (1 << 7) /* Bit 7: Bus Error Interrupt */ +#define CAN_IER_IDIE (1 << 8) /* Bit 8: ID Ready Interrupt Enable */ +#define CAN_IER_TIE2 (1 << 9) /* Bit 9: Transmit Interrupt Enable for Buffer2 */ +#define CAN_IER_TIE3 (1 << 10) /* Bit 10: Transmit Interrupt Enable for Buffer3 */ + /* Bits 11-31: Reserved */ +/* Bus Timing */ + +#define CAN_BTR_BRP_SHIFT (0) /* Bits 0-9: Baud Rate Prescaler */ +#define CAN_BTR_BRP_MASK (0x3ff << CAN_BTR_BRP_SHIFT) + /* Bits 10-13: Reserved */ +#define CAN_BTR_SJW_SHIFT (14) /* Bits 14-15: Synchronization Jump Width */ +#define CAN_BTR_SJW_MASK (3 << CAN_BTR_SJW_SHIFT) +#define CAN_BTR_TESG1_SHIFT (16) /* Bits 16-19: Sync to sample delay */ +#define CAN_BTR_TESG1_MASK (15 << CAN_BTR_TESG1_SHIFT) +#define CAN_BTR_TESG2_SHIFT (20) /* Bits 20-22: smaple to next delay */ +#define CAN_BTR_TESG2_MASK (7 << CAN_BTR_TESG2_SHIFT) +#define CAN_BTR_SAM (1 << 23) /* Bit 23: Sampling */ + /* Bits 24-31: Reserved */ +/* Error Warning Limit */ + +#define CAN_EWL_SHIFT (0) /* Bits 0-7: Error warning limit */ +#define CAN_EWL_MASK (0xff << CAN_EWL_SHIFT) + /* Bits 8-31: Reserved */ +/* Status Register */ + +#define CAN_SR_RBS1 (1 << 0) /* Bit 0: Receive Buffer Status */ +#define CAN_SR_DOS1 (1 << 1) /* Bit 1: Data Overrun Status */ +#define CAN_SR_TBS1 (1 << 2) /* Bit 2: Transmit Buffer Status 1 */ +#define CAN_SR_TCS1 (1 << 3) /* Bit 3: Transmission Complete Status */ +#define CAN_SR_RS1 (1 << 4) /* Bit 4: Receive Status */ +#define CAN_SR_TS1 (1 << 5) /* Bit 5: Transmit Status 1 */ +#define CAN_SR_ES1 (1 << 6) /* Bit 6: Error Status */ +#define CAN_SR_BS1 (1 << 7) /* Bit 7: Bus Status */ +#define CAN_SR_RBS2 (1 << 8) /* Bit 8: Receive Buffer Status */ +#define CAN_SR_DOS2 (1 << 9) /* Bit 9: Data Overrun Status */ +#define CAN_SR_TBS2 (1 << 10) /* Bit 10: Transmit Buffer Status 2 */ +#define CAN_SR_TCS2 (1 << 11) /* Bit 11: Transmission Complete Status */ +#define CAN_SR_RS2 (1 << 12) /* Bit 12: Receive Status */ +#define CAN_SR_TS2 (1 << 13) /* Bit 13: Transmit Status 2 */ +#define CAN_SR_ES2 (1 << 14) /* Bit 14: Error Status */ +#define CAN_SR_BS2 (1 << 15) /* Bit 15: Bus Status */ +#define CAN_SR_RBS3 (1 << 16) /* Bit 16: Receive Buffer Status */ +#define CAN_SR_DOS3 (1 << 17) /* Bit 17: Data Overrun Status */ +#define CAN_SR_TBS3 (1 << 18) /* Bit 18: Transmit Buffer Status 3 */ +#define CAN_SR_TCS3 (1 << 19) /* Bit 19: Transmission Complete Status */ +#define CAN_SR_RS3 (1 << 20) /* Bit 20: Receive Status */ +#define CAN_SR_TS3 (1 << 21) /* Bit 21: Transmit Status 3 */ +#define CAN_SR_ES3 (1 << 22) /* Bit 22: Error Status */ +#define CAN_SR_BS3 (1 << 23) /* Bit 23: Bus Status */ + /* Bits 24-31: Reserved */ +/* Receive frame status */ + +#define CAN_RFS_ID_SHIFT (0) /* Bits 0-9: ID Index */ +#define CAN_RFS_ID_MASK (0x03ff << CAN_RFS_ID_SHIFT) +#define CAN_RFS_BP (1 << 10) /* Bit 10: Received in AF Bypass mode */ + /* Bits 11-15: Reserved */ +#define CAN_RFS_DLC_SHIFT (16) /* Bits 16-19: Message Data Length Code (DLC) */ +#define CAN_RFS_DLC_MASK (15 << CAN_RFS_DLC_SHIFT) + /* Bits 20-29: Reserved */ +#define CAN_RFS_RTR (1 << 30) /* Bit 30: Message Remote Transmission Request */ +#define CAN_RFS_FF (1 << 31) /* Bit 31: Message 29-bit vs 11-bit ID */ + +/* Received Identifier */ + +#define CAN_RID_ID11_MASK (0x7ff) /* Bits 0-10: 11-bit Identifier (FF=0) */ + /* Bits 11-31: Reserved */ +#define CAN_RID_ID29_MASK (0x1fffffff) /* Bits 0-28: 29-bit Identifiter (FF=1) */ + /* Bits 29-31: Reserved */ +/* Received data bytes 1-4 */ + +#define CAN_RDA_DATA1_SHIFT (0) /* Bits 0-7: If CANRFS >= 1 */ +#define CAN_RDA_DATA1_MASK (0x0ff << CAN_RDA_DATA1_SHIFT) +#define CAN_RDA_DATA2_SHIFT (8) /* Bits 8-15: If CANRFS >= 2 */ +#define CAN_RDA_DATA2_MASK (0x0ff << CAN_RDA_DATA2_SHIFT) +#define CAN_RDA_DATA3_SHIFT (16) /* Bits 16-23: If CANRFS >= 3 */ +#define CAN_RDA_DATA3_MASK (0x0ff << CAN_RDA_DATA3_SHIFT) +#define CAN_RDA_DATA4_SHIFT (24) /* Bits 24-31: If CANRFS >= 4 */ +#define CAN_RDA_DATA4_MASK (0x0ff << CAN_RDA_DATA4_SHIFT) + +/* Received data bytes 5-8 */ + +#define CAN_RDB_DATA5_SHIFT (0) /* Bits 0-7: If CANRFS >= 5 */ +#define CAN_RDB_DATA5_MASK (0x0ff << CAN_RDB_DATA5_SHIFT) +#define CAN_RDB_DATA6_SHIFT (8) /* Bits 8-15: If CANRFS >= 6 */ +#define CAN_RDB_DATA6_MASK (0x0ff << CAN_RDB_DATA6_SHIFT) +#define CAN_RDB_DATA7_SHIFT (16) /* Bits 16-23: If CANRFS >= 7 */ +#define CAN_RDB_DATA7_MASK (0x0ff << CAN_RDB_DATA7_SHIFT) +#define CAN_RDB_DATA8_SHIFT (24) /* Bits 24-31: If CANRFS >= 8 */ +#define CAN_RDB_DATA8_MASK (0x0ff << CAN_RDB_DATA8_SHIFT) + +/* Transmit frame info (Tx Buffer 1), Transmit frame info (Tx Buffer 2), and + * Transmit frame info (Tx Buffer 3) common bit field definitions + */ + +#define CAN_TFI_PRIO_SHIFT (0) /* Bits 0-7: TX buffer priority */ +#define CAN_TFI_PRIO_MASK (0xff << CAN_TFI_PRIO_SHIFT) + /* Bits 8-15: Reserved */ +#define CAN_TFI_DLC_SHIFT (16) /* Bits 16-19: TX Data Length Code */ +#define CAN_TFI_DLC_MASK (15 << CAN_TFI_DLC_SHIFT) + /* Bits 20-29: Reserved */ +#define CAN_TFI_RTR (1 << 30) /* Bit 30: TX RTR bit */ +#define CAN_TFI_FF (1 << 31) /* Bit 31: Message 29-bit vs 11-bit ID */ + +/* Transmit Identifier (Tx Buffer 1), Transmit Identifier (Tx Buffer 2), and + * Transmit Identifier (Tx Buffer 3) common bit field definitions. + */ + +#define CAN_TID_ID11_MASK (0x7ff) /* Bits 0-10: 11-bit Identifier (FF=0) */ + /* Bits 11-31: Reserved */ +#define CAN_TID_ID29_MASK (0x1fffffff) /* Bits 0-28: 29-bit Identifiter (FF=1) */ + /* Bits 29-31: Reserved */ + +/* Transmit data bytes 1-4 (Tx Buffer 1), Transmit data bytes 1-4 (Tx Buffer 2), and + * Transmit data bytes 1-4 (Tx Buffer 3) common bit field definitions. + */ + +#define CAN_TDA_DATA1_SHIFT (0) /* Bits 0-7: RTR=0 && DLC >= 1 */ +#define CAN_TDA_DATA1_MASK (0x0ff << CAN_TDA_DATA1_SHIFT) +#define CAN_TDA_DATA2_SHIFT (8) /* Bits 8-15: RTR=0 && DLC >= 2 */ +#define CAN_TDA_DATA2_MASK (0x0ff << CAN_TDA_DATA2_SHIFT) +#define CAN_TDA_DATA3_SHIFT (16) /* Bits 16-23: RTR=0 && DLC >= 3 */ +#define CAN_TDA_DATA3_MASK (0x0ff << CAN_TDA_DATA3_SHIFT) +#define CAN_TDA_DATA4_SHIFT (24) /* Bits 24-31: RTR=0 && DLC >= 4 */ +#define CAN_TDA_DATA4_MASK (0x0ff << CAN_TDA_DATA4_SHIFT) + +/* Transmit data bytes 5-8 (Tx Buffer 1), Transmit data bytes 5-8 (Tx Buffer 2), and + * Transmit data bytes 5-8 (Tx Buffer 3) common bit field definitions. + */ + +#define CAN_RDB_DATA5_SHIFT (0) /* Bits 0-7: RTR=0 && DLC >= 5 */ +#define CAN_RDB_DATA5_MASK (0x0ff << CAN_RDB_DATA5_SHIFT) +#define CAN_RDB_DATA6_SHIFT (8) /* Bits 8-15: RTR=0 && DLC >= 6 */ +#define CAN_RDB_DATA6_MASK (0x0ff << CAN_RDB_DATA6_SHIFT) +#define CAN_RDB_DATA7_SHIFT (16) /* Bits 16-23: RTR=0 && DLC >= 7 */ +#define CAN_RDB_DATA7_MASK (0x0ff << CAN_RDB_DATA7_SHIFT) +#define CAN_RDB_DATA8_SHIFT (24) /* Bits 24-31: RTR=0 && DLC >= 8 */ +#define CAN_RDB_DATA8_MASK (0x0ff << CAN_RDB_DATA8_SHIFT) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_CAN_H */ diff --git a/nuttx/arch/arm/src/stm32/stm32_can.c b/nuttx/arch/arm/src/stm32/stm32_can.c index df986f4fe..08f932b37 100755 --- a/nuttx/arch/arm/src/stm32/stm32_can.c +++ b/nuttx/arch/arm/src/stm32/stm32_can.c @@ -708,7 +708,7 @@ static int can_ioctl(FAR struct can_dev_s *dev, int cmd, unsigned long arg) * ****************************************************************************/ -static int can_remoterequest(FAR struct can_dev_s *dev, uint16_t id) +static int can_remoterequest(FAR struct can_dev_s *dev, uint16_t id) { #warning "Remote request not implemented" return -ENOSYS; @@ -918,7 +918,8 @@ static bool can_txempty(FAR struct can_dev_s *dev) * CAN RX FIFO 0 interrupt handler * * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. + * irq - The IRQ number of the interrupt. + * context - The register state save array at the time of the interrupt. * * Returned Value: * Zero on success; a negated errno on failure diff --git a/nuttx/configs/olimex-lpc1766stk/README.txt b/nuttx/configs/olimex-lpc1766stk/README.txt index 9edbfc513..4a00f0e36 100755 --- a/nuttx/configs/olimex-lpc1766stk/README.txt +++ b/nuttx/configs/olimex-lpc1766stk/README.txt @@ -879,6 +879,20 @@ Where <subdir> is one of the following: +CONFIG_GPIO_IRQ=y +CONFIG_ARCH_IRQBUTTONS=y + 4. This example supports the CAN loopback test (apps/examples/can) but this + must be manually enabled by selecting: + + CONFIG_CAN=y : Enable the generic CAN infrastructure + CONFIG_LPC17_CAN1=y : Enable CAN1 + CONFIG_CAN_LOOPBACK=y : Enable CAN loopback mode + + See also apps/examples/README.txt + + Special CAN-only debug options: + + CONFIG_DEBUG_CAN + CONFIG_CAN_REGDEBUG + nx: An example using the NuttX graphics system (NX). This example uses the Nokia 6100 LCD driver. NOTE: The Nokia 6100 driver does not diff --git a/nuttx/configs/olimex-lpc1766stk/nsh/appconfig b/nuttx/configs/olimex-lpc1766stk/nsh/appconfig index a2f7f9f26..e9af6d3b2 100644 --- a/nuttx/configs/olimex-lpc1766stk/nsh/appconfig +++ b/nuttx/configs/olimex-lpc1766stk/nsh/appconfig @@ -55,3 +55,8 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CONFIGURED_APPS += examples/buttons endif +ifeq ($(CONFIG_CAN),y) +CONFIGURED_APPS += examples/can +endif + + diff --git a/nuttx/configs/olimex-lpc1766stk/nsh/defconfig b/nuttx/configs/olimex-lpc1766stk/nsh/defconfig index 404e7c7f3..fb163ef41 100755 --- a/nuttx/configs/olimex-lpc1766stk/nsh/defconfig +++ b/nuttx/configs/olimex-lpc1766stk/nsh/defconfig @@ -337,6 +337,8 @@ CONFIG_DEBUG_VERBOSE=n CONFIG_DEBUG_SYMBOLS=n CONFIG_DEBUG_NET=n CONFIG_DEBUG_USB=n +CONFIG_DEBUG_GPIO=n +CONFIG_DEBUG_CAN=n CONFIG_MM_REGIONS=2 CONFIG_ARCH_LOWPUTC=y CONFIG_RR_INTERVAL=200 @@ -625,6 +627,28 @@ CONFIG_NET_DHCP_LIGHT=n CONFIG_NET_RESOLV_ENTRIES=4 # +# CAN device driver settings +# +# CONFIG_CAN - Enables CAN support (one or both of CONFIG_LPC17_CAN1 or +# CONFIG_LPC17_CAN2 must also be defined) +# CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages. +# Default: 8 +# CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests. +# Default: 4 +# CONFIG_CAN_LOOPBACK - A CAN driver may or may not support a loopback +# mode for testing. The STM32 CAN driver does support loopback mode. +# CONFIG_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC17_CAN1 is defined. +# CONFIG_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC17_CAN2 is defined. +# +CONFIG_CAN=n +#CONFIG_CAN_FIFOSIZE +#CONFIG_CAN_NPENDINGRTR +CONFIG_CAN_LOOPBACK=n +CONFIG_CAN_REGDEBUG=n +CONFIG_CAN1_BAUD=700000 +CONFIG_CAN2_BAUD=700000 + +# # USB Device Configuration # # CONFIG_USBDEV diff --git a/nuttx/configs/olimex-lpc1766stk/src/Makefile b/nuttx/configs/olimex-lpc1766stk/src/Makefile index f006461bc..a2bdab303 100755 --- a/nuttx/configs/olimex-lpc1766stk/src/Makefile +++ b/nuttx/configs/olimex-lpc1766stk/src/Makefile @@ -1,7 +1,7 @@ ############################################################################ # configs/olimex-lpc1766stk/src/Makefile # -# Copyright (C) 2010 Gregory Nutt. All rights reserved. +# Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved. # Author: Gregory Nutt <gnutt@nuttx.org> # # Redistribution and use in source and binary forms, with or without @@ -56,6 +56,10 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += up_buttons.c endif +ifeq ($(CONFIG_CAN),y) +CSRCS += up_can.c +endif + AOBJS = $(ASRCS:.S=$(OBJEXT)) COBJS = $(CSRCS:.c=$(OBJEXT)) diff --git a/nuttx/configs/stm3240g-eval/src/up_can.c b/nuttx/configs/stm3240g-eval/src/up_can.c index eafcec0bf..713a5325a 100644 --- a/nuttx/configs/stm3240g-eval/src/up_can.c +++ b/nuttx/configs/stm3240g-eval/src/up_can.c @@ -139,4 +139,4 @@ int can_devinit(void) return OK; } -#endif /* CONFIG_STM32_CAN || CONFIG_STM32_CAN2 || CONFIG_STM32_CAN3 */ +#endif /* CONFIG_CAN && (CONFIG_STM32_CAN2 || CONFIG_STM32_CAN3) */ |