diff options
| -rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32_eth.h | 14 | ||||
| -rwxr-xr-x | nuttx/arch/arm/src/stm32/stm32_eth.c | 521 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c | 10 | ||||
| -rw-r--r-- | nuttx/arch/mips/src/pic32mx/pic32mx-head.S | 4 | ||||
| -rwxr-xr-x | nuttx/configs/stm3240g-eval/README.txt | 19 | ||||
| -rwxr-xr-x | nuttx/configs/stm3240g-eval/include/board.h | 22 | ||||
| -rwxr-xr-x | nuttx/configs/stm3240g-eval/nsh/defconfig | 33 | ||||
| -rwxr-xr-x | nuttx/configs/stm3240g-eval/ostest/defconfig | 33 |
8 files changed, 616 insertions, 40 deletions
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_eth.h b/nuttx/arch/arm/src/stm32/chip/stm32_eth.h index b757992a6..6237521fe 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32_eth.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32_eth.h @@ -245,10 +245,18 @@ #define ETH_MACMIIAR_MW (1 << 1) /* Bit 1: MII write */ #define ETH_MACMIIAR_CR_SHIFT (2) /* Bits 2-4: Clock range */ #define ETH_MACMIIAR_CR_MASK (7 << ETH_MACMIIAR_CR_SHIFT) -# define ETH_MACMIIAR_CR_60_100 (0 << ETH_MACMIIAR_CR_SHIFT) /* 000 60-100 MHz HCLK/42 */ +#if 0 /* Per the reference manual */ +# define ETH_MACMIIAR_CR_60_100 (0 << ETH_MACMIIAR_CR_SHIFT) /* 000 60-100 MHzHCLK/42 */ # define ETH_MACMIIAR_CR_100_168 (1 << ETH_MACMIIAR_CR_SHIFT) /* 001 100-168 MHz HCLK/62 */ -# define ETH_MACMIIAR_CR_20_35 (2 << ETH_MACMIIAR_CR_SHIFT) /* 010 20-35 MHz HCLK/16 */ -# define ETH_MACMIIAR_CR_35_60 (3 << ETH_MACMIIAR_CR_SHIFT) /* 011 35-60 MHz HCLK/26 */ +# define ETH_MACMIIAR_CR_20_35 (2 << ETH_MACMIIAR_CR_SHIFT) /* 010 20-35 MHz HCLK/16 */ +# define ETH_MACMIIAR_CR_35_60 (3 << ETH_MACMIIAR_CR_SHIFT) /* 011 35-60 MHz HCLK/26 */ +#else /* Per the driver example */ +# define ETH_MACMIIAR_CR_60_100 (0 << ETH_MACMIIAR_CR_SHIFT) /* 000 60-100 MHz HCLK/42 */ +# define ETH_MACMIIAR_CR_100_150 (1 << ETH_MACMIIAR_CR_SHIFT) /* 001 100-150 MHz HCLK/62 */ +# define ETH_MACMIIAR_CR_20_35 (2 << ETH_MACMIIAR_CR_SHIFT) /* 010 20-35 MHz HCLK/16 */ +# define ETH_MACMIIAR_CR_35_60 (3 << ETH_MACMIIAR_CR_SHIFT) /* 011 35-60 MHz HCLK/26 */ +# define ETH_MACMIIAR_CR_150_168 (4 << ETH_MACMIIAR_CR_SHIFT) /* 100 150-168 MHz HCLK/102 */ +#endif #define ETH_MACMIIAR_MR_SHIFT (6) /* Bits 6-10: MII register */ #define ETH_MACMIIAR_MR_MASK (31 << ETH_MACMIIAR_MR_SHIFT) #define ETH_MACMIIAR_PA_SHIFT (11) /* Bits 11-15: PHY address */ diff --git a/nuttx/arch/arm/src/stm32/stm32_eth.c b/nuttx/arch/arm/src/stm32/stm32_eth.c index eb372262c..381de2e1c 100755 --- a/nuttx/arch/arm/src/stm32/stm32_eth.c +++ b/nuttx/arch/arm/src/stm32/stm32_eth.c @@ -50,6 +50,7 @@ #include <nuttx/irq.h> #include <nuttx/arch.h> +#include <nuttx/mii.h> #include <net/uip/uip.h> #include <net/uip/uip-arp.h> @@ -75,11 +76,22 @@ * Definitions ****************************************************************************/ /* Configuration ************************************************************/ +/* See configs/stm3240g-eval/README.txt for an explanation of the configuration + * settings. + */ + +#if STM32_NETHERNET > 1 +# error "Logic to support multiple Ethernet interfaces is incomplete" +#endif #ifndef CONFIG_STM32_SYSCFG # error "CONFIG_STM32_SYSCFG must be defined in the NuttX configuration" #endif +#ifndef CONFIG_STM32_PHYADDR +# error "CONFIG_STM32_PHYADDR must be defined in the NuttX configuration" +#endif + #if !defined(CONFIG_STM32_MII) && !defined(CONFIG_STM32_RMII) # warning "Neither CONFIG_STM32_MII nor CONFIG_STM32_RMII defined" #endif @@ -93,8 +105,68 @@ # warning "Neither CONFIG_STM32_MII_MCO1 nor CONFIG_STM32_MII_MCO2 defined" # endif # if defined(CONFIG_STM32_MII_MCO1) && defined(CONFIG_STM32_MII_MCO2) -# warning "Both CONFIG_STM32_MII_MCO1 and CONFIG_STM32_MII_MCO2 defined" +# error "Both CONFIG_STM32_MII_MCO1 and CONFIG_STM32_MII_MCO2 defined" +# endif +#endif + +#ifdef CONFIG_STM32_AUTONEG +# ifndef CONFIG_STM32_PHYSR +# error "CONFIG_STM32_PHYSR must be defined in the NuttX configuration" # endif +# ifndef CONFIG_STM32_PHYSR_SPEED +# error "CONFIG_STM32_PHYSR_SPEED must be defined in the NuttX configuration" +# endif +# ifndef CONFIG_STM32_PHYSR_100MBPS +# error "CONFIG_STM32_PHYSR_100MBPS must be defined in the NuttX configuration" +# endif +# ifndef CONFIG_STM32_PHYSR_MODE +# error "CONFIG_STM32_PHYSR_MODE must be defined in the NuttX configuration" +# endif +# ifndef CONFIG_STM32_PHYSR_FULLDUPLEX +# error "CONFIG_STM32_PHYSR_FULLDUPLEX must be defined in the NuttX configuration" +# endif +#endif + +#ifdef CONFIG_STM32_ETH_PTP +# warning "CONFIG_STM32_ETH_PTP is not yet supported" +#endif + +/* This driver always uses enhanced descriptors. However, this would not be + * the cased if support is added for stamping and/or IPv4 checksum offload + */ + +#define CONFIG_STM32_ETH_ENHANCEDDESC 1 + +/* Ethernet buffer sizes and numbers */ + +#ifndef CONFIG_STM32_ETH_RXBUFSIZE +# define CONFIG_STM32_ETH_RXBUFSIZE CONFIG_NET_BUFSIZE +#endif +#ifndef CONFIG_STM32_ETH_TXBUFSIZE +# define CONFIG_STM32_ETH_TXBUFSIZE CONFIG_NET_BUFSIZE +#endif +#ifndef CONFIG_STM32_ETH_RXNBUFFERS +# define CONFIG_STM32_ETH_RXNBUFFERS 20 +#endif +#ifndef CONFIG_STM32_ETH_TXNBUFFERS +# define CONFIG_STM32_ETH_TXNBUFFERS 5 +#endif + +/* Clocking *****************************************************************/ +/* Set MACMIIAR CR bits depending on HCLK setting */ + +#if STM32_HCLK_FREQUENCY >= 20000000 && STM32_HCLK_FREQUENCY < 35000000 +# define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_20_35 +#elif STM32_HCLK_FREQUENCY >= 35000000 && STM32_HCLK_FREQUENCY < 60000000 +# define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_35_60 +#elif STM32_HCLK_FREQUENCY >= 60000000 && STM32_HCLK_FREQUENCY < 100000000 +# define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_60_100 +#elif STM32_HCLK_FREQUENCY >= 100000000 && STM32_HCLK_FREQUENCY < 150000000 +# define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_100_150 +#elif STM32_HCLK_FREQUENCY >= 150000000 && STM32_HCLK_FREQUENCY <= 168000000 +# define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_150_168 +#else +# error "STM32_HCLK_FREQUENCY not supportable" #endif /* Timing *******************************************************************/ @@ -102,12 +174,22 @@ * second */ -#define STM32_WDDELAY (1*CLK_TCK) -#define STM32_POLLHSEC (1*2) +#define STM32_WDDELAY (1*CLK_TCK) +#define STM32_POLLHSEC (1*2) /* TX timeout = 1 minute */ -#define STM32_TXTIMEOUT (60*CLK_TCK) +#define STM32_TXTIMEOUT (60*CLK_TCK) + +/* PHY reset/configuration delays in milliseconds */ + +#define PHY_RESET_DELAY (65) +#define PHY_CONFIG_DELAY (1000) + +/* PHY read/write delays in loop counts */ + +#define PHY_READ_TIMEOUT (0x0004ffff) +#define PHY_WRITE_TIMEOUT (0x0004ffff) /* Helpers ******************************************************************/ /* This is a helper pointer for accessing the contents of the Ethernet @@ -126,7 +208,9 @@ struct stm32_ethmac_s { - bool bifup; /* true:ifup false:ifdown */ + uint8_t ifup : 1; /* true:ifup false:ifdown */ + uint8_t mbps100 : 1; /* 100MBps operation (vs 10 MBps) */ + uint8_t fduplex : 1; /* Full (vs. half) duplex */ WDOG_ID txpoll; /* TX poll timer */ WDOG_ID txtimeout; /* TX timeout timer */ @@ -171,9 +255,18 @@ static int stm32_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac); static int stm32_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac); #endif -/* Initialization */ +/* PHY Initialization */ + +static int stm32_phyread(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t *value); +static int stm32_phywrite(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t value); +static int stm32_phyinit(FAR struct stm32_ethmac_s *priv); + +/* MAC/DMA Initialization */ static inline void stm32_ethgpioconfig(FAR struct stm32_ethmac_s *priv); +static void stm32_ethreset(FAR struct stm32_ethmac_s *priv); +static int stm32_macconfig(FAR struct stm32_ethmac_s *priv); +static int stm32_ethconfig(FAR struct stm32_ethmac_s *priv); /**************************************************************************** * Private Functions @@ -508,7 +601,7 @@ static int stm32_ifup(struct uip_driver_s *dev) /* Enable the Ethernet interrupt */ - priv->bifup = true; + priv->ifup = true; up_enable_irq(STM32_IRQ_ETH); return OK; } @@ -551,7 +644,7 @@ static int stm32_ifdown(struct uip_driver_s *dev) /* Mark the device "down" */ - priv->bifup = false; + priv->ifup = false; irqrestore(flags); return OK; } @@ -588,7 +681,7 @@ static int stm32_txavail(struct uip_driver_s *dev) /* Ignore the notification if the interface is not yet up */ - if (priv->bifup) + if (priv->ifup) { /* Check if there is room in the hardware to hold another outgoing packet. */ @@ -660,6 +753,267 @@ static int stm32_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac) #endif /**************************************************************************** + * Function: stm32_phyread + * + * Description: + * Read a PHY register. + * + * Parameters: + * phydevaddr - The PHY device address + * phyregaddr - The PHY register address + * value - The location to return the 16-bit PHY register value. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +static int stm32_phyread(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t *value) +{ + volatile uint32_t timeout; + uint32_t regval; + + /* Configure the MACMIIAR register, preserving CSR Clock Range CR[2:0] bits */ + + regval = getreg32(STM32_ETH_MACMIIAR); + regval &= ETH_MACMIIAR_CR_MASK; + + /* Set the PHY device address, PHY register address, and set the buy bit. + * the ETH_MACMIIAR_MW is clear, indicating a read operation. + */ + + regval |= (((uint32_t)phydevaddr << ETH_MACMIIAR_PA_SHIFT) & ETH_MACMIIAR_PA_MASK); + regval |= (((uint32_t)phyregaddr << ETH_MACMIIAR_MR_SHIFT) & ETH_MACMIIAR_MR_MASK); + regval |= ETH_MACMIIAR_MB; + + putreg32(regval, STM32_ETH_MACMIIAR); + + /* Wait for the transfer to complete */ + + for (timeout = 0; timeout < PHY_READ_TIMEOUT; timeout++) + { + if ((getreg32(STM32_ETH_MACMIIAR) && ETH_MACMIIAR_MB) == 0) + { + *value = (uint16_t)getreg32(STM32_ETH_MACMIIDR); + return OK; + } + } + + ndbg("MII transfer timed out: phydevaddr: %04x phyregaddr: %04x\n", + phydevaddr, phyregaddr); + + return -ETIMEDOUT; +} + +/**************************************************************************** + * Function: stm32_phywrite + * + * Description: + * Write to a PHY register. + * + * Parameters: + * phydevaddr - The PHY device address + * phyregaddr - The PHY register address + * value - The 16-bit value to write to the PHY register value. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +static int stm32_phywrite(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t value) +{ + volatile uint32_t timeout; + uint32_t regval; + + /* Configure the MACMIIAR register, preserving CSR Clock Range CR[2:0] bits */ + + regval = getreg32(STM32_ETH_MACMIIAR); + regval &= ETH_MACMIIAR_CR_MASK; + + /* Set the PHY device address, PHY register address, and set the busy bit. + * the ETH_MACMIIAR_MW is set, indicating a write operation. + */ + + regval |= (((uint32_t)phydevaddr << ETH_MACMIIAR_PA_SHIFT) & ETH_MACMIIAR_PA_MASK); + regval |= (((uint32_t)phyregaddr << ETH_MACMIIAR_MR_SHIFT) & ETH_MACMIIAR_MR_MASK); + regval |= (ETH_MACMIIAR_MB | ETH_MACMIIAR_MW); + + /* Write the value into the MACIIDR register before setting the new MACMIIAR + * register value. + */ + + putreg32(value, STM32_ETH_MACMIIDR); + putreg32(regval, STM32_ETH_MACMIIAR); + + /* Wait for the transfer to complete */ + + for (timeout = 0; timeout < PHY_WRITE_TIMEOUT; timeout++) + { + if ((getreg32(STM32_ETH_MACMIIAR) && ETH_MACMIIAR_MB) == 0) + { + return OK; + } + } + + ndbg("MII transfer timed out: phydevaddr: %04x phyregaddr: %04x value: %04x\n", + phydevaddr, phyregaddr, value); + + return -ETIMEDOUT; +} + +/**************************************************************************** + * Function: stm32_phyinit + * + * Description: + * Configure the PHY and determine the link speed/duplex. + * + * Parameters: + * priv - A reference to the private driver state structure + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +static int stm32_phyinit(FAR struct stm32_ethmac_s *priv) +{ + volatile uint32_t timeout; + uint32_t regval; + uint16_t phyval; + int ret; + + /* Assume 10MBps and half duplex */ + + priv->mbps100 = 0; + priv->fduplex = 0; + + /* Setup up PHY clocking by setting the SR field in the MACMIIAR register */ + + regval = getreg32(STM32_ETH_MACMIIAR); + regval &= ~ETH_MACMIIAR_CR_MASK; + regval |= ETH_MACMIIAR_CR; + putreg32(regval, STM32_ETH_MACMIIAR); + + /* Put the PHY in reset mode */ + + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_RESET); + if (ret < 0) + { + return ret; + } + up_mdelay(PHY_RESET_DELAY); + + /* Perform auto-negotion if so configured */ + +#ifdef CONFIG_STM32_AUTONEG + /* Wait for link status */ + + for (timeout = 0; timeout < PHY_READ_TIMEOUT; timeout++) + { + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval); + if (ret < 0) + { + return ret; + } + else if ((phyval & MII_MSR_LINKSTATUS) != 0) + { + break; + } + } + + if (timeout >= PHY_READ_TIMEOUT) + { + ndbg("Timed out waiting for link status\n"); + return -ETIMEDOUT; + } + + /* Enable auto-gegotiation */ + + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_ANENABLE); + if (ret < 0) + { + return ret; + } + + /* Wait until auto-negotiation completes */ + + for (timeout = 0; timeout < PHY_READ_TIMEOUT; timeout++) + { + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval); + if (ret < 0) + { + return ret; + } + else if ((phyval & MII_MSR_ANEGCOMPLETE) != 0) + { + break; + } + } + + if (timeout >= PHY_READ_TIMEOUT) + { + ndbg("Timed out waiting for auto-negotiation\n"); + return -ETIMEDOUT; + } + + /* Read the result of the auto-negotiation from the PHY-specific register */ + + ret = stm32_phyread(CONFIG_STM32_PHYADDR, CONFIG_STM32_PHYSR, &phyval); + if (ret < 0) + { + ndbg("Failed to read PHY status register\n"); + return ret; + } + + /* Remember the selected speed and duplex modes */ + + if ((phyval & CONFIG_STM32_PHYSR_MODE) == CONFIG_STM32_PHYSR_FULLDUPLEX) + { + priv->fduplex = 1; + } + + if ((phyval & CONFIG_STM32_PHYSR_SPEED) == CONFIG_STM32_PHYSR_100MBPS) + { + priv->mbps100 = 1; + } + +#else /* Auto-negotion not selected */ + + phyval = 0; +#ifdef CONFIG_STM32_ETHFD + phyval |= MII_MCR_FULLDPLX; +#endif +#ifdef CONFIG_STM32_ETH100MBPS + phyval |= MII_MCR_SPEED100; +#endif + + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, phyval); + if (ret < 0) + { + return ret; + } + up_mdelay(PHY_CONFIG_DELAY); + + /* Remember the selected speed and duplex modes */ + +#ifdef CONFIG_STM32_ETHFD + priv->fduplex = 1; +#endif +#ifdef CONFIG_STM32_ETH100MBPS + priv->mbps100 = 1; +#endif +#endif + return OK; +} + +/**************************************************************************** * Function: stm32_ethgpioconfig * * Description: @@ -669,13 +1023,12 @@ static int stm32_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac) * priv - A reference to the private driver state structure * * Returned Value: - * OK on success; Negated errno on failure. + * None. * * Assumptions: * ****************************************************************************/ -#if STM32_NETHERNET == 1 static inline void stm32_ethgpioconfig(FAR struct stm32_ethmac_s *priv) { /* Configure GPIO pins to support Ethernet */ @@ -704,24 +1057,21 @@ static inline void stm32_ethgpioconfig(FAR struct stm32_ethmac_s *priv) * PLLI2S clock (through a configurable prescaler) on PC9 pin." */ -# warning "REVISIT: This is very board-specific" # if defined(CONFIG_STM32_MII_MCO1) - /* Configure MC01 to drive the PHY */ + /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking + * info. + */ stm32_configgpio(GPIO_MCO1); - - /* Output HSE clock (25MHz) on MCO pin (PA8) to clock the PHY */ - - stm32_mco1config(RCC_CFGR_MCO1_HSE, RCC_CFGR_MCO1PRE_NONE); + stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); # elif defined(CONFIG_STM32_MII_MCO2) - /* Configure MC02 to drive the PHY */ + /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking + * info. + */ stm32_configgpio(GPIO_MCO2); - - /* Output HSE clock (25MHz) on MCO pin (PA8) to clock the PHY */ - - stm32_mco2config(RCC_CFGR_MCO2_HSE, RCC_CFGR_MCO2PRE_NONE); + stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); # endif /* MII interface pins (17): @@ -776,9 +1126,114 @@ static inline void stm32_ethgpioconfig(FAR struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_ETH_PPS_OUT); } -#else -# warning "This would need to be re-designed to support multiple interfaces" -#endif + +/**************************************************************************** + * Function: stm32_ethreset + * + * Description: + * Reset the Ethernet block. + * + * Parameters: + * priv - A reference to the private driver state structure + * + * Returned Value: + * None. + * + * Assumptions: + * + ****************************************************************************/ + +static void stm32_ethreset(FAR struct stm32_ethmac_s *priv) +{ + uint32_t regval; + + /* Reset the Ethernet on the AHB1 bus */ + + regval = getreg32(STM32_RCC_AHB1RSTR); + regval |= RCC_AHB1RSTR_ETHMACRST; + putreg32(regval, STM32_RCC_AHB1RSTR); + + regval &= ~RCC_AHB1RSTR_ETHMACRST; + putreg32(regval, STM32_RCC_AHB1RSTR); + + /* Perform a software reset by setting the SR bit in the DMABMR register. + * This Resets all MAC subsystem internal registers and logic. After this + * reset all the registers holds their reset values. + */ + + regval = getreg32(STM32_ETH_DMABMR); + regval |= ETH_DMABMR_SR; + putreg32(regval, STM32_ETH_DMABMR); + + /* Wait for software reset to complete. The SR bit is cleared automatically + * after the reset operation has completed in all of the core clock domains. + */ + + while ((getreg32(STM32_ETH_DMABMR) & ETH_DMABMR_SR) != 0); +} + +/**************************************************************************** + * Function: stm32_macconfig + * + * Description: + * Configure the Ethernet MAC for DMA operation. + * + * Parameters: + * priv - A reference to the private driver state structure + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +static int stm32_macconfig(FAR struct stm32_ethmac_s *priv) +{ +#warning "Missing logic" + return -ENOSYS; +} + +/**************************************************************************** + * Function: stm32_ethconfig + * + * Description: + * Configure the Ethernet interface for DMA operation. + * + * Parameters: + * priv - A reference to the private driver state structure + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +static int stm32_ethconfig(FAR struct stm32_ethmac_s *priv) +{ + int ret; + + /* NOTE: The Ethernet clocks were initialized early in the boot-up + * sequence in stm32_rcc.c. + */ + + /* Reset the Ethernet block */ + + stm32_ethreset(priv); + + /* Initialize the PHY */ + + ret = stm32_phyinit(priv); + if (ret < 0) + { + return ret; + } + + /* Initialize the MAC and DMA */ + + return stm32_macconfig(priv); +} /**************************************************************************** * Public Functions @@ -811,6 +1266,7 @@ static inline int stm32_ethinitialize(int intf) { struct stm32_ethmac_s *priv; + int ret; /* Get the interface structure associated with this interface number. */ @@ -838,7 +1294,13 @@ int stm32_ethinitialize(int intf) stm32_ethgpioconfig(priv); - /* Check if a Ethernet chip is recognized at its I/O base */ + /* Configure the Ethernet interface for DMA operation. */ + + ret = stm32_ethconfig(priv); + if (ret < 0) + { + return ret; + } /* Attach the IRQ to the driver */ @@ -849,11 +1311,12 @@ int stm32_ethinitialize(int intf) return -EAGAIN; } - /* Put the interface in the down state. This usually amounts to resetting - * the device and/or calling stm32_ifdown(). - */ + /* Put the interface in the down state. */ + + stm32_ifdown(&priv->dev); /* Read the MAC address from the hardware into priv->dev.d_mac.ether_addr_octet */ +#warning "Missing logic" /* Register the device with the OS so that socket IOCTLs can be performed */ diff --git a/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c b/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c index c1b6c66d3..91f362059 100644 --- a/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c +++ b/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c @@ -184,8 +184,14 @@ static inline void rcc_enableahb1(void) #ifdef CONFIG_STM32_ETHMAC /* Ethernet MAC clocking */ - regval |= (RCC_AHB1ENR_ETHMACEN|RCC_AHB1ENR_ETHMACTXEN| - RCC_AHB1ENR_ETHMACRXEN|RCC_AHB1ENR_ETHMACPTPEN); + regval |= (RCC_AHB1ENR_ETHMACEN|RCC_AHB1ENR_ETHMACTXEN|RCC_AHB1ENR_ETHMACRXEN); + +#ifdef CONFIG_STM32_ETH_PTP + /* Precision Time Protocol (PTP) */ + + regval |= RCC_AHB1ENR_ETHMACPTPEN; + +#endif #endif #ifdef CONFIG_STM32_OTGHS diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-head.S b/nuttx/arch/mips/src/pic32mx/pic32mx-head.S index 860004980..611738395 100644 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-head.S +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-head.S @@ -161,7 +161,9 @@ __reset: * Name: _gen_exception * * Description: - * General Exception Vector Handler. Jumps to _exception_handler + * General Exception Vector Handler. Jumps to _exception_handler. NOTE: + * we set the BEV bit in the status register so all interrupt vectors + * should go through the _bev_exception. * * Input Parameters: * None diff --git a/nuttx/configs/stm3240g-eval/README.txt b/nuttx/configs/stm3240g-eval/README.txt index 2cd5339e4..25ee3ce34 100755 --- a/nuttx/configs/stm3240g-eval/README.txt +++ b/nuttx/configs/stm3240g-eval/README.txt @@ -374,10 +374,29 @@ STM3240G-EVAL-specific Configuration Options CONFIG_SDIO_WIDTH_D1_ONLY - Select 1-bit transfer mode. Default: 4-bit transfer mode. + CONFIG_STM32_PHYADDR - The 5-bit address of the PHY on the board CONFIG_STM32_MII - Support Ethernet MII interface CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface CONFIG_STM32_RMII - Support Ethernet RMII interface + CONFIG_STM32_AUTONEG - Use PHY autonegotion to determine speed and mode + CONFIG_STM32_ETHFD - If CONFIG_STM32_AUTONEG is not defined, then this + may be defined to select full duplex mode. Default: half-duplex + CONFIG_STM32_ETH100MBPS - If CONFIG_STM32_AUTONEG is not defined, then this + may be defined to select 100 MBps speed. Default: 10 Mbps + CONFIG_STM32_PHYSR - This must be provided if CONFIG_STM32_AUTONEG is + defined. The PHY status register address may diff from PHY to PHY. This + configuration sets the address of the PHY status register. + CONFIG_STM32_PHYSR_SPEED - This must be provided if CONFIG_STM32_AUTONEG is + defined. This provides bit mask indicating 10 or 100MBps speed. + CONFIG_STM32_PHYSR_100MBPS - This must be provided if CONFIG_STM32_AUTONEG is + defined. This provides the value of the speed bit(s) indicating 100MBps speed. + CONFIG_STM32_PHYSR_MODE - This must be provided if CONFIG_STM32_AUTONEG is + defined. This provide bit mask indicating full or half duplex modes. + CONFIG_STM32_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32_AUTONEG is + defined. This provides the value of the mode bits indicating full duplex mode. + CONFIG_STM32_ETH_PTP - Precision Time Protocol (PTP). Not supported + but some hooks are indicated with this condition. STM3240G-EVAL LCD Hardware Configuration diff --git a/nuttx/configs/stm3240g-eval/include/board.h b/nuttx/configs/stm3240g-eval/include/board.h index 1a1c6738f..663ad7eda 100755 --- a/nuttx/configs/stm3240g-eval/include/board.h +++ b/nuttx/configs/stm3240g-eval/include/board.h @@ -172,8 +172,26 @@ # define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) #endif -/* LED definitions ******************************************************************/ +/* Ethernet *************************************************************************/ +/* We need to provide clocking to the MII PHY via MCO1 (PA8) */ + +#if defined(CONFIG_NET) && defined(CONFIG_STM32_ETHMAC) + +# if !defined(CONFIG_STM32_MII) +# warning "CONFIG_STM32_MII required for Ethernet" +# elif !defined(CONFIG_STM32_MII_MCO1) +# warning "CONFIG_STM32_MII_MCO1 required for Ethernet MII" +# else + + /* Output HSE clock (25MHz) on MCO1 pin (PA8) to clock the PHY */ + +# define BOARD_CFGR_MC01_SOURCE RCC_CFGR_MCO1_HSE +# define BOARD_CFGR_MC01_DIVIDER RCC_CFGR_MCO1PRE_NONE +# endif +#endif + +/* LED definitions ******************************************************************/ /* The STM3240G-EVAL board has 4 LEDs that we will encode as: */ #define LED_STARTED 0 /* LED1 */ @@ -185,6 +203,7 @@ #define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ #define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ +/* Button definitions ***************************************************************/ /* The STM3240G-EVAL supports three buttons: */ #define BUTTON_WAKEUP 0 @@ -200,6 +219,7 @@ /* Alternate function pin selections ************************************************/ /* UART3: + * * - PC11 is MicroSDCard_D3 & RS232/IrDA_RX (JP22 open) * - PC10 is MicroSDCard_D2 & RSS232/IrDA_TX */ diff --git a/nuttx/configs/stm3240g-eval/nsh/defconfig b/nuttx/configs/stm3240g-eval/nsh/defconfig index 490b32a7b..ce69e0295 100755 --- a/nuttx/configs/stm3240g-eval/nsh/defconfig +++ b/nuttx/configs/stm3240g-eval/nsh/defconfig @@ -258,15 +258,44 @@ CONFIG_SSI_POLLWAIT=y # # STM32F40xxx Ethernet device driver settings # +# CONFIG_STM32_PHYADDR - The 5-bit address of the PHY on the board # CONFIG_STM32_MII - Support Ethernet MII interface # CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface # CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface # CONFIG_STM32_RMII - Support Ethernet RMII interface -# +# CONFIG_STM32_AUTONEG - Use PHY autonegotion to determine speed and mode +# CONFIG_STM32_ETHFD - If CONFIG_STM32_AUTONEG is not defined, then this +# may be defined to select full duplex mode. Default: half-duplex +# CONFIG_STM32_ETH100MBPS - If CONFIG_STM32_AUTONEG is not defined, then this +# may be defined to select 100 MBps speed. Default: 10 Mbps +# CONFIG_STM32_PHYSR - This must be provided if CONFIG_STM32_AUTONEG is +# defined. The PHY status register address may diff from PHY to PHY. This +# configuration sets the address of the PHY status register. +# CONFIG_STM32_PHYSR_SPEED - This must be provided if CONFIG_STM32_AUTONEG is +# defined. This provides bit mask indicating 10 or 100MBps speed. +# CONFIG_STM32_PHYSR_100MBPS - This must be provided if CONFIG_STM32_AUTONEG is +# defined. This provides the value of the speed bit(s) indicating 100MBps speed. +# CONFIG_STM32_PHYSR_MODE - This must be provided if CONFIG_STM32_AUTONEG is +# defined. This provide bit mask indicating full or half duplex modes. +# CONFIG_STM32_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32_AUTONEG is +# defined. This provides the value of the mode bits indicating full duplex mode. +# CONFIG_STM32_ETH_PTP - Precision Time Protocol (PTP). Not supported +# but some hooks are indicated with this condition. +# +CONFIG_STM32_PHYADDR=0x01 CONFIG_STM32_MII=y CONFIG_STM32_MII_MCO1=y CONFIG_STM32_MII_MCO2=n CONFIG_STM32_RMII=n +CONFIG_STM32_AUTONEG=y +#CONFIG_STM32_ETHFD +#CONFIG_STM32_ETH100MB +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_ETH_PTP=n # # General build options @@ -684,7 +713,7 @@ CONFIG_NET=n CONFIG_NET_IPv6=n CONFIG_NSOCKET_DESCRIPTORS=10 CONFIG_NET_SOCKOPTS=y -CONFIG_NET_BUFSIZE=420 +CONFIG_NET_BUFSIZE=562 CONFIG_NET_TCP=y CONFIG_NET_TCP_CONNS=40 CONFIG_NET_MAX_LISTENPORTS=40 diff --git a/nuttx/configs/stm3240g-eval/ostest/defconfig b/nuttx/configs/stm3240g-eval/ostest/defconfig index cced8c8f2..cc91d8a53 100755 --- a/nuttx/configs/stm3240g-eval/ostest/defconfig +++ b/nuttx/configs/stm3240g-eval/ostest/defconfig @@ -258,15 +258,44 @@ CONFIG_SSI_POLLWAIT=y # # STM32F40xxx Ethernet device driver settings # +# CONFIG_STM32_PHYADDR - The 5-bit address of the PHY on the board # CONFIG_STM32_MII - Support Ethernet MII interface # CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface # CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface # CONFIG_STM32_RMII - Support Ethernet RMII interface -# +# CONFIG_STM32_AUTONEG - Use PHY autonegotion to determine speed and mode +# CONFIG_STM32_ETHFD - If CONFIG_STM32_AUTONEG is not defined, then this +# may be defined to select full duplex mode. Default: half-duplex +# CONFIG_STM32_ETH100MBPS - If CONFIG_STM32_AUTONEG is not defined, then this +# may be defined to select 100 MBps speed. Default: 10 Mbps +# CONFIG_STM32_PHYSR - This must be provided if CONFIG_STM32_AUTONEG is +# defined. The PHY status register address may diff from PHY to PHY. This +# configuration sets the address of the PHY status register. +# CONFIG_STM32_PHYSR_SPEED - This must be provided if CONFIG_STM32_AUTONEG is +# defined. This provides bit mask indicating 10 or 100MBps speed. +# CONFIG_STM32_PHYSR_100MBPS - This must be provided if CONFIG_STM32_AUTONEG is +# defined. This provides the value of the speed bit(s) indicating 100MBps speed. +# CONFIG_STM32_PHYSR_MODE - This must be provided if CONFIG_STM32_AUTONEG is +# defined. This provide bit mask indicating full or half duplex modes. +# CONFIG_STM32_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32_AUTONEG is +# defined. This provides the value of the mode bits indicating full duplex mode. +# CONFIG_STM32_ETH_PTP - Precision Time Protocol (PTP). Not supported +# but some hooks are indicated with this condition. +# +CONFIG_STM32_PHYADDR=0x01 CONFIG_STM32_MII=y CONFIG_STM32_MII_MCO1=y CONFIG_STM32_MII_MCO2=n CONFIG_STM32_RMII=n +CONFIG_STM32_AUTONEG=y +#CONFIG_STM32_ETHFD +#CONFIG_STM32_ETH100MBPS +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_ETH_PTP=n # # General build options @@ -648,7 +677,7 @@ CONFIG_NET=n CONFIG_NET_IPv6=n CONFIG_NSOCKET_DESCRIPTORS=0 CONFIG_NET_SOCKOPTS=y -CONFIG_NET_BUFSIZE=420 +CONFIG_NET_BUFSIZE=562 CONFIG_NET_TCP=n CONFIG_NET_TCP_CONNS=40 CONFIG_NET_MAX_LISTENPORTS=40 |