diff options
| -rw-r--r-- | nuttx/Documentation/NuttXNxFlat.html | 87 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/lpc43xx/chip/lpc43_rgu.h | 4 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/lpc43xx/chip/lpc43_scu.h | 421 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.h | 379 |
4 files changed, 858 insertions, 33 deletions
diff --git a/nuttx/Documentation/NuttXNxFlat.html b/nuttx/Documentation/NuttXNxFlat.html index 622953b21..3a5939787 100644 --- a/nuttx/Documentation/NuttXNxFlat.html +++ b/nuttx/Documentation/NuttXNxFlat.html @@ -10,7 +10,7 @@ <td> <h1><big><font color="#3c34ec"><i>NXFLAT</i></font></big></h1> <h2><font color="#dc143c">>>> Under Construction <<<</font></h2> - <p>Last Updated: May 8, 2011</p> + <p>Last Updated: June 29, 2012</p> </td> </tr> </table> @@ -193,43 +193,64 @@ <a name="limitations"><h2>1.3 Limitations</h2></a> <ul> - <li><b>ROMFS (or RAM maps) Only</b>. - The initial NXFLAT release will work only with wither (1) executable modules residing on a ROMFS - file system, or (2) executables provided on other file systems provided that <code>CONFIG_FS_RAMMAP</code> - is defined. - That is because the loader depends on the capability to <code>mmap()</code> the code segment. - See the <a href="NuttxUserGuide.html#mmapxip">NuttX User Guide</a> for further information. - NUTTX does not provide any general kind of file mapping capability. - In fact, <i>true </i>file mapping is only possible with RTOSs and MCUs that provide an MMU<sup>1</sup> - and only ROMFS supports that kind of XIP execution from FLASH. - It is possible to simulate file mapping by allocating memory and copy the file into memory. - NXFLAT would work that kind of file mapping to and that feature could easily be added to NuttX. + <li><b>ROMFS (or RAM mapping) Only</b> + <ul> + <p> + The current NXFLAT release will work only with either (1) NXFLAT executable modules residing on a ROMFS file system, or (2) executables residing on other file systems provided that <code>CONFIG_FS_RAMMAP</code> is defined. + This limitation is because the loader depends on the capability to <code>mmap()</code> the code segment. + See the <a href="NuttxUserGuide.html#mmapxip">NuttX User Guide</a> for further information. + </p> + <p> + NUTTX does not provide any general kind of file mapping capability. + In fact, <i>true</i> file mapping is only possible with MCUs that provide an MMU<sup>1</sup>. + Without an MMU, file system may support eXecution In Place (XIP) to mimic file mapping. + Only the ROMFS file system supports that kind of XIP execution need by NXFLAT. + </p> + <p> + It is also possible to <i>simulate</i> file mapping by allocating memory, copying the NXFLAT binary file into memory, and executing from the copy of the executable file in RAM. + That capability can be enabled with the <code>CONFIG_FS_RAMMAP</code> configuration option. + With that option enabled, NXFLAT will work that kind of file system but will require copying of all NXFLAT executables to RAM. + </p> + </ul> </li> - <li><b>GCC/ARM/Cortex-M3 Only</b> - At present, the NXFLAT toolchain is only available for ARM and Cortex-M3 (thumb2) targets. + <li><b>GCC/ARM/Cortex-M3/4 Only</b> + <ul> + <p> + At present, the NXFLAT toolchain is only available for ARM and Cortex-M3/4 (thumb2) targets. + </p> + </ul> </li> <li><b>Read-Only Data in RAM</b> - Read-only data must reside in RAM. - In code generated by GCC, all data references are indexed by the PIC<sup>2</sup> base register - (that is usually R10 or <i>sl</i> for the ARM processors). - The includes read-only data (<code>.rodata</code>). - Embedded firmware developers normally like to keep <code>.rodata</code> in FLASH with the code sections. - But because all data is referenced with the PIC base register, all of that data must lie in RAM. - A NXFLAT change to work around this is under investigation<sup>3</sup>. + <ul> + <p> + Read-only data must reside in RAM. + In code generated by GCC, all data references are indexed by the PIC<sup>2</sup> base register (that is usually R10 or <i>sl</i> for the ARM processors). + The includes read-only data (<code>.rodata</code>). + Embedded firmware developers normally like to keep <code>.rodata</code> in FLASH with the code sections. + But because all data is referenced with the PIC base register, all of that data must lie in RAM. + A NXFLAT change to work around this is under investigation<sup>3</sup>. + </p> + </ul> </li> <li><b>Globally Scoped Function Function Pointers</b> - If a function pointer is taken to a statically defined function, then (at least for ARM) GCC will - generate a relocation that NXFLAT cannot handle. - The workaround is make all such functions global in scope. - A fix would involve a change to the GCC compiler as described in <a href="#pictext">Appendix B</a>. + <ul> + <p> + If a function pointer is taken to a statically defined function, then (at least for ARM) GCC will generate a relocation that NXFLAT cannot handle. + The workaround is make all such functions global in scope. + A fix would involve a change to the GCC compiler as described in <a href="#pictext">Appendix B</a>. + </p> + </ul> </li> - <li><b>No Callbacks</b> - Callbacks through function pointers must be avoided or, when then cannot be avoided, handled very specially. - The reason for this is that the PIC module requires setting of a special value in a PIC register. - If the callback does not set the PIC register, then the called back function will fail because - it will be unable to correct access data memory. - Special logic is in place to handle: Signal callbacks, watchdog timer callbacks. - But other callbacks (like those used with <code>qsort()</code> must be avoided in an NXFLAT module. + <li><b>Special Handling of Callbacks</b> + <ul> + <p> + Callbacks through function pointers must be avoided or, when then cannot be avoided, handled very specially. + The reason for this is that the PIC module requires setting of a special value in a PIC register. + If the callback does not set the PIC register, then the called back function will fail because it will be unable to correctly access data memory. + Special logic is in place to handle some NuttX callbacks: Signal callbacks and watchdog timer callbacks. + But other callbacks (like those used with <code>qsort()</code> must be avoided in an NXFLAT module. + </p> + </ul> </li> </ul> @@ -240,7 +261,7 @@ At run time, the <code>.rodata</code> offsets will be indexed by a RAM address. If the dynamic loader were to offset those <code>.rodata</code> offsets properly, it still might be possible to reference <code>.rodata</code> in ROM. - That work around is still a top of investigation at this time.</small> + That work around is still a topic of investigation at this time.</small> </p></ul> <a name="supported"><h2>1.4 Supported Processors</h2></a> diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_rgu.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_rgu.h index 36c979f17..2c2f997ea 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_rgu.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_rgu.h @@ -164,6 +164,8 @@ #define LPC43_RGU_ACTIVE0 (LPC43_RGU_BASE+LPC43_RGU_ACTIVE0_OFFSET) #define LPC43_RGU_ACTIVE1 (LPC43_RGU_BASE+LPC43_RGU_ACTIVE1_OFFSET) +/* External Status Registers */ + #define LPC43_RGU_EXTSTAT(n) (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT_OFFSET(n)) #define LPC43_RGU_EXTSTAT0 (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT0_OFFSET) #define LPC43_RGU_EXTSTAT1 (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT1_OFFSET) @@ -211,6 +213,8 @@ #define LPC43_RGU_EXTSTAT57 (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT57_OFFSET) #define LPC43_RGU_EXTSTAT58 (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT58_OFFSET) +/* Alternative naming */ + #define LPC43_RGU_EXTSTAT_CORE_RST LPC43_RGU_EXTSTAT0 #define LPC43_RGU_EXTSTAT_PERIPH_RST LPC43_RGU_EXTSTAT1 #define LPC43_RGU_EXTSTAT_MASTER_RST LPC43_RGU_EXTSTAT2 diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_scu.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_scu.h new file mode 100644 index 000000000..59678c114 --- /dev/null +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_scu.h @@ -0,0 +1,421 @@ +/**************************************************************************************************** + * arch/arm/src/lpc43xx/chip/lpc43_scu.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SCU_SCU_H +#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SCU_SCU_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include <nuttx/config.h> + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ +/* Register Offsets *********************************************************************************/ + +/* Pin Groups */ + +#define SPSP0 0 +#define SPSP1 1 +#define SPSP2 2 +#define SPSP3 3 +#define SPSP4 4 +#define SPSP5 5 +#define SPSP6 6 +#define SPSP7 7 +#define SPSP8 8 +#define SPSP9 9 +#define SPSP10 10 +#define SPSP11 11 +#define SPSP12 12 +#define SPSP13 13 +#define SPSP14 14 +#define SPSP15 15 + +#define LPC43_SCU_SFSP_OFFSET(p,n) (((p) << 7) | ((n) << 2)) +#define LPC43_SCU_SFSP0_OFFSET(n) (0x0000 | ((n) << 2)) +#define LPC43_SCU_SFSP1_OFFSET(n) (0x0080 | ((n) << 2)) +#define LPC43_SCU_SFSP2_OFFSET(n) (0x0100 | ((n) << 2)) +#define LPC43_SCU_SFSP3_OFFSET(n) (0x0180 | ((n) << 2)) +#define LPC43_SCU_SFSP4_OFFSET(n) (0x0200 | ((n) << 2)) +#define LPC43_SCU_SFSP5_OFFSET(n) (0x0280 | ((n) << 2)) +#define LPC43_SCU_SFSP6_OFFSET(n) (0x0300 | ((n) << 2)) +#define LPC43_SCU_SFSP7_OFFSET(n) (0x0380 | ((n) << 2)) +#define LPC43_SCU_SFSP8_OFFSET(n) (0x0400 | ((n) << 2)) +#define LPC43_SCU_SFSP9_OFFSET(n) (0x0480 | ((n) << 2)) +#define LPC43_SCU_SFSPA_OFFSET(n) (0x0500 | ((n) << 2)) +#define LPC43_SCU_SFSPB_OFFSET(n) (0x0580 | ((n) << 2)) +#define LPC43_SCU_SFSPC_OFFSET(n) (0x0600 | ((n) << 2)) +#define LPC43_SCU_SFSPD_OFFSET(n) (0x0680 | ((n) << 2)) +#define LPC43_SCU_SFSPE_OFFSET(n) (0x0700 | ((n) << 2)) +#define LPC43_SCU_SFSPF_OFFSET(n) (0x0780 | ((n) << 2)) + +/* CLKn pins */ + +#define SFSCLK0 0 +#define SFSCLK1 1 +#define SFSCLK2 2 +#define SFSCLK3 3 + +#define LPC43_SCU_SFSCLK_OFFSET(n) (0x0c00 | ((n) << 2)) +#define LPC43_SCU_SFSCLK0_OFFSET 0x0c00 +#define LPC43_SCU_SFSCLK1_OFFSET 0x0c04 +#define LPC43_SCU_SFSCLK2_OFFSET 0x0c08 +#define LPC43_SCU_SFSCLK3_OFFSET 0x0c0c + +/* USB1 USB1_DP/USB1_DM pins and I2C-bus open-drain pins */ + +#define LPC43_SCU_SFSUSB_OFFSET 0x0c80 +#define LPC43_SCU_SFSI2C0_OFFSET 0x0c84 + +/* ADC pin select registers */ + +#define ENAIO0 0 +#define ENAIO1 1 +#define ENAIO2 2 + +#define LPC43_SCU_ENAIO_OFFSET(n) (0x0c88 | ((n) << 2)) +#define LPC43_SCU_ENAIO0_OFFSET 0x0c88 +#define LPC43_SCU_ENAIO1_OFFSET 0x0c8c +#define LPC43_SCU_ENAIO2_OFFSET 0x0c90 + +/* EMC delay register */ + +#define LPC43_SCU_EMCDELAYCLK_OFFSET 0x0d00 + +/* Pin interrupt select registers */ + +#define PINTSEL0 0 +#define PINTSEL1 1 + +#define LPC43_SCU_PINTSEL_OFFSET(n) (0x0e00 | ((n) << 2)) +#define LPC43_SCU_PINTSEL0_OFFSET 0x0e00 +#define LPC43_SCU_PINTSEL1_OFFSET 0x0e04 + +/* Register Addresses *******************************************************************************/ + +/* Pin Groups */ + +#define LPC43_SCU_SFSP(p,n) (LPC43_SCU_BASE+LPC43_SCU_SFSP_OFFSET(p,n)) +#define LPC43_SCU_SFSP0(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP0_OFFSET(n)) +#define LPC43_SCU_SFSP1(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP1_OFFSET(n)) +#define LPC43_SCU_SFSP2(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP2_OFFSET(n)) +#define LPC43_SCU_SFSP3(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP3_OFFSET(n)) +#define LPC43_SCU_SFSP4(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP4_OFFSET(n)) +#define LPC43_SCU_SFSP5(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP5_OFFSET(n)) +#define LPC43_SCU_SFSP6(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP6_OFFSET(n)) +#define LPC43_SCU_SFSP7(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP7_OFFSET(n)) +#define LPC43_SCU_SFSP8(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP8_OFFSET(n)) +#define LPC43_SCU_SFSP9(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP9_OFFSET(n)) +#define LPC43_SCU_SFSPA(n) (LPC43_SCU_BASE+LPC43_SCU_SFSPA_OFFSET(n)) +#define LPC43_SCU_SFSPB(n) (LPC43_SCU_BASE+LPC43_SCU_SFSPB_OFFSET(n)) +#define LPC43_SCU_SFSPC(n) (LPC43_SCU_BASE+LPC43_SCU_SFSPC_OFFSET(n)) +#define LPC43_SCU_SFSPD(n) (LPC43_SCU_BASE+LPC43_SCU_SFSPD_OFFSET(n)) +#define LPC43_SCU_SFSPE(n) (LPC43_SCU_BASE+LPC43_SCU_SFSPE_OFFSET(n)) +#define LPC43_SCU_SFSPF(n) (LPC43_SCU_BASE+LPC43_SCU_SFSPF_OFFSET(n)) + +/* CLKn pins */ + +#define LPC43_SCU_SFSCLK(n) (LPC43_SCU_BASE+LPC43_SCU_SFSCLK_OFFSET(n)) +#define LPC43_SCU_SFSCLK0 (LPC43_SCU_BASE+LPC43_SCU_SFSCLK0_OFFSET) +#define LPC43_SCU_SFSCLK1 (LPC43_SCU_BASE+LPC43_SCU_SFSCLK1_OFFSET) +#define LPC43_SCU_SFSCLK2 (LPC43_SCU_BASE+LPC43_SCU_SFSCLK2_OFFSET) +#define LPC43_SCU_SFSCLK3 (LPC43_SCU_BASE+LPC43_SCU_SFSCLK3_OFFSET) + +/* USB1 USB1_DP/USB1_DM pins and I2C-bus open-drain pins */ + +#define LPC43_SCU_SFSUSB (LPC43_SCU_BASE+LPC43_SCU_SFSUSB_OFFSET) +#define LPC43_SCU_SFSI2C0 (LPC43_SCU_BASE+LPC43_SCU_SFSI2C0_OFFSET) + +/* ADC pin select registers */ + +#define LPC43_SCU_ENAIO(n) (LPC43_SCU_BASE+LPC43_SCU_ENAIO_OFFSET(n)) +#define LPC43_SCU_ENAIO0 (LPC43_SCU_BASE+LPC43_SCU_ENAIO0_OFFSET) +#define LPC43_SCU_ENAIO1 (LPC43_SCU_BASE+LPC43_SCU_ENAIO1_OFFSET) +#define LPC43_SCU_ENAIO2 (LPC43_SCU_BASE+LPC43_SCU_ENAIO2_OFFSET) + +/* EMC delay register */ + +#define LPC43_SCU_EMCDELAYCLK (LPC43_SCU_BASE+LPC43_SCU_EMCDELAYCLK_OFFSET) + +/* Pin interrupt select registers */ + +#define LPC43_SCU_PINTSEL(n) (LPC43_SCU_BASE+LPC43_SCU_PINTSEL_OFFSET(n)) +#define LPC43_SCU_PINTSEL0 (LPC43_SCU_BASE+LPC43_SCU_PINTSEL0_OFFSET) +#define LPC43_SCU_PINTSEL1 (LPC43_SCU_BASE+LPC43_SCU_PINTSEL1_OFFSET) + +/* Register Bit Definitions *************************************************************************/ +/* Common Pin configuration register bit settings */ + +#define SCU_PIN_MODE_SHIFT (0) /* Bits 0-2: Select pin function */ +#define SCU_PIN_MODE_MASK (7 << SCU_PIN_MODE_SHIFT) +# define SCU_PIN_MODE_FUNC(n) ((n) << SCU_PIN_MODE_SHIFT) +# define SCU_PIN_MODE_FUNC0 (0 << SCU_PIN_MODE_SHIFT) /* Function 0 (default) */ +# define SCU_PIN_MODE_FUNC1 (1 << SCU_PIN_MODE_SHIFT) /* Function 1 */ +# define SCU_PIN_MODE_FUNC2 (2 << SCU_PIN_MODE_SHIFT) /* Function 2 */ +# define SCU_PIN_MODE_FUNC3 (3 << SCU_PIN_MODE_SHIFT) /* Function 3 */ +# define SCU_PIN_MODE_FUNC4 (4 << SCU_PIN_MODE_SHIFT) /* Function 4 */ +# define SCU_PIN_MODE_FUNC5 (5 << SCU_PIN_MODE_SHIFT) /* Function 5 */ +# define SCU_PIN_MODE_FUNC6 (6 << SCU_PIN_MODE_SHIFT) /* Function 6 */ +# define SCU_PIN_MODE_FUNC7 (7 << SCU_PIN_MODE_SHIFT) /* Function 7 */ +#define SCU_PIN_EPD (1 << 3) /* Bit 3: Enable pull-down resistor at pad */ +#define SCU_PIN_EPUN (1 << 4) /* Bit 4: Disable pull-up resistor at pad */ + /* Bit 5: Usage varies with pin type */ +#define SCU_PIN_EZI (1 << 6) /* Bit 6: Input buffer enable */ +#define SCU_PIN_ZIF (1 << 7) /* Bit 7: Input glitch filter */ + /* Bits 8-9: Usage varies with pin type */ + /* Bits 10-31: Reserved */ +/* Pin configuration registers for normal-drive pins (only): + * + * P0_0 and P0_1 + * P1_0 to P1_16 and P1_18 to P1_20 + * P2_0 to P2_2 and P2_6 to P2_13 + * P3_0 to P3_2 and P3_4 to P3_8 + * P4_0 to P4_10 + * P5_0 to P5_7 + * P6_0 to P6_12 + * P7_0 to P7_7 + * P8_3 to P8_8 + * P9_0 to P9_6 + * PA_0 and PA_4 + * PB_0 to PB_6 + * PC_0 to PC_14 + * PE_0 to PE_15 + * PF_0 to PF_11 + */ + /* Bits 0-4: Same as common bit definitions */ +#define SCU_NDPIN_EHS (1 << 5) /* Bit 5: EHS Select Slew rate. + /* Bits 6-31: Same as common bit definitions */ +/* Pin configuration registers for high-speed pins + * + * P1_17 + * P2_3 to P2_5 + * P8_0 to P8_2 + * PA_1 to PA_3 + */ + /* Bits 0-7: Same as common bit definitions */ +#define SCU_HDPIN_EHD_SHIFT (8) /* Bits 8-9: Select drive strength */ +#define SCU_HDPIN_EHD_MASK (3 << SCU_HDPIN_EHD_SHIFT) +# define SCU_HDPIN_EHD_NORMAL (0 << SCU_HDPIN_EHD_SHIFT) /* Normal-drive: 4 mA drive strength */ +# define SCU_HDPIN_EHD_MEDIUM (1 << SCU_HDPIN_EHD_SHIFT) /* Medium-drive: 8 mA drive strength */ +# define SCU_HDPIN_EHD_HIGH (2 << SCU_HDPIN_EHD_SHIFT) /* High-drive: 14 mA drive strength */ +# define SCU_HDPIN_EHD_ULTRA (3 << SCU_HDPIN_EHD_SHIFT) /* Ultra high-drive: 20 mA drive strength */ + /* Bits 10-31: Reserved */ +/* Pin configuration registers for high-speed pins + * + * P3_3 and pins CLK0 to CLK3 + */ + /* Bits 0-4: Same as common bit definitions */ +#define SCU_HSPIN_EHS (1 << 5) /* Bit 5: EHS Select Slew rate. + /* Bits 6-31: Same as common bit definitions */ +/* Pin configuration register for USB1 pins USB1_DP/USB1_DM */ + +#define SCU_SFSUSB_AIM (1 << 0) /* Bit 0: Differential data input AIP/AIM */ +#define SCU_SFSUSB_ESEA (1 << 1) /* Bit 1: Control signal for differential input or single input */ +#define SCU_SFSUSB_EPD (1 << 2) /* Bit 2: Enable pull-down connect */ + /* Bit 3: Reserved */ +#define SCU_SFSUSB_EPWR (1 << 4) /* Bit 4: Power mode */ +#define SCU_SFSUSB_VBUS (1 << 5) /* Bit 5: Enable the vbus_valid signal */ + /* Bits 6-31: Reserved */ +/* Pin configuration register for open-drain I2C-bus pins */ + +#define SCU_SFSI2C0_SCL_EFP (1 << 0) /* Bit 0: Select input glitch filter time constant for the SCL pin */ + /* Bit 1: Reserved */ +#define SCU_SFSI2C0_SCL_EHD (1 << 2) /* Bit 2: Select I2C mode for the SCL pin */ +#define SCU_SFSI2C0_SCL_EZI (1 << 3) /* Bit 3: Enable the input receiver for the SCL pin */ + /* Bits 4-6: Reserved */ +#define SCU_SFSI2C0_SCL_ZIF (1 << 7) /* Bit 7: Enable or disable input glitch filter for the SCL pin */ +#define SCU_SFSI2C0_SDA_EFP (1 << 8) /* Bit 8: Select input glitch filter time constant for the SDA pin */ + /* Bit 9: Reserved */ +#define SCU_SFSI2C0_SDA_EHD (1 << 10) /* Bit 10: Select I2C mode for the SDA pin */ +#define SCU_SFSI2C0_SDA_EZI (1 << 11) /* Bit 11: Enable the input receiver for the SDA pin */ + /* Bits 12-14: Reserved */ +#define SCU_SFSI2C0_SDA_ZIF (1 << 15) /* Bit 15: Enable or disable input glitch filter for the SDA pin */ + /* Bits 16-31: Reserved */ +/* ADC0 function select register. The following pins are controlled by the ENAIO0 register: + * + * Pin ADC function ENAIO0 register bit + * P4_3 ADC0_0 0 + * P4_1 ADC0_1 1 + * PF_8 ADC0_2 2 + * P7_5 ADC0_3 3 + * P7_4 ADC0_4 4 + * PF_10 ADC0_5 5 + * PB_6 ADC0_6 6 + */ + +#define SCU_ENAI00_ADC0(n) (1 << (n)) +#define SCU_ENAI00_ADC0_0 (1 << 0) /* Select ADC0_0 */ +#define SCU_ENAI00_ADC0_1 (1 << 1) /* Select ADC0_1 */ +#define SCU_ENAI00_ADC0_2 (1 << 2) /* Select ADC0_2 */ +#define SCU_ENAI00_ADC0_3 (1 << 3) /* Select ADC0_3 */ +#define SCU_ENAI00_ADC0_4 (1 << 4) /* Select ADC0_4 */ +#define SCU_ENAI00_ADC0_5 (1 << 5) /* Select ADC0_5 */ +#define SCU_ENAI00_ADC0_6 (1 << 6) /* Select ADC0_6 */ + +/* ADC1 function select register. The following pins are controlled by the ENAIO1 register: + * + * Pin ADC function ENAIO0 register bit + * PC_3 ADC1_0 0 + * PC_0 ADC1_1 1 + * PF_9 ADC1_2 2 + * PF_6 ADC1_3 3 + * PF_5 ADC1_4 4 + * PF_11 ADC1_5 5 + * P7_7 ADC1_6 6 + * PF_7 ADC1_7 7 + */ + +#define SCU_ENAI01_ADC1(n) (1 << (n)) +#define SCU_ENAI01_ADC1_0 (1 << 0) /* Select ADC1_0 */ +#define SCU_ENAI01_ADC1_1 (1 << 1) /* Select ADC1_1 */ +#define SCU_ENAI01_ADC1_2 (1 << 2) /* Select ADC1_2 */ +#define SCU_ENAI01_ADC1_3 (1 << 3) /* Select ADC1_3 */ +#define SCU_ENAI01_ADC1_4 (1 << 4) /* Select ADC1_4 */ +#define SCU_ENAI01_ADC1_5 (1 << 5) /* Select ADC1_5 */ +#define SCU_ENAI01_ADC1_6 (1 << 6) /* Select ADC1_6 */ +#define SCU_ENAI01_ADC1_7 (1 << 7) /* Select ADC1_7 */ + +/* Analog function select register. The following pins are controlled by the ENAIO2 register: + * + * Pin ADC function ENAIO0 register bit + * P4_4 DAC 0 + * PF_7 BG (band gap output) 4 + */ + +#define SCU_ENAI02_DAC (1 << 0) /* Select DAC */ +#define SCU_ENAI02_BG (1 << 4) /* Select band gap output */ + +/* EMC clock delay register. The value 0x1111 corresponds to about 0.5 ns of delay */ + +#define SCU_EMCDELAYCLK_SHIFT (0) /* Bits 0-15: EMC_CLKn SDRAM clock output delay */ +#define SCU_EMCDELAYCLK_MASK (0xffff << SCU_EMCDELAYCLK_SHIFT) +# define SCU_EMCDELAYCLK(n( ((n) << SCU_EMCDELAYCLK_SHIFT) /* 0=no delay, N*0x1111 = N*0.5 ns delay */ + /* Bits 16-31: Reserved */ +/* Pin interrupt select register 0 */ + +#define SCU_GPIO_PORT0 0 +#define SCU_GPIO_PORT1 1 +#define SCU_GPIO_PORT2 2 +#define SCU_GPIO_PORT3 3 +#define SCU_GPIO_PORT4 4 +#define SCU_GPIO_PORT5 5 +#define SCU_GPIO_PORT6 6 +#define SCU_GPIO_PORT7 7 + +#define SCU_GPIO_PIN0 0 +#define SCU_GPIO_PIN1 1 +#define SCU_GPIO_PIN2 2 +#define SCU_GPIO_PIN3 3 +#define SCU_GPIO_PIN4 4 +#define SCU_GPIO_PIN5 5 +#define SCU_GPIO_PIN6 6 +#define SCU_GPIO_PIN7 7 +#define SCU_GPIO_PIN8 8 +#define SCU_GPIO_PIN9 9 +#define SCU_GPIO_PIN10 10 +#define SCU_GPIO_PIN11 11 +#define SCU_GPIO_PIN12 12 +#define SCU_GPIO_PIN13 13 +#define SCU_GPIO_PIN14 14 +#define SCU_GPIO_PIN15 15 +#define SCU_GPIO_PIN16 16 +#define SCU_GPIO_PIN17 17 +#define SCU_GPIO_PIN18 18 +#define SCU_GPIO_PIN19 19 +#define SCU_GPIO_PIN20 20 +#define SCU_GPIO_PIN21 21 +#define SCU_GPIO_PIN22 22 +#define SCU_GPIO_PIN23 23 +#define SCU_GPIO_PIN24 24 +#define SCU_GPIO_PIN25 25 +#define SCU_GPIO_PIN26 26 +#define SCU_GPIO_PIN27 27 +#define SCU_GPIO_PIN28 28 +#define SCU_GPIO_PIN29 29 +#define SCU_GPIO_PIN30 30 +#define SCU_GPIO_PIN31 31 + +#define SCU_PINTSEL0_INTPIN0_SHIFT (0) /* Bits 0-4: Pint interrupt 0 */ +#define SCU_PINTSEL0_INTPIN0_MASK (31 << SCU_PINTSEL0_INTPIN0_SHIFT) +#define SCU_PINTSEL0_PORTSEL0_SHIFT (5) /* Bits 5-7: Pin interrupt 0 */ +#define SCU_PINTSEL0_PORTSEL0_MASK (7 << SCU_PINTSEL0_PORTSEL0_SHIFT) +#define SCU_PINTSEL0_INTPIN1_SHIFT (8) /* Bits 8-12: Pint interrupt 1 */ +#define SCU_PINTSEL0_INTPIN1_MASK (31 << SCU_PINTSEL0_INTPIN1_SHIFT) +#define SCU_PINTSEL0_PORTSEL1_SHIFT (13) /* Bits 13-15: Pin interrupt 1 */ +#define SCU_PINTSEL0_PORTSEL1_MASK (7 << SCU_PINTSEL0_PORTSEL1_SHIFT) +#define SCU_PINTSEL0_INTPIN2_SHIFT (16) /* Bits 16-20: Pint interrupt 2 */ +#define SCU_PINTSEL0_INTPIN2_MASK (31 << SCU_PINTSEL0_INTPIN2_SHIFT) +#define SCU_PINTSEL0_PORTSEL2_SHIFT (21) /* Bits 21-23: Pin interrupt 2 */ +#define SCU_PINTSEL0_PORTSEL2_MASK (7 << SCU_PINTSEL0_PORTSEL2_SHIFT) +#define SCU_PINTSEL0_INTPIN3_SHIFT (24) /* Bits 24-28: Pint interrupt 3 */ +#define SCU_PINTSEL0_INTPIN3_MASK (31 << SCU_PINTSEL0_INTPIN3_SHIFT) +#define SCU_PINTSEL0_PORTSEL3_SHIFT (29) /* Bits 29-31: Pin interrupt 3 */ +#define SCU_PINTSEL0_PORTSEL3_MASK (7 << SCU_PINTSEL0_PORTSEL3_SHIFT) + +/* Pin interrupt select register 1 */ + +#define SCU_PINTSEL1_INTPIN4_SHIFT (0) /* Bits 0-4: Pint interrupt 4 */ +#define SCU_PINTSEL1_INTPIN4_MASK (31 << SCU_PINTSEL1_INTPIN4_SHIFT) +#define SCU_PINTSEL1_PORTSEL4_SHIFT (5) /* Bits 5-7: Pin interrupt 4 */ +#define SCU_PINTSEL1_PORTSEL4_MASK (7 << SCU_PINTSEL1_PORTSEL4_SHIFT) +#define SCU_PINTSEL1_INTPIN5_SHIFT (8) /* Bits 8-12: Pint interrupt 5 */ +#define SCU_PINTSEL1_INTPIN5_MASK (31 << SCU_PINTSEL1_INTPIN5_SHIFT) +#define SCU_PINTSEL1_PORTSEL5_SHIFT (13) /* Bits 13-15: Pin interrupt 5 */ +#define SCU_PINTSEL1_PORTSEL5_MASK (7 << SCU_PINTSEL1_PORTSEL5_SHIFT) +#define SCU_PINTSEL1_INTPIN6_SHIFT (16) /* Bits 16-20: Pint interrupt 6 */ +#define SCU_PINTSEL1_INTPIN6_MASK (31 << SCU_PINTSEL1_INTPIN6_SHIFT) +#define SCU_PINTSEL1_PORTSEL6_SHIFT (21) /* Bits 21-23: Pin interrupt 6 */ +#define SCU_PINTSEL1_PORTSEL6_MASK (7 << SCU_PINTSEL1_PORTSEL6_SHIFT) +#define SCU_PINTSEL1_INTPIN7_SHIFT (24) /* Bits 24-28: Pint interrupt 7 */ +#define SCU_PINTSEL1_INTPIN7_MASK (31 << SCU_PINTSEL1_INTPIN7_SHIFT) +#define SCU_PINTSEL1_PORTSEL7_SHIFT (29) /* Bits 29-31: Pin interrupt 7 */ +#define SCU_PINTSEL1_PORTSEL7_MASK (7 << SCU_PINTSEL1_PORTSEL7_SHIFT) + +/**************************************************************************************************** + * Public Types + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Data + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Functions + ****************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SCU_SCU_H */ diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.h b/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.h new file mode 100644 index 000000000..838d27ddb --- /dev/null +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.h @@ -0,0 +1,379 @@ +/******************************************************************************************** + * arch/arm/src/lpc43xx/lpc43_pinconfig.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC43XX_PINCONFIG_H +#define __ARCH_ARM_SRC_LPC43XX_PINCONFIG_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include <nuttx/config.h> + +/* Include the chip capabilities and SCU definitions file */ + +#include "chip.h" +#include "chip/lpc43_scu.h" + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ +/* Each configurable pin can be individually configured by software in several modes. The + * following definitions provide the bit encoding that is used to define a pin configuration. + * Note that these pins do not corresponding GPIO ports and pins. + * + * 20-bit Encoding: 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * Normal Pins: AMM. UUDD IGWS SSSP PPPP + * Alternate Function Pins: AFFF UUDD IGWS SSSP PPPP + */ + +/* Alternate vs Normal encoding: + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * A... .... .... .... .... + */ + +#define PINCONF_ALTERNATE (1 << 19) /* Bit 19: 1=Alternate function */ +#define PINCONF_NORMAL (0) /* Bit 19: 0=Normal function */ + +#define PINCONF_IS_ALTERNATE(p) ((p) & PINCONF_ALTERNATE) != 0) +#define PINCONF_IS_NORMAL(p) ((p) & PINCONF_ALTERNATE) == 0) + +/* Alternate function number: + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * AFFF UUDD IGWS SSSP PPPP + * .FFF .... .... .... .... + */ + +#define PINCONF_FUNC_SHIFT (16) /* Bits 16-18: Alternate function number */ +#define PINCONF_FUNC_MASK (7 << PINCONF_MODE_SHIFT) + +/* Mode of a normal pin + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .MM. .... .... .... .... + */ + +#define _PINCONF_OUTPUT (1 << 18) /* Bit 18: 1=Output */ +#define _PINCONF_INPUT (0) /* Bit 18: 0=Input */ +#define _PINCONF_ANALOG (1 << 17) /* Bit 17: 1=Analog */ +#define _PINCONF_DIGITAL (0) /* Bit 17: 0=Digital */ + +#define PINCONF_MODE_SHIFT (17) /* Bits 17-18 = Mode of a normal pin*/ +#define PINCONF_MODE_MASK (3 << PINCONF_MODE_SHIFT) +# define PINCONF_MODE_INPUT (_PINCONF_INPUT | _PINCONF_DIGITAL) +# define PINCONF_MODE_OUTPUT (_PINCONF_OUTPUT | _PINCONF_DIGITAL) +# define PINCONF_MODE_ANALOGIN (_PINCONF_INPUT | _PINCONF_ANALOG) +# define PINCONF_MODE_ANALOGOUT (_PINCONF_OUTPUT | _PINCONF_ANALOG) + +#define PINCONF_IS_OUTPUT(p) ((p) & _PINCONF_OUTPUT) != 0) +#define PINCONF_IS_INPUT(p) ((p) & _PINCONF_OUTPUT) == 0) + +#define PINCONF_IS_ANALOG(p) ((p) & _PINCONF_ANALOG) != 0) +#define PINCONF_IS_DIGITAL(p) ((p) & _PINCONF_ANALOG) == 0) + +/* Pull-up/down resisters. These selections are available for all pins but may not + * make sense for all pins. NOTE: that both pull up and down is not precluded. + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... UU.. .... .... .... + */ + +#define PINCONF_PULLUP (1 << 15) /* Bit 15: 1=Pull-up */ +#define PINCONF_PULLDOWN (1 << 14) /* Bit 14: 1=Pull-down */ +#define PINCONF_FLOAT (0) /* Bit 14-15=0 if neither */ + +#define PINCONF_IS_PULLUP(p) ((p) & PINCONF_PULLUP) != 0) +#define PINCONF_IS_PULLDOWN(p) ((p) & PINCONF_PULLDOWN) != 0) +#define PINCONF_IS_FLOAT(p) ((p) & (PINCONF_PULLUP|PINCONF_PULLDOWN) == 0) + +/* Drive strength. These selections are available only for high-drive pins + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... ..DD .... .... .... + */ + +#define PINCONF_DRIVE_SHIFT (12) /* Bits 12-13 = Pin drive strength */ +#define PINCONF_DRIVE_MASK (3 << PINCONF_MODE_SHIFT) +# define PINCONF_DRIVE_NORMAL (0 << PINCONF_MODE_SHIFT) +# define PINCONF_DRIVE_MEDIUM (1 << PINCONF_MODE_SHIFT) +# define PINCONF_DRIVE_HIGH (2 << PINCONF_MODE_SHIFT) +# define PINCONF_DRIVE_ULTRA (3 << PINCONF_MODE_SHIFT) + +/* Input buffer enable + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... .... I... .... .... + */ + +#define PINCONF_INBUFFER (1 << 11) /* Bit 11: 1=Enabled input buffer */ +#define PINCONF_INBUFFER_ENABLED(p) ((p) & PINCONF_INBUFFER) != 0) + +/* Glitch filter enable + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... .... .G.. .... .... + */ + +#define PINCONF_GLITCH (1 << 10) /* Bit 10: 1=Glitch filter enable */ +#define PINCONF_GLITCH_ENABLE(p) ((p) & PINCONF_GLITCH) == 0) + +/* Slew rate + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... .... ..W. .... .... + */ + +#define PINCONF_SLEW_FAST (1 << 9) /* Bit 9: 1=Alternate function */ +#define PINCONF_SLEW_SLOW (0) /* Bit 9: 0=Normal function */ + +#define PINCONF_IS_SLEW_FAST(p) ((p) & PINCONF_SLEW_FAST) != 0) +#define PINCONF_IS_SLOW_SLOW(p) ((p) & PINCONF_SLEW_FAST) == 0) + +/* Pin configuration sets: + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... .... ...S SSS. .... + */ + +#define PINCONF_PINS_SHIFT (5) /* Bits 5-8: Pin set */ +#define PINCONF_PINS_MASK (15 << PINCONF_PINS_SHIFT) +# define PINCONF_PINS0 (0 << PINCONF_PINS_SHIFT) +# define PINCONF_PINS1 (1 << PINCONF_PINS_SHIFT) +# define PINCONF_PINS2 (2 << PINCONF_PINS_SHIFT) +# define PINCONF_PINS3 (3 << PINCONF_PINS_SHIFT) +# define PINCONF_PINS4 (4 << PINCONF_PINS_SHIFT) +# define PINCONF_PINS5 (5 << PINCONF_PINS_SHIFT) +# define PINCONF_PINS6 (6 << PINCONF_PINS_SHIFT) +# define PINCONF_PINS7 (7 << PINCONF_PINS_SHIFT) +# define PINCONF_PINS8 (8 << PINCONF_PINS_SHIFT) +# define PINCONF_PINS9 (9 << PINCONF_PINS_SHIFT) +# define PINCONF_PINSA (10 << PINCONF_PINS_SHIFT) +# define PINCONF_PINSB (11 << PINCONF_PINS_SHIFT) +# define PINCONF_PINSC (12 << PINCONF_PINS_SHIFT) +# define PINCONF_PINSD (13 << PINCONF_PINS_SHIFT) +# define PINCONF_PINSE (14 << PINCONF_PINS_SHIFT) +# define PINCONF_PINSF (15 << PINCONF_PINS_SHIFT) + +/* Pin numbers: + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... .... .... ...P PPPP + */ + +#define PINCONF_PIN_SHIFT (0) /* Bits 0-4: Pin number */ +#define PINCONF_PIN_MASK (31 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_0 (0 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_1 (1 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_2 (2 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_3 (3 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_4 (4 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_5 (5 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_6 (6 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_7 (7 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_8 (8 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_9 (9 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_10 (10 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_11 (11 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_12 (12 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_13 (13 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_14 (14 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_15 (15 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_16 (16 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_17 (17 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_18 (18 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_19 (19 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_20 (20 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_21 (21 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_22 (22 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_23 (23 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_24 (24 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_25 (25 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_26 (26 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_27 (27 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_28 (28 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_29 (29 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_30 (30 << PINCONF_PIN_SHIFT) +# define PINCONF_PIN_31 (31 << PINCONF_PIN_SHIFT) + +/* GPIO input pins may also be configurated as interrupting inputs. */ + +#define NUM_GPIO_PORTS 8 +#define NUM_GPIO_PINS 8 + +#define GPIO_PORT_SHIFT (4) /* Bits 4-6: Pin set */ +#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT) +# define GPIO_PORT0 (0 << GPIO_PORT_SHIFT) +# define GPIO_PORT1 (1 << GPIO_PORT_SHIFT) +# define GPIO_PORT2 (2 << GPIO_PORT_SHIFT) +# define GPIO_PORT3 (3 << GPIO_PORT_SHIFT) +# define GPIO_PORT4 (4 << GPIO_PORT_SHIFT) +# define GPIO_PORT5 (5 << GPIO_PORT_SHIFT) +# define GPIO_PORT6 (6 << GPIO_PORT_SHIFT) +# define GPIO_PORT7 (7 << GPIO_PORT_SHIFT) + +#define GPIO_PIN_SHIFT (0) /* Bits 0-2: Pin number */ +#define GPIO_PIN_MASK (7 << GPIO_PIN_SHIFT) +# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) +# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) +# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) +# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) +# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) +# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) +# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) +# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +/******************************************************************************************** + * Public Data + ********************************************************************************************/ + +/* Base addresses for each GPIO block */ + +extern const uint32_t g_gpiobase[NUM_GPIO_PORTS]; + +/******************************************************************************************** + * Public Functions + ********************************************************************************************/ + +/******************************************************************************************** + * Name: lpc43_pinconfig + * + * Description: + * Configure a pin based on bit-encoded description of the pin. + * + * Returned Value: + * OK on success; A negated errno value on failure. + * + ************************************************************************************/ + +EXTERN int lpc43_pinconfig(uint32_t pinset); + +/************************************************************************************ + * Name: lpc43_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + * Returned Value: + * None + * + ************************************************************************************/ + +EXTERN void lpc43_gpiowrite(uint8_t gpioset, bool value); + +/************************************************************************************ + * Name: lpc43_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + * Returned Value: + * The boolean state of the input pin + * + ************************************************************************************/ + +EXTERN bool lpc43_gpioread(uint8_t gpioset); + +/************************************************************************************ + * Name: lpc43_gpiointerrupt + * + * Description: + * Configure to receive GPIO interrupts on the select GPIO pin, reveiving the + * interrupt with the sectioned interrupt handler. The GPIO interrupt may be + * disabled by providing a NULL value for the interrupt handler function pointer. + * + * Parameters: + * - gpioset: GPIO pin identification + * - rising: Enable interrupt generation on the rising edge + * - falling: Enable interrupt generation on the falling edge + * - func: Interrupt handler + * + * Returns: + * The previous value of the interrupt handler function pointer. This value may, + * for example, be used to restore the previous handler when multiple handlers are + * used. + * + ************************************************************************************/ + +EXTERN xcpt_t lpc43_gpiointerrupt(uint8_t gpioset, bool risingedge, bool fallingedge, + xcpt_t func); + +/************************************************************************************ + * Function: lpc43_dumppinconfig + * + * Description: + * Dump all pin configuration registers associated with the provided base address + * + ************************************************************************************/ + +#ifdef CONFIG_DEBUG +EXTERN int lpc43_dumppinconfig(uint32_t pinset, const char *msg); +#else +# define lpc43_dumppinconfig(p,m) +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ARCH_ARM_SRC_LPC43XX_PINCONFIG_H */ |