diff options
-rwxr-xr-x | nuttx/arch/avr/src/at91uc3/Make.defs | 3 | ||||
-rw-r--r-- | nuttx/arch/avr/src/at91uc3/at91uc3_clkinit.c | 89 | ||||
-rwxr-xr-x | nuttx/arch/avr/src/at91uc3/at91uc3_pm.h | 7 | ||||
-rw-r--r-- | nuttx/arch/avr/src/at91uc3/at91uc3_serial.c | 4 | ||||
-rw-r--r-- | nuttx/arch/avr/src/at91uc3/at91uc3_timerisr.c | 190 | ||||
-rw-r--r-- | nuttx/arch/avr/src/avr32/up_nommuhead.S | 8 | ||||
-rwxr-xr-x | nuttx/arch/avr/src/avr32/up_switchcontext.S | 123 | ||||
-rwxr-xr-x | nuttx/configs/avr32dev1/include/board.h | 17 | ||||
-rw-r--r-- | nuttx/include/time.h | 2 |
9 files changed, 417 insertions, 26 deletions
diff --git a/nuttx/arch/avr/src/at91uc3/Make.defs b/nuttx/arch/avr/src/at91uc3/Make.defs index 4318ccf38..30600515a 100755 --- a/nuttx/arch/avr/src/at91uc3/Make.defs +++ b/nuttx/arch/avr/src/at91uc3/Make.defs @@ -52,7 +52,8 @@ CMN_CSRCS = up_assert.c up_allocateheap.c up_blocktask.c up_copystate.c \ CHIP_ASRCS = CHIP_CSRCS = at91uc3_clkinit.c at91uc3_gpio.c at91uc3_irq.c \ - at91uc3_lowconsole.c at91uc3_lowinit.c at91uc3_serial.c + at91uc3_lowconsole.c at91uc3_lowinit.c at91uc3_serial.c \ + at91uc3_timerisr.c # Configuration-dependent AT91UC3 files diff --git a/nuttx/arch/avr/src/at91uc3/at91uc3_clkinit.c b/nuttx/arch/avr/src/at91uc3/at91uc3_clkinit.c index 34cf9112f..5fa707600 100644 --- a/nuttx/arch/avr/src/at91uc3/at91uc3_clkinit.c +++ b/nuttx/arch/avr/src/at91uc3/at91uc3_clkinit.c @@ -73,18 +73,43 @@ **************************************************************************/ /************************************************************************** - * Public Functions + * Name: up_enableosc32 + * + * Description: + * Initialiaze the 32KHz oscillaor. This oscillaor is used by the RTC + * logic to provide the sysem timer. + * **************************************************************************/ -/************************************************************************************ - * Name: up_clkinit +static inline void up_enableosc32(void) +{ + uint32_t regval; + + /* Select the 32KHz oscillator crystal */ + + regval = getreg32(AVR32_PM_OSCCTRL32); + regval &= ~PM_OSCCTRL32_MODE_MASK; + regval |= PM_OSCCTRL32_MODE_XTAL; + putreg32(regval, AVR32_PM_OSCCTRL32); + + /* Enable the 32-kHz clock */ + + regval = getreg32(AVR32_PM_OSCCTRL32); + regval &= ~PM_OSCCTRL_STARTUP_MASK; + regval |= PM_OSCCTRL32_EN|(AVR32_OSC32STARTUP << PM_OSCCTRL_STARTUP_SHIFT); + putreg32(regval, AVR32_PM_OSCCTRL32); +} + +/************************************************************************** + * Name: up_enableosc0 * * Description: - * Initialiaze clock/PLL settings per the definitions in the board.h file. + * Initialiaze clock/PLL settings per the definitions in the board.h + * file. * - ************************************************************************************/ + **************************************************************************/ -void up_clkinitialize(void) +static inline void up_enableosc0(void) { uint32_t regval; @@ -121,16 +146,60 @@ void up_clkinitialize(void) /* Wait for CLK0 to be ready */ while ((getreg32(AVR32_PM_POSCSR) & PM_POSCSR_OSC0RDY) == 0); +} - /* Then switch the main clock to OSC0 */ +/************************************************************************** + * Name: up_mainclk + * + * Description: + * Initialiaze clock/PLL settings per the definitions in the board.h + * file. + * + **************************************************************************/ +static inline void up_mainclk(uint32_t mcsel) +{ + uint32_t regval; + regval = getreg32(AVR32_PM_MCCTRL); regval &= ~PM_MCCTRL_MCSEL_MASK; - regval |= PM_MCCTRL_MCSEL_OSC0; + regval |= mcsel; putreg32(regval, AVR32_PM_MCCTRL); +} + +/************************************************************************** + * Public Functions + **************************************************************************/ - /* Now, enable PLL0 */ -#warning "Missing Logic" +/************************************************************************** + * Name: up_clkinit + * + * Description: + * Initialiaze clock/PLL settings per the definitions in the board.h + * file. + * + **************************************************************************/ + +void up_clkinitialize(void) +{ + /* Enable the 32KHz oscillator (need by the RTC module) */ + + up_enableosc32(); + +#if defined(AVR32_CLOCK_OSC0) + /* Enable OSC0 using the settings in board.h */ + + up_enableosc0(); + + /* Then switch the main clock to OSC0 */ + + up_mainclk(PM_MCCTRL_MCSEL_OSC0); + +#elif defined(AVR32_CLOCK_PLL0) +# warning "Missing Logic" +#else +# error "No main clock" +#endif } diff --git a/nuttx/arch/avr/src/at91uc3/at91uc3_pm.h b/nuttx/arch/avr/src/at91uc3/at91uc3_pm.h index 27f7d0b03..162c3b055 100755 --- a/nuttx/arch/avr/src/at91uc3/at91uc3_pm.h +++ b/nuttx/arch/avr/src/at91uc3/at91uc3_pm.h @@ -149,9 +149,9 @@ # define PM_PLL_PLLOPT_WBWDIS (4 << PM_PLL_PLLOPT_SHIFT) /* Disable the Wide-Bandwidth mode */ #define PM_PLL_PLLDIV_SHIFT (8) /* Bits 8-11: PLL Division Factor */ #define PM_PLL_PLLDIV_MASK (15 << PM_PLL_PLLDIV_SHIFT) -#define PM_PLL_PLLMUL_SHIFT (16) /* Bits 16-19: PLL Multiply Factor */ +#define PM_PLL_PLLMUL_SHIFT (16) /* Bits 16-19: PLL Multiply Factor */ #define PM_PLL_PLLMUL_MASK (15 << PM_PLL_PLLMUL_SHIFT) -#define PM_PLL_PLLCOUNT_SHIFT (24) /* Bits 24-29: PLL Count */ +#define PM_PLL_PLLCOUNT_SHIFT (24) /* Bits 24-29: PLL Count */ #define PM_PLL_PLLCOUNT_MASK (0x3f << PM_PLL_PLLCOUNT_SHIFT) /* Oscillator 0/1 Control Register Bit-field Definitions */ @@ -179,7 +179,7 @@ #define PM_OSCCTRL32_MODE_SHIFT (8) /* Bits 8-10: Oscillator Mode */ #define PM_OSCCTRL32_MODE_MASK (7 << PM_OSCCTRL32_MODE_SHIFT) # define PM_OSCCTRL32_MODE_EXT (0 << PM_OSCCTRL32_MODE_SHIFT) /* External clock */ -# define PM_OSCCTRL32_MODE_XTALp9 (1 << PM_OSCCTRL32_MODE_SHIFT) /* Crystal */ +# define PM_OSCCTRL32_MODE_XTAL (1 << PM_OSCCTRL32_MODE_SHIFT) /* Crystal */ #define PM_OSCCTRL32_STARTUPSHIFT (16) /* Bits 16-18: Oscillator Startup Time */ #define PM_OSCCTRL32_STARTUP_MASK (7 << PM_OSCCTRL32_STARTUP_SHIFT) # define PM_OSCCTRL32_STARTUP_0 (0 << PM_OSCCTRL32_STARTUP_SHIFT) /* Num RCOsc cycles */ @@ -196,7 +196,6 @@ /* Interrupt Status Register Bit-field Definitions */ /* Interrupt Clear Register Bit-field Definitions */ - #define PM_INT_LOCK0 (1 << 0) /* Bit 0: PLL0 locked */ #define PM_INT_LOCK1 (1 << 1) /* Bit 1: PLL1 locked */ #define PM_INT_CKRDY (1 << 5) /* Bit 5: Clock Ready */ diff --git a/nuttx/arch/avr/src/at91uc3/at91uc3_serial.c b/nuttx/arch/avr/src/at91uc3/at91uc3_serial.c index e6f7fbb8d..80b9a8658 100644 --- a/nuttx/arch/avr/src/at91uc3/at91uc3_serial.c +++ b/nuttx/arch/avr/src/at91uc3/at91uc3_serial.c @@ -733,7 +733,9 @@ static bool up_txready(struct uart_dev_s *dev) * Description: * Performs the low level USART initialization early in debug so that the * serial console will be available during bootup. This must be called - * before up_serialinit. + * before up_serialinit. NOTE: This function depends on GPIO pin + * configuration performed in up_consoleinit() and main clock iniialization + * performed in up_clkinitialize(). * ****************************************************************************/ diff --git a/nuttx/arch/avr/src/at91uc3/at91uc3_timerisr.c b/nuttx/arch/avr/src/at91uc3/at91uc3_timerisr.c new file mode 100644 index 000000000..e38648952 --- /dev/null +++ b/nuttx/arch/avr/src/at91uc3/at91uc3_timerisr.c @@ -0,0 +1,190 @@ +/**************************************************************************** + * arch/avr/src/at91uc3/at91uc3_timerisr.c + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <debug.h> +#include <nuttx/arch.h> +#include <arch/board/board.h> + +#include "up_arch.h" + +#include "chip.h" +#include "at91uc3_internal.h" +#include "at91uc3_rtc.h" + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/* The desired timer interrupt frequency is normally provided by the + * definition CLK_TCK (see include/time.h). CLK_TCK defines the desired + * number of system clock ticks per second. That value is a user configurable + * setting that defaults to 100 (100 ticks per second = 10 MS interval). + * + * However, the AVR RTC does not support that default value well and so, we + * will insist that default is over-ridden by CONFIG_TICKS_PER_MSEC in the + * configuration file. Further, we will insist that CONFIG_TICKS_PER_MSEC + * have the value 8 (see reasoning below). + */ + +#if defined(CONFIG_MSEC_PER_TICK) && CONFIG_MSEC_PER_TICK != 10 +# error "Only a 100KHz system clock is supported" +#endif + +/* The frequency of the RTC is given by: + * + * fRTC = fINPUT / 2**(PSEL + 1) + * + * Using the 32KHz clock, various RTC counting can be obtained: + * + * fRTC = 32000 / 2**16 = 32000/65536 = 0.49Hz -> 2048 ms per tick + * fRTC = 32000 / 2**15 = 32000/32768 = 0.98Hz -> 1024 ms per tick + * fRTC = 32000 / 2**14 = 32000/16384 = 1.95Hz -> 512 ms per tick + * fRTC = 32000 / 2**13 = 32000/8192 = 3.9Hz -> 256 ms per tick + * fRTC = 32000 / 2**12 = 32000/4096 = 7.8Hz -> 128 ms per tick + * fRTC = 32000 / 2**11 = 32000/2048 = 15.6Hz -> 64 ms per tick + * fRTC = 32000 / 2**10 = 32000/1024 = 31.3Hz -> 32 ms per tick + * fRTC = 32000 / 2**9 = 32000/512 = 62.5Hz -> 16 ms per tick + * fRTC = 32000 / 2**8 = 32000/256 = 125Hz -> 8 ms per tick + * fRTC = 32000 / 2**7 = 32000/128 = 250Hz -> 4 ms per tick + * fRTC = 32000 / 2**6 = 32000/64 = 500Hz -> 2 ms per tick + * fRTC = 32000 / 2**5 = 32000/32 = 1KHz -> 1 ms per tick + * fRTC = 32000 / 2**4 = 32000/16 = 2KHz -> 500 us per tick + * fRTC = 32000 / 2**3 = 32000/8 = 4KHz -> 250 us per tick + * fRTC = 32000 / 2**2 = 32000/4 = 8KHz -> 125 us per tick + * fRTC = 32000 / 2 = 16KHz -> 62.5 us per tick + * + * We'll use PSEL == 1 (fRTC == 125ns) and we will set TOP to 79. + * Therefore, the TOP interrupt should occur after 79+1=80 counts + * at a rate of 125us x 80 = 10 ms + */ + +#define AV32_PSEL 15 +#define AV32_TOP (80-1) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: rtc_busy + * + * Description: + * Make sure that the RTC is no busy before trying to operate on it. If + * the RTC is busy, it will discard writes to TOP, VAL, and CTRL. + * + ****************************************************************************/ + +static void rtc_waitnotbusy(void) +{ + while ((getreg32(AVR32_RTC_CTRL) & RTC_CTRL_BUSY) == 0); +} + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: up_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + ****************************************************************************/ + +int up_timerisr(int irq, uint32_t *regs) +{ + /* Clear the pending timer interrupt */ + + putreg32(RTC_INT_TOPI, AVR32_RTC_ICR); + + /* Process timer interrupt */ + + sched_process_timer(); + return 0; +} + +/**************************************************************************** + * Function: up_timerinit + * + * Description: + * This function is called during start-up to initialize the timer + * interrupt. NOTE: This function depends on setup of OSC32 by + * up_clkinitialize(). + * + ****************************************************************************/ + +void up_timerinit(void) +{ + uint32_t regval; + + /* Configure the RTC. Source == 32KHz OSC32 */ + + rtc_waitnotbusy(); + putreg32((RTC_CTRL_CLK32 | (AV32_PSEL << RTC_CTRL_PSEL_SHIFT) | RTC_CTRL_CLKEN), + AVR32_RTC_CTRL); + + /* Set the counter value to zero and the TOP value to AVR32_TOP (see above) */ + + rtc_waitnotbusy(); + putreg32(0, AVR32_RTC_VAL); + putreg32(AV32_TOP, AVR32_RTC_TOP); + + /* Attach the timer interrupt vector */ + + (void)irq_attach(AVR32_IRQ_RTC, (xcpt_t)up_timerisr); + + /* Enable RTC interrupts */ + + putreg32(RTC_INT_TOPI, AVR32_RTC_IER); + + /* Enable the RTC */ + + rtc_waitnotbusy(); + regval = getreg32(AVR32_RTC_CTRL); + regval |= RTC_CTRL_EN; + putreg32(regval, AVR32_RTC_CTRL); +} diff --git a/nuttx/arch/avr/src/avr32/up_nommuhead.S b/nuttx/arch/avr/src/avr32/up_nommuhead.S index 7a4f2ae49..9ac92e217 100644 --- a/nuttx/arch/avr/src/avr32/up_nommuhead.S +++ b/nuttx/arch/avr/src/avr32/up_nommuhead.S @@ -57,7 +57,7 @@ #endif .global up_lowinit /* Perform low level initialization */ .global os_start /* NuttX entry point */ - .global vectors /* Vector base address */ + .global vectortab /* Vector base address */ /**************************************************************************** * Macros @@ -85,7 +85,7 @@ __start: /* Set up the vector base address so interrupts can be enabled. */ - lda.w r0, vectors + lda.w r0, .Lvectortab mtsr AVR32_EVBA, r0 /* Enable exception processing */ @@ -137,7 +137,9 @@ __start: rjmp os_start .Lstackbase: - .long _ebss+CONFIG_IDLETHREAD_STACKSIZE-4 + .word _ebss+CONFIG_IDLETHREAD_STACKSIZE-4 +.Lvectortab: + .word vectortab .size __start, .-__start /* This global variable is unsigned long g_heapbase and is diff --git a/nuttx/arch/avr/src/avr32/up_switchcontext.S b/nuttx/arch/avr/src/avr32/up_switchcontext.S new file mode 100755 index 000000000..8ecfbe2cd --- /dev/null +++ b/nuttx/arch/avr/src/avr32/up_switchcontext.S @@ -0,0 +1,123 @@ +/************************************************************************************ + * arch/avr/src/avr32/up_switchcontext.S + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> +#include <arch/irq.h> +#include <arch/avr32/avr32.h> + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Global Symbols + ************************************************************************************/ + + .file "up_switchcontext.S" + +/************************************************************************************ + * Macros + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: up_switchcontext + * + * Description: + * Save the current thread context and restore the specified context. The full + * C function prototype is: + * + * void up_switchcontext(uint32_t *saveregs, uint32_t *restoreregs); + * + * Return: + * up_switchcontext forces a context switch to the task "canned" in restoreregs. + * It does not 'return' in the normal sense, rather, it will context switch back + * to the function point. When it does 'return,' it is because the blocked + * task hat was "pickeled" in the saveregs "can" is again ready to run and has + * execution priority. + * + * Assumptions: + * global interrupts disabled by the caller. + * + ************************************************************************************/ + + .text + .globl up_switchcontext + .type up_switchcontext, @function +up_switchcontext: + /* "Pickle" the current thread context in the saveregs "can." r12=saveregs. */ + /* xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx */ + /* ^r12 */ + /* Sample SR and set r12 to just after the LR storage location. */ + /* xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx */ + /* ^r12 */ + + mfsr r10, AVR32_SR + sub r12, -4*(REG_LR+1) + + /* Then "push" PC=LR, LR, SR, and SP as ther are on entry. */ + /* xx xx xx xx xx xx xx xx SP SR PC LR xx xx xx xx xx */ + /* ^r12 */ + + st.w --r12, lr + st.w --r12, lr + st.w --r12, r10 + st.w --r12, sp + + /* Save the preserved/static registers, r0-r7. There is no reason to save the */ + /* scratch/volatile registers, r8-r12, in this context. */ + /* 07 06 05 04 03 02 01 00 SP SR PC LR xx xx xx xx xx */ + /* ^r12 */ + + stm --r12, r0-r7 + + /* Finally, let up_fullcontextrestore handling the re-instatement of the thread */ + /* "canned" in restoregs. */ + + mov r12, r11 + lddpc pc, .Lup_fullcontextrestore + +.Lup_fullcontextrestore: + .word up_fullcontextrestore + .size up_switchcontext, .-up_switchcontext + .end + diff --git a/nuttx/configs/avr32dev1/include/board.h b/nuttx/configs/avr32dev1/include/board.h index 77d5cd5a3..7931e3525 100755 --- a/nuttx/configs/avr32dev1/include/board.h +++ b/nuttx/configs/avr32dev1/include/board.h @@ -50,16 +50,21 @@ /* Clocking *************************************************************************/ /* #define AVR32_FRCOSC 15200 RCOsc frequency in Hz */ -#define AVR32_FOSC32 32768 /* Osc32 frequency in Hz */ -#define AVR32_OSC32STARTUP 3 /* Osc32 startup time in RCOsc periods */ +#define AVR32_FOSC32 32768 /* OSC32 frequency in Hz */ +#define AVR32_OSC32STARTUP 3 /* OSC32 startup time in RCOsc periods */ -#define AVR32_FOSC0 12000000 /* Osc0 frequency in Hz */ -#define AVR32_OSC0STARTUP 3 /* Osc0 startup time in RCOsc periods. +#define AVR32_FOSC0 12000000 /* OSC0 frequency in Hz */ +#define AVR32_OSC0STARTUP 3 /* OSC0 startup time in RCOsc periods. -/* #define AVR32_FOSC1 12000000 Osc1 frequency: Hz. - * #define AVR32_OSC1STARTUP 3 Osc1 startup time in RCOsc periods. +/* #define AVR32_FOSC1 12000000 OSC1 frequency: Hz. + * #define AVR32_OSC1STARTUP 3 OSC1 startup time in RCOsc periods. */ +/* Select OSC0 as the main clock */ + +#define AVR32_CLOCK_OSC0 1 +#undef AVR32_CLOCK_PLL0 + #define AVR32_CPU_CLOCK AVR32_FOSC0 #define AVR32_PBA_CLOCK AVR32_FOSC0 diff --git a/nuttx/include/time.h b/nuttx/include/time.h index 36c21f766..d38e96283 100644 --- a/nuttx/include/time.h +++ b/nuttx/include/time.h @@ -1,7 +1,7 @@ /******************************************************************************** * include/time.h * - * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2010 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <spudmonkey@racsa.co.cr> * * Redistribution and use in source and binary forms, with or without |