diff options
Diffstat (limited to 'nuttx/arch/arm/src/lm3s/lm3s_irq.c')
| -rw-r--r-- | nuttx/arch/arm/src/lm3s/lm3s_irq.c | 162 |
1 files changed, 156 insertions, 6 deletions
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_irq.c b/nuttx/arch/arm/src/lm3s/lm3s_irq.c index 31da0754d..b85800cb8 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_irq.c +++ b/nuttx/arch/arm/src/lm3s/lm3s_irq.c @@ -50,6 +50,12 @@ * Definitions ****************************************************************************/ +#define DEFPRIORITY32 \ + (NVIC_SYSH_PRIORITY_DEFAULT << 24 |\ + NVIC_SYSH_PRIORITY_DEFAULT << 16 |\ + NVIC_SYSH_PRIORITY_DEFAULT << 8 |\ + NVIC_SYSH_PRIORITY_DEFAULT) + /**************************************************************************** * Public Data ****************************************************************************/ @@ -65,6 +71,70 @@ uint32 *current_regs; ****************************************************************************/ /**************************************************************************** + * Name: lml3s_irqinfo + * + * Description: + * Given an IRQ number, provide the register and bit setting to enable or + * disable the irq. + * + ****************************************************************************/ + +static int lml3s_irqinfo(int irq, uint32 *regaddr, uint32 *bit) +{ + DEBUGASSERT(irq >= LMSB_IRQ_MPU && irq < NR_IRQS); + + /* Check for external interrupt */ + + if (irq >= LM3S_IRQ_INTERRUPTS) + { + if (irq < LM3S_IRQ_INTERRUPTS + 32) + { + *regaddr = NVIC_IRQ0_31_ENABLE; + *bit = 1 << (irq - LM3S_IRQ_INTERRUPTS); + } + else if (irq < NR_IRQS) + { + *regaddr = NVIC_IRQ32_63_ENABLE; + *bit = 1 << (irq - LM3S_IRQ_INTERRUPTS - 32); + } + else + { + return ERROR; /* Invalid interrupt */ + } + } + + /* Handler processor exceptions. Only a few can be disabled */ + + else + { + *regaddr = NVIC_SYSHCON; + if (irq == LMSB_IRQ_MPU) + { + *bit = NVIC_SYSHCON_MEMFAULTENA; + } + else if (irq == LMSB_IRQ_BUSFAULT) + { + *bit = NVIC_SYSHCON_BUSFAULTENA; + } + else if (irq == LMSB_IRQ_USAGEFAULT) + { + *bit = NVIC_SYSHCON_USGFAULTENA; + } + else if (irq == LMSB_IRQ_SYSTICK) + { + *regaddr = NVIC_SYSTICK_CTRL; + *bit = NVIC_SYSTICK_CTRL_ENABLE; + } + else + { + return ERROR; /* Invalid or unsupported exception */ + } + } + + return OK; +} + +/**************************************************************************** * Public Funtions ****************************************************************************/ @@ -74,9 +144,29 @@ uint32 *current_regs; void up_irqinitialize(void) { - /* Clear, disable and configure all interrupts. */ - -# warning "Missing logic" + /* Disable all interrupts */ + + putreg32(0, NVIC_IRQ0_31_ENABLE); + putreg32(0, NVIC_IRQ32_63_ENABLE); + + /* Set all interrrupts (and exceptions) to the default priority */ + + putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ32_35_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ36_39_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ40_43_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ44_47_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ48_51_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ52_55_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ56_59_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ60_63_PRIORITY); /* currents_regs is non-NULL only while processing an interrupt */ @@ -120,7 +210,18 @@ void up_irqinitialize(void) void up_disable_irq(int irq) { -# warning "Missing logic" + uint32 regaddr; + uint32 regval; + uint32 bit; + + if (lml3s_irqinfo(irq, ®addr, &bit) == 0) + { + /* Clear the appropriate bit in the register to enable the interrupt */ + + regval = getreg32(regaddr); + regval &= ~bit; + putreg32(regval, regaddr); + } } /**************************************************************************** @@ -133,7 +234,18 @@ void up_disable_irq(int irq) void up_enable_irq(int irq) { -# warning "Missing logic" + uint32 regaddr; + uint32 regval; + uint32 bit; + + if (lml3s_irqinfo(irq, ®addr, &bit) == 0) + { + /* Set the appropriate bit in the register to enable the interrupt */ + + regval = getreg32(regaddr); + regval |= bit; + putreg32(regval, regaddr); + } } /**************************************************************************** @@ -146,9 +258,47 @@ void up_enable_irq(int irq) void up_maskack_irq(int irq) { -# warning "Missing logic" + up_disable_irq(irq); } +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an IRQ. + * + * Since this API is not supported on all architectures, it should be + * avoided in common implementations where possible. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQPRIO +int up_prioritize_irq(int irq, int priority) +{ + uint32 regaddr; + uint32 regval; + int shift; + + DEBUGASSERT(irq >= LMSB_IRQ_MPU && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MAX); + + if (irq < LM3S_IRQ_INTERRUPTS) + { + regaddr = NVIC_SYSH_PRIORITY(irq); + } + else + { + irq -= LM3S_IRQ_INTERRUPTS; + regaddr = NVIC_IRQ_PRIORITY(irq); + } + + regval = getreg32(regaddr); + shift = ((irq & 3) << 3); + regval &= ~(0xff << shift); + regval |= (priority << shift); + putreg32(regval, regaddr); + return OK; +} +#endif /**************************************************************************** * Name: lm3s_nmi, lm3s_hardfault, lm3s_mpu, lm3s_busfault, lm3s_usagefault, |