1 files changed, 22 insertions, 22 deletions
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h b/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h
index 002954bfe..39fa161fc 100755
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h
@@ -43,7 +43,7 @@
 #include <nuttx/config.h>
 
 #include "chip.h"
-#include "lp17_memorymap.h"
+#include "lpc17_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -66,7 +66,7 @@
 
 /* GPIO interrupt block register offsets ********************************************/
 
-#define LPC17_GPIOINT(n)                 (0x10*(n) + 0x80)
+#define LPC17_GPIOINT_OFFSET(n)          (0x10*(n) + 0x80)
 #define LPC17_GPIOINT0_OFFSET            0x0080
 #define LPC17_GPIOINT2_OFFSET            0x00a0
 
@@ -80,7 +80,7 @@
 /* Register addresses ***************************************************************/
 /* GPIO block register addresses ****************************************************/
 
-#define LPC17_FIO_BASE(n)                (LPC17_GPIO_BASE+LPC17_GPIOINT(n))
+#define LPC17_FIO_BASE(n)                (LPC17_GPIO_BASE+LPC17_GPIOINT_OFFSET(n))
 #define LPC17_FIO0_BASE                  (LPC17_GPIO_BASE+LPC17_FIO0_OFFSET)
 #define LPC17_FIO1_BASE                  (LPC17_GPIO_BASE+LPC17_FIO1_OFFSET)
 #define LPC17_FIO2_BASE                  (LPC17_GPIO_BASE+LPC17_FIO2_OFFSET)
@@ -125,33 +125,33 @@
 
 /* GPIO interrupt block register addresses ******************************************/
 
-#define LPC17_GPIOINT(n)                 (0x10*(n) + 0x80)
-#define LPC17_GPIOINT0_OFFSET            0x0080
-#define LPC17_GPIOINT2_OFFSET            0x00a0
+#define LPC17_GPIOINTn_BASE(n)           (LPC17_GPIOINT_BASE+LPC17_GPIOINT_OFFSET(n))
+#define LPC17_GPIOINT0_BASE              (LPC17_GPIOINT_BASE+LPC17_GPIOINT0_OFFSET)
+#define LPC17_GPIOINT2_BASE              (LPC17_GPIOINT_BASE+LPC17_GPIOINT2_OFFSET)
 
-#define LPC17_GPIOINT_IOINTSTATUS        (LPC17_GPIOINT0_OFFSET+LPC17_GPIOINT_IOINTSTATUS_OFFSET)
+#define LPC17_GPIOINT_IOINTSTATUS        (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_IOINTSTATUS_OFFSET)
 
-#define LPC17_GPIOINT_INTSTATR(n)        (LPC17_GPIOINT(n)+LPC17_GPIOINT_INTSTATR_OFFSET)
-#define LPC17_GPIOINT_INTSTATF(n)        (LPC17_GPIOINT(n)+LPC17_GPIOINT_INTSTATF_OFFSET)
-#define LPC17_GPIOINT_INTCLR(n)          (LPC17_GPIOINT(n)+LPC17_GPIOINT_INTCLR_OFFSET)
-#define LPC17_GPIOINT_INTENR(n)          (LPC17_GPIOINT(n)+LPC17_GPIOINT_INTENR_OFFSET)
-#define LPC17_GPIOINT_INTENF(n)          (LPC17_GPIOINT(n)+LPC17_GPIOINT_INTENF_OFFSET)
+#define LPC17_GPIOINT_INTSTATR(n)        (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTSTATR_OFFSET)
+#define LPC17_GPIOINT_INTSTATF(n)        (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTSTATF_OFFSET)
+#define LPC17_GPIOINT_INTCLR(n)          (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTCLR_OFFSET)
+#define LPC17_GPIOINT_INTENR(n)          (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTENR_OFFSET)
+#define LPC17_GPIOINT_INTENF(n)          (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTENF_OFFSET)
 
 /* Pins P0.0-31 (P0.12-14 nad P0.31 are reserved) */
 
-#define LPC17_GPIOINT0_INTSTATR          (LPC17_GPIOINT0_OFFSET+LPC17_GPIOINT_INTSTATR_OFFSET)
-#define LPC17_GPIOINT0_INTSTATF          (LPC17_GPIOINT0_OFFSET+LPC17_GPIOINT_INTSTATF_OFFSET)
-#define LPC17_GPIOINT0_INTCLR            (LPC17_GPIOINT0_OFFSET+LPC17_GPIOINT_INTCLR_OFFSET)
-#define LPC17_GPIOINT0_INTENR            (LPC17_GPIOINT0_OFFSET+LPC17_GPIOINT_INTENR_OFFSET)
-#define LPC17_GPIOINT0_INTENF            (LPC17_GPIOINT0_OFFSET+LPC17_GPIOINT_INTENF_OFFSET)
+#define LPC17_GPIOINT0_INTSTATR          (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTSTATR_OFFSET)
+#define LPC17_GPIOINT0_INTSTATF          (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTSTATF_OFFSET)
+#define LPC17_GPIOINT0_INTCLR            (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTCLR_OFFSET)
+#define LPC17_GPIOINT0_INTENR            (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTENR_OFFSET)
+#define LPC17_GPIOINT0_INTENF            (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTENF_OFFSET)
 
 /* Pins P2.0-13 (P0.14-31 are reserved) */
 
-#define LPC17_GPIOINT2_INTSTATR          (LPC17_GPIOINT2_OFFSET+LPC17_GPIOINT_INTSTATR_OFFSET)
-#define LPC17_GPIOINT2_INTSTATF          (LPC17_GPIOINT2_OFFSET+LPC17_GPIOINT_INTSTATF_OFFSET)
-#define LPC17_GPIOINT2_INTCLR            (LPC17_GPIOINT2_OFFSET+LPC17_GPIOINT_INTCLR_OFFSET)
-#define LPC17_GPIOINT2_INTENR            (LPC17_GPIOINT2_OFFSET+LPC17_GPIOINT_INTENR_OFFSET)
-#define LPC17_GPIOINT2_INTENF            (LPC17_GPIOINT2_OFFSET+LPC17_GPIOINT_INTENF_OFFSET)
+#define LPC17_GPIOINT2_INTSTATR          (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTSTATR_OFFSET)
+#define LPC17_GPIOINT2_INTSTATF          (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTSTATF_OFFSET)
+#define LPC17_GPIOINT2_INTCLR            (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTCLR_OFFSET)
+#define LPC17_GPIOINT2_INTENR            (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTENR_OFFSET)
+#define LPC17_GPIOINT2_INTENF            (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTENF_OFFSET)
 
 /* Register bit definitions *********************************************************/
 /* GPIO block register bit definitions **********************************************/