diff options
Diffstat (limited to 'nuttx/arch/arm/src/lpc17xx/lpc17_serial.h')
| -rwxr-xr-x | nuttx/arch/arm/src/lpc17xx/lpc17_serial.h | 139 |
1 files changed, 0 insertions, 139 deletions
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_serial.h b/nuttx/arch/arm/src/lpc17xx/lpc17_serial.h index 64ee62a65..b293aba0c 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_serial.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_serial.h @@ -112,145 +112,6 @@ ************************************************************************************/
/************************************************************************************
- * Name: lpc17_uartcclkdiv
- *
- * Descrption:
- * Select a CCLK divider to produce the UART PCLK. The stratey is to select the
- * smallest divisor that results in an solution within range of the 16-bit
- * DLM and DLL divisor:
- *
- * PCLK = CCLK / divisor
- * BAUD = PCLK / (16 * DL)
- *
- * Ignoring the fractional divider for now.
- *
- * NOTE: This is an inline function. If a typical optimization level is used and
- * a constant is provided for the desired frequency, then most of the following
- * logic will be optimized away.
- *
- ************************************************************************************/
-
-static inline uint8_t lpc17_uartcclkdiv(uint32_t baud)
-{
- /* Ignoring the fractional divider, the BAUD is given by:
- *
- * BAUD = PCLK / (16 * DL), or
- * DL = PCLK / BAUD / 16
- *
- * Where:
- *
- * PCLK = CCLK / divisor.
- *
- * Check divisor == 1. This works if the upper limit is met
- *
- * DL < 0xffff, or
- * PCLK / BAUD / 16 < 0xffff, or
- * CCLK / BAUD / 16 < 0xffff, or
- * CCLK < BAUD * 0xffff * 16
- * BAUD > CCLK / 0xffff / 16
- *
- * And the lower limit is met (we can't allow DL to get very close to one).
- *
- * DL >= MinDL
- * CCLK / BAUD / 16 >= MinDL, or
- * BAUD <= CCLK / 16 / MinDL
- */
-
- if (baud < (LPC17_CCLK / 16 / UART_MINDL ))
- {
- return SYSCON_PCLKSEL_CCLK;
- }
-
- /* Check divisor == 2. This works if:
- *
- * 2 * CCLK / BAUD / 16 < 0xffff, or
- * BAUD > CCLK / 0xffff / 8
- *
- * And
- *
- * 2 * CCLK / BAUD / 16 >= MinDL, or
- * BAUD <= CCLK / 8 / MinDL
- */
-
- else if (baud < (LPC17_CCLK / 8 / UART_MINDL ))
- {
- return SYSCON_PCLKSEL_CCLK2;
- }
-
- /* Check divisor == 4. This works if:
- *
- * 4 * CCLK / BAUD / 16 < 0xffff, or
- * BAUD > CCLK / 0xffff / 4
- *
- * And
- *
- * 4 * CCLK / BAUD / 16 >= MinDL, or
- * BAUD <= CCLK / 4 / MinDL
- */
-
- else if (baud < (LPC17_CCLK / 4 / UART_MINDL ))
- {
- return SYSCON_PCLKSEL_CCLK4;
- }
-
- /* Check divisor == 8. This works if:
- *
- * 8 * CCLK / BAUD / 16 < 0xffff, or
- * BAUD > CCLK / 0xffff / 2
- *
- * And
- *
- * 8 * CCLK / BAUD / 16 >= MinDL, or
- * BAUD <= CCLK / 2 / MinDL
- */
-
- else /* if (baud < (LPC17_CCLK / 2 / UART_MINDL )) */
- {
- return SYSCON_PCLKSEL_CCLK8;
- }
-}
-
-/************************************************************************************
- * Name: lpc17_uartdl
- *
- * Descrption:
- * Select a divider to produce the BAUD from the UART PCLK.
- *
- * BAUD = PCLK / (16 * DL), or
- * DL = PCLK / BAUD / 16
- *
- * Ignoring the fractional divider for now.
- *
- ************************************************************************************/
-
-static inline uint32_t lpc17_uartdl(uint32_t baud, uint8_t divcode)
-{
- uint32_t num;
-
- switch (divcode)
- {
-
- case SYSCON_PCLKSEL_CCLK4: /* PCLK_peripheral = CCLK/4 */
- num = (LPC17_CCLK / 4);
- break;
-
- case SYSCON_PCLKSEL_CCLK: /* PCLK_peripheral = CCLK */
- num = LPC17_CCLK;
- break;
-
- case SYSCON_PCLKSEL_CCLK2: /* PCLK_peripheral = CCLK/2 */
- num = (LPC17_CCLK / 2);
- break;
-
- case SYSCON_PCLKSEL_CCLK8: /* PCLK_peripheral = CCLK/8 (except CAN1, CAN2, and CAN) */
- default:
- num = (LPC17_CCLK / 8);
- break;
- }
- return num / (baud << 4);
-}
-
-/************************************************************************************
* Public Functions
************************************************************************************/
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