1 files changed, 9 insertions, 9 deletions
diff --git a/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c b/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c
index 4c74fa912..46e847e54 100644
--- a/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c
+++ b/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c
@@ -86,7 +86,7 @@ static inline void rcc_reset(void)
   regval  = getreg32(STM32_RCC_CR);
   regval &= ~(RCC_CR_HSEON|RCC_CR_CSSON|RCC_CR_PLLON);
   putreg32(regval, STM32_RCC_CR);
- 
+
   /* Reset PLLCFGR register to reset default */
 
   putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG);
@@ -586,7 +586,7 @@ static inline void rcc_enableapb2(void)
  *
  * Description:
  *   Called to change to new clock based on settings in board.h
- * 
+ *
  *   NOTE:  This logic would need to be extended if you need to select low-
  *   power clocking modes!
  ****************************************************************************/
@@ -598,7 +598,7 @@ static void stm32_stdclockconfig(void)
   volatile int32_t timeout;
 
   /* Enable External High-Speed Clock (HSE) */
- 
+
   regval  = getreg32(STM32_RCC_CR);
   regval |= RCC_CR_HSEON;           /* Enable HSE */
   putreg32(regval, STM32_RCC_CR);
@@ -642,7 +642,7 @@ static void stm32_stdclockconfig(void)
       putreg32(regval, STM32_PWR_CR);
 
       /* Set the HCLK source/divider */
- 
+
       regval = getreg32(STM32_RCC_CFGR);
       regval &= ~RCC_CFGR_HPRE_MASK;
       regval |= STM32_RCC_CFGR_HPRE;
@@ -654,7 +654,7 @@ static void stm32_stdclockconfig(void)
       regval &= ~RCC_CFGR_PPRE2_MASK;
       regval |= STM32_RCC_CFGR_PPRE2;
       putreg32(regval, STM32_RCC_CFGR);
-  
+
       /* Set the PCLK1 divider */
 
       regval = getreg32(STM32_RCC_CFGR);
@@ -673,13 +673,13 @@ static void stm32_stdclockconfig(void)
       regval = getreg32(STM32_RCC_CR);
       regval |= RCC_CR_PLLON;
       putreg32(regval, STM32_RCC_CR);
- 
+
       /* Wait until the PLL is ready */
-  
+
       while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0)
         {
         }
- 
+
 #if defined(CONFIG_STM32_STM32F429)
       /* Enable the Over-drive to extend the clock frequency to 180 Mhz */
 
@@ -716,7 +716,7 @@ static void stm32_stdclockconfig(void)
       putreg32(regval, STM32_RCC_CFGR);
 
       /* Wait until the PLL source is used as the system clock source */
-  
+
       while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL)
         {
         }