diff options
Diffstat (limited to 'nuttx/arch/arm/src')
68 files changed, 7483 insertions, 2214 deletions
diff --git a/nuttx/arch/arm/src/armv7-m/nvic.h b/nuttx/arch/arm/src/armv7-m/nvic.h index e6d6f8e9e..2d76e4e6b 100644 --- a/nuttx/arch/arm/src/armv7-m/nvic.h +++ b/nuttx/arch/arm/src/armv7-m/nvic.h @@ -399,8 +399,8 @@ /* Interrrupt controller type (INCTCTL_TYPE) */ -#define NVIC_ICTR_INTLINESNUM_SHIFT 0 /* Bits 4-0: Number of interrupt intputs / 32 */ -#define NVIC_ICTR_INTLINESNUM_MASK (0x1f << NVIC_ICTR_INTLINESNUM_SHIFT) +#define NVIC_ICTR_INTLINESNUM_SHIFT 0 /* Bits 0-3: Number of interrupt inputs / 32 - 1 */ +#define NVIC_ICTR_INTLINESNUM_MASK (15 << NVIC_ICTR_INTLINESNUM_SHIFT) /* SysTick control and status register (SYSTICK_CTRL) */ diff --git a/nuttx/arch/arm/src/lpc17xx/Kconfig b/nuttx/arch/arm/src/lpc17xx/Kconfig index 6f8967054..ff383bae4 100644 --- a/nuttx/arch/arm/src/lpc17xx/Kconfig +++ b/nuttx/arch/arm/src/lpc17xx/Kconfig @@ -335,20 +335,6 @@ config SERIAL_TERMIOS If this is not defined, then the terminal settings (baud, parity, etc). are not configurable at runtime; serial streams cannot be flushed, etc.. -config UART0_FLOWCONTROL - bool "UART0 flow control" - depends on LPC17_UART0 - default n - ---help--- - Enable UART0 flow control - -config UART1_FLOWCONTROL - bool "UART1 flow control" - depends on LPC17_UART1 - default n - ---help--- - Enable UART1 flow control - config UART1_RINGINDICATOR bool "UART1 ring indicator" depends on LPC17_UART1 @@ -356,20 +342,6 @@ config UART1_RINGINDICATOR ---help--- Enable UART1 ring indicator -config UART2_FLOWCONTROL - bool "UART0 flow control" - depends on LPC17_UART2 - default n - ---help--- - Enable UART2 flow control - -config UART3_FLOWCONTROL - bool "UART3 flow control" - depends on LPC17_UART3 - default n - ---help--- - Enable UART3 flow control - endmenu menu "ADC driver options" diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_lowputc.c b/nuttx/arch/arm/src/lpc17xx/lpc17_lowputc.c index 9ff0eab60..3926c8712 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_lowputc.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_lowputc.c @@ -359,7 +359,7 @@ void lpc17_lowsetup(void) #elif defined(CONFIG_UART1_SERIAL_CONSOLE) lpc17_configgpio(GPIO_UART1_TXD); lpc17_configgpio(GPIO_UART1_RXD); -#ifdef CONFIG_UART1_FLOWCONTROL +#if defined(CONFIG_UART1_IFLOWCONTROL) || defined(CONFIG_UART1_OFLOWCONTROL) lpc17_configgpio(GPIO_UART1_CTS); lpc17_configgpio(GPIO_UART1_DCD); lpc17_configgpio(GPIO_UART1_DSR); diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_serial.c b/nuttx/arch/arm/src/lpc17xx/lpc17_serial.c index 6bf519ac3..ed1a37814 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_serial.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_serial.c @@ -736,7 +736,7 @@ static inline void lpc17_uart1config(void) lpc17_configgpio(GPIO_UART1_TXD); lpc17_configgpio(GPIO_UART1_RXD); -#ifdef CONFIG_UART1_FLOWCONTROL +#if defined(CONFIG_UART1_IFLOWCONTROL) || defined(CONFIG_UART1_OFLOWCONTROL) lpc17_configgpio(GPIO_UART1_CTS); lpc17_configgpio(GPIO_UART1_RTS); lpc17_configgpio(GPIO_UART1_DCD); @@ -943,10 +943,16 @@ static int up_setup(struct uart_dev_s *dev) /* Enable Auto-RTS and Auto-CS Flow Control in the Modem Control Register */ -#ifdef CONFIG_UART1_FLOWCONTROL +#if defined(CONFIG_UART1_IFLOWCONTROL) || defined(CONFIG_UART1_OFLOWCONTROL) if (priv->uartbase == LPC17_UART1_BASE) { +#if defined(CONFIG_UART1_IFLOWCONTROL) && defined(CONFIG_UART1_OFLOWCONTROL) up_serialout(priv, LPC17_UART_MCR_OFFSET, (UART_MCR_RTSEN|UART_MCR_CTSEN)); +#elif defined(CONFIG_UART1_IFLOWCONTROL) + up_serialout(priv, LPC17_UART_MCR_OFFSET, UART_MCR_RTSEN); +#else + up_serialout(priv, LPC17_UART_MCR_OFFSET, UART_MCR_CTSEN); +#endif } #endif diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_serial.h b/nuttx/arch/arm/src/lpc17xx/lpc17_serial.h index 95e8155de..3db62f7f8 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_serial.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_serial.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/lpc17xx/lpc17_serial.h * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -96,11 +96,15 @@ /* Check UART flow control (Only supported by UART1) */ -# undef CONFIG_UART0_FLOWCONTROL -# undef CONFIG_UART2_FLOWCONTROL -# undef CONFIG_UART3_FLOWCONTROL +# undef CONFIG_UART0_IFLOWCONTROL +# undef CONFIG_UART0_OFLOWCONTROL +# undef CONFIG_UART2_IFLOWCONTROL +# undef CONFIG_UART2_OFLOWCONTROL +# undef CONFIG_UART3_IFLOWCONTROL +# undef CONFIG_UART3_OFLOWCONTROL #ifndef CONFIG_LPC17_UART1 -# undef CONFIG_UART1_FLOWCONTROL +# undef CONFIG_UART1_IFLOWCONTROL +# undef CONFIG_UART1_OFLOWCONTROL #endif /* We cannot allow the DLM/DLL divisor to become to small or will will lose too diff --git a/nuttx/arch/arm/src/sam34/Kconfig b/nuttx/arch/arm/src/sam34/Kconfig index b26dec659..bcc5ebab9 100644 --- a/nuttx/arch/arm/src/sam34/Kconfig +++ b/nuttx/arch/arm/src/sam34/Kconfig @@ -3,10 +3,10 @@ # see misc/tools/kconfig-language.txt. # -comment "AT91SAM3/SAM4 Configuration Options" +comment "AT91SAM3/4 Configuration Options" choice - prompt "AT91SAM3 Chip Selection" + prompt "AT91SAM3/4 Chip Selection" default ARCH_CHIP_AT91SAM3U4E depends on ARCH_CHIP_SAM34 @@ -75,52 +75,52 @@ config ARCH_CHIP_ATSAM4LS4A select ARCH_CORTEXM4 select ARCH_CHIP_SAM4L -config CONFIG_ARCH_CHIP_ATSAM4SD32C +config ARCH_CHIP_ATSAM4SD32C bool "ATSAM4SD32C" select ARCH_CORTEXM4 select ARCH_CHIP_SAM4S -config CONFIG_ARCH_CHIP_ATSAM4SD32B +config ARCH_CHIP_ATSAM4SD32B bool "ATSAM4SD32B" select ARCH_CORTEXM4 select ARCH_CHIP_SAM4S -config CONFIG_ARCH_CHIP_ATSAM4SD16C +config ARCH_CHIP_ATSAM4SD16C bool "ATSAM4SD16C" select ARCH_CORTEXM4 select ARCH_CHIP_SAM4S -config CONFIG_ARCH_CHIP_ATSAM4SD16B +config ARCH_CHIP_ATSAM4SD16B bool "ATSAM4SD16B" select ARCH_CORTEXM4 select ARCH_CHIP_SAM4S -config CONFIG_ARCH_CHIP_ATSAM4SA16C +config ARCH_CHIP_ATSAM4SA16C bool "ATSAM4SA16C" select ARCH_CORTEXM4 select ARCH_CHIP_SAM4S -config CONFIG_ARCH_CHIP_ATSAM4SA16B +config ARCH_CHIP_ATSAM4SA16B bool "ATSAM4SA16B" select ARCH_CORTEXM4 select ARCH_CHIP_SAM4S -config CONFIG_ARCH_CHIP_ATSAM4S16C +config ARCH_CHIP_ATSAM4S16C bool "ATSAM4S16C" select ARCH_CORTEXM4 select ARCH_CHIP_SAM4S -config CONFIG_ARCH_CHIP_ATSAM4S16B +config ARCH_CHIP_ATSAM4S16B bool "ATSAM4S16B" select ARCH_CORTEXM4 select ARCH_CHIP_SAM4S -config CONFIG_ARCH_CHIP_ATSAM4S8C +config ARCH_CHIP_ATSAM4S8C bool "ATSAM4S8C" select ARCH_CORTEXM4 select ARCH_CHIP_SAM4S -config CONFIG_ARCH_CHIP_ATSAM4S8B +config ARCH_CHIP_ATSAM4S8B bool "ATSAM4S8B" select ARCH_CORTEXM4 select ARCH_CHIP_SAM4S @@ -134,59 +134,305 @@ config ARCH_CHIP_SAM3U config ARCH_CHIP_SAM4L bool default n + select ARCH_RAMFUNCS config ARCH_CHIP_SAM4S bool default n -menu "AT91SAM3 Peripheral Support" +menu "AT91SAM3/4 Peripheral Support" config SAM_PICOCACHE bool "PICOCACHE" - depends on ARCH_CHIP_SAM4L default y + depends on ARCH_CHIP_SAM4L -config SAM34_DMA - bool "DMA" +config SAM34_OCD + bool "On-chip DEBUG" + depends on ARCH_CHIP_SAM4L + default y if DEBUG_SYMBOLS + default n if !DEBUG_SYMBOLS + +config SAM34_APBA + bool "APBA bridge" default n - select ARCH_DMA + depends on ARCH_CHIP_SAM4L -config SAM34_NAND - bool "NAND support" +config SAM34_AESA + bool "Advanced Encryption Standard (AESA)" default n + depends on ARCH_CHIP_SAM4L -config SAM34_HSMCI - bool "HSMCI" +config SAM34_IISC + bool "Inter-IC Sound (I2S) Controller" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_SPI + bool "Serial Peripheral Interface (SPI)" + default n + +config SAM34_SSC + bool "Synchronous Serial Controller (SSC)" + default n + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S + +config SAM34_TC0 + bool "Timer/Counter 0 (TC0)" + default n + +config SAM34_TC1 + bool "Timer/Counter 1 (TC1)" + default n + +config SAM34_TC2 + bool "Timer/Counter 2 (TC2)" + default n + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S + +config SAM34_TC3 + bool "Timer/Counter 3 (TC3)" + default n + depends on ARCH_CHIP_SAM4S + +config SAM34_TC4 + bool "Timer/Counter 4 (TC4)" default n + depends on ARCH_CHIP_SAM4S -config SAM34_UART - bool "UART" +config SAM34_TC5 + bool "Timer/Counter 5 (TC5)" + default n + depends on ARCH_CHIP_SAM4S + +config SAM34_PWM + bool "Pulse Width Modulation (PWM) Controller" + default n + depends on ARCH_CHIP_SAM3U|| ARCH_CHIP_SAM4S + +config SAM34_TWIM0 + bool "Two-wire Master Interface 0 (TWIM0)" + default n + +config SAM34_TWIS0 + bool "Two-wire Slave Interface 0 (TWIS0)" + default n + +config SAM34_TWIM1 + bool "Two-wire Master Interface 1 (TWIM1)" + default n + +config SAM34_TWIS1 + bool "Two-wire Slave Interface 1 (TWIS1)" + default n + +config SAM34_TWIM2 + bool "Two-wire Master Interface 2 (TWIM2)" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_TWIM3 + bool "Two-wire Master Interface 3 (TWIM3)" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_UART0 + bool "UART 0" default y + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S + select ARCH_HAVE_UART0 + +config SAM34_UART1 + bool "UART 1" + default n + depends on ARCH_CHIP_SAM4S + select ARCH_HAVE_UART1 + +config SAM34_PICOUART + bool "PicoUART" + default n + depends on ARCH_CHIP_SAM4L select ARCH_HAVE_UART config SAM34_USART0 - bool "USART0" + bool "USART 0" default n + select ARCH_HAVE_USART0 config SAM34_USART1 - bool "USART1" + bool "USART 1" default n + select ARCH_HAVE_USART1 config SAM34_USART2 - bool "USART2" + bool "USART 2" default n + select ARCH_HAVE_USART2 + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4L config SAM34_USART3 - bool "USART3" + bool "USART 3" default n + select ARCH_HAVE_USART3 + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4L -config SAM34_SPI - bool "SPI" +config SAM34_ADC12B + bool "12-bit ADC Controller" + default n + +config SAM34_ADC + bool "10-bit ADC Controller" + default n + depends on ARCH_CHIP_SAM3U + +config SAM34_DACC + bool "Digital To Analog Converter (DAC)" + default n + depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S + +config SAM34_ACC + bool "Analog Comparator (AC)" + default n + depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S + +config SAM34_GLOC + bool "GLOC" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_ABDACB + bool "Audio Bitstream DAC (ABDAC)" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_TRNG + bool "True Random Number Generator (TRNG)" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_PARC + bool "Parallel Capture (PARC)" default n + depends on ARCH_CHIP_SAM4L + +config SAM34_CATB + bool "Capacitive Touch Module B (CATB)" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_LCDCA + bool "LCD Controller A (LCDCA)" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_HRAMC1 + bool "HRAMC1 (picoCache RAM)" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_SMC + bool "Static Memory Controller (SMC)" + default n + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S + +config SAM34_NAND + bool "NAND support" + default n + depends on ARCH_CHIP_SAM3U + +config SAM34_HMATRIX + bool "HMATRIX" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_PDCA + bool "Peripheral DMA controller (PDC)" + default n + depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S + select ARCH_DMA + +config SAM34_DMA + bool "DMA controller" + default n + depends on ARCH_CHIP_SAM3U + select ARCH_DMA + +config SAM34_CRCCU + bool "CRC Calculation Unit" + default n + depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S + +config SAM34_UDPHS + bool "USB Device High Speed" + default n + depends on ARCH_CHIP_SAM3U + +config SAM34_UDP + bool "USB Device Full Speed" + default n + depends on ARCH_CHIP_SAM4S + +config SAM34_USBC + bool "USB 2.0 Interface" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_PEVC + bool "Peripheral Event Controller" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_CHIPID + bool "Chip ID" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_FREQM + bool "Frequency Meter (FREQM)" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_AST + bool "Asynchronous Timer (AST)" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_RTC + bool "Real Time Clock (RTC)" + default n + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S + +config SAM34_RTT + bool "Real Time Timer (RTT)" + default n + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S + +config SAM34_WDT + bool "Watchdog Timer (WDT)" + default n + +config SAM34_EIC + bool "External Interrupt Controller (EIC)" + default n + depends on ARCH_CHIP_SAM4L + +config SAM34_HSMCI + bool "High Speed Multimedia Card Interface (HSMCI)" + default n + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S endmenu -menu "AT91SAM3 UART Configuration" +config SAM32_RESET_PERIPHCLKS + bool "Enable all peripheral clocks on reset" + default n + depends on ARCH_CHIP_SAM4L + ---help--- + By default, only a few necessary peripheral clocks are enabled at + reset. If this setting is enabled, then all clocking will be enabled + to all of the selected peripherals on reset. + +comment "AT91SAM3/4 USART Configuration" config USART0_ISUART bool "USART0 is a UART" @@ -212,9 +458,13 @@ config USART3_ISUART depends on SAM34_USART3 select ARCH_HAVE_USART2 -endmenu +comment "AT91SAM3/4 GPIO Interrupt Configuration" +config GPIO_IRQ + bool "GPIO pin interrupts" + ---help--- + Enable support for interrupting GPIO pins -menu "AT91SAM3 GPIO Interrupt Configuration" +if GPIO_IRQ config GPIOA_IRQ bool "GPIOA interrupts" @@ -228,4 +478,30 @@ config GPIOC_IRQ bool "GPIOC interrupts" default n -endmenu +endif + +if SAM34_WDT +comment "AT91SAM3/4 Watchdog Configuration"| + +config WDT_ENABLED_ON_RESET + bool "Enabled on reset" + default n + ---help--- + The WDT can be enabled at reset. This is controlled by the WDTAUTO + fuse. The WDT will be set in basic mode, RCSYS is set as source for + CLK_CNT, and PSEL will be set to a value giving Tpsel above 100 ms + (SAM4L) + + This setting informs that start-up logic that the watchdog is + enabled. + +config WDT_DISABLE_ON_RESET + bool "Disable on reset" + default n + depends on WDT_ENABLED_ON_RESET + ---help--- + If the WDT can be enabled at reset then this setting may be used to + configure and disable the watchdog timer very early in the boot + sequence. + +endif diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_eefc.h b/nuttx/arch/arm/src/sam34/chip/sam3u_eefc.h index 05ffad19b..974aef0cd 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam3u_eefc.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_eefc.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam3u_eefc.h + * Enhanced Embedded Flash Controller (EEFC) defintions for the SAM3U and SAM4S * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -74,20 +75,38 @@ #define SAM_EEFC1_FRR (SAM_EEFC1_BASE+SAM_EEFC_FRR_OFFSET) /* EEFC register bit definitions ********************************************************/ +/* EEFC Flash Mode Register */ #define EEFC_FMR_FRDY (1 << 0) /* Bit 0: Ready Interrupt Enable */ #define EEFC_FMR_FWS_SHIFT (8) /* Bits 8-11: Flash Wait State */ #define EEFC_FMR_FWS_MASK (15 << EEFC_FMR_FWS_SHIFT) + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define EEFC_FMR_SCOD (1 << 16) /* Bit 16: Sequential Code Optimization Disable */ +#endif + #define EEFC_FMR_FAM (1 << 24) /* Bit 24: Flash Access Mode */ +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define EEFC_FMR_CLOE (1 << 26) /* Bit 26: Code Loops Optimization Enable */ +#endif + +/* EEFC Flash Command Register */ + #define EEFC_FCR_FCMD_SHIFT (0) /* Bits 0-7: Flash Command */ #define EEFC_FCR_FCMD_MASK (0xff << EEFC_FCR_FCMD_SHIFT) + # define EEFC_FCR_FCMD_GETD (0 << EEFC_FCR_FCMD_SHIFT) /* Get Flash Descriptor */ # define EEFC_FCR_FCMD_WP (1 << EEFC_FCR_FCMD_SHIFT) /* Write page */ # define EEFC_FCR_FCMD_WPL (2 << EEFC_FCR_FCMD_SHIFT) /* Write page and lock */ # define EEFC_FCR_FCMD_EWP (3 << EEFC_FCR_FCMD_SHIFT) /* Erase page and write page */ # define EEFC_FCR_FCMD_EWPL (4 << EEFC_FCR_FCMD_SHIFT) /* Erase page and write page then lock */ # define EEFC_FCR_FCMD_EA (5 << EEFC_FCR_FCMD_SHIFT) /* Erase all */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define EEFC_FCR_FCMD_EPA (7 << EEFC_FCR_FCMD_SHIFT) /* Erase Pages */ +#endif + # define EEFC_FCR_FCMD_SLB (8 << EEFC_FCR_FCMD_SHIFT) /* Set Lock Bit */ # define EEFC_FCR_FCMD_CLB (9 << EEFC_FCR_FCMD_SHIFT) /* Clear Lock Bit */ # define EEFC_FCR_FCMD_GLB (10 << EEFC_FCR_FCMD_SHIFT) /* Get Lock Bit */ @@ -96,15 +115,32 @@ # define EEFC_FCR_FCMD_GGPB (13 << EEFC_FCR_FCMD_SHIFT) /* Get GPNVM Bit */ # define EEFC_FCR_FCMD_STUI (14 << EEFC_FCR_FCMD_SHIFT) /* Start Read Unique Identifier */ # define EEFC_FCR_FCMD_SPUI (15 << EEFC_FCR_FCMD_SHIFT) /* Stop Read Unique Identifier */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define EEFC_FCR_FCMD_GCALB (16 << EEFC_FCR_FCMD_SHIFT) /* Get CALIB Bit */ +# define EEFC_FCR_FCMD_ES (17 << EEFC_FCR_FCMD_SHIFT) /* Erase Sector */ +# define EEFC_FCR_FCMD_WUS (18 << EEFC_FCR_FCMD_SHIFT) /* Write User Signature */ +# define EEFC_FCR_FCMD_EUS (19 << EEFC_FCR_FCMD_SHIFT) /* Erase User Signature */ +# define EEFC_FCR_FCMD_STUS (20 << EEFC_FCR_FCMD_SHIFT) /* Start Read User Signature */ +# define EEFC_FCR_FCMD_SPUS (21 << EEFC_FCR_FCMD_SHIFT) /* Stop Read User Signature */ +#endif + #define EEFC_FCR_FARG_SHIFT (8) /* Bits 8-23: Flash Command Argument */ #define EEFC_FCR_FARG_MASK (0xffff << EEFC_FCR_FARG_SHIFT) #define EEFC_FCR_FKEY_SHIFT (24) /* Bits 24-31: Flash Writing Protection Key */ -#define EEFC_FCR_FKEY__MASK (0xff << EEFC_FCR_FKEY_SHIFT) +#define EEFC_FCR_FKEY_MASK (0xff << EEFC_FCR_FKEY_SHIFT) +# define EEFC_FCR_FKEY_PASSWD (0x5a << EEFC_FCR_FKEY_SHIFT) + +/* EEFC Flash Status Register */ #define EEFC_FSR_FRDY (1 << 0) /* Bit 0: Flash Ready Status */ #define EEFC_FSR_FCMDE (1 << 1) /* Bit 1: Flash Command Error Status */ #define EEFC_FSR_FLOCKE (1 << 2) /* Bit 2: Flash Lock Error Status */ +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define EEFC_FSR_FLERR (1 << 3) /* Bit 3: Flash Error Status */ +#endif + /**************************************************************************************** * Public Types ****************************************************************************************/ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_matrix.h b/nuttx/arch/arm/src/sam34/chip/sam3u_matrix.h index 6fed14092..6a8274006 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_matrix.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_matrix.h @@ -1,5 +1,6 @@ /**************************************************************************************** - * arch/arm/src/sam34/chip/sam_matric.h + * arch/arm/src/sam34/chip/sam_34matrix.h + * Bux matrix definitions for the SAM3U and SAM4S * * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -33,8 +34,8 @@ * ****************************************************************************************/ -#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_MATRIX_H -#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_MATRIX_H +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_MATRIX_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_MATRIX_H /**************************************************************************************** * Included Files @@ -64,12 +65,16 @@ #define SAM_MATRIX_SCFG2_OFFSET 0x0048 /* Slave Configuration Register 2 */ #define SAM_MATRIX_SCFG3_OFFSET 0x004c /* Slave Configuration Register 3 */ #define SAM_MATRIX_SCFG4_OFFSET 0x0050 /* Slave Configuration Register 4 */ -#define SAM_MATRIX_SCFG5_OFFSET 0x0054 /* Slave Configuration Register 5 */ -#define SAM_MATRIX_SCFG6_OFFSET 0x0058 /* Slave Configuration Register 6 */ -#define SAM_MATRIX_SCFG7_OFFSET 0x005c /* Slave Configuration Register 7 */ -#define SAM_MATRIX_SCFG8_OFFSET 0x0060 /* Slave Configuration Register 8 */ -#define SAM_MATRIX_SCFG9_OFFSET 0x0064 /* Slave Configuration Register 9 */ - /* 0x0068-0x007c: Reserved */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_MATRIX_SCFG5_OFFSET 0x0054 /* Slave Configuration Register 5 */ +# define SAM_MATRIX_SCFG6_OFFSET 0x0058 /* Slave Configuration Register 6 */ +# define SAM_MATRIX_SCFG7_OFFSET 0x005c /* Slave Configuration Register 7 */ +# define SAM_MATRIX_SCFG8_OFFSET 0x0060 /* Slave Configuration Register 8 */ +# define SAM_MATRIX_SCFG9_OFFSET 0x0064 /* Slave Configuration Register 9 */ + /* 0x0068-0x007c: Reserved (SAM3U) */ +#endif + /* 0x0054-0x007c: Reserved (SAM4S) */ #define SAM_MATRIX_PRAS_OFFSET(n) (0x0080+((n)<<3)) #define SAM_MATRIX_PRAS0_OFFSET 0x0080 /* Priority Register A for Slave 0 */ /* 0x0084: Reserved */ @@ -80,19 +85,29 @@ #define SAM_MATRIX_PRAS3_OFFSET 0x0098 /* Priority Register A for Slave 3 */ /* 0x009c: Reserved */ #define SAM_MATRIX_PRAS4_OFFSET 0x00a0 /* Priority Register A for Slave 4 */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) /* 0x00a4: Reserved */ -#define SAM_MATRIX_PRAS5_OFFSET 0x00a8 /* Priority Register A for Slave 5 */ +# define SAM_MATRIX_PRAS5_OFFSET 0x00a8 /* Priority Register A for Slave 5 */ /* 0x00ac: Reserved */ -#define SAM_MATRIX_PRAS6_OFFSET 0x00b0 /* Priority Register A for Slave 6 */ +# define SAM_MATRIX_PRAS6_OFFSET 0x00b0 /* Priority Register A for Slave 6 */ /* 0x00b4: Reserved */ -#define SAM_MATRIX_PRAS7_OFFSET 0x00b8 /* Priority Register A for Slave 7 */ +# define SAM_MATRIX_PRAS7_OFFSET 0x00b8 /* Priority Register A for Slave 7 */ /* 0x00bc: Reserved */ -#define SAM_MATRIX_PRAS8_OFFSET 0x00c0 /* Priority Register A for Slave 8 */ +# define SAM_MATRIX_PRAS8_OFFSET 0x00c0 /* Priority Register A for Slave 8 */ /* 0x00c4: Reserved */ -#define SAM_MATRIX_PRAS9_OFFSET 0x00c8 /* Priority Register A for Slave 9 */ +# define SAM_MATRIX_PRAS9_OFFSET 0x00c8 /* Priority Register A for Slave 9 */ /* 0x00cc-0x00fc: Reserved */ -#define SAM_MATRIX_MRCR_OFFSET 0x0100 /* Master Remap Control Register */ - /* 0x0104-0x010c: Reserved */ +# define SAM_MATRIX_MRCR_OFFSET 0x0100 /* Master Remap Control Register */ + /* 0x0104-0x01e0: Reserved */ +#elif defined(CONFIG_ARCH_CHIP_SAM4S) + /* 0x00a4-0x110: Reserved */ +# define SAM_MATRIX_CCFG_SYSIO_OFFSET 0x0114 /* System I/O Configuration Register */ + /* 0x0118: Reserved */ +# define SAM_MATRIX_CCFG_SMCNFCS_OFFSET 0x011c /* SMC Chip Select NAND Flash Assignment Register */ + /* 0x0120-0x01e0: Reserved */ +#endif + #define SAM_MATRIX_WPMR_OFFSET 0x01e4 /* Write Protect Mode Register */ #define SAM_MATRIX_WPSR_OFFSET 0x01e8 /* Write Protect Status Register */ /* 0x0110 - 0x01fc: Reserved */ @@ -112,11 +127,13 @@ #define SAM_MATRIX_SCFG2 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG2_OFFSET) #define SAM_MATRIX_SCFG3 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG3_OFFSET) #define SAM_MATRIX_SCFG4 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG4_OFFSET) -#define SAM_MATRIX_SCFG5 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG5_OFFSET) -#define SAM_MATRIX_SCFG6 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG6_OFFSET) -#define SAM_MATRIX_SCFG7 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG7_OFFSET) -#define SAM_MATRIX_SCFG8 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG8_OFFSET) -#define SAM_MATRIX_SCFG9 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG9_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_MATRIX_SCFG5 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG5_OFFSET) +# define SAM_MATRIX_SCFG6 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG6_OFFSET) +# define SAM_MATRIX_SCFG7 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG7_OFFSET) +# define SAM_MATRIX_SCFG8 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG8_OFFSET) +# define SAM_MATRIX_SCFG9 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG9_OFFSET) +#endif #define SAM_MATRIX_PRAS(n) (SAM_MATRIX_BASE+SAM_MATRIX_PRAS_OFFSET(n)) #define SAM_MATRIX_PRAS0 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS0_OFFSET) @@ -124,17 +141,26 @@ #define SAM_MATRIX_PRAS2 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS2_OFFSET) #define SAM_MATRIX_PRAS3 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS3_OFFSET) #define SAM_MATRIX_PRAS4 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS4_OFFSET) -#define SAM_MATRIX_PRAS5 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS5_OFFSET) -#define SAM_MATRIX_PRAS6 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS6_OFFSET) -#define SAM_MATRIX_PRAS7 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS7_OFFSET) -#define SAM_MATRIX_PRAS8 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS8_OFFSET) -#define SAM_MATRIX_PRAS9 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS9_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_MATRIX_PRAS5 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS5_OFFSET) +# define SAM_MATRIX_PRAS6 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS6_OFFSET) +# define SAM_MATRIX_PRAS7 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS7_OFFSET) +# define SAM_MATRIX_PRAS8 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS8_OFFSET) +# define SAM_MATRIX_PRAS9 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS9_OFFSET) +#endif + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_MATRIX_MRCR (SAM_MATRIX_BASE+SAM_MATRIX_MRCR_OFFSET) +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_MATRIX_CCFG_SYSIO (SAM_MATRIX_BASE+SAM_MATRIX_CCFG_SYSIO_OFFSET) +# define SAM_MATRIX_CCFG_SMCNFCS (SAM_MATRIX_BASE+SAM_MATRIX_CCFG_SMCNFCS_OFFSET) +#endif -#define SAM_MATRIX_MRCR (SAM_MATRIX_BASE+SAM_MATRIX_MRCR_OFFSET) #define SAM_MATRIX_WPMR (SAM_MATRIX_BASE+SAM_MATRIX_WPMR_OFFSET) #define SAM_MATRIX_WPSR (SAM_MATRIX_BASE+SAM_MATRIX_WPSR_OFFSET) /* MATRIX register bit definitions ******************************************************/ +/* Master Configuration Registers */ #define MATRIX_MCFG_ULBT_SHIFT (0) /* Bits 0-2: Undefined Length Burst Type */ #define MATRIX_MCFG_ULBT_MASK (7 << MATRIX_MCFG_ULBT_SHIFT) @@ -144,6 +170,8 @@ # define MATRIX_MCFG_ULBT_8BEAT (3 << MATRIX_MCFG_ULBT_SHIFT) /* Eight Beat Burst */ # define MATRIX_MCFG_ULBT_16BEAT (4 << MATRIX_MCFG_ULBT_SHIFT) /* Sixteen Beat Burst */ +/* Bus Matrix Slave Configuration Registers */ + #define MATRIX_SCFG_SLOTCYCLE_SHIFT (0) /* Bits 0-7: Maximum Number of Allowed Cycles for a Burst */ #define MATRIX_SCFG_SLOTCYCLE_MASK (0xff << MATRIX_SCFG_SLOTCYCLE_SHIFT) #define MATRIX_SCFG_DEFMSTRTYPE_SHIFT (16) /* Bits 16-17: Default Master Type */ @@ -165,12 +193,13 @@ # define MATRIX_SCFG8_FIXEDDEFMSTR_HDMA (4 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) # define MATRIX_SCFG9_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) # define MATRIX_SCFG9_FIXEDDEFMSTR_HDMA (4 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) - #define MATRIX_SCFG_ARBT_SHIFT (24) /* Bits 24-25: Arbitration Type */ #define MATRIX_SCFG_ARBT_MASK (3 << MATRIX_SCFG_ARBT_SHIFT) # define MATRIX_SCFG_ARBT_RR (0 << MATRIX_SCFG_ARBT_SHIFT) /* Round-Robin Arbitration */ # define MATRIX_SCFG_ARBT_FIXED (1 << MATRIX_SCFG_ARBT_SHIFT) /* Fixed Priority Arbitration */ +/* Bus Matrix Priority Registers For Slaves */ + #define MATRIX_PRAS_MPR_SHIFT(x) ((n)<<2) #define MATRIX_PRAS_MPR_MASK(x) (3 << MATRIX_PRAS_MPR_SHIFT(x)) #define MATRIX_PRAS_M0PR_SHIFT (0) /* Bits 0-1: Master 0 Priority */ @@ -184,16 +213,46 @@ #define MATRIX_PRAS_M4PR_SHIFT (16) /* Bits 16-17 Master 4 Priority */ #define MATRIX_PRAS_M4PR_MASK (3 << MATRIX_PRAS_M4PR_SHIFT) -#define MATRIX_MRCR_RCB(x) (1 << (x)) -#define MATRIX_MRCR_RCB0 (1 << 0) /* Bit 0: Remap Command Bit for AHB Master 0 */ -#define MATRIX_MRCR_RCB1 (1 << 1) /* Bit 1: Remap Command Bit for AHB Master 1 */ -#define MATRIX_MRCR_RCB2 (1 << 2) /* Bit 2: Remap Command Bit for AHB Master 2 */ -#define MATRIX_MRCR_RCB3 (1 << 3) /* Bit 3: Remap Command Bit for AHB Master 3 */ -#define MATRIX_MRCR_RCB4 (1 << 4) /* Bit 4: Remap Command Bit for AHB Master 4 */ +/* System I/O Configuration Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define MATRIX_CCFG_SYSIO_SYSIO4 (1 << 4) /* Bit 4: PB4 or TDI Assignment */ +# define MATRIX_CCFG_SYSIO_SYSIO5 (1 << 5) /* Bit 5: PB5 or TDO/TRACESWO Assignment */ +# define MATRIX_CCFG_SYSIO_SYSIO6 (1 << 6) /* Bit 6: PB6 or TMS/SWDIO Assignment */ +# define MATRIX_CCFG_SYSIO_SYSIO7 (1 << 7) /* Bit 7: PB7 or TCK/SWCLK Assignment */ +# define MATRIX_CCFG_SYSIO_SYSIO10 (1 << 10) /* Bit 10: PB10 or DDM Assignment */ +# define MATRIX_CCFG_SYSIO_SYSIO11 (1 << 11) /* Bit 11: PB11 or DDP Assignment */ +# define MATRIX_CCFG_SYSIO_SYSIO12 (1 << 12) /* Bit 12: PB12 or ERASE Assignment */ +#endif + +/* SMC Chip Select NAND Flash Assignment Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define MATRIX_CCFG_SMCNFCS_SMC_NFCS0 (1 << 0) /* Bit 0: SMC NAND Flash Chip Select 0 Assignment */ +# define MATRIX_CCFG_SMCNFCS_SMC_NFCS1 (1 << 1) /* Bit 1: SMC NAND Flash Chip Select 2 Assignment */ +# define MATRIX_CCFG_SMCNFCS_SMC_NFCS2 (1 << 2) /* Bit 2: SMC NAND Flash Chip Select 2 Assignment */ +# define MATRIX_CCFG_SMCNFCS_SMC_NFCS3 (1 << 3) /* Bit 3: SMC NAND Flash Chip Select 3 Assignment */ +#endif + +/* Master Remap Control Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define MATRIX_MRCR_RCB(x) (1 << (x)) +# define MATRIX_MRCR_RCB0 (1 << 0) /* Bit 0: Remap Command Bit for AHB Master 0 */ +# define MATRIX_MRCR_RCB1 (1 << 1) /* Bit 1: Remap Command Bit for AHB Master 1 */ +# define MATRIX_MRCR_RCB2 (1 << 2) /* Bit 2: Remap Command Bit for AHB Master 2 */ +# define MATRIX_MRCR_RCB3 (1 << 3) /* Bit 3: Remap Command Bit for AHB Master 3 */ +# define MATRIX_MRCR_RCB4 (1 << 4) /* Bit 4: Remap Command Bit for AHB Master 4 */ +#endif + +/* Write Protect Mode Register */ #define MATRIX_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ #define MATRIX_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY (Write-only) */ #define MATRIX_WPMR_WPKEY_MASK (0x00ffffff << MATRIX_WPMR_WPKEY_SHIFT) +# define MATRIX_WPMR_WPKEY (0x004d4154 << MATRIX_WPMR_WPKEY_SHIFT) + +/* Write Protect Status Register */ #define MATRIX_WPSR_WPVS (1 << 0) /* Bit 0: Enable Write Protect */ #define MATRIX_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ @@ -211,4 +270,4 @@ * Public Functions ****************************************************************************************/ -#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_MATRIX_H */ +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_MATRIX_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_memorymap.h b/nuttx/arch/arm/src/sam34/chip/sam3u_memorymap.h index 7e66c0b50..e1b9822b2 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam3u_memorymap.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_memorymap.h @@ -91,7 +91,7 @@ # define SAM_SYSCTRLR_BASE 0x400e0000 /* 0x400e0000-0x400e25ff: System controller */ /* 0x400e2600-0x400fffff: Reserved */ /* 0x40100000-0x41ffffff: Reserved */ -# define SAM_BBPERIPH__BASE 0x42000000 /* 0x42000000-0x43ffffff: 32Mb bit-band alias */ +# define SAM_BBPERIPH_BASE 0x42000000 /* 0x42000000-0x43ffffff: 32Mb bit-band alias */ /* 0x44000000-0x5fffffff: Reserved */ #define SAM_EXTSRAM_BASE 0x60000000 /* 0x60000000-0x9fffffff: External SRAM */ # define SAM_EXTCS_BASE 0x60000000 /* 0x60000000-0x63ffffff: Chip selects */ @@ -111,14 +111,14 @@ #define SAM_SMC_BASE 0x400e0000 /* 0x400e0000-0x400e01ff: Static Memory Controller */ #define SAM_MATRIX_BASE 0x400e0200 /* 0x400e0200-0x400e03ff: MATRIX */ #define SAM_PMC_BASE 0x400e0400 /* 0x400e0400-0x400e05ff: Power Management Controller */ -#define SAM_UART_BASE 0x400e0600 /* 0x400e0600-0x400e073f: UART */ +#define SAM_UART0_BASE 0x400e0600 /* 0x400e0600-0x400e073f: UART 0 */ #define SAM_CHIPID_BASE 0x400e0740 /* 0x400e0740-0x400e07ff: CHIP ID */ #define SAM_EEFC_BASE 0x400e0800 /* 0x400e0800-0x400e0bff: Enhanced Embedded Flash Controllers*/ -# define SAM_EEFCN_BASE(n) (0x400e0800+((n)<<9)) +# define SAM_EEFCN_BASE(n) (0x400e0800 + ((n) << 9)) # define SAM_EEFC0_BASE 0x400e0800 /* 0x400e0800-0x400e09ff: Enhanced Embedded Flash Controller 0 */ # define SAM_EEFC1_BASE 0x400e0a00 /* 0x400e0a00-0x400e0bff: Enhanced Embedded Flash Controller 1 */ #define SAM_PIO_BASE 0x400e0c00 /* 0x400e0c00-0x400e11ff: Parallel I/O Controllers */ -# define SAM_PION_BASE(n) (0x400e0c00+((n)<<9)) +# define SAM_PION_BASE(n) (0x400e0c00 + ((n) << 9)) # define SAM_PIOA_BASE 0x400e0c00 /* 0x400e0c00-0x400e0dff: Parallel I/O Controller A */ # define SAM_PIOB_BASE 0x400e0e00 /* 0x400e0e00-0x400e0fff: Parallel I/O Controller B */ # define SAM_PIOC_BASE 0x400e1000 /* 0x400e1000-0x400e11ff: Parallel I/O Controller C */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_pinmap.h b/nuttx/arch/arm/src/sam34/chip/sam3u_pinmap.h index fbcffbfd0..e508a3b4c 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam3u_pinmap.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_pinmap.h @@ -122,12 +122,12 @@ #define GPIO_MCI_DA (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOA|GPIO_PIN4) #define GPIO_MCI_DAT0IN (GPIO_INPUT|GPIO_CFG_PULLUP|GPIO_PORT_PIOA|GPIO_PIN5) -#define GPIO_PWMC_PWMH0 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN0) -#define GPIO_PWMC_PWML0 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN7) -#define GPIO_PWMC_PWMH1 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN1) -#define GPIO_PWMC_PWML1 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN8) -#define GPIO_PWMC_PWMH2 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN2) -#define GPIO_PWMC_PWML2 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN9) +#define GPIO_PWM0_H (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN0) +#define GPIO_PWM0_L (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN7) +#define GPIO_PWM1_H (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN1) +#define GPIO_PWM1_L (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN8) +#define GPIO_PWM2_H (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN2) +#define GPIO_PWM2_L (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN9) #define GPIO_SPI0_MISO (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN13) #define GPIO_SPI0_MOSI (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN14) @@ -149,13 +149,13 @@ #define GPIO_PCK0 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN21) -#define GPIO_TWI_TWD0 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN9) -#define GPIO_TWI_TWCK0 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN10) -#define GPIO_TWI_TWD1 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN24) -#define GPIO_TWI_TWCK1 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN25) +#define GPIO_TWI0_D (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN9) +#define GPIO_TWI0_CK (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN10) +#define GPIO_TW1I_D (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN24) +#define GPIO_TWI1_CK (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN25) -#define GPIO_UART_TXD (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN12) -#define GPIO_UART_RXD (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN11) +#define GPIO_UART0_TXD (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN12) +#define GPIO_UART0_RXD (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN11) #define GPIO_USART0_CTS (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN8) #define GPIO_USART0_DCD (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN11) diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_pio.h b/nuttx/arch/arm/src/sam34/chip/sam3u_pio.h index 14ceb0724..bc037bd5a 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam3u_pio.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_pio.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam3u_pio.h + * Parallel Input/Output (PIO) Controller definitions for the SAM3U * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -299,15 +300,15 @@ /* PIO Write Protect Mode Register */ -#define PIO_WPMR_WPEN 1 << 0) /* Bit 0: Write Protect Enable */ -#define PIO_WPMR_WPKEY_SHIFT 8) /* Bits 8-31: Write Protect KEY */ -#define PIO_WPMR_WPKEY_MASK 0xffffff << PIO_WPMR_WPKEY_SHIFT) +#define PIO_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ +#define PIO_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ +#define PIO_WPMR_WPKEY_MASK (0xffffff << PIO_WPMR_WPKEY_SHIFT) /* PIO Write Protect Status Register */ -#define PIO_WPSR_WPVS 1 << 0) /* Bit 0: Write Protect Violation Status */ -#define PIO_WPSR_WPVSRC_SHIFT 8) /* Bits 8-23: Write Protect Violation Source */ -#define PIO_WPSR_WPVSRC_MASK 0xffff << PIO_WPSR_WPVSRC_SHIFT) +#define PIO_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */ +#define PIO_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ +#define PIO_WPSR_WPVSRC_MASK (0xffff << PIO_WPSR_WPVSRC_SHIFT) /**************************************************************************************** * Public Types diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h b/nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h new file mode 100644 index 000000000..500ad5701 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h @@ -0,0 +1,478 @@ +/******************************************************************************************** + * arch/arm/src/sam34/chip/sam3u_pmc.h + * Power Management Controller (PMC) for the SAM3U and SAM4S + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PMC_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PMC_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ + +/* PMC register offsets *********************************************************************/ + +#define SAM_PMC_SCER_OFFSET 0x0000 /* System Clock Enable Register */ +#define SAM_PMC_SCDR_OFFSET 0x0004 /* System Clock Disable Register */ +#define SAM_PMC_SCSR_OFFSET 0x0008 /* System Clock Status Register */ + /* 0x000c: Reserved */ +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_PMC_PCER0_OFFSET 0x0010 /* Peripheral Clock Enable Register 0 */ +# define SAM_PMC_PCDR0_OFFSET 0x0014 /* Peripheral Clock Disable Register 0 */ +# define SAM_PMC_PCSR0_OFFSET 0x0018 /* Peripheral Clock Status Register 0 */ +#elif defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_PMC_PCER_OFFSET 0x0010 /* Peripheral Clock Enable Register */ +# define SAM_PMC_PCDR_OFFSET 0x0014 /* Peripheral Clock Disable Register */ +# define SAM_PMC_PCSR_OFFSET 0x0018 /* Peripheral Clock Status Register */ +#endif + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_PMC_CKGR_UCKR_OFFSET 0x001c /* UTMI Clock Register */ +#endif + /* 0x001c: Reserved (SAM4S)*/ +#define SAM_PMC_CKGR_MOR_OFFSET 0x0020 /* Main Oscillator Register */ +#define SAM_PMC_CKGR_MCFR_OFFSET 0x0024 /* Main Clock Frequency Register */ +#define SAM_PMC_CKGR_PLLAR_OFFSET 0x0028 /* PLLA Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_PMC_CKGR_PLLBR_OFFSET 0x002c /* PLLB Register */ +#endif + /* 0x002c: Reserved (SAM3U)*/ +#define SAM_PMC_MCKR_OFFSET 0x0030 /* Master Clock Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) + /* 0x0034 Reserved */ +# define SAM_PMC_USB_OFFSET 0x0038 /* USB Clock Register PMC_USB */ + /* 0x003c Reserved */ +#endif + /* 0x0034-0x003c Reserved (SAM3U) */ +#define SAM_PMC_PCK_OFFSET(n) (0x0040 + ((n) << 2)) +#define SAM_PMC_PCK0_OFFSET 0x0040 /* Programmable Clock 0 Register */ +#define SAM_PMC_PCK1_OFFSET 0x0044 /* Programmable Clock 1 Register */ +#define SAM_PMC_PCK2_OFFSET 0x0048 /* Programmable Clock 2 Register */ + /* 0x004c-0x005c: Reserved */ +#define SAM_PMC_IER_OFFSET 0x0060 /* Interrupt Enable Register */ +#define SAM_PMC_IDR_OFFSET 0x0064 /* Interrupt Disable Register */ +#define SAM_PMC_SR_OFFSET 0x0068 /* Status Register */ +#define SAM_PMC_IMR_OFFSET 0x006c /* Interrupt Mask Register */ +#define SAM_PMC_FSMR_OFFSET 0x0070 /* Fast Startup Mode Register */ +#define SAM_PMC_FSPR_OFFSET 0x0074 /* Fast Startup Polarity Register */ +#define SAM_PMC_FOCR_OFFSET 0x0078 /* Fault Output Clear Register */ + /* 0x007c-0x00e0: Reserved */ +#define SAM_PMC_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */ +#define SAM_PMC_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) + /* 0x00ec-0x00fc Reserved */ +# define SAM_PMC_PCER1_OFFSET 0x0100 /* Peripheral Clock Enable Register 1 */ +# define SAM_PMC_PCDR1_OFFSET 0x0104 /* Peripheral Clock Disable Register 1 */ +# define SAM_PMC_PCSR1_OFFSET 0x0108 /* Peripheral Clock Status Register 1 */ + /* 0x010c Reserved */ +# define SAM_PMC_OCR_OFFSET 0x0110 /* Oscillator Calibration Register */ + /* 0x003c Reserved */ +#endif + +/* PMC register adresses ********************************************************************/ + +#define SAM_PMC_SCER (SAM_PMC_BASE+SAM_PMC_SCER_OFFSET) +#define SAM_PMC_SCDR (SAM_PMC_BASE+SAM_PMC_SCDR_OFFSET) +#define SAM_PMC_SCSR (SAM_PMC_BASE+SAM_PMC_SCSR_OFFSET) + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_PMC_PCER0 (SAM_PMC_BASE+SAM_PMC_PCER0_OFFSET) +#elif defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_PMC_PCER (SAM_PMC_BASE+SAM_PMC_PCER_OFFSET) +#endif + +#define SAM_PMC_PCDR (SAM_PMC_BASE+SAM_PMC_PCDR_OFFSET) +#define SAM_PMC_PCSR (SAM_PMC_BASE+SAM_PMC_PCSR_OFFSET) + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_PMC_CKGR_UCKR (SAM_PMC_BASE+SAM_PMC_CKGR_UCKR_OFFSET) +#endif + +#define SAM_PMC_CKGR_MOR (SAM_PMC_BASE+SAM_PMC_CKGR_MOR_OFFSET) +#define SAM_PMC_CKGR_MCFR (SAM_PMC_BASE+SAM_PMC_CKGR_MCFR_OFFSET) +#define SAM_PMC_CKGR_PLLAR (SAM_PMC_BASE+SAM_PMC_CKGR_PLLAR_OFFSET) + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_PMC_CKGR_PLLBR (SAM_PMC_BASE+SAM_PMC_CKGR_PLLBR_OFFSET) +# define SAM_PMC_USB (SAM_PMC_BASE+SAM_PMC_USB_OFFSET) +#endif + +#define SAM_PMC_MCKR (SAM_PMC_BASE+SAM_PMC_MCKR_OFFSET) +#define SAM_PMC_PCK(n) (SAM_PMC_BASE+SAM_PMC_PCK_OFFSET(n)) +#define SAM_PMC_PCK0 (SAM_PMC_BASE+SAM_PMC_PCK0_OFFSET) +#define SAM_PMC_PCK1 (SAM_PMC_BASE+SAM_PMC_PCK1_OFFSET) +#define SAM_PMC_PCK2 (SAM_PMC_BASE+SAM_PMC_PCK2_OFFSET) +#define SAM_PMC_IER (SAM_PMC_BASE+SAM_PMC_IER_OFFSET) +#define SAM_PMC_IDR (SAM_PMC_BASE+SAM_PMC_IDR_OFFSET) +#define SAM_PMC_SR (SAM_PMC_BASE+SAM_PMC_SR_OFFSET) +#define SAM_PMC_IMR (SAM_PMC_BASE+SAM_PMC_IMR_OFFSET) +#define SAM_PMC_FSMR (SAM_PMC_BASE+SAM_PMC_FSMR_OFFSET) +#define SAM_PMC_FSPR (SAM_PMC_BASE+SAM_PMC_FSPR_OFFSET) +#define SAM_PMC_FOCR (SAM_PMC_BASE+SAM_PMC_FOCR_OFFSET) +#define SAM_PMC_WPMR (SAM_PMC_BASE+SAM_PMC_WPMR_OFFSET) +#define SAM_PMC_WPSR (SAM_PMC_BASE+SAM_PMC_WPSR_OFFSET) + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_PMC_PCER1 (SAM_PMC_BASE+SAM_PMC_PCER1_OFFSET) +# define SAM_PMC_PCDR1 (SAM_PMC_BASE+SAM_PMC_PCDR1_OFFSET) +# define SAM_PMC_PCSR1 (SAM_PMC_BASE+SAM_PMC_PCSR1_OFFSET) +# define SAM_PMC_OCR (SAM_PMC_BASE+SAM_PMC_OCR_OFFSET) +#endif + +/* PMC register bit definitions *************************************************************/ + +/* PMC System Clock Enable Register, PMC System Clock Disable Register, and PMC System + * Clock Status Register common bit-field definitions + */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_UDP (1 << 7) /* Bit 7: USB Device Port Clock Enable */ +#endif + +#define PMC_PCK(n) (1 << ((n) + 8) +#define PMC_PCK0 (1 << 8) /* Bit 8: Programmable Clock 0 Output Enable */ +#define PMC_PCK1 (1 << 9) /* Bit 9: Programmable Clock 1 Output Enable */ +#define PMC_PCK2 (1 << 10) /* Bit 10: Programmable Clock 2 Output Enable */ + +/* PMC Peripheral Clock Enable Register, PMC Peripheral Clock Disable Register, and PMC + * Peripheral Clock Status Register common bit-field definitions. + */ + +#define PMC_PIDL(n) (1 << (n)) +#define PMC_PID2 (1 << 2) /* Bit 2: Peripheral Clock 2 Enable */ +#define PMC_PID3 (1 << 3) /* Bit 3: Peripheral Clock 3 Enable */ +#define PMC_PID4 (1 << 4) /* Bit 4: Peripheral Clock 4 Enable */ +#define PMC_PID5 (1 << 5) /* Bit 5: Peripheral Clock 5 Enable */ +#define PMC_PID6 (1 << 6) /* Bit 6: Peripheral Clock 6 Enable */ +#define PMC_PID7 (1 << 7) /* Bit 7: Peripheral Clock 7 Enable */ +#define PMC_PID8 (1 << 8) /* Bit 8: Peripheral Clock 8 Enable */ +#define PMC_PID9 (1 << 9) /* Bit 9: Peripheral Clock 9 Enable */ +#define PMC_PID10 (1 << 10) /* Bit 10: Peripheral Clock 10 Enable */ +#define PMC_PID11 (1 << 11) /* Bit 11: Peripheral Clock 11 Enable */ +#define PMC_PID12 (1 << 12) /* Bit 12: Peripheral Clock 12 Enable */ +#define PMC_PID13 (1 << 13) /* Bit 13: Peripheral Clock 13 Enable */ +#define PMC_PID14 (1 << 14) /* Bit 14: Peripheral Clock 14 Enable */ +#define PMC_PID15 (1 << 15) /* Bit 15: Peripheral Clock 15 Enable */ +#define PMC_PID16 (1 << 16) /* Bit 16: Peripheral Clock 16 Enable */ +#define PMC_PID17 (1 << 17) /* Bit 17: Peripheral Clock 17 Enable */ +#define PMC_PID18 (1 << 18) /* Bit 18: Peripheral Clock 18 Enable */ +#define PMC_PID19 (1 << 19) /* Bit 19: Peripheral Clock 19 Enable */ +#define PMC_PID20 (1 << 20) /* Bit 20: Peripheral Clock 20 Enable */ +#define PMC_PID21 (1 << 21) /* Bit 21: Peripheral Clock 21 Enable */ +#define PMC_PID22 (1 << 22) /* Bit 22: Peripheral Clock 22 Enable */ +#define PMC_PID23 (1 << 23) /* Bit 23: Peripheral Clock 23 Enable */ +#define PMC_PID24 (1 << 24) /* Bit 24: Peripheral Clock 24 Enable */ +#define PMC_PID25 (1 << 25) /* Bit 25: Peripheral Clock 25 Enable */ +#define PMC_PID26 (1 << 26) /* Bit 26: Peripheral Clock 26 Enable */ +#define PMC_PID27 (1 << 27) /* Bit 27: Peripheral Clock 27 Enable */ +#define PMC_PID28 (1 << 28) /* Bit 28: Peripheral Clock 28 Enable */ +#define PMC_PID29 (1 << 29) /* Bit 29: Peripheral Clock 29 Enable */ +#define PMC_PID30 (1 << 30) /* Bit 30: Peripheral Clock 30 Enable */ +#define PMC_PID31 (1 << 31) /* Bit 31: Peripheral Clock 31 Enable */ + +/* PMC UTMI Clock Configuration Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define PMC_CKGR_UCKR_UPLLEN (1 << 16) /* Bit 16: UTMI PLL Enable */ +# define PMC_CKGR_UCKR_UPLLCOUNT_SHIFT (20) /* Bits 20-23: UTMI PLL Start-up Time */ +# define PMC_CKGR_UCKR_UPLLCOUNT_MASK (15 << PMC_CKGR_UCKR_UPLLCOUNT_SHIFT) +#endif + +/* PMC Clock Generator Main Oscillator Register */ + +#define PMC_CKGR_MOR_MOSCXTEN (1 << 0) /* Bit 0: Main Crystal Oscillator Enable */ +#define PMC_CKGR_MOR_MOSCXTBY (1 << 1) /* Bit 1: Main Crystal Oscillator Bypass */ +#define PMC_CKGR_MOR_WAITMODE (1 << 2) /* Bit 2: Wait Mode Command */ +#define PMC_CKGR_MOR_MOSCRCEN (1 << 3) /* Bit 3: Main On-Chip RC Oscillator Enable */ +#define PMC_CKGR_MOR_MOSCRCF_SHIFT (4) /* Bits 4-6: Main On-Chip RC Oscillator Frequency Selection */ +#define PMC_CKGR_MOR_MOSCRCF_MASK (7 << PMC_CKGR_MOR_MOSCRCF_SHIFT) +# define PMC_CKGR_MOR_MOSCRCF_4MHz (0 << PMC_CKGR_MOR_MOSCRCF_SHIFT) /* Fast RC Osc is 4MHz (default) */ +# define PMC_CKGR_MOR_MOSCRCF_8MHz (1 << PMC_CKGR_MOR_MOSCRCF_SHIFT) /* Fast RC Osc is 8MHz */ +# define PMC_CKGR_MOR_MOSCRCF_12MHz (2 << PMC_CKGR_MOR_MOSCRCF_SHIFT) /* Fast RC Osc is 12MHz */ +#define PMC_CKGR_MOR_MOSCXTST_SHIFT (8) /* Bits 8-16: Main Crystal Oscillator Start-up Time */ +#define PMC_CKGR_MOR_MOSCXTST_MASK (0x1ff << PMC_CKGR_MOR_MOSCXTST_SHIFT) +#define PMC_CKGR_MOR_KEY_SHIFT (16) /* Bits 16-23: Password */ +#define PMC_CKGR_MOR_KEY_MASK (0xff << PMC_CKGR_MOR_KEY_SHIFT) +# define PMC_CKGR_MOR_KEY (0x37 << PMC_CKGR_MOR_KEY_SHIFT) +#define PMC_CKGR_MOR_MOSCSEL (1 << 24) /* Bit 24: Main Oscillator Selection */ +#define PMC_CKGR_MOR_CFDEN (1 << 25) /* Bit 25: Clock Failure Detector Enable */ + +/* PMC Clock Generator Main Clock Frequency Register */ + +#define PMC_CKGR_MCFR_MAINF_SHIFT (0) /* Bits 0-15: Main Clock Frequency */ +#define PMC_CKGR_MCFR_MAINF_MASK (0xffff << PMC_CKGR_MCFR_MAINF_SHIFT) +#define PMC_CKGR_MCFR_MAINFRDY (1 << 16) /* Bit 16: Main Clock Ready */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_CKGR_MCFR_RCMEAS (1 << 20) /* Bit 20: RC Oscillator Frequency Measure (write-only) */ +#endif + +/* PMC Clock Generator PLLA Register */ + +#define PMC_CKGR_PLLAR_DIV_SHIFT (0) /* Bits 0-7: Divider */ +#define PMC_CKGR_PLLAR_DIV_MASK (0xff << PMC_CKGR_PLLAR_DIV_SHIFT) +# define PMC_CKGR_PLLAR_DIV_ZERO (0 << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider output is 0 */ +# define PMC_CKGR_PLLAR_DIV_BYPASS (1 << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider is bypassed (DIV=1) */ +# define PMC_CKGR_PLLAR_DIV(n) ((n) << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider output is DIV=n, n=2..255 */ + +#define PMC_CKGR_PLLAR_COUNT_SHIFT (8) /* Bits 8-13: PLLA Counter */ +#define PMC_CKGR_PLLAR_COUNT_MASK (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define PMC_CKGR_PLLAR_STMODE_SHIFT (14) /* Bits 14-15: Start Mode */ +# define PMC_CKGR_PLLAR_STMODE_MASK (3 << PMC_CKGR_PLLAR_STMODE_SHIFT) +# define PMC_CKGR_PLLAR_STMODE_FAST (0 << PMC_CKGR_PLLAR_STMODE_SHIFT) /* Fast Startup */ +# define PMC_CKGR_PLLAR_STMODE_NORMAL (2 << PMC_CKGR_PLLAR_STMODE_SHIFT) /* Normal Startup */ +#endif + +#define PMC_CKGR_PLLAR_MUL_SHIFT (16) /* Bits 16-26: PLLA Multiplier */ +#define PMC_CKGR_PLLAR_MUL_MASK (0x7ff << PMC_CKGR_PLLAR_MUL_SHIFT) +#define PMC_CKGR_PLLAR_ONE (1 << 29) /* Bit 29: Always one */ + +/* PLLB Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_CKGR_PLLBR_DIV_SHIFT (0) /* Bits 0-7: Divider */ +# define PMC_CKGR_PLLBR_DIV_MASK (0xff << PMC_CKGR_PLLBR_DIV_SHIFT) +# define PMC_CKGR_PLLBR_DIV_ZERO (0 << PMC_CKGR_PLLBR_DIV_SHIFT) /* Divider output is 0 */ +# define PMC_CKGR_PLLBR_DIV_BYPASS (1 << PMC_CKGR_PLLBR_DIV_SHIFT) /* Divider is bypassed (DIV=1) */ +# define PMC_CKGR_PLLBR_DIV(n) ((n) << PMC_CKGR_PLLBR_DIV_SHIFT) /* Divider output is DIV=n, n=2..255 */ +# define PMC_CKGR_PLLBR_COUNT_SHIFT (8) /* Bits 8-13: PLLA Counter */ +# define PMC_CKGR_PLLBR_COUNT_MASK (63 << PMC_CKGR_PLLBR_COUNT_SHIFT) +# define PMC_CKGR_PLLBR_MUL_SHIFT (16) /* Bits 16-26: PLLA Multiplier */ +# define PMC_CKGR_PLLBR_MUL_MASK (0x7ff << PMC_CKGR_PLLBR_MUL_SHIFT) +#endif + +/* USB Clock Register PMC_USB */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_USB_USBS (1 << 0) /* Bit 0: USB Input Clock Selection */ +# define PMC_USB_USBS_PLLA (0) +# define PMC_USB_USBS_PLLB PMC_USB_USBS +# define PMC_USB_USBDIV_SHIFT (8) /* Bits 8-11: Divider for USB Clock */ +# define PMC_USB_USBDIV_MASK (15 << PMC_USB_USBDIV_SHIFT) +#endif + +/* PMC Master Clock Register */ + +#define PMC_MCKR_CSS_SHIFT (0) /* Bits 0-1: Master Clock Source Selection */ +#define PMC_MCKR_CSS_MASK (3 << PMC_MCKR_CSS_SHIFT) +# define PMC_MCKR_CSS_SLOW (0 << PMC_MCKR_CSS_SHIFT) /* Slow Clock */ +# define PMC_MCKR_CSS_MAIN (1 << PMC_MCKR_CSS_SHIFT) /* Main Clock */ +# define PMC_MCKR_CSS_PLLA (2 << PMC_MCKR_CSS_SHIFT) /* PLLA Clock */ + +# if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_MCKR_CSS_PLLB (3 << PMC_MCKR_CSS_SHIFT) /* PLLB Clock */ +# elif defined(CONFIG_ARCH_CHIP_SAM3U) +# define PMC_MCKR_CSS_UPLL (3 << PMC_MCKR_CSS_SHIFT) /* UPLL Clock */ +# endif + +#define PMC_MCKR_PRES_SHIFT (4) /* Bits 4-6: Processor Clock Prescaler */ +#define PMC_MCKR_PRES_MASK (7 << PMC_MCKR_PRES_SHIFT) +# define PMC_MCKR_PRES_DIV1 (0 << PMC_MCKR_PRES_SHIFT) /* Selected clock */ +# define PMC_MCKR_PRES_DIV2 (1 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 2 */ +# define PMC_MCKR_PRES_DIV4 (2 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 4 */ +# define PMC_MCKR_PRES_DIV8 (3 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 8 */ +# define PMC_MCKR_PRES_DIV16 (4 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 16 */ +# define PMC_MCKR_PRES_DIV32 (5 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 32 */ +# define PMC_MCKR_PRES_DIV64 (6 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 64 */ +# define PMC_MCKR_PRES_DIV3 (7 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 3 */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_MCKR_PLLADIV2 (1 << 13) /* Bit 13: PLLA Divider */ +# define PMC_MCKR_PLLBDIV2 (1 << 14) /* Bit 14: PLLB Divider */ +#elif defined(CONFIG_ARCH_CHIP_SAM3U) +# define PMC_MCKR_UPLLDIV (1 << 13) /* Bit 13: UPLL Divider */ +#endif + +/* PMC Programmable Clock Register (0,1,2) */ + +#define PMC_PCK_CSS_SHIFT (0) /* Bits 0-2: Master Clock Source Selection */ +#define PMC_PCK_CSS_MASK (7 << PMC_PCK_CSS_MASK) +# define PMC_PCK_CSS_SLOW (0 << PMC_PCK_CSS_MASK) /* Slow Clock */ +# define PMC_PCK_CSS_MAIN (1 << PMC_PCK_CSS_MASK) /* Main Clock */ +# define PMC_PCK_CSS_PLLA (2 << PMC_PCK_CSS_MASK) /* PLLA Clock */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_PCK_CSS_PLLB (3 << PMC_PCK_CSS_MASK) /* PLLB Clock */ +#elif defined(CONFIG_ARCH_CHIP_SAM3U) +# define PMC_PCK_CSS_UPLL (3 << PMC_PCK_CSS_MASK) /* UPLL Clock */ +#endif + +# define PMC_PCK_CSS_MCK (4 << PMC_PCK_CSS_MASK) /* Master Clock */ + +#define PMC_PCK_PRES_SHIFT (4) /* Bits 4-6: Programmable Clock Prescaler */ +#define PMC_PCK_PRES_MASK (7 << PMC_PCK_PRES_SHIFT) +# define PMC_PCK_PRES_DIV1 (0 << PMC_PCK_PRES_SHIFT) /* Selected clock */ +# define PMC_PCK_PRES_DIV2 (1 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 2 */ +# define PMC_PCK_PRES_DIV4 (2 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 4 */ +# define PMC_PCK_PRES_DIV8 (3 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 8 */ +# define PMC_PCK_PRES_DIV16 (4 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 16 */ +# define PMC_PCK_PRES_DIV32 (5 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 32 */ +# define PMC_PCK_PRES_DIV64 (6 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 64 */ + +/* PMC Interrupt Enable Register, PMC Interrupt Disable Register, PMC Status Register, + * and PMC Interrupt Mask Register common bit-field definitions + */ + +#define PMC_INT_MOSCXTS (1 << 0) /* Bit 0: Main Crystal Oscillator Status Interrupt */ +#define PMC_INT_LOCKA (1 << 1) /* Bit 1: PLL A Lock Interrupt */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_INT_LOCKB (1 << 2) /* Bit 2: PLL B Lock Interrupt */ +#endif + +#define PMC_INT_MCKRDY (1 << 3) /* Bit 3: Master Clock Ready Interrupt */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define PMC_INT_LOCKU (1 << 6) /* Bit 6: UTMI PLL Lock Interrupt */ +#endif + +#define PMC_SR_OSCSELS (1 << 7) /* Bit 7: Slow Clock Oscillator Selection (SR only) */ +#define PMC_INT_PCKRDY(n) (1 << ((n)+8) +#define PMC_INT_PCKRDY0 (1 << 8) /* Bit 8: Programmable Clock Ready 0 Interrupt */ +#define PMC_INT_PCKRDY1 (1 << 9) /* Bit 9: Programmable Clock Ready 1 Interrupt */ +#define PMC_INT_PCKRDY2 (1 << 10) /* Bit 10: Programmable Clock Ready 2 Interrupt */ +#define PMC_INT_MOSCSELS (1 << 16) /* Bit 16: Main Oscillator Selection Status Interrupt */ +#define PMC_INT_MOSCRCS (1 << 17) /* Bit 17: Main On-Chip RC Status Interrupt */ +#define PMC_INT_CFDEV (1 << 18) /* Bit 18: Clock Failure Detector Event Interrupt */ +#define PMC_SR_CFDS (1 << 19) /* Bit 19: Clock Failure Detector Status (SR only) */ +#define PMC_SR_FOS (1 << 20) /* Bit 20: Clock Failure Detector Fault Output Status (SR only) */ + +/* PMC Fast Startup Mode Register and PMC Fast Startup Polarity Register common bit-field + * definitions + */ + +#define PMC_FSTI(n) (1 << (n)) +#define PMC_FSTI0 (1 << 0) /* Bit 0: Fast Startup Input 0 */ +#define PMC_FSTI1 (1 << 1) /* Bit 1: Fast Startup Input 1 */ +#define PMC_FSTI2 (1 << 2) /* Bit 2: Fast Startup Input 2 */ +#define PMC_FSTI3 (1 << 3) /* Bit 3: Fast Startup Input 3 */ +#define PMC_FSTI4 (1 << 4) /* Bit 4: Fast Startup Input 4 */ +#define PMC_FSTI5 (1 << 5) /* Bit 5: Fast Startup Input 5 */ +#define PMC_FSTI6 (1 << 6) /* Bit 6: Fast Startup Input 6 */ +#define PMC_FSTI7 (1 << 7) /* Bit 7: Fast Startup Input 7 */ +#define PMC_FSTI8 (1 << 8) /* Bit 8: Fast Startup Input 8 */ +#define PMC_FSTI9 (1 << 9) /* Bit 9: Fast Startup Input 9 */ +#define PMC_FSTI10 (1 << 10) /* Bit 10: Fast Startup Input 10 */ +#define PMC_FSTI11 (1 << 11) /* Bit 11: Fast Startup Input 11 */ +#define PMC_FSTI12 (1 << 12) /* Bit 12: Fast Startup Input 12 */ +#define PMC_FSTI13 (1 << 13) /* Bit 13: Fast Startup Input 13 */ +#define PMC_FSTI14 (1 << 14) /* Bit 14: Fast Startup Input 14 */ +#define PMC_FSTI15 (1 << 15) /* Bit 15: Fast Startup Input 15 */ +#define PMC_FSMR_RTTAL (1 << 16) /* Bit 16: RTT Alarm Enable (MR only) */ +#define PMC_FSMR_RTCAL (1 << 17) /* Bit 17: RTC Alarm Enable (MR only) */ +#define PMC_FSMR_USBAL (1 << 18) /* Bit 18: USB Alarm Enable (MR only) */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define PMC_FSMR_LPM (1 << 20) /* Bit 20: Low Power Mode (MR only) */ +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_FSMR_FLPM_SHIFT (21) /* Bit 21-22: Low Power Mode (MR only) */ +# define PMC_FSMR_FLPM_MASK (3 << PMC_FSMR_FLPM_SHIFT) +# define PMC_FSMR_FLPM_PWRDOWN (0 << PMC_FSMR_FLPM_SHIFT) /* Flash Standby Mode */ +# define PMC_FSMR_FLPM_STANDBY (1 << PMC_FSMR_FLPM_SHIFT) /* Flash deep power down mode */ +# define PMC_FSMR_FLPM_IDLE (2 << PMC_FSMR_FLPM_SHIFT) /* Idle mode */ +#endif + +/* Fast Startup Polarity Register */ + +#define PMC_FSTP(n) (1 << (n)) /* Fast Startup Input Polarityn, n=0..15 */ + +/* PMC Fault Output Clear Register */ + +#define PMC_FOCLR (1 << 0) /* Bit 0: Fault Output Clear */ + +/* PMC Write Protect Mode Register */ + +#define PMC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ +#define PMC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ +#define PMC_WPMR_WPKEY_MASK (0x00ffffff << PMC_WPMR_WPKEY_SHIFT) +# define PMC_WPMR_WPKEY (0x00504d43 << PMC_WPMR_WPKEY_SHIFT) + +/* PMC Write Protect Status Register */ + +#define PMC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */ +#define PMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ +#define PMC_WPSR_WPVSRC_MASK (0xffff << PMC_WPSR_WPVSRC_SHIFT) + +/* Peripheral Clock Enable Register 1 */ +/* Peripheral Clock Disable Register 1 */ +/* Peripheral Clock Status Register 1 */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_PIDH(n) (1 << ((n) - 32)) +# define PMC_PID32 (1 << 0) /* Bit 0: PID32 */ +# define PMC_PID33 (1 << 1) /* Bit 1: PID33 */ +# define PMC_PID34 (1 << 2) /* Bit 2: PID34 */ +#endif + +/* Oscillator Calibration Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_OCR_CAL4_SHIFT (0) /* Bits 0-6: 4MHzRC Oscillator Calibration */ +# define PMC_OCR_CAL4_MASK (0x7f << PMC_OCR_CAL4_SHIFT) +# define PMC_OCR_SEL4 (1 << 7) /* Bit 7: Select 4MHz RC Oscillator Calibration */ +# define PMC_OCR_CAL8_SHIFT (8) /* Bits 8-14: 8MHzRC Oscillator Calibration */ +# define PMC_OCR_CAL8_MASK (0x7f << PMC_OCR_CAL8_SHIFT) +# define PMC_OCR_SEL8 (1 << 15) /* Bit 15: Select 8MHz RC Oscillator Calibration */ +# define PMC_OCR_CAL12_SHIFT (16) /* Bits 16-22: 12MHzRC Oscillator Calibration */ +# define PMC_OCR_CAL12_MASK (0x7f << PMC_OCR_CAL12_SHIFT) +# define PMC_OCR_SEL12 (1 << 23) /* Bit 23: Select 12MHz RC Oscillator Calibration */ +#endif + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +/******************************************************************************************** + * Public Data + ********************************************************************************************/ + +/******************************************************************************************** + * Public Functions + ********************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PMC_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_supc.h b/nuttx/arch/arm/src/sam34/chip/sam3u_supc.h index 88f9452d8..aea757717 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam3u_supc.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_supc.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam3u_supc.h + * Supply Controller (SUPC) definitions for the SAM3U and SAM4S * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -51,93 +52,159 @@ /* SUPC register offsets ****************************************************************/ -#define SAM_SUPC_CR_OFFSET 0x00 /* Supply Controller Control Register */ -#define SAM_SUPC_SMMR_OFFSET 0x04 /* Supply Controller Supply Monitor Mode Register */ -#define SAM_SUPC_MR_OFFSET 0x08 /* Supply Controller Mode Register */ -#define SAM_SUPC_WUMR_OFFSET 0x0c /* Supply Controller Wake Up Mode Register */ -#define SAM_SUPC_WUIR_OFFSET 0x10 /* Supply Controller Wake Up Inputs Register */ -#define SAM_SUPC_SR_OFFSET 0x14 /* Supply Controller Status Register */ +#define SAM_SUPC_CR_OFFSET 0x00 /* Supply Controller Control Register */ +#define SAM_SUPC_SMMR_OFFSET 0x04 /* Supply Controller Supply Monitor Mode Register */ +#define SAM_SUPC_MR_OFFSET 0x08 /* Supply Controller Mode Register */ +#define SAM_SUPC_WUMR_OFFSET 0x0c /* Supply Controller Wake Up Mode Register */ +#define SAM_SUPC_WUIR_OFFSET 0x10 /* Supply Controller Wake Up Inputs Register */ +#define SAM_SUPC_SR_OFFSET 0x14 /* Supply Controller Status Register */ /* SUPC register adresses ***************************************************************/ -#define SAM_SUPC_CR (SAM_SUPC_BASE+SAM_SUPC_CR_OFFSET) -#define SAM_SUPC_SMMR (SAM_SUPC_BASE+SAM_SUPC_SMMR_OFFSET) -#define SAM_SUPC_MR (SAM_SUPC_BASE+SAM_SUPC_MR_OFFSET) -#define SAM_SUPC_WUMR (SAM_SUPC_BASE+SAM_SUPC_WUMR_OFFSET) -#define SAM_SUPC_WUIR (SAM_SUPC_BASE+SAM_SUPC_WUIR_OFFSET) -#define SAM_SUPC_SR (SAM_SUPC_BASE+SAM_SUPC_SR_OFFSET) +#define SAM_SUPC_CR (SAM_SUPC_BASE+SAM_SUPC_CR_OFFSET) +#define SAM_SUPC_SMMR (SAM_SUPC_BASE+SAM_SUPC_SMMR_OFFSET) +#define SAM_SUPC_MR (SAM_SUPC_BASE+SAM_SUPC_MR_OFFSET) +#define SAM_SUPC_WUMR (SAM_SUPC_BASE+SAM_SUPC_WUMR_OFFSET) +#define SAM_SUPC_WUIR (SAM_SUPC_BASE+SAM_SUPC_WUIR_OFFSET) +#define SAM_SUPC_SR (SAM_SUPC_BASE+SAM_SUPC_SR_OFFSET) /* SUPC register bit definitions ********************************************************/ +/* Supply Controller Control Register */ + +#define SUPC_CR_VROFF (1 << 2) /* Bit 2: Voltage Regulator Off */ +#define SUPC_CR_XTALSEL (1 << 3) /* Bit 3: Crystal Oscillator Select */ +#define SUPC_CR_KEY_SHIFT (24) /* Bits 24-31: Password */ +#define SUPC_CR_KEY_MASK (0xff << SUPC_CR_KEY_SHIFT) +# define SUPR_CR_KEY (0xa5 << SUPC_CR_KEY_SHIFT) + +/* Supply Controller Supply Monitor Mode Register */ + +#define SUPC_SMMR_SMTH_SHIFT (0) /* Bits 0-3: Supply Monitor Threshold */ +#define SUPC_SMMR_SMTH_MASK (15 << SUPC_SMMR_SMTH_SHIFT) + +# if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SUPC_SMMR_SMTH_1p6V (0 << SUPC_SMMR_SMTH_SHIFT) /* 1.56 < 1.6 < 1.64 */ +# define SUPC_SMMR_SMTH_1p7V (1 << SUPC_SMMR_SMTH_SHIFT) /* 1.68 < 1.72 < 1.76 */ +# define SUPC_SMMR_SMTH_1p8V (2 << SUPC_SMMR_SMTH_SHIFT) /* 1.79 < 1.84 < 1.89 */ +# define SUPC_SMMR_SMTH_2p0V (3 << SUPC_SMMR_SMTH_SHIFT) /* 1.91 < 1.96 < 2.01 */ +# define SUPC_SMMR_SMTH_2p1V (4 << SUPC_SMMR_SMTH_SHIFT) /* 2.03 < 2.08 < 2.13 */ +# define SUPC_SMMR_SMTH_2p2V (5 << SUPC_SMMR_SMTH_SHIFT) /* 2.15 < 2.2 < 2.23 */ +# define SUPC_SMMR_SMTH_2p3V (6 << SUPC_SMMR_SMTH_SHIFT) /* 2.26 < 2.32 < 2.38 */ +# define SUPC_SMMR_SMTH_2p4V (7 << SUPC_SMMR_SMTH_SHIFT) /* 2.38 < 2.44 < 2.50 */ +# define SUPC_SMMR_SMTH_2p6V (8 << SUPC_SMMR_SMTH_SHIFT) /* 2.50 < 2.56 < 2.62 */ +# define SUPC_SMMR_SMTH_2p7V (9 << SUPC_SMMR_SMTH_SHIFT) /* 2.61 < 2.68 < 2.75 */ +# define SUPC_SMMR_SMTH_2p8V (10 << SUPC_SMMR_SMTH_SHIFT) /* 2.73 < 2.8 < 2.87 */ +# define SUPC_SMMR_SMTH_2p9V (11 << SUPC_SMMR_SMTH_SHIFT) /* 2.85 < 2.92 < 2.99 */ +# define SUPC_SMMR_SMTH_3p0V (12 << SUPC_SMMR_SMTH_SHIFT) /* 2.96 < 3.04 < 3.12 */ +# define SUPC_SMMR_SMTH_3p2V (13 << SUPC_SMMR_SMTH_SHIFT) /* 3.08 < 3.16 < 3.24 */ +# define SUPC_SMMR_SMTH_3p3V (14 << SUPC_SMMR_SMTH_SHIFT) /* 3.20 < 3.28 < 3.36 */ +# define SUPC_SMMR_SMTH_3p4V (15 << SUPC_SMMR_SMTH_SHIFT) /* 3.32 < 3.4 < 3.49 */ +# elif defined(CONFIG_ARCH_CHIP_SAM3U) +# define SUPC_SMMR_SMTH_1p9V (0 << SUPC_SMMR_SMTH_SHIFT) /* 1.9V */ +# define SUPC_SMMR_SMTH_2p0V (1 << SUPC_SMMR_SMTH_SHIFT) /* 2.0V */ +# define SUPC_SMMR_SMTH_2p1V (2 << SUPC_SMMR_SMTH_SHIFT) /* 2.1V */ +# define SUPC_SMMR_SMTH_2p2V (3 << SUPC_SMMR_SMTH_SHIFT) /* 2.2V */ +# define SUPC_SMMR_SMTH_2p3V (4 << SUPC_SMMR_SMTH_SHIFT) /* 2.3V */ +# define SUPC_SMMR_SMTH_2p4V (5 << SUPC_SMMR_SMTH_SHIFT) /* 2.4V */ +# define SUPC_SMMR_SMTH_2p5V (6 << SUPC_SMMR_SMTH_SHIFT) /* 2.5V */ +# define SUPC_SMMR_SMTH_2p6V (7 << SUPC_SMMR_SMTH_SHIFT) /* 2.6V */ +# define SUPC_SMMR_SMTH_2p7V (8 << SUPC_SMMR_SMTH_SHIFT) /* 2.7V */ +# define SUPC_SMMR_SMTH_2p8V (9 << SUPC_SMMR_SMTH_SHIFT) /* 2.8V */ +# define SUPC_SMMR_SMTH_2p9V (10 << SUPC_SMMR_SMTH_SHIFT) /* 2.9V */ +# define SUPC_SMMR_SMTH_3p0V (11 << SUPC_SMMR_SMTH_SHIFT) /* 3.0V */ +# define SUPC_SMMR_SMTH_3p1V (12 << SUPC_SMMR_SMTH_SHIFT) /* 3.1V */ +# define SUPC_SMMR_SMTH_3p2V (13 << SUPC_SMMR_SMTH_SHIFT) /* 3.2V */ +# define SUPC_SMMR_SMTH_3p3V (14 << SUPC_SMMR_SMTH_SHIFT) /* 3.3V */ +# define SUPC_SMMR_SMTH_3p4V (15 << SUPC_SMMR_SMTH_SHIFT) /* 3.4V */ +#endif + +#define SUPC_SMMR_SMSMPL_SHIFT (8) /* Bits 8-10: Supply Monitor Sampling Period */ +#define SUPC_SMMR_SMSMPL_MASK (7 << SUPC_SMMR_SMSMPL_SHIFT) +# define SUPC_SMMR_SMSMPL_SMD (0 << SUPC_SMMR_SMSMPL_SHIFT) /* Supply Monitor disabled */ +# define SUPC_SMMR_SMSMPL_CSM (1 << SUPC_SMMR_SMSMPL_SHIFT) /* Continuous Supply Monitor */ +# define SUPC_SMMR_SMSMPL_32SLCK (2 << SUPC_SMMR_SMSMPL_SHIFT) /* Eevery 32 SLCK periods */ +# define SUPC_SMMR_SMSMPL_256SLCK (3 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 256 SLCK periods */ +# define SUPC_SMMR_SMSMPL_2048SLCK (4 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 2,048 SLCK periods */ +#define SUPC_SMMR_SMRSTEN (1 << 12) /* Bit 12: Supply Monitor Reset Enable */ +#define SUPC_SMMR_SMIEN (1 << 13) /* Bit 13: Supply Monitor Interrupt Enable */ + +/* Supply Controller Mode Register */ + +#define SUPC_MR_BODRSTEN (1 << 12) /* Bit 12: Brownout Detector Reset Enable */ +#define SUPC_MR_BODDIS (1 << 13) /* Bit 13: Brownout Detector Disable */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SUPC_MR_ONREG (1 << 14) /* Bit 14: Voltage Regulator enable */ +#elif defined(CONFIG_ARCH_CHIP_SAM3U) +# define SUPC_MR_VDDIORDY (1 << 14) /* Bit 14: VDDIO Ready */ +#endif + +#define SUPC_MR_OSCBYPASS (1 << 20) /* Bit 20: Oscillator Bypass */ +#define SUPC_MR_KEY_SHIFT (24) /* Bits 24-31: Password Key */ +#define SUPC_MR_KEY_MASK (0xff << SUPC_MR_KEY_SHIFT) + +/* Supply Controller Wake Up Mode Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SUPC_WUMR_FWUPEN (1 << 0) /* Bit 0: Force Wake Up Enable */ +#endif + +#define SUPC_WUMR_SMEN (1 << 1) /* Bit 1: Supply Monitor Wake Up Enable */ +#define SUPC_WUMR_RTTEN (1 << 2) /* Bit 2: Real Time Timer Wake Up Enable */ +#define SUPC_WUMR_RTCEN (1 << 3) /* Bit 3: Real Time Clock Wake Up Enable */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SUPC_WUMR_LPDBCEN0 (1 << 5) /* Bit 5: Low power Debouncer ENable WKUP0 */ +# define SUPC_WUMR_LPDBCEN1 (1 << 6) /* Bit 6: Low power Debouncer ENable WKUP1 */ +# define SUPC_WUMR_LPDBCCLR (1 << 7) /* Bit 7: Low power Debouncer Clear */ +#elif defined(CONFIG_ARCH_CHIP_SAM3U) +# define SUPC_WUMR_FWUPDBC_SHIFT (8) /* Bits 8-10: Force Wake Up Debouncer */ +# define SUPC_WUMR_FWUPDBC_MASK (7 << SUPC_WUMR_FWUPDBC_SHIFT) +# define SUPC_WUMR_FWUPDBC_1SCLK (0 << SUPC_WUMR_FWUPDBC_SHIFT) /* Immediate, no debouncing */ +# define SUPC_WUMR_FWUPDBC_3SCLK (1 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 3 SLCK periods */ +# define SUPC_WUMR_FWUPDBC_32SCLK (2 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32 SLCK periods */ +# define SUPC_WUMR_FWUPDBC_512SCLK (3 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 512 SLCK periods */ +# define SUPC_WUMR_FWUPDBC_4096SCLK (4 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 4096 SLCK periods */ +# define SUPC_WUMR_FWUPDBC_32768SCLK (5 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32768 SLCK periods */ +#endif + +#define SUPC_WUMR_WKUPDBC_SHIFT (12) /* Bits 12-14: Wake Up Inputs Debouncer */ +#define SUPC_WUMR_WKUPDBC_MASK (7 << SUPC_WUMR_WKUPDBC_SHIFT) +# define SUPC_WUMR_WKUPDBC_1SCLK (0 << SUPC_WUMR_WKUPDBC_SHIFT) /* Immediate, no debouncing */ +# define SUPC_WUMR_WKUPDBC_3SCLK (1 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 3 SLCK periods */ +# define SUPC_WUMR_WKUPDBC_32SCLK (2 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32 SLCK periods */ +# define SUPC_WUMR_WKUPDBC_512SCLK (3 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 512 SLCK periods */ +# define SUPC_WUMR_WKUPDBC_4096SCLK (4 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 4096 SLCK periods */ +# define SUPC_WUMR_WKUPDBC_32768SCLK (5 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32768 SLCK periods */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SUPC_WUMR_LPDBC_SHIFT (16) /* Bits 16-18: Low Power Debouncer Period */ +# define SUPC_WUMR_LPDBC_MASK (7 << SUPC_WUMR_LPDBC_SHIFT) +# define SUPC_WUMR_LPDBC_DISABLE (0 << SUPC_WUMR_LPDBC_SHIFT) /* Disable low power debouncer */ +# define SUPC_WUMR_LPDBC_2_RTCOUT0 (1 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 2 RTCOUT0 */ +# define SUPC_WUMR_LPDBC_3_RTCOUT0 (2 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 3 RTCOUT0 */ +# define SUPC_WUMR_LPDBC_4_RTCOUT0 (3 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 4 RTCOUT0 */ +# define SUPC_WUMR_LPDBC_5_RTCOUT0 (4 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 5 RTCOUT0 */ +# define SUPC_WUMR_LPDBC_6_RTCOUT0 (5 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 6 RTCOUT0 */ +# define SUPC_WUMR_LPDBC_7_RTCOUT0 (6 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 7 RTCOUT0 */ +# define SUPC_WUMR_LPDBC_8_RTCOUT0 (7 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 8 RTCOUT0 */ +#endif + +/* System Controller Wake Up Inputs Register */ + +#define SUPC_WUIR_WKUPEN_SHIFT (0) /* Bits 0-15: Wake Up Input Enable 0 to 15 */ +#define SUPC_WUIR_WKUPEN_MASK (0xffff << SUPC_WUIR_WKUPEN_SHIFT) +# define SUPC_WUIR_WKUPEN(n) ((1 << (n)) << SUPC_WUIR_WKUPEN_SHIFT) +#define SUPC_WUIR_WKUPT_SHIFT (16) /* Bits 16-31 Wake Up Input Transition 0 to 15 */ +#define SUPC_WUIR_WKUPT_MASK (0xffff << SUPC_WUIR_WKUPT_SHIFT) +# define SUPC_WUIR_WKUPT(n) ((1 << (n)) << SUPC_WUIR_WKUPT_SHIFT) + +/* Supply Controller Status Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SUPC_SR_FWUPS (1 << 0) /* Bit 0: FWUP Wake Up Status */ +#endif -#define SUPC_CR_VROFF (1 << 2) /* Bit 2: Voltage Regulator Off */ -#define SUPC_CR_XTALSEL (1 << 3) /* Bit 3: Crystal Oscillator Select */ -#define SUPC_CR_KEY_SHIFT (24) /* Bits 24-31: Password */ -#define SUPC_CR_KEY_MASK (0xff << SUPC_CR_KEY_SHIFT) - -#define SUPC_SMMR_SMTH_SHIFT (0) /* Bits 0-3: Supply Monitor Threshold */ -#define SUPC_SMMR_SMTH_MASK (15 << SUPC_SMMR_SMTH_SHIFT) -# define SUPC_SMMR_SMTH_1p9V (0 << SUPC_SMMR_SMTH_SHIFT) /* 1.9V */ -# define SUPC_SMMR_SMTH_2p0V (1 << SUPC_SMMR_SMTH_SHIFT) /* 2.0V */ -# define SUPC_SMMR_SMTH_2p1V (2 << SUPC_SMMR_SMTH_SHIFT) /* 2.1V */ -# define SUPC_SMMR_SMTH_2p2V (3 << SUPC_SMMR_SMTH_SHIFT) /* 2.2V */ -# define SUPC_SMMR_SMTH_2p3V (4 << SUPC_SMMR_SMTH_SHIFT) /* 2.3V */ -# define SUPC_SMMR_SMTH_2p4V (5 << SUPC_SMMR_SMTH_SHIFT) /* 2.4V */ -# define SUPC_SMMR_SMTH_2p5V (6 << SUPC_SMMR_SMTH_SHIFT) /* 2.5V */ -# define SUPC_SMMR_SMTH_2p6V (7 << SUPC_SMMR_SMTH_SHIFT) /* 2.6V */ -# define SUPC_SMMR_SMTH_2p7V (8 << SUPC_SMMR_SMTH_SHIFT) /* 2.7V */ -# define SUPC_SMMR_SMTH_2p8V (9 << SUPC_SMMR_SMTH_SHIFT) /* 2.8V */ -# define SUPC_SMMR_SMTH_2p9V (10 << SUPC_SMMR_SMTH_SHIFT) /* 2.9V */ -# define SUPC_SMMR_SMTH_3p0V (11 << SUPC_SMMR_SMTH_SHIFT) /* 3.0V */ -# define SUPC_SMMR_SMTH_3p1V (12 << SUPC_SMMR_SMTH_SHIFT) /* 3.1V */ -# define SUPC_SMMR_SMTH_3p2V (13 << SUPC_SMMR_SMTH_SHIFT) /* 3.2V */ -# define SUPC_SMMR_SMTH_3p3V (14 << SUPC_SMMR_SMTH_SHIFT) /* 3.3V */ -# define SUPC_SMMR_SMTH_3p4V (15 << SUPC_SMMR_SMTH_SHIFT) /* 3.4V */ -#define SUPC_SMMR_SMSMPL_SHIFT (8) /* Bits 8-10: Supply Monitor Sampling Period */ -#define SUPC_SMMR_SMSMPL_MASK (7 << SUPC_SMMR_SMSMPL_SHIFT) -# define SUPC_SMMR_SMSMPL_SMD (0 << SUPC_SMMR_SMSMPL_SHIFT) /* Supply Monitor disabled */ -# define SUPC_SMMR_SMSMPL_CSM (1 << SUPC_SMMR_SMSMPL_SHIFT) /* Continuous Supply Monitor */ -# define SUPC_SMMR_SMSMPL_32SLCK (2 << SUPC_SMMR_SMSMPL_SHIFT) /* Eevery 32 SLCK periods */ -# define SUPC_SMMR_SMSMPL_256SLCK (3 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 256 SLCK periods */ -# define SUPC_SMMR_SMSMPL_2048SLCK (4 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 2,048 SLCK periods */ -#define SUPC_SMMR_SMRSTEN (1 << 12) /* Bit 12: Supply Monitor Reset Enable */ -#define SUPC_SMMR_SMIEN (1 << 13) /* Bit 13: Supply Monitor Interrupt Enable */ - -#define SUPC_MR_BODRSTEN (1 << 12) /* Bit 12: Brownout Detector Reset Enable */ -#define SUPC_MR_BODDIS (1 << 13) /* Bit 13: Brownout Detector Disable */ -#define SUPC_MR_VDDIORDY (1 << 14) /* Bit 14: VDDIO Ready */ -#define SUPC_MR_OSCBYPASS (1 << 20) /* Bit 20: Oscillator Bypass */ -#define SUPC_MR_KEY_SHIFT (24) /* Bits 24-31: Password Key */ -#define SUPC_MR_KEY_MASK (0xff << SUPC_MR_KEY_SHIFT) - -#define SUPC_WUMR_FWUPEN (1 << 0) /* Bit 0: Force Wake Up Enable */ -#define SUPC_WUMR_SMEN (1 << 1) /* Bit 1: Supply Monitor Wake Up Enable */ -#define SUPC_WUMR_RTTEN (1 << 2) /* Bit 2: Real Time Timer Wake Up Enable */ -#define SUPC_WUMR_RTCEN (1 << 3) /* Bit 3: Real Time Clock Wake Up Enable */ -#define SUPC_WUMR_FWUPDBC_SHIFT (8) /* Bits 8-10: Force Wake Up Debouncer */ -#define SUPC_WUMR_FWUPDBC_MASK (7 << SUPC_WUMR_FWUPDBC_SHIFT) - #define SUPC_WUMR_FWUPDBC_1SCLK (0 << SUPC_WUMR_FWUPDBC_SHIFT) /* Immediate, no debouncing */ - #define SUPC_WUMR_FWUPDBC_3SCLK (1 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 3 SLCK periods */ - #define SUPC_WUMR_FWUPDBC_32SCLK (2 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32 SLCK periods */ - #define SUPC_WUMR_FWUPDBC_512SCLK (3 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 512 SLCK periods */ - #define SUPC_WUMR_FWUPDBC_4096SCLK (4 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 4096 SLCK periods */ - #define SUPC_WUMR_FWUPDBC_32768SCLK (5 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32768 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_SHIFT (12) /* Bits 12-14: Wake Up Inputs Debouncer */ -#define SUPC_WUMR_WKUPDBC_MASK (7 << SUPC_WUMR_WKUPDBC_SHIFT) -# define SUPC_WUMR_WKUPDBC_1SCLK (0 << SUPC_WUMR_WKUPDBC_SHIFT) /* Immediate, no debouncing */ -# define SUPC_WUMR_WKUPDBC_3SCLK (1 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 3 SLCK periods */ -# define SUPC_WUMR_WKUPDBC_32SCLK (2 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32 SLCK periods */ -# define SUPC_WUMR_WKUPDBC_512SCLK (3 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 512 SLCK periods */ -# define SUPC_WUMR_WKUPDBC_4096SCLK (4 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 4096 SLCK periods */ -# define SUPC_WUMR_WKUPDBC_32768SCLK (5 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32768 SLCK periods */ - -#define SUPC_WUIR_WKUPEN_SHIFT (0) /* Bits 0-15: Wake Up Input Enable 0 to 15 */ -#define SUPC_WUIR_WKUPEN_MASK (0xffff << SUPC_WUIR_WKUPEN_SHIFT) -#define SUPC_WUIR_WKUPEN(n) ((1 << (n)) << SUPC_WUIR_WKUPEN_SHIFT) -#define SUPC_WUIR_WKUPT_SHIFT (16) /* Bits 16-31 Wake Up Input Transition 0 to 15 */ -#define SUPC_WUIR_WKUPT_MASK (0xffff << SUPC_WUIR_WKUPT_SHIFT) -#define SUPC_WUIR_WKUPT(n) ((1 << (n)) << SUPC_WUIR_WKUPT_SHIFT) - -#define SUPC_SR_FWUPS (1 << 0) /* Bit 0: FWUP Wake Up Status */ #define SUPC_SR_WKUPS (1 << 1) /* Bit 1: WKUP Wake Up Status */ #define SUPC_SR_SMWS (1 << 2) /* Bit 2: Supply Monitor Detection Wake Up Status */ #define SUPC_SR_BODRSTS (1 << 3) /* Bit 3: Brownout Detector Reset Status */ @@ -145,7 +212,14 @@ #define SUPC_SR_SMS (1 << 5) /* Bit 5: Supply Monitor Status */ #define SUPC_SR_SMOS (1 << 6) /* Bit 6: Supply Monitor Output Status */ #define SUPC_SR_OSCSEL (1 << 7) /* Bit 7: 32-kHz Oscillator Selection Status */ -#define SUPC_SR_FWUPIS (1 << 12) /* Bit 12: FWUP Input Status */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SUPC_SR_FWUPIS (1 << 12) /* Bit 12: FWUP Input Status */ +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# define SUPC_SR_LPDBCS0 (1 << 13) /* Bit 13: Low Power Debouncer Wake Up Status on WKUP0 */ +# define SUPC_SR_LPDBCS1 (1 << 14) /* Bit 14: Low Power Debouncer Wake Up Status on WKUP1 */ +#endif + #define SUPC_SR_WKUPIS_SHIFT (16) /* Bits 16-31: WKUP Input Status 0 to 15 */ #define SUPC_SR_WKUPIS_MASK (0xffff << SUPC_SR_WKUPIS_SHIFT) diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_uart.h b/nuttx/arch/arm/src/sam34/chip/sam3u_uart.h new file mode 100644 index 000000000..bf2dbff2d --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_uart.h @@ -0,0 +1,433 @@ +/************************************************************************************************ + * arch/arm/src/sam34/chip/sam3u_uart.h + * Universal Asynchronous Receiver Transmitter (UART) and Universal Synchronous Asynchronous + * Receiver Transmitter (USART) definitions for the SAM3U and SAM4S + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_UART_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_UART_H + +/************************************************************************************************ + * Included Files + ************************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ + +/* UART register offsets ************************************************************************/ + +#define SAM_UART_CR_OFFSET 0x0000 /* Control Register (Common) */ +#define SAM_UART_MR_OFFSET 0x0004 /* Mode Register (Common) */ +#define SAM_UART_IER_OFFSET 0x0008 /* Interrupt Enable Register (Common) */ +#define SAM_UART_IDR_OFFSET 0x000c /* Interrupt Disable Register (Common) */ +#define SAM_UART_IMR_OFFSET 0x0010 /* Interrupt Mask Register (Common) */ +#define SAM_UART_SR_OFFSET 0x0014 /* [Channel] Status Register (Common) */ +#define SAM_UART_RHR_OFFSET 0x0018 /* Receive Holding Register (Common) */ +#define SAM_UART_THR_OFFSET 0x001c /* Transmit Holding Register (Common) */ +#define SAM_UART_BRGR_OFFSET 0x0020 /* Baud Rate Generator Register (Common) */ + /* 0x0024-0x003c: Reserved (UART) */ +#define SAM_UART_RTOR_OFFSET 0x0024 /* Receiver Time-out Register (USART only) */ +#define SAM_UART_TTGR_OFFSET 0x0028 /* Transmitter Timeguard Register (USART only) */ + /* 0x002c-0x003c: Reserved (USART) */ +#define SAM_UART_FIDI_OFFSET 0x0040 /* FI DI Ratio Register (USART only) */ +#define SAM_UART_NER_OFFSET 0x0044 /* Number of Errors Register ((USART only) */ + /* 0x0048: Reserved (USART) */ +#define SAM_UART_IFR_OFFSET 0x004c /* IrDA Filter Register (USART only) */ +#define SAM_UART_MAN_OFFSET 0x0050 /* Manchester Encoder Decoder Register (USART only) */ +#define SAM_UART_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register (USART only) */ +#define SAM_UART_WPSR_OFFSET 0x00e8 /* Write Protect Status Register (USART only) */ + /* 0x005c-0xf8: Reserved (USART) */ +#define SAM_UART_VERSION_OFFSET 0x00fc /* Version Register (USART only) */ + /* 0x0100-0x0124: PDC Area (Common) */ + +/* UART register adresses ***********************************************************************/ + +#define SAM_UART0_CR (SAM_UART0_BASE+SAM_UART_CR_OFFSET) +#define SAM_UART0_MR (SAM_UART0_BASE+SAM_UART_MR_OFFSET) +#define SAM_UART0_IER (SAM_UART0_BASE+SAM_UART_IER_OFFSET) +#define SAM_UART0_IDR (SAM_UART0_BASE+SAM_UART_IDR_OFFSET) +#define SAM_UART0_IMR (SAM_UART0_BASE+SAM_UART_IMR_OFFSET) +#define SAM_UART0_SR (SAM_UART0_BASE+SAM_UART_SR_OFFSET) +#define SAM_UART0_RHR (SAM_UART0_BASE+SAM_UART_RHR_OFFSET) +#define SAM_UART0_THR (SAM_UART0_BASE+SAM_UART_THR_OFFSET) +#define SAM_UART0_BRGR (SAM_UART0_BASE+SAM_UART_BRGR_OFFSET) + +#define SAM_UART1_CR (SAM_UART1_BASE+SAM_UART_CR_OFFSET) +#define SAM_UART1_MR (SAM_UART1_BASE+SAM_UART_MR_OFFSET) +#define SAM_UART1_IER (SAM_UART1_BASE+SAM_UART_IER_OFFSET) +#define SAM_UART1_IDR (SAM_UART1_BASE+SAM_UART_IDR_OFFSET) +#define SAM_UART1_IMR (SAM_UART1_BASE+SAM_UART_IMR_OFFSET) +#define SAM_UART1_SR (SAM_UART1_BASE+SAM_UART_SR_OFFSET) +#define SAM_UART1_RHR (SAM_UART1_BASE+SAM_UART_RHR_OFFSET) +#define SAM_UART1_THR (SAM_UART1_BASE+SAM_UART_THR_OFFSET) +#define SAM_UART1_BRGR (SAM_UART1_BASE+SAM_UART_BRGR_OFFSET) + +#define SAM_USART_CR(n) (SAM_USARTN_BASE(n)+SAM_UART_CR_OFFSET) +#define SAM_USART_MR(n) (SAM_USARTN_BASE(n)+SAM_UART_MR_OFFSET) +#define SAM_USART_IER(n) (SAM_USARTN_BASE(n)+SAM_UART_IER_OFFSET) +#define SAM_USART_IDR(n) (SAM_USARTN_BASE(n)+SAM_UART_IDR_OFFSET) +#define SAM_USART_IMR(n) (SAM_USARTN_BASE(n)+SAM_UART_IMR_OFFSET) +#define SAM_USART_SR(n) (SAM_USARTN_BASE(n)+SAM_UART_SR_OFFSET) +#define SAM_USART_RHR(n) (SAM_USARTN_BASE(n)+SAM_UART_RHR_OFFSET) +#define SAM_USART_THR(n) (SAM_USARTN_BASE(n)+SAM_UART_THR_OFFSET) +#define SAM_USART_BRGR(n) (SAM_USARTN_BASE(n)+SAM_UART_BRGR_OFFSET) +#define SAM_USART_RTOR(n) (SAM_USARTN_BASE(n)+SAM_UART_RTOR_OFFSET) +#define SAM_USART_TTGR(n) (SAM_USARTN_BASE(n)+SAM_UART_TTGR_OFFSET) +#define SAM_USART_FIDI(n) (SAM_USARTN_BASE(n)+SAM_UART_FIDI_OFFSET) +#define SAM_USART_NER(n) (SAM_USARTN_BASE(n)+SAM_UART_NER_OFFSET) +#define SAM_USART_IFR(n) (SAM_USARTN_BASE(n)+SAM_UART_IFR_OFFSET) +#define SAM_USART_MAN(n) (SAM_USARTN_BASE(n)+SAM_UART_MAN_OFFSET) +#define SAM_USART_WPMR(n) (SAM_USARTN_BASE(n)+SAM_UART_WPMR_OFFSET) +#define SAM_USART_WPSR(n) (SAM_USARTN_BASE(n)+SAM_UART_WPSR_OFFSET) +#define SAM_USART_VERSION(n) (SAM_USARTN_BASE(n)+SAM_UART_VERSION_OFFSET) + +#define SAM_USART0_CR (SAM_USART0_BASE+SAM_UART_CR_OFFSET) +#define SAM_USART0_MR (SAM_USART0_BASE+SAM_UART_MR_OFFSET) +#define SAM_USART0_IER (SAM_USART0_BASE+SAM_UART_IER_OFFSET) +#define SAM_USART0_IDR (SAM_USART0_BASE+SAM_UART_IDR_OFFSET) +#define SAM_USART0_IMR (SAM_USART0_BASE+SAM_UART_IMR_OFFSET) +#define SAM_USART0_SR (SAM_USART0_BASE+SAM_UART_SR_OFFSET) +#define SAM_USART0_RHR (SAM_USART0_BASE+SAM_UART_RHR_OFFSET) +#define SAM_USART0_THR (SAM_USART0_BASE+SAM_UART_THR_OFFSET) +#define SAM_USART0_BRGR (SAM_USART0_BASE+SAM_UART_BRGR_OFFSET) +#define SAM_USART0_RTOR (SAM_USART0_BASE+SAM_UART_RTOR_OFFSET) +#define SAM_USART0_TTGR (SAM_USART0_BASE+SAM_UART_TTGR_OFFSET) +#define SAM_USART0_FIDI (SAM_USART0_BASE+SAM_UART_FIDI_OFFSET) +#define SAM_USART0_NER (SAM_USART0_BASE+SAM_UART_NER_OFFSET) +#define SAM_USART0_IFR (SAM_USART0_BASE+SAM_UART_IFR_OFFSET) +#define SAM_USART0_MAN (SAM_USART0_BASE+SAM_UART_MAN_OFFSET) +#define SAM_USART0_WPMR (SAM_USART0_BASE+SAM_UART_WPMR_OFFSET) +#define SAM_USART0_WPSR (SAM_USART0_BASE+SAM_UART_WPSR_OFFSET) +#define SAM_USART0_VERSION (SAM_USART0_BASE+SAM_UART_VERSION_OFFSET) + +#define SAM_USART1_CR (SAM_USART1_BASE+SAM_UART_CR_OFFSET) +#define SAM_USART1_MR (SAM_USART1_BASE+SAM_UART_MR_OFFSET) +#define SAM_USART1_IER (SAM_USART1_BASE+SAM_UART_IER_OFFSET) +#define SAM_USART1_IDR (SAM_USART1_BASE+SAM_UART_IDR_OFFSET) +#define SAM_USART1_IMR (SAM_USART1_BASE+SAM_UART_IMR_OFFSET) +#define SAM_USART1_SR (SAM_USART1_BASE+SAM_UART_SR_OFFSET) +#define SAM_USART1_RHR (SAM_USART1_BASE+SAM_UART_RHR_OFFSET) +#define SAM_USART1_THR (SAM_USART1_BASE+SAM_UART_THR_OFFSET) +#define SAM_USART1_BRGR (SAM_USART1_BASE+SAM_UART_BRGR_OFFSET) +#define SAM_USART1_RTOR (SAM_USART1_BASE+SAM_UART_RTOR_OFFSET) +#define SAM_USART1_TTGR (SAM_USART1_BASE+SAM_UART_TTGR_OFFSET) +#define SAM_USART1_FIDI (SAM_USART1_BASE+SAM_UART_FIDI_OFFSET) +#define SAM_USART1_NER (SAM_USART1_BASE+SAM_UART_NER_OFFSET) +#define SAM_USART1_IFR (SAM_USART1_BASE+SAM_UART_IFR_OFFSET) +#define SAM_USART1_MAN (SAM_USART1_BASE+SAM_UART_MAN_OFFSET) +#define SAM_USART1_WPMR (SAM_USART1_BASE+SAM_UART_WPMR_OFFSET) +#define SAM_USART1_WPSR (SAM_USART1_BASE+SAM_UART_WPSR_OFFSET) +#define SAM_USART1_VERSION (SAM_USART1_BASE+SAM_UART_VERSION_OFFSET) + +#define SAM_USART2_CR (SAM_USART2_BASE+SAM_UART_CR_OFFSET) +#define SAM_USART2_MR (SAM_USART2_BASE+SAM_UART_MR_OFFSET) +#define SAM_USART2_IER (SAM_USART2_BASE+SAM_UART_IER_OFFSET) +#define SAM_USART2_IDR (SAM_USART2_BASE+SAM_UART_IDR_OFFSET) +#define SAM_USART2_IMR (SAM_USART2_BASE+SAM_UART_IMR_OFFSET) +#define SAM_USART2_SR (SAM_USART2_BASE+SAM_UART_SR_OFFSET) +#define SAM_USART2_RHR (SAM_USART2_BASE+SAM_UART_RHR_OFFSET) +#define SAM_USART2_THR (SAM_USART2_BASE+SAM_UART_THR_OFFSET) +#define SAM_USART2_BRGR (SAM_USART2_BASE+SAM_UART_BRGR_OFFSET) +#define SAM_USART2_RTOR (SAM_USART2_BASE+SAM_UART_RTOR_OFFSET) +#define SAM_USART2_TTGR (SAM_USART2_BASE+SAM_UART_TTGR_OFFSET) +#define SAM_USART2_FIDI (SAM_USART2_BASE+SAM_UART_FIDI_OFFSET) +#define SAM_USART2_NER (SAM_USART2_BASE+SAM_UART_NER_OFFSET) +#define SAM_USART2_IFR (SAM_USART2_BASE+SAM_UART_IFR_OFFSET) +#define SAM_USART2_MAN (SAM_USART2_BASE+SAM_UART_MAN_OFFSET) +#define SAM_USART2_WPMR (SAM_USART2_BASE+SAM_UART_WPMR_OFFSET) +#define SAM_USART2_WPSR (SAM_USART2_BASE+SAM_UART_WPSR_OFFSET) +#define SAM_USART2_VERSION (SAM_USART2_BASE+SAM_UART_VERSION_OFFSET) + +#define SAM_USART3_CR (SAM_USART3_BASE+SAM_UART_CR_OFFSET) +#define SAM_USART3_MR (SAM_USART3_BASE+SAM_UART_MR_OFFSET) +#define SAM_USART3_IER (SAM_USART3_BASE+SAM_UART_IER_OFFSET) +#define SAM_USART3_IDR (SAM_USART3_BASE+SAM_UART_IDR_OFFSET) +#define SAM_USART3_IMR (SAM_USART3_BASE+SAM_UART_IMR_OFFSET) +#define SAM_USART3_SR (SAM_USART3_BASE+SAM_UART_SR_OFFSET) +#define SAM_USART3_RHR (SAM_USART3_BASE+SAM_UART_RHR_OFFSET) +#define SAM_USART3_THR (SAM_USART3_BASE+SAM_UART_THR_OFFSET) +#define SAM_USART3_BRGR (SAM_USART3_BASE+SAM_UART_BRGR_OFFSET) +#define SAM_USART3_RTOR (SAM_USART3_BASE+SAM_UART_RTOR_OFFSET) +#define SAM_USART3_TTGR (SAM_USART3_BASE+SAM_UART_TTGR_OFFSET) +#define SAM_USART3_FIDI (SAM_USART3_BASE+SAM_UART_FIDI_OFFSET) +#define SAM_USART3_NER (SAM_USART3_BASE+SAM_UART_NER_OFFSET) +#define SAM_USART3_IFR (SAM_USART3_BASE+SAM_UART_IFR_OFFSET) +#define SAM_USART3_MAN (SAM_USART3_BASE+SAM_UART_MAN_OFFSET) +#define SAM_USART3_WPMR (SAM_USART3_BASE+SAM_UART_WPMR_OFFSET) +#define SAM_USART3_WPSR (SAM_USART3_BASE+SAM_UART_WPSR_OFFSET) +#define SAM_USART3_VERSION (SAM_USART3_BASE+SAM_UART_VERSION_OFFSET) + +/* UART register bit definitions ****************************************************************/ + +/* UART Control Register */ + +#define UART_CR_RSTRX (1 << 2) /* Bit 2: Reset Receiver (Common) */ +#define UART_CR_RSTTX (1 << 3) /* Bit 3: Reset Transmitter (Common) */ +#define UART_CR_RXEN (1 << 4) /* Bit 4: Receiver Enable (Common) */ +#define UART_CR_RXDIS (1 << 5) /* Bit 5: Receiver Disable (Common) */ +#define UART_CR_TXEN (1 << 6) /* Bit 6: Transmitter Enable (Common) */ +#define UART_CR_TXDIS (1 << 7) /* Bit 7: Transmitter Disable (Common) */ +#define UART_CR_RSTSTA (1 << 8) /* Bit 8: Reset Status Bits (Common) */ +#define UART_CR_STTBRK (1 << 9) /* Bit 9: Start Break (USART only) */ +#define UART_CR_STPBRK (1 << 10) /* Bit 10: Stop Break (USART only) */ +#define UART_CR_STTTO (1 << 11) /* Bit 11: Start Time-out (USART only) */ +#define UART_CR_SENDA (1 << 12) /* Bit 12: Send Address (USART only) */ +#define UART_CR_RSTIT (1 << 13) /* Bit 13: Reset Iterations (USART only) */ +#define UART_CR_RSTNACK (1 << 14) /* Bit 14: Reset Non Acknowledge (USART only) */ +#define UART_CR_RETTO (1 << 15) /* Bit 15: Rearm Time-out (USART only) */ +#define UART_CR_RTSEN (1 << 18) /* Bit 18: Request to Send Enable (USART only) */ +#define UART_CR_FCS (1 << 18) /* Bit 18: Force SPI Chip Select (USART SPI mode only) */ +#define UART_CR_RTSDIS (1 << 19) /* Bit 19: Request to Send Disable (USART only) */ +#define UART_CR_RCS (1 << 19) /* Bit 19: Release SPI Chip Select (USART SPI mode only) */ + +/* UART Mode Register and USART Mode Register (UART MODE) */ + +#define UART_MR_MODE_SHIFT (0) /* Bits 0-3: (USART only) */ +#define UART_MR_MODE_MASK (15 << UART_MR_MODE_SHIFT) +# define UART_MR_MODE_NORMAL (0 << UART_MR_MODE_SHIFT) /* Normal */ +# define UART_MR_MODE_RS485 (1 << UART_MR_MODE_SHIFT) /* RS485 */ +# define UART_MR_MODE_HWHS (2 << UART_MR_MODE_SHIFT) /* Hardware Handshaking */ +# define UART_MR_MODE_ISO7816_0 (4 << UART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 0 */ +# define UART_MR_MODE_ISO7816_1 (6 << UART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 1 */ +# define UART_MR_MODE_IRDA (8 << UART_MR_MODE_SHIFT) /* IrDA */ +# define UART_MR_MODE_SPIMSTR (14 << UART_MR_MODE_SHIFT) /* SPI Master (SPI mode only) */ +# define UART_MR_MODE_SPISLV (15 << UART_MR_MODE_SHIFT) /* SPI Slave (SPI mode only) */ +#define UART_MR_USCLKS_SHIFT (4) /* Bits 4-5: Clock Selection (USART only) */ +#define UART_MR_USCLKS_MASK (3 << UART_MR_USCLKS_SHIFT) +# define UART_MR_USCLKS_MCK (0 << UART_MR_USCLKS_SHIFT) /* MCK */ +# define UART_MR_USCLKS_MCKDIV (1 << UART_MR_USCLKS_SHIFT) /* MCK/DIV (DIV = 8) */ +# define UART_MR_USCLKS_SCK (3 << UART_MR_USCLKS_SHIFT) /* SCK */ +#define UART_MR_CHRL_SHIFT (6) /* Bits 6-7: Character Length (USART only) */ +#define UART_MR_CHRL_MASK (3 << UART_MR_CHRL_SHIFT) +# define UART_MR_CHRL_5BITS (0 << UART_MR_CHRL_SHIFT) /* 5 bits */ +# define UART_MR_CHRL_6BITS (1 << UART_MR_CHRL_SHIFT) /* 6 bits */ +# define UART_MR_CHRL_7BITS (2 << UART_MR_CHRL_SHIFT) /* 7 bits */ +# define UART_MR_CHRL_8BITS (3 << UART_MR_CHRL_SHIFT) /* 8 bits */ +#define UART_MR_SYNC (1 << 8) /* Bit 8: Synchronous Mode Select (USART only) */ +#define UART_MR_CPHA (1 << 8) /* Bit 8: SPI Clock Phase (USART SPI mode only) */ +#define UART_MR_PAR_SHIFT (9) /* Bits 9-11: Parity Type (Common) */ +#define UART_MR_PAR_MASK (7 << UART_MR_PAR_SHIFT) +# define UART_MR_PAR_EVEN (0 << UART_MR_PAR_SHIFT) /* Even parity (Common) */ +# define UART_MR_PAR_ODD (1 << UART_MR_PAR_SHIFT) /* Odd parity (Common) */ +# define UART_MR_PAR_SPACE (2 << UART_MR_PAR_SHIFT) /* Space: parity forced to 0 (Common) */ +# define UART_MR_PAR_MARK (3 << UART_MR_PAR_SHIFT) /* Mark: parity forced to 1 (Common) */ +# define UART_MR_PAR_NONE (4 << UART_MR_PAR_SHIFT) /* No parity (Common) */ +# define UART_MR_PAR_MULTIDROP (6 << UART_MR_PAR_SHIFT) /* Multidrop mode (USART only) */ +#define UART_MR_NBSTOP_SHIFT (12) /* Bits 12-13: Number of Stop Bits (USART only) */ +#define UART_MR_NBSTOP_MASK (3 << UART_MR_NBSTOP_SHIFT) +# define UART_MR_NBSTOP_1 (0 << UART_MR_NBSTOP_SHIFT) /* 1 stop bit 1 stop bit */ +# define UART_MR_NBSTOP_1p5 (1 << UART_MR_NBSTOP_SHIFT) /* 1.5 stop bits */ +# define UART_MR_NBSTOP_2 (2 << UART_MR_NBSTOP_SHIFT) /* 2 stop bits 2 stop bits */ +#define UART_MR_CHMODE_SHIFT (14) /* Bits 14-15: Channel Mode (Common) */ +#define UART_MR_CHMODE_MASK (3 << UART_MR_CHMODE_SHIFT) +# define UART_MR_CHMODE_NORMAL (0 << UART_MR_CHMODE_SHIFT) /* Normal Mode */ +# define UART_MR_CHMODE_ECHO (1 << UART_MR_CHMODE_SHIFT) /* Automatic Echo */ +# define UART_MR_CHMODE_LLPBK (2 << UART_MR_CHMODE_SHIFT) /* Local Loopback */ +# define UART_MR_CHMODE_RLPBK (3 << UART_MR_CHMODE_SHIFT) /* Remote Loopback */ +#define UART_MR_MSBF (1 << 16) /* Bit 16: Most Significant Bit first (USART only) */ +#define UART_MR_CPOL (1 << 16) /* Bit 16: SPI Clock Polarity (USART SPI mode only) */ +#define UART_MR_MODE9 (1 << 17) /* Bit 17: 9-bit Character Length (USART only) */ +#define UART_MR_CLKO (1 << 18) /* Bit 18: Clock Output Select (USART only) */ +#define UART_MR_OVER (1 << 19) /* Bit 19: Oversampling Mode (USART only) */ +#define UART_MR_INACK (1 << 20) /* Bit 20: Inhibit Non Acknowledge (USART only) */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define UART_MR_WRDBT (1 << 20) /* Bit 20: Wait Read Data Before Transfer (SPI mode only) */ +#endif + +#define UART_MR_DSNACK (1 << 21) /* Bit 21: Disable Successive NACK (USART only) */ +#define UART_MR_VARSYNC (1 << 22) /* Bit 22: Variable Synchronization of Command/Data Sync Start Frame Delimiter (USART only) */ +#define UART_MR_INVDATA (1 << 23) /* Bit 23: INverted Data (USART only) */ +#define UART_MR_MAXITER_SHIFT (24) /* Bits 24-26: Max iterations (ISO7816 T=0 (USART only) */ +#define UART_MR_MAXITER_MASK (7 << UART_MR_MAXITER_SHIFT) +#define UART_MR_FILTER (1 << 28) /* Bit 28: Infrared Receive Line Filter (USART only) */ +#define UART_MR_MAN (1 << 29) /* Bit 29: Manchester Encoder/Decoder Enable (USART only) */ +#define UART_MR_MODSYNC (1 << 30) /* Bit 30: Manchester Synchronization Mode (USART only) */ +#define UART_MR_ONEBIT (1 << 31) /* Bit 31: Start Frame Delimiter Selector (USART only) */ + +/* UART Interrupt Enable Register, UART Interrupt Disable Register, UART Interrupt Mask + * Register, and UART Status Register common bit field definitions + */ + +#define UART_INT_RXRDY (1 << 0) /* Bit 0: RXRDY Interrupt (Common) */ +#define UART_INT_TXRDY (1 << 1) /* Bit 1: TXRDY Interrupt (Common) */ +#define UART_INT_RXBRK (1 << 2) /* Bit 2: Break Received/End of Break */ +#define UART_INT_ENDRX (1 << 3) /* Bit 3: End of Receive Transfer Interrupt (Common) */ +#define UART_INT_ENDTX (1 << 4) /* Bit 4: End of Transmit Interrupt (Common) */ +#define UART_INT_OVRE (1 << 5) /* Bit 5: Overrun Error Interrupt (Common) */ +#define UART_INT_FRAME (1 << 6) /* Bit 6: Framing Error Interrupt (Common) */ +#define UART_INT_PARE (1 << 7) /* Bit 7: Parity Error Interrupt (Common) */ +#define UART_INT_TIMEOUT (1 << 8) /* Bit 8: Time-out Interrupt (USART only) */ +#define UART_INT_TXEMPTY (1 << 9) /* Bit 9: TXEMPTY Interrupt (Common) */ +#define UART_INT_ITER (1 << 10) /* Bit 10: Iteration Interrupt (USART only) */ +#define UART_INT_UNRE (1 << 10) /* Bit 10: SPI Underrun Error Interrupt (USART SPI mode only) */ +#define UART_INT_TXBUFE (1 << 11) /* Bit 11: Buffer Empty Interrupt (Common) */ +#define UART_INT_RXBUFF (1 << 12) /* Bit 12: Buffer Full Interrupt (Common) */ +#define UART_INT_NACK (1 << 13) /* Bit 13: Non Acknowledge Interrupt (USART only) */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define UART_INT_RIIC (1 << 16) /* Bit 16: Ring Indicator Input Change Enable */ +# define UART_INT_DSRIC (1 << 17) /* Bit 17: Data Set Ready Input Change Enable */ +# define UART_INT_DCDIC (1 << 18) /* Bit 18: Data Carrier Detect Input Change Interrupt Enable */ +#endif + +#define UART_INT_CTSIC (1 << 19) /* Bit 19: Clear to Send Input Change Interrupt (USART only) */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define UART_SR_RI (1 << 20) /* Bit 20: Image of RI Input */ +# define UART_SR_DSR (1 << 21) /* Bit 21: Image of DSR Input */ +# define UART_SR_DCD (1 << 22) /* Bit 22: Image of DCD Input */ +# define UART_SR_CTS (1 << 23) /* Bit 23: Image of CTS Input */ +#endif + +#define UART_INT_MANE (1 << 24) /* Bit 24: Manchester Error Interrupt (USART only) */ + +/* UART Receiver Holding Register */ + +#if 0 +# define UART_RHR_RXCHR_SHIFT (0) /* Bits 0-7: Received Character (UART only) */ +# define UART_RHR_RXCHR_MASK (0xff << UART_RHR_RXCHR_SHIFT) +#endif +#define UART_RHR_RXCHR_SHIFT (0) /* Bits 0-8: Received Character (USART only) */ +#define UART_RHR_RXCHR_MASK (0x1ff << UART_RHR_RXCHR_SHIFT) +#define UART_RHR_RXSYNH (1 << 15) /* Bit 15: Received Sync (USART only) */ + +/* UART Transmit Holding Register */ + +#if 0 +# define UART_THR_TXCHR_SHIFT (0) /* Bits 0-7: Character to be Transmitted (UART only) */ +# define UART_THR_TXCHR_MASK (0xff << UART_THR_TXCHR_SHIFT) +#endif +#define UART_THR_TXCHR_SHIFT (0) /* Bits 0-8: Character to be Transmitted (USART only) */ +#define UART_THR_TXCHR_MASK (0x1ff << UART_THR_TXCHR_SHIFT) +#define UART_THR_TXSYNH (1 << 15) /* Bit 15: Sync Field to be tran (USART only) */ + +/* UART Baud Rate Generator Register */ + +#define UART_BRGR_CD_SHIFT (0) /* Bits 0-15: Clock Divisor (Common) */ +#define UART_BRGR_CD_MASK (0xffff << UART_BRGR_CD_SHIFT) +#define UART_BRGR_FP_SHIFT (16) /* Bits 16-18: Fractional Part (USART only) */ +#define UART_BRGR_FP_MASK (7 << UART_BRGR_FP_SHIFT) + +/* USART Receiver Time-out Register (USART only) */ + +#define UART_RTOR_TO_SHIFT (0) /* Bits 0-15: Time-out Value (USART only) */ +#define UART_RTOR_TO_MASK (0xffff << UART_RTOR_TO_SHIFT) + +/* USART Transmitter Timeguard Register (USART only) */ + +#define UART_TTGR_TG_SHIFT (0) /* Bits 0-7: Timeguard Value (USART only) */ +#define UART_TTGR_TG_MASK (0xff << UART_TTGR_TG_SHIFT) + +/* USART FI DI RATIO Register (USART only) */ + +#define UART_FIDI_RATIO_SHIFT (0) /* Bits 0-10: FI Over DI Ratio Value (USART only) */ +#define UART_FIDI_RATIO_MASK (0x7ff << UART_FIDI_RATIO_SHIFT) + +/* USART Number of Errors Register (USART only) */ + +#define UART_NER_NBERRORS_SHIFT (0) /* Bits 0-7: Number of Errrors (USART only) */ +#define UART_NER_NBERRORS_MASK (0xff << UART_NER_NBERRORS_SHIFT) + +/* USART IrDA FILTER Register (USART only) */ + +#define UART_IFR_IRDAFILTER_SHIFT (0) /* Bits 0-7: IrDA Filter (USART only) */ +#define UART_IFR_IRDAFILTER_MASK (0xff << UART_IFR_IRDAFILTER_SHIFT) + +/* USART Manchester Configuration Register (USART only) */ + +#define UART_MAN_TXPL_SHIFT (0) /* Bits 0-3: Transmitter Preamble Length (USART only) */ +#define UART_MAN_TXPL_MASK (15 << UART_MAN_TXPL_SHIFT) +#define UART_MAN_TXPP_SHIFT (8) /* Bits 8-9: Transmitter Preamble Pattern (USART only) */ +#define UART_MAN_TXPP_MASK (3 << UART_MAN_TXPP_SHIFT) +# define UART_MAN_TXPP_ALLONE (0 << UART_MAN_TXPP_SHIFT) /* ALL_ONE */ +# define UART_MAN_TXPP_ALLZERO (1 << UART_MAN_TXPP_SHIFT) /* ALL_ZERO */ +# define UART_MAN_TXPP_ZEROONE (2 << UART_MAN_TXPP_SHIFT) /* ZERO_ONE */ +# define UART_MAN_TXPP_ONEZERO (3 << UART_MAN_TXPP_SHIFT) /* ONE_ZERO */ +#define UART_MAN_TXMPOL (1 << 12) /* Bit 12: Transmitter Manchester Polarity (USART only) */ +#define UART_MAN_RXPL_SHIFT (16) /* Bits 16-19: Receiver Preamble Length (USART only) */ +#define UART_MAN_RXPL_MASK (15 << UART_MAN_RXPL_SHIFT) +#define UART_MAN_RXPP_SHIFT (24) /* Bits 24-25: Receiver Preamble Pattern detected (USART only) */ +#define UART_MAN_RXPP_MASK (3 << UART_MAN_RXPP_SHIFT) +# define UART_MAN_RXPP_ALLONE (0 << UART_MAN_RXPP_SHIFT) /* ALL_ONE */ +# define UART_MAN_RXPP_ALLZERO (1 << UART_MAN_RXPP_SHIFT) /* ALL_ZERO */ +# define UART_MAN_RXPP_ZEROONE (2 << UART_MAN_RXPP_SHIFT) /* ZERO_ONE */ +# define UART_MAN_RXPP_ONEZERO (3 << UART_MAN_RXPP_SHIFT) /* ONE_ZERO */ +#define UART_MAN_RXMPOL (1 << 28) /* Bit 28: Receiver Manchester Polarity (USART only) */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define UART_MAN_ONE (1 << 29) /* Bit 29: Must Be Set to 1 */ +#endif + +#define UART_MAN_DRIFT (1 << 30) /* Bit 30: Drift compensation (USART only) */ + +/* USART Write Protect Mode Register (USART only) */ + +#define UART_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable (USART only) */ +#define UART_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY (USART only) */ +#define UART_WPMR_WPKEY_MASK (0x00ffffff << UART_WPMR_WPKEY_SHIFT) +# define UART_WPMR_WPKEY (0x00555341 << UART_WPMR_WPKEY_SHIFT) + +/* USART Write Protect Status Register (USART only) */ + +#define UART_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status (USART only) */ +#define UART_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source (USART only) */ +#define UART_WPSR_WPVSRC_MASK (0xffff << UART_WPSR_WPVSRC_SHIFT) + +/* USART Version Register */ + +#define UART_VERSION_VERSION_SHIFT (0) /* Bits 0-11: Macrocell version number (USART only) */ +#define UART_VERSION_VERSION_MASK (0xfff << UART_VERSION_VERSION_SHIFT) +#define UART_VERSION_MFN_SHIFT (16) /* Bits 16-18: Reserved (USART only) */ +#define UART_VERSION_MFN_MASK (7 << UART_VERSION_MFN_SHIFT) + +/************************************************************************************************ + * Public Types + ************************************************************************************************/ + +/************************************************************************************************ + * Public Data + ************************************************************************************************/ + +/************************************************************************************************ + * Public Functions + ************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_UART_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_vectors.h b/nuttx/arch/arm/src/sam34/chip/sam3u_vectors.h index fd4c1a39e..2af4ac734 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam3u_vectors.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_vectors.h @@ -62,7 +62,7 @@ VECTOR(sam_pmc, SAM_IRQ_PMC) /* Vector 16+5: Power Management Controller */ VECTOR(sam_eefc0, SAM_IRQ_EEFC0) /* Vector 16+6: Enhanced Embedded Flash Controller 0 */ VECTOR(sam_eefc1, SAM_IRQ_EEFC1) /* Vector 16+7: Enhanced Embedded Flash Controller 1 */ - VECTOR(sam_uart, SAM_IRQ_UART) /* Vector 16+8: Universal Asynchronous Receiver Transmitter */ + VECTOR(sam_uart0, SAM_IRQ_UART0) /* Vector 16+8: Universal Asynchronous Receiver Transmitter */ VECTOR(sam_smc, SAM_IRQ_SMC) /* Vector 16+9: Static Memory Controller */ VECTOR(sam_pioa, SAM_IRQ_PIOA) /* Vector 16+10: Parallel I/O Controller A */ VECTOR(sam_piob, SAM_IRQ_PIOB) /* Vector 16+11: Parallel I/O Controller B */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_wdt.h b/nuttx/arch/arm/src/sam34/chip/sam3u_wdt.h index ffe0cb96d..04132cd4b 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_wdt.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_wdt.h @@ -1,5 +1,6 @@ /**************************************************************************************** - * arch/arm/src/sam34/chip/sam_wdt.h + * arch/arm/src/sam34/chip/sam3u_wdt.h + * Watchdog Timer (WDT) definitions for the SAM3U and SAM4S * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -33,8 +34,8 @@ * ****************************************************************************************/ -#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_WDT_H -#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_WDT_H +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_WDT_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_WDT_H /**************************************************************************************** * Included Files @@ -62,22 +63,27 @@ #define SAM_WDT_SR (SAM_WDT_BASE+SAM_WDT_SR_OFFSET) /* WDT register bit definitions ********************************************************/ +/* Watchdog Timer Control Register */ #define WDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Rest */ #define WDT_CR_KEY_SHIFT (24) /* Bits 24-31: Password */ #define WDT_CR_KEY_MASK (0xff << WDT_CR_KEY_SHIFT) +/* Watchdog Timer Mode Register */ + #define WDT_MR_WDV_SHIFT (0) /* Bits 0-11: Watchdog Counter Value */ #define WDT_MR_WDV_MASK (0xfff << WDT_MR_WDV_SHIFT) #define WDT_MR_WDFIEN (1 << 12) /* Bit 12: Watchdog Fault Interrupt Enable */ #define WDT_MR_WDRSTEN (1 << 13) /* Bit 13: Watchdog Reset Enable */ #define WDT_MR_WDRPROC (1 << 14) /* Bit 14: Watchdog Reset Processor */ #define WDT_MR_WDDIS (1 << 15) /* Bit 15: Watchdog Disable */ -#define WDT_MR_WDD_SHIFT (16) /* Bits 16-17: Watchdog Delta Value */ +#define WDT_MR_WDD_SHIFT (16) /* Bits 16-27: Watchdog Delta Value */ #define WDT_MR_WDD_MASK (0xfff << WDT_MR_WDD_SHIFT) #define WDT_MR_WDDBGHLT (1 << 28) /* Bit 28: Watchdog Debug Halt */ #define WDT_MR_WDIDLEHLT (1 << 29) /* Bit 29: Watchdog Idle Halt */ +/* Watchdog Timer Status Register */ + #define WDT_SR_WDUNF (1 << 0) /* Bit 0: Watchdog Underflow */ #define WDT_SR_WDERR (1 << 1) /* Bit 1: Watchdog Error */ @@ -93,4 +99,4 @@ * Public Functions ****************************************************************************************/ -#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_WDT_H */ +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_WDT_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_bpm.h b/nuttx/arch/arm/src/sam34/chip/sam4l_bpm.h new file mode 100644 index 000000000..05ba546c9 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_bpm.h @@ -0,0 +1,178 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam4l_bpm.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_BPM_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_BPM_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* BPM register offsets ****************************************************************/ + +#define SAM_BPM_IER_OFFSET 0x0000 /* Interrupt Enable Register */ +#define SAM_BPM_IDR_OFFSET 0x0004 /* Interrupt Disable Register */ +#define SAM_BPM_IMR_OFFSET 0x0008 /* Interrupt Mask Register */ +#define SAM_BPM_ISR_OFFSET 0x000c /* Interrupt Status Register */ +#define SAM_BPM_ICR_OFFSET 0x0010 /* Interrupt Clear Register */ +#define SAM_BPM_SR_OFFSET 0x0014 /* Status Register */ +#define SAM_BPM_UNLOCK_OFFSET 0x0018 /* Unlock Register */ +#define SAM_BPM_PMCON_OFFSET 0x001c /* Power Mode Control Register */ +#define SAM_BPM_BKUPWCAUSE_OFFSET 0x0028 /* Backup Wake up Cause Register */ +#define SAM_BPM_BKUPWEN_OFFSET 0x002c /* Backup Wake up Enable Register */ +#define SAM_BPM_BKUPPMUX_OFFSET 0x0030 /* Backup Pin Muxing Register */ +#define SAM_BPM_IORET_OFFSET 0x0034 /* Input Output Retention Register */ +#define SAM_BPM_VERSION_OFFSET 0x00fc /* Version Register */ + +/* BPM register adresses ***************************************************************/ + +#define SAM_BPM_IER (SAM_BPM_BASE+SAM_BPM_IER_OFFSET) +#define SAM_BPM_IDR (SAM_BPM_BASE+SAM_BPM_IDR_OFFSET) +#define SAM_BPM_IMR (SAM_BPM_BASE+SAM_BPM_IMR_OFFSET) +#define SAM_BPM_ISR (SAM_BPM_BASE+SAM_BPM_ISR_OFFSET) +#define SAM_BPM_ICR (SAM_BPM_BASE+SAM_BPM_ICR_OFFSET) +#define SAM_BPM_SR (SAM_BPM_BASE+SAM_BPM_SR_OFFSET) +#define SAM_BPM_UNLOCK (SAM_BPM_BASE+SAM_BPM_UNLOCK_OFFSET) +#define SAM_BPM_PMCON (SAM_BPM_BASE+SAM_BPM_PMCON_OFFSET) +#define SAM_BPM_BKUPWCAUSE (SAM_BPM_BASE+SAM_BPM_BKUPWCAUSE_OFFSET) +#define SAM_BPM_BKUPWEN (SAM_BPM_BASE+SAM_BPM_BKUPWEN_OFFSET) +#define SAM_BPM_BKUPPMUX (SAM_BPM_BASE+SAM_BPM_BKUPPMUX_OFFSET) +#define SAM_BPM_IORET (SAM_BPM_BASE+SAM_BPM_IORET_OFFSET) +#define SAM_BPM_VERSION (SAM_BPM_BASE+SAM_BPM_VERSION_OFFSET) + +/* BPM register bit definitions ********************************************************/ + +/* Interrupt Enable Register */ +/* Interrupt Disable Register */ +/* Interrupt Mask Register */ +/* Interrupt Status Register */ +/* Interrupt Clear Register */ +/* Status Register */ + +#define BPM_INT_PSOK (1 << 0) /* Bit 0: Power Scaling OK */ +#define BPM_INT_AE (1 << 31) /* Bit 31: Access Error */ + +/* Unlock Register */ + +#define BPM_UNLOCK_ADDR_SHIFT (0) /* Bits 0-9: Unlock Address */ +#define BPM_UNLOCK_ADDR_MASK (0x3ff << BPM_UNLOCK_ADDR_SHIFT) +# define BPM_UNLOCK_ADDR(n) ((n) << BPM_UNLOCK_ADDR_SHIFT) +#define BPM_UNLOCK_KEY_SHIFT (24) /* Bits 24-31: Unlock Key */ +#define BPM_UNLOCK_KEY_MASK (0xff << BPM_UNLOCK_KEY_SHIFT) +# define BPM_UNLOCK_KEY(n) ((n) << BPM_UNLOCK_KEY_SHIFT) + +/* Power Mode Control Register */ + +#define BPM_PMCON_PS_SHIFT (0) /* Bits 0-1: Power Scaling Configuration Value */ +#define BPM_PMCON_PS_MASK (3 << BPM_PMCON_PS_SHIFT) +# define BPM_PMCON_PS0 (0 << BPM_PMCON_PS_SHIFT) +# define BPM_PMCON_PS1 (1 << BPM_PMCON_PS_SHIFT) +# define BPM_PMCON_PS2 (2 << BPM_PMCON_PS_SHIFT) +#define BPM_PMCON_PSCREQ (1 << 2) /* Bit 2: Power Scaling Change Request */ +#define BPM_PMCON_PSCM (1 << 3) /* Bit 3: Power Scaling Change Mode */ +#define BPM_PMCON_BKUP (1 << 8) /* Bit 8: BACKUP Mode */ +#define BPM_PMCON_RET (1 << 9) /* Bit 9: RETENTION Mode */ +#define BPM_PMCON_SLEEP_SHIFT (12) /* Bits 12-13: SLEEP mode Configuration */ +#define BPM_PMCON_SLEEP_MASK (3 << BPM_PMCON_SLEEP_SHIFT) +# define BPM_PMCON_SLEEP_SLEEP0 (0 << BPM_PMCON_SLEEP_SHIFT) /* CPU clock stopped */ +# define BPM_PMCON_SLEEP_SLEEP1 (1 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB clocks stopped */ +# define BPM_PMCON_SLEEP_SLEEP2 (2 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB+PB+GCLK clocks stopped */ +# define BPM_PMCON_SLEEP_SLEEP3 (3 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB+PB+GCLK+sources stopped */ +#define BPM_PMCON_CK32S (1 << 16) /* Bit 16: 32kHz-1kHz Clock Source Selection */ +#define BPM_PMCON_FASTWKUP (1 << 24) /* Bit 24: Fast Wakeup */ + +/* Backup Wake up Cause Register */ + +#define BPM_BKUPWCAUSE_EIC (1 << 0) /* Bit 0: EIC */ +#define BPM_BKUPWCAUSE_AST (1 << 1) /* Bit 1: AST */ +#define BPM_BKUPWCAUSE_WDT (1 << 2) /* Bit 2: WDT interrupt */ +#define BPM_BKUPWCAUSE_BOD33 (1 << 3) /* Bit 3: BOD33 interrupt */ +#define BPM_BKUPWCAUSE_BOD18 (1 << 4) /* Bit 4: BOD18 interrupt */ +#define BPM_BKUPWCAUSE_PICOUART (1 << 5) /* Bit 5: PICOUART interrupt */ + +/* Backup Wake up Enable Register */ + +#define BPM_BKUPWEN_EICEN (1 << 0) /* Bit 0: EIC */ +#define BPM_BKUPWEN_ASTEN (1 << 1) /* Bit 1: AST */ +#define BPM_BKUPWEN_WDTEN (1 << 2) /* Bit 2: WDT interrupt */ +#define BPM_BKUPWEN_BOD33EN (1 << 3) /* Bit 3: BOD33 interrupt */ +#define BPM_BKUPWEN_BOD18EN (1 << 4) /* Bit 4: BOD18 interrupt */ +#define BPM_BKUPWEN_PICOUARTEN (1 << 5) /* Bit 5: PICOUART interrupt */ + +/* Backup Pin Muxing Register */ + +#define BPM_BKUPPMUX_EIC0 (1 << 0) /* Bit 0: PB01 EIC[0] */ +#define BPM_BKUPPMUX_EIC1 (1 << 1) /* Bit 1: PA06 EIC[1] */ +#define BPM_BKUPPMUX_EIC2 (1 << 2) /* Bit 2: PA04 EIC[2] */ +#define BPM_BKUPPMUX_EIC3 (1 << 3) /* Bit 3: PA05 EIC[3] */ +#define BPM_BKUPPMUX_EIC4 (1 << 4) /* Bit 4: PA07 EIC[4] */ +#define BPM_BKUPPMUX_EIC5 (1 << 5) /* Bit 5: PC03 EIC[5] */ +#define BPM_BKUPPMUX_EIC6 (1 << 6) /* Bit 6: PC04 EIC[6] */ +#define BPM_BKUPPMUX_EIC7 (1 << 7) /* Bit 7: PC05 EIC[7] */ +#define BPM_BKUPPMUX_EIC8 (1 << 8) /* Bit 8: PC06 EIC[8] */ + +/* Input Output Retention Register */ + +#define BPM_IORET_RET (1 << 0) /* Bit 0: : Retention on I/O lines after wakeup */ + +/* Version Register */ + +#define BPM_VERSION_SHIFT (0) /* Bits 0-11: Version Number */ +#define BPM_VERSION_MASK (0xfff << BPM_VERSION_VERSION_SHIFT) +#define BPM_VERSION_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */ +#define BPM_VERSION_VARIANT_MASK (15 << BPM_VERSION_VARIANT_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_BPM_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_bscif.h b/nuttx/arch/arm/src/sam34/chip/sam4l_bscif.h new file mode 100644 index 000000000..a1663aa7a --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_bscif.h @@ -0,0 +1,316 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam4l_bscif.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_BSCIF_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_BSCIF_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* BSCIF register offsets ***************************************************************/ + +#define SAM_BSCIF_IER_OFFSET 0x0000 /* Interrupt Enable Register */ +#define SAM_BSCIF_IDR_OFFSET 0x0004 /* Interrupt Disable Register */ +#define SAM_BSCIF_IMR_OFFSET 0x0008 /* Interrupt Mask Register */ +#define SAM_BSCIF_ISR_OFFSET 0x000c /* Interrupt Status Register */ +#define SAM_BSCIF_ICR_OFFSET 0x0010 /* Interrupt Clear Register */ +#define SAM_BSCIF_PCLKSR_OFFSET 0x0014 /* Power and Clocks Status Register */ +#define SAM_BSCIF_UNLOCK_OFFSET 0x0018 /* Unlock Register */ +#define SAM_BSCIF_CSCR_OFFSET 0x001c /* Chip Specific Configuration Register */ +#define SAM_BSCIF_OSCCTRL32_OFFSET 0x0020 /* Oscillator 32 Control Register */ +#define SAM_BSCIF_RC32KCR_OFFSET 0x0024 /* 32kHz RC Oscillator Control Register */ +#define SAM_BSCIF_RC32KTUNE_OFFSET 0x0028 /* 32kHz RC Oscillator Tuning Register */ +#define SAM_BSCIF_BOD33CTRL_OFFSET 0x002c /* BOD33 Control Register */ +#define SAM_BSCIF_BOD33LEVEL_OFFSET 0x0030 /* BOD33 Level Register */ +#define SAM_BSCIF_BOD33SAMPLING_OFFSET 0x0034 /* BOD33 Sampling Control Register */ +#define SAM_BSCIF_BOD18CTRL_OFFSET 0x0038 /* BOD18 Control Register */ +#define SAM_BSCIF_BOD18LEVEL_OFFSET 0x003c /* BOD18 Level Register */ +#define SAM_BSCIF_BOD18SAMPLING_OFFSET 0x0040 /* BOD18 Sampling Control Register */ +#define SAM_BSCIF_VREGCR_OFFSET 0x0044 /* Voltage Regulator Configuration Register */ +#define SAM_BSCIF_RC1MCR_OFFSET 0x0058 /* 1MHz RC Clock Configuration Register */ +#define SAM_BSCIF_BGCTRL_OFFSET 0x0060 /* Bandgap Control Register */ +#define SAM_BSCIF_BGS_OFFSET 0x0064 /* Bandgap Status Register */ +#define SAM_BSCIF_BR_OFFSET(n) (0x0078+((n)<<2) /* 0x0078-0x0084 Backup register n=0..3 */ +#define SAM_BSCIF_BR0_OFFSET 0x0078 /* Backup register 0 */ +#define SAM_BSCIF_BR1_OFFSET 0x007c /* Backup register 1 */ +#define SAM_BSCIF_BR2_OFFSET 0x0080 /* Backup register 2 */ +#define SAM_BSCIF_BR3_OFFSET 0x0004 /* Backup register 3 */ +#define SAM_BSCIF_BRIFBVERSION_OFFSET 0x03e4 /* Backup Register Interface Version Register */ +#define SAM_BSCIF_BGREFIFBVERSION_OFFSET 0x03e8 /* BGREFIF Version Register */ +#define SAM_BSCIF_VREGIFGVERSION_OFFSET 0x03ec /* Voltage Regulator Version Register */ +#define SAM_BSCIF_BODIFCVERSION_OFFSET 0x03f0 /* BOD Version Register */ +#define SAM_BSCIF_RC32KIFBVERSION_OFFSET 0x03f4 /* 32kHz RC Oscillator Version Register */ +#define SAM_BSCIF_OSC32IFAVERSION_OFFSET 0x03f8 /* 32 kHz Oscillator Version Register */ +#define SAM_BSCIF_VERSION_OFFSET 0x03fc /* BSCIF Version Register */ + +/* BSCIF register adresses **************************************************************/ + +#define SAM_BSCIF_IER (SAM_BSCIF_BASE+SAM_BSCIF_IER_OFFSET) +#define SAM_BSCIF_IDR (SAM_BSCIF_BASE+SAM_BSCIF_IDR_OFFSET) +#define SAM_BSCIF_IMR (SAM_BSCIF_BASE+SAM_BSCIF_IMR_OFFSET) +#define SAM_BSCIF_ISR (SAM_BSCIF_BASE+SAM_BSCIF_ISR_OFFSET) +#define SAM_BSCIF_ICR (SAM_BSCIF_BASE+SAM_BSCIF_ICR_OFFSET) +#define SAM_BSCIF_PCLKSR (SAM_BSCIF_BASE+SAM_BSCIF_PCLKSR_OFFSET) +#define SAM_BSCIF_UNLOCK (SAM_BSCIF_BASE+SAM_BSCIF_UNLOCK_OFFSET) +#define SAM_BSCIF_CSCR (SAM_BSCIF_BASE+SAM_BSCIF_CSCR_OFFSET) +#define SAM_BSCIF_OSCCTRL32 (SAM_BSCIF_BASE+SAM_BSCIF_OSCCTRL32_OFFSET) +#define SAM_BSCIF_RC32KCR (SAM_BSCIF_BASE+SAM_BSCIF_RC32KCR_OFFSET) +#define SAM_BSCIF_RC32KTUNE (SAM_BSCIF_BASE+SAM_BSCIF_RC32KTUNE_OFFSET) +#define SAM_BSCIF_BOD33CTRL (SAM_BSCIF_BASE+SAM_BSCIF_BOD33CTRL_OFFSET) +#define SAM_BSCIF_BOD33LEVEL (SAM_BSCIF_BASE+SAM_BSCIF_BOD33LEVEL_OFFSET) +#define SAM_BSCIF_BOD33SAMPLING (SAM_BSCIF_BASE+SAM_BSCIF_BOD33SAMPLING_OFFSET) +#define SAM_BSCIF_BOD18CTRL (SAM_BSCIF_BASE+SAM_BSCIF_BOD18CTRL_OFFSET) +#define SAM_BSCIF_BOD18LEVEL (SAM_BSCIF_BASE+SAM_BSCIF_BOD18LEVEL_OFFSET) +#define SAM_BSCIF_BOD18SAMPLING (SAM_BSCIF_BASE+SAM_BSCIF_BOD18SAMPLING_OFFSET) +#define SAM_BSCIF_VREGCR (SAM_BSCIF_BASE+SAM_BSCIF_VREGCR_OFFSET) +#define SAM_BSCIF_RC1MCR (SAM_BSCIF_BASE+SAM_BSCIF_RC1MCR_OFFSET) +#define SAM_BSCIF_BGCTRL (SAM_BSCIF_BASE+SAM_BSCIF_BGCTRL_OFFSET) +#define SAM_BSCIF_BGS (SAM_BSCIF_BASE+SAM_BSCIF_BGS_OFFSET) +#define SAM_BSCIF_BR(n) (SAM_BSCIF_BASE+SAM_BSCIF_BR_OFFSET(n)) +#define SAM_BSCIF_BR0 (SAM_BSCIF_BASE+SAM_BSCIF_BR0_OFFSET) +#define SAM_BSCIF_BR1 (SAM_BSCIF_BASE+SAM_BSCIF_BR1_OFFSET) +#define SAM_BSCIF_BR2 (SAM_BSCIF_BASE+SAM_BSCIF_BR2_OFFSET) +#define SAM_BSCIF_BR3 (SAM_BSCIF_BASE+SAM_BSCIF_BR3_OFFSET) +#define SAM_BSCIF_BRIFBVERSION (SAM_BSCIF_BASE+SAM_BSCIF_BRIFBVERSION_OFFSET) +#define SAM_BSCIF_BGREFIFBVERSION (SAM_BSCIF_BASE+SAM_BSCIF_BGREFIFBVERSION_OFFSET) +#define SAM_BSCIF_VREGIFGVERSION (SAM_BSCIF_BASE+SAM_BSCIF_VREGIFGVERSION_OFFSET) +#define SAM_BSCIF_BODIFCVERSION (SAM_BSCIF_BASE+SAM_BSCIF_BODIFCVERSION_OFFSET) +#define SAM_BSCIF_RC32KIFBVERSION (SAM_BSCIF_BASE+SAM_BSCIF_RC32KIFBVERSION_OFFSET) +#define SAM_BSCIF_OSC32IFAVERSION (SAM_BSCIF_BASE+SAM_BSCIF_OSC32IFAVERSION_OFFSET) +#define SAM_BSCIF_VERSION (SAM_BSCIF_BASE+SAM_BSCIF_VERSION_OFFSET) + +/* BSCIF register bit definitions *******************************************************/ + +/* Interrupt Enable Register */ +/* Interrupt Disable Register */ +/* Interrupt Mask Register */ +/* Interrupt Status Register */ +/* Interrupt Clear Register */ + +#define BSCIF_INT_OSC32RDY (1 << 0) /* Bit 0 */ +#define BSCIF_INT_RC32KRDY (1 << 1) /* Bit 1 */ +#define BSCIF_INT_RC32KLOCK (1 << 2) /* Bit 2 */ +#define BSCIF_INT_RC32KREFE (1 << 3) /* Bit 3 */ +#define BSCIF_INT_RC32KSAT (1 << 4) /* Bit 4 */ +#define BSCIF_INT_BOD33DET (1 << 5) /* Bit 5 */ +#define BSCIF_INT_BOD18DET (1 << 6) /* Bit 6 */ +#define BSCIF_INT_BOD33SYNRDY (1 << 7) /* Bit 7 */ +#define BSCIF_INT_BOD18SYNRDY (1 << 8) /* Bit 8 */ +#define BSCIF_INT_SSWRDY (1 << 9) /* Bit 9: Buck voltage regulator has stopped switching */ +#define BSCIF_INT_VREGOK (1 << 10) /* Bit 10 */ +#define BSCIF_INT_LPBGRDY (1 << 12) /* Bit 12 */ +#define BSCIF_INT_AE (1 << 31) /* Bit 31 */ + +/* Power and Clocks Status Register */ + +#define BSCIF_PCLKSR_OSC32RDY (1 << 0) /* Bit 0 */ +#define BSCIF_PCLKSR_RC32KRDY (1 << 1) /* Bit 1 */ +#define BSCIF_PCLKSR_RC32KLOCK (1 << 2) /* Bit 2 */ +#define BSCIF_PCLKSR_RC32KREFE (1 << 3) /* Bit 3 */ +#define BSCIF_PCLKSR_RC32KSAT (1 << 4) /* Bit 4 */ +#define BSCIF_PCLKSR_BOD33DET (1 << 5) /* Bit 5 */ +#define BSCIF_PCLKSR_BOD18DET (1 << 6) /* Bit 6 */ +#define BSCIF_PCLKSR_BOD33SYNRDY (1 << 7) /* Bit 7 */ +#define BSCIF_PCLKSR_BOD18SYNRDY (1 << 8) /* Bit 8 */ +#define BSCIF_PCLKSR_SSWRDY (1 << 9) /* Bit 9: Buck voltage regulator has stopped switching */ +#define BSCIF_PCLKSR_VREGOK (1 << 10) /* Bit 10 */ +#define BSCIF_PCLKSR_RC1MRDY (1 << 11) /* Bit 11 */ +#define BSCIF_PCLKSR_LPBGRDY (1 << 12) /* Bit 12 */ + +/* Unlock Register */ + +#define BSCIF_UNLOCK_ADDR_SHIFT (0) /* Bits 0-9: Unlock Address */ +#define BSCIF_UNLOCK_ADDR_MASK (0x3ff << BSCIF_UNLOCK_ADDR_SHIFT) +# define BSCIF_UNLOCK_ADDR(n) ((n) << BSCIF_UNLOCK_ADDR_SHIFT) +#define BSCIF_UNLOCK_KEY_SHIFT (24) /* Bits 24-31: Unlock Key */ +#define BSCIF_UNLOCK_KEY_MASK (0xff << BSCIF_UNLOCK_KEY_SHIFT) +# define BSCIF_UNLOCK_KEY(n) ((n) << BSCIF_UNLOCK_KEY_SHIFT) + +/* Chip Specific Configuration Register */ + +/* Oscillator 32 Control Register */ + +#define BSCIF_OSCCTRL32_OSC32EN (1 << 0) /* Bit 0: 32 KHz Oscillator Enable */ +#define BSCIF_OSCCTRL32_EN32K (1 << 2) /* Bit 2: 32 KHz output Enable */ +#define BSCIF_OSCCTRL32_EN1K (1 << 3) /* Bit 3: 1 KHz output Enable */ +#define BSCIF_OSCCTRL32_MODE_SHIFT (8) /* Bits 8-10: Oscillator Mode */ +#define BSCIF_OSCCTRL32_MODE_MASK (7 << BSCIF_OSCCTRL32_MODE_SHIFT) +# define BSCIF_OSCCTRL32_MODE_EXTCLK (0 << BSCIF_OSCCTRL32_MODE_SHIFT) /* External clock */ +# define BSCIF_OSCCTRL32_MODE_XTAL (1 << BSCIF_OSCCTRL32_MODE_SHIFT) /* Crystal mode */ +# define BSCIF_OSCCTRL32_MODE_XTALAC (3 << BSCIF_OSCCTRL32_MODE_SHIFT) /* Crystal + amplitude controlled mode */ +# define BSCIF_OSCCTRL32_MODE_XTALHC (4 << BSCIF_OSCCTRL32_MODE_SHIFT) /* Crystal + high current mode */ +# define BSCIF_OSCCTRL32_MODE_XTALHCAC (5 << BSCIF_OSCCTRL32_MODE_SHIFT) /* Crystal + high current + amplitude controlled mode */ +#define BSCIF_OSCCTRL32_SELCURR_SHIFT (12) /* Bits 12-15: Current Selection */ +#define BSCIF_OSCCTRL32_SELCURR_MASK (15 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_50 (0 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_75 (1 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_100 (2 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_125 (3 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_150 (4 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_175 (5 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_200 (6 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_225 (7 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_250 (8 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_275 (9 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_300 (10 << BSCIF_OSCCTRL32_SELCURR_SHIFT) /* (recommended value) */ +# define BSCIF_OSCCTRL32_SELCURR_325 (11 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_350 (12 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_375 (13 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_400 (14 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +# define BSCIF_OSCCTRL32_SELCURR_425 (15 << BSCIF_OSCCTRL32_SELCURR_SHIFT) +#define BSCIF_OSCCTRL32_STARTUP_SHIFT (16) /* Bits 16-18: Oscillator Start-up Time */ +#define BSCIF_OSCCTRL32_STARTUP_MASK (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) +# define BSCIF_OSCCTRL32_STARTUP_0 (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) +# define BSCIF_OSCCTRL32_STARTUP_128 (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 128 1.1 ms */ +# define BSCIF_OSCCTRL32_STARTUP_8K (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 8192 72.3 ms */ +# define BSCIF_OSCCTRL32_STARTUP_16K (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 16384 143 ms */ +# define BSCIF_OSCCTRL32_STARTUP_64K (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 65536 570 ms */ +# define BSCIF_OSCCTRL32_STARTUP_128K (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 131072 1.1 s */ +# define BSCIF_OSCCTRL32_STARTUP_256K (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 262144 2.3 s */ +# define BSCIF_OSCCTRL32_STARTUP_512K (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 524288 4.6 s */ +#define BSCIF_OSCCTRL32_RESERVED (1 << 31) /* Bit 31: Reserved, must always be written as zero */ + +/* 32kHz RC Oscillator Control Register */ + +#define BSCIF_RC32KCR_EN (1 << 0) /* Bit 0: Enable as Generic clock source */ +#define BSCIF_RC32KCR_TCEN (1 << 1) /* Bit 1: Temperature Compensation Enable */ +#define BSCIF_RC32KCR_EN32K (1 << 2) /* Bit 2: Enable 32 KHz output */ +#define BSCIF_RC32KCR_EN1K (1 << 3) /* Bit 3: Enable 1 kHz output */ +#define BSCIF_RC32KCR_MODE (1 << 4) /* Bit 4: Mode Selection */ +#define BSCIF_RC32KCR_REF (1 << 5) /* Bit 5: Reference select */ +#define BSCIF_RC32KCR_FCD (1 << 7) /* Bit 7: Flash calibration done */ + +/* 32kHz RC Oscillator Tuning Register */ + +#define BSCIF_RC32KTUNE_FINE_SHIFT (0) /* Bits 0-5: Fine Value */ +#define BSCIF_RC32KTUNE_FINE_MASK (0x3f << BSCIF_RC32KTUNE_FINE_SHIFT) +#define BSCIF_RC32KTUNE_COARSE_SHIFT (16) /* Bits 16-22: Coarse value */ +#define BSCIF_RC32KTUNE_COARSE_MASK (0x7f << BSCIF_RC32KTUNE_COARSE_SHIFT) + +/* BOD33 Control Register */ +/* BOD18 Control Register */ + +#define BSCIF_BODCTRL_EN (1 << 0) /* Bit 0: Enable */ +#define BSCIF_BODCTRL_HYST (1 << 1) /* Bit 1: BOD Hysteresis */ +#define BSCIF_BODCTRL_ACTION_SHIFT (8) /* Bits 8-9: Action */ +# define BSCIF_BODCTRL_ACTION_RESET (1 << BSCIF_BODCTRL_ACTION_SHIFT) /* The BOD generates a reset */ +# define BSCIF_BODCTRL_ACTION_INTR (2 << BSCIF_BODCTRL_ACTION_SHIFT) /* The BOD generates an interrupt */ +#define BSCIF_BODCTRL_MODE (1 << 0) /* Bit 0: Operation modes */ +#define BSCIF_BODCTRL_FCD (1 << 0) /* Bit 0: BOD Fuse Calibration Done */ +#define BSCIF_BODCTRL_SFV (1 << 0) /* Bit 0: BOD Control Register Store Final Value */ + +/* BOD33 Level Register */ +/* BOD18 Level Register */ + +#define BSCIF_BODLEVEL_CEN (1 << 0) /* Bit 0: Clock Enable */ +#define BSCIF_BODLEVEL_CSSEL (1 << 1) /* Bit 1: Clock Source Select */ +#define BSCIF_BODLEVEL_PSEL_SHIFT (8) /* Bits 8-11: Prescaler Select */ +#define BSCIF_BODLEVEL_PSEL_MASK (15 << BSCIF_BODLEVEL_PSEL_SHIFT) + +/* BOD33 Sampling Control Register */ +/* BOD18 Sampling Control Register */ + +#define BSCIF_BODSAMPLING_VAL_SHIFT (0) /* Bits 0-5: BOD Value */ +#define BSCIF_BODSAMPLING_VAL_MASK (0x3f << BSCIF_BODSAMPLING_VAL_SHIFT) +#define BSCIF_BODSAMPLING_RANGE (1 << 31) /* Bit 31: BOD Threshold Range (available for BOD18 only */ + +/* Voltage Regulator Configuration Register */ + +#define BSCIF_VREGCR_DIS (1 << 0) /* Bit 0: Voltage Regulator disable */ +#define BSCIF_VREGCR_SSG (1 << 8) /* Bit 8: Spread Spectrum Generator Enable */ +#define BSCIF_VREGCR_SSW (1 << 9) /* Bit 9: Stop Switching */ +#define BSCIF_VREGCR_SSWEVT (1 << 10) /* Bit 10: Stop Switching On Event Enable */ +#define BSCIF_VREGCR_SFV (1 << 31) /* Bit 31: Store Final Value */ + +/* 1MHz RC Clock Configuration Register */ + +#define BSCIF_RC1MCR_FCD (1 << 0) /* Bit 0: Flash Calibration Done */ +#define BSCIF_RC1MCR_CLKOEN (1 << 7) /* Bit 7: 1MHz RC Osc Clock Output Enable */ +#define BSCIF_RC1MCR_CLKCAL_SHIFT (8) /* Bits 8-12: 1MHz RC Osc Calibration */ +#define BSCIF_RC1MCR_CLKCAL_MASK (31 << BSCIF_RC1MCR_CLKCAL_SHIFT) + +/* Bandgap Control Register */ + +#define BSCIF_BGCTRL_ADCISEL_SHIFT (0) /* Bits 0-1: ADC Input Selection */ +#define BSCIF_BGCTRL_ADCISEL_MASK (3 << BSCIF_BGCTRL_ADCISEL_SHIFT) +#define BSCIF_BGCTRL_TSEN (1 << 8) + +/* Bandgap Status Register */ + +#define BSCIF_BGS_BGBUFRDY_SHIFT (0) /* Bits 0-7: Bandgap Buffer Ready */ +#define BSCIF_BGS_BGBUFRDY_MASK (0xff << BSCIF_BGS_BGBUFRDY_SHIFT) +#define BSCIF_BGS_BGRDY (1 << 16) /* Bit 16: Bandgap Voltage Reference Ready */ +#define BSCIF_BGS_LPBGRDY (1 << 17) /* Bit 17: Low Power Bandgap Voltage Reference Ready */ +#define BSCIF_BGS_VREF_SHIFT (18) /* Bits 18-19: Voltage Reference Used by the System */ +#define BSCIF_BGS_VREF_MASK (3 << BSCIF_BGS_VREF_SHIFT) + +/* 0x0078-0x0084 Backup register n=0..3 (32-bit data) */ + +/* Backup Register Interface Version Register */ +/* BGREFIF Version Register */ +/* Voltage Regulator Version Register */ +/* BOD Version Register */ +/* 32kHz RC Oscillator Version Register */ +/* 32 kHz Oscillator Version Register */ +/* BSCIF Version Register */ + +#define BSCIF_VERSION_SHIFT (0) /* Bits 0-11: Version Number */ +#define BSCIF_VERSION_MASK (0xfff << BSCIF_VERSION_VERSION_SHIFT) +#define BSCIF_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */ +#define BSCIF_VARIANT_MASK (15 << BSCIF_VARIANT_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_BSCIF_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_flashcalw.h b/nuttx/arch/arm/src/sam34/chip/sam4l_flashcalw.h index d2503aa18..6902578d7 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam4l_flashcalw.h +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_flashcalw.h @@ -80,7 +80,7 @@ #define SAM_FLASHCALW_FCMD (SAM_FLASHCALW_BASE+SAM_FLASHCALW_FCMD_OFFSET) #define SAM_FLASHCALW_FSR (SAM_FLASHCALW_BASE+SAM_FLASHCALW_FSR_OFFSET) #define SAM_FLASHCALW_FPR (SAM_FLASHCALW_BASE+SAM_FLASHCALW_FPR_OFFSET) -#define SAM_FLASHCALW_FSR (SAM_FLASHCALW_BASE+SAM_FLASHCALW_FSR_OFFSET) +#define SAM_FLASHCALW_FVR (SAM_FLASHCALW_BASE+SAM_FLASHCALW_FVR_OFFSET) #define SAM_FLASHCALW_FGPFRHI (SAM_FLASHCALW_BASE+SAM_FLASHCALW_FGPFRHI_OFFSET) #define SAM_FLASHCALW_FGPFRLO (SAM_FLASHCALW_BASE+SAM_FLASHCALW_FGPFRLO_OFFSET) @@ -131,6 +131,7 @@ #define FLASHCALW_FCMD_PAGEN_MASK (0xffff << FLASHCALW_FCMD_PAGEN_SHIFT) #define FLASHCALW_FCMD_KEY_SHIFT (14) /* Bits 24-31: Write protection key */ #define FLASHCALW_FCMD_KEY_MASK (0xff << FLASHCALW_FCMD_KEY_SHIFT) +# define FLASHCALW_FCMD_KEY (0xa5 << FLASHCALW_FCMD_KEY_SHIFT) /* Flash Status Register */ @@ -161,7 +162,6 @@ #define FLASHCALW_FSR_LOCK15 (1 << 31) /* Bit 31: Lock Region 15 Lock Status */ /* Flash Parameter Register */ -#define FLASHCALW_FPR_ #define FLASHCALW_FPR_FSZ_SHIFT (0) /* Bits 0-3: Flash Size */ #define FLASHCALW_FPR_FSZ_MASK (15 << FLASHCALW_FPR_FSZ_SHIFT) @@ -333,6 +333,36 @@ #define FLASH_CMD_HSEN 16 /* High Speed Mode Enable */ #define FLASH_CMD_HSDIS 17 /* High Speed Mode Disable */ +/* Maximum CPU frequency for 0 and 1 FLASH wait states (FWS) in various modes + * (Table 42-30 in the big data sheet). + * + * ------- ------------------- ---------- ---------- + * Power Flash Read Mode Flash Maximum + * Sclaing Wait Operating + * Mode HSEN HSDIS FASTWKUP States Frequency + * ------- ---- ----- -------- ---------- ---------- + * PS0 X X 1 12MHz + * " " X 0 18MHz + * " " X 1 36MHz + * PS1 X X 1 12MHz + * " " X 0 8MHz + * " " X 1 12MHz + * PS2 X 0 24Mhz + * " " X 1 48MHz + * ------- ---- ----- -------- ---------- ---------- + */ + +#define FLASH_MAXFREQ_PS0_HSDIS_FASTWKUP_FWS1 (12000000ul) +#define FLASH_MAXFREQ_PS0_HSDIS_FWS0 (18000000ul) +#define FLASH_MAXFREQ_PS0_HSDIS_FWS1 (36000000ul) + +#define FLASH_MAXFREQ_PS1_HSDIS_FASTWKUP_FWS1 (12000000ul) +#define FLASH_MAXFREQ_PS1_HSDIS_FWS0 (8000000ul) +#define FLASH_MAXFREQ_PS1_HSDIS_FWS1 (12000000ul) + +#define FLASH_MAXFREQ_PS2_HSEN_FWS0 (24000000ul) +#define FLASH_MAXFREQ_PS2_HSEN_FWS1 (48000000ul) + /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_picouart.h b/nuttx/arch/arm/src/sam34/chip/sam4l_picouart.h new file mode 100644 index 000000000..ea7c42864 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_picouart.h @@ -0,0 +1,121 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam4l_picouart.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_PICOUART_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_PICOUART_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* PICOUART register offsets ************************************************************/ + +#define SAM_PICOUART_CR_OFFSET 0x0000 /* Control Register */ +#define SAM_PICOUART_CFG_OFFSET 0x0004 /* Configuration Register */ +#define SAM_PICOUART_SR_OFFSET 0x0008 /* Status Register */ +#define SAM_PICOUART_RHR_OFFSET 0x000c /* Receive Holding Register */ +#define SAM_PICOUART_VERSION_OFFSET 0x0020 /* Version Register */ + +/* PICOUART register adresses ***********************************************************/ + +#define SAM_PICOUART_CR_OFFSET 0x0000 /* Control Register */ +#define SAM_PICOUART_CR_OFFSET 0x0000 /* Control Register */ +#define SAM_PICOUART_CFG_OFFSET 0x0004 /* Configuration Register */ +#define SAM_PICOUART_CFG_OFFSET 0x0004 /* Configuration Register */ +#define SAM_PICOUART_SR_OFFSET 0x0008 /* Status Register */ +#define SAM_PICOUART_SR_OFFSET 0x0008 /* Status Register */ +#define SAM_PICOUART_RHR_OFFSET 0x000c /* Receive Holding Register */ +#define SAM_PICOUART_RHR_OFFSET 0x000c /* Receive Holding Register */ +#define SAM_PICOUART_VERSION_OFFSET 0x0020 /* Version Register */ +#define SAM_PICOUART_VERSION_OFFSET 0x0020 /* Version Register */ + +/* PICOUART register bit definitions ****************************************************/ + +/* Control Register */ + +#define PICOUART_CR_EN (1 << 0) /* Bit 0: Enable */ +#define PICOUART_CR_DIS (1 << 1) /* Bit 1: Disable */ + +/* Configuration Register */ + +#define PICOUART_CFG_SOURCE_SHIFT (0) /* Bit 0-1: Source Enable Mode */ +#define PICOUART_CFG_SOURCE_MASK (3 << PICOUART_CFG_SOURCE_SHIFT) +# define PICOUART_CFG_SOURCE_WE (0 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up and event disable */ +# define PICOUART_CFG_SOURCE_WESB (1 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up or event enable on start bit detection */ +# define PICOUART_CFG_SOURCE_WEFF (2 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up or event enable on full frame reception */ +# define PICOUART_CFG_SOURCE_WECH (3 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up or event enable on character recognition */ +#define PICOUART_CFG_ACTION (1 << 0) /* Bit 0: Action to perform */ +#define PICOUART_CFG_MATCH_SHIFT (8) /* Bit 8-15: Data Match */ +#define PICOUART_CFG_MATCH_SHIFT (8) /* Bit 8-15: Data Match */ +#define PICOUART_CFG_MATCH_MASK (0xff << PICOUART_CFG_MATCH_SHIFT) + +/* Status Register */ + +#define PICOUART_SR_EN (1 << 0) /* Bit 0: Enable Status */ +#define PICOUART_SR_DRDY (1 << 1) /* Bit 1: Data Ready */ + +/* Receive Holding Register */ + +#define PICOUART_RHR_MASK 0xff + +/* Version Register */ + +#define PICOUART_VERSION_SHIFT (0) /* Bits 0-11: Macrocell version number */ +#define PICOUART_VERSION_MASK (0xfff << PICOUART_VERSION_SHIFT) +#define PICOUART_VARIANT_SHIFT (16) /* Bits 16-18: Reserved */ +#define PICOUART_VARIANT_MASK (7 << PICOUART_VARIANT_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_PICOUART_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_pinmap.h b/nuttx/arch/arm/src/sam34/chip/sam4l_pinmap.h index c4babee65..68f4b2074 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam4l_pinmap.h +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_pinmap.h @@ -48,7 +48,7 @@ /************************************************************************************ * Definitions ************************************************************************************/ -/* Alternate Pin Functions. +/* Alternate Pin Functions. * * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. * Drivers, however, will use the pin selection without the numeric suffix. diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_pm.h b/nuttx/arch/arm/src/sam34/chip/sam4l_pm.h index ba78b3a95..86a55af8d 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam4l_pm.h +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_pm.h @@ -145,7 +145,7 @@ /* CPU Mask Register Bit-field Definitions */ -#define PM_CPUMASK_OCD (1 << 0) /* Bit 0: OCD */ +#define PM_CPUMASK_OCD (1 << 0) /* Bit 0: On-Chip Debug */ /* HSB Mask Register Bit-field Definitions */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_scif.h b/nuttx/arch/arm/src/sam34/chip/sam4l_scif.h new file mode 100644 index 000000000..d6f6661e6 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_scif.h @@ -0,0 +1,432 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam4l_scif.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_SCIF_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_SCIF_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* SCIF register offsets ****************************************************************/ + +#define SAM_SCIF_IER_OFFSET 0x0000 /* Interrupt Enable Register */ +#define SAM_SCIF_IDR_OFFSET 0x0004 /* Interrupt Disable Register */ +#define SAM_SCIF_IMR_OFFSET 0x0008 /* Interrupt Mask Register */ +#define SAM_SCIF_ISR_OFFSET 0x000c /* Interrupt Status Register */ +#define SAM_SCIF_ICR_OFFSET 0x0010 /* Interrupt Clear Register */ +#define SAM_SCIF_PCLKSR_OFFSET 0x0014 /* Power and Clocks Status Register */ +#define SAM_SCIF_UNLOCK_OFFSET 0x0018 /* Unlock Register */ +#define SAM_SCIF_CSCR_OFFSET 0x001c /* Chip Specific Configuration Register */ +#define SAM_SCIF_OSCCTRL0_OFFSET 0x0020 /* Oscillator Control Register */ +#define SAM_SCIF_PLL0_OFFSET 0x0024 /* PLL0 Control Register */ +#define SAM_SCIF_DFLL0CONF_OFFSET 0x0028 /* DFLL0 Config Register */ +#define SAM_SCIF_DFLL0VAL_OFFSET 0x002c /* DFLL Value Register */ +#define SAM_SCIF_DFLL0MUL_OFFSET 0x0030 /* DFLL0 Multiplier Register */ +#define SAM_SCIF_DFLL0STEP_OFFSET 0x0034 /* DFLL0 Step Register */ +#define SAM_SCIF_DFLL0SSG_OFFSET 0x0038 /* DFLL0 Spread Spectrum Generator Control Register */ +#define SAM_SCIF_DFLL0RATIO_OFFSET 0x003c /* DFLL0 Ratio Register */ +#define SAM_SCIF_DFLL0SYNC_OFFSET 0x0040 /* DFLL0 Synchronization Register */ +#define SAM_SCIF_RCCR_OFFSET 0x0044 /* System RC Oscillator Calibration Register */ +#define SAM_SCIF_RCFASTCFG_OFFSET 0x0048 /* 4/8/12MHz RC Oscillator Configuration Register */ +#define SAM_SCIF_RCFASTSR_OFFSET 0x004c /* 4/8/12MHz RC Oscillator Status Register */ +#define SAM_SCIF_RC80MCR_OFFSET 0x0050 /* 80MHz RC Oscillator Register */ +#define SAM_SCIF_HRPCR_OFFSET 0x0064 /* High Resolution Prescaler Control Register */ +#define SAM_SCIF_FPCR_OFFSET 0x0068 /* Fractional Prescaler Control Register */ +#define SAM_SCIF_FPMUL_OFFSET 0x006c /* Fractional Prescaler Multiplier Register */ +#define SAM_SCIF_FPDIV_OFFSET 0x0070 /* Fractional Prescaler DIVIDER Register */ +#define SAM_SCIF_GCCTRL0_OFFSET 0x0074 /* Generic Clock Control0 */ +#define SAM_SCIF_GCCTRL1_OFFSET 0x0078 /* Generic Clock Control1 */ +#define SAM_SCIF_GCCTRL2_OFFSET 0x007c /* Generic Clock Control2 */ +#define SAM_SCIF_GCCTRL3_OFFSET 0x0080 /* Generic Clock Control3 */ +#define SAM_SCIF_GCCTRL4_OFFSET 0x0084 /* Generic Clock Control4 */ +#define SAM_SCIF_GCCTRL5_OFFSET 0x0088 /* Generic Clock Control5 */ +#define SAM_SCIF_GCCTRL6_OFFSET 0x008c /* Generic Clock Control6 */ +#define SAM_SCIF_GCCTRL7_OFFSET 0x0090 /* Generic Clock Control7 */ +#define SAM_SCIF_GCCTRL8_OFFSET 0x0094 /* Generic Clock Control8 */ +#define SAM_SCIF_GCCTRL9_OFFSET 0x0098 /* Generic Clock Control9 */ +#define SAM_SCIF_GCCTRL10_OFFSET 0x009c /* Generic Clock Control10 */ +#define SAM_SCIF_GCCTRL11_OFFSET 0x00a0 /* Generic Clock Control11 */ +#define SAM_SCIF_RCFASTVERSION_OFFSET 0x03d8 /* 4/8/12MHz RC Oscillator Version Register */ +#define SAM_SCIF_GCLKPRESCVERSION_OFFSET 0x03dc /* Generic Clock Prescaler Version Register */ +#define SAM_SCIF_PLLIFAVERSION_OFFSET 0x03e0 /* PLL Version Register */ +#define SAM_SCIF_OSCIFAVERSION_OFFSET 0x03e4 /* Oscillator0 Version Register */ +#define SAM_SCIF_DFLLIFBVERSION_OFFSET 0x03e8 /* DFLL Version Register */ +#define SAM_SCIF_RCOSCIFAVERSION_OFFSET 0x03ec /* System RC Oscillator Version Register */ +#define SAM_SCIF_RC80MVERSION_OFFSET 0x03f4 /* 80MHz RC Oscillator Version Register */ +#define SAM_SCIF_GCLKVERSION_OFFSET 0x03f8 /* Generic Clock Version Register */ +#define SAM_SCIF_VERSION_OFFSET 0x03fc /* SCIF Version Register */ + +/* SCIF register adresses ***************************************************************/ + +#define SAM_SCIF_IER (SAM_SCIF_BASE+SAM_SCIF_IER_OFFSET) +#define SAM_SCIF_IDR (SAM_SCIF_BASE+SAM_SCIF_IDR_OFFSET) +#define SAM_SCIF_IMR (SAM_SCIF_BASE+SAM_SCIF_IMR_OFFSET) +#define SAM_SCIF_ISR (SAM_SCIF_BASE+SAM_SCIF_ISR_OFFSET) +#define SAM_SCIF_ICR (SAM_SCIF_BASE+SAM_SCIF_ICR_OFFSET) +#define SAM_SCIF_PCLKSR (SAM_SCIF_BASE+SAM_SCIF_PCLKSR_OFFSET) +#define SAM_SCIF_UNLOCK (SAM_SCIF_BASE+SAM_SCIF_UNLOCK_OFFSET) +#define SAM_SCIF_CSCR (SAM_SCIF_BASE+SAM_SCIF_CSCR_OFFSET) +#define SAM_SCIF_OSCCTRL0 (SAM_SCIF_BASE+SAM_SCIF_OSCCTRL0_OFFSET) +#define SAM_SCIF_PLL0 (SAM_SCIF_BASE+SAM_SCIF_PLL0_OFFSET) +#define SAM_SCIF_DFLL0CONF (SAM_SCIF_BASE+SAM_SCIF_DFLL0CONF_OFFSET) +#define SAM_SCIF_DFLL0VAL (SAM_SCIF_BASE+SAM_SCIF_DFLL0VAL_OFFSET) +#define SAM_SCIF_DFLL0MUL (SAM_SCIF_BASE+SAM_SCIF_DFLL0MUL_OFFSET) +#define SAM_SCIF_DFLL0STEP (SAM_SCIF_BASE+SAM_SCIF_DFLL0STEP_OFFSET) +#define SAM_SCIF_DFLL0SSG (SAM_SCIF_BASE+SAM_SCIF_DFLL0SSG_OFFSET) +#define SAM_SCIF_DFLL0RATIO (SAM_SCIF_BASE+SAM_SCIF_DFLL0RATIO_OFFSET) +#define SAM_SCIF_DFLL0SYNC (SAM_SCIF_BASE+SAM_SCIF_DFLL0SYNC_OFFSET) +#define SAM_SCIF_RCCR (SAM_SCIF_BASE+SAM_SCIF_RCCR_OFFSET) +#define SAM_SCIF_RCFASTCFG (SAM_SCIF_BASE+SAM_SCIF_RCFASTCFG_OFFSET) +#define SAM_SCIF_RCFASTSR (SAM_SCIF_BASE+SAM_SCIF_RCFASTSR_OFFSET) +#define SAM_SCIF_RC80MCR (SAM_SCIF_BASE+SAM_SCIF_RC80MCR_OFFSET) +#define SAM_SCIF_HRPCR (SAM_SCIF_BASE+SAM_SCIF_HRPCR_OFFSET) +#define SAM_SCIF_FPCR (SAM_SCIF_BASE+SAM_SCIF_FPCR_OFFSET) +#define SAM_SCIF_FPMUL (SAM_SCIF_BASE+SAM_SCIF_FPMUL_OFFSET) +#define SAM_SCIF_FPDIV (SAM_SCIF_BASE+SAM_SCIF_FPDIV_OFFSET) +#define SAM_SCIF_GCCTRL0 (SAM_SCIF_BASE+SAM_SCIF_GCCTRL0_OFFSET) +#define SAM_SCIF_GCCTRL1 (SAM_SCIF_BASE+SAM_SCIF_GCCTRL1_OFFSET) +#define SAM_SCIF_GCCTRL2 (SAM_SCIF_BASE+SAM_SCIF_GCCTRL2_OFFSET) +#define SAM_SCIF_GCCTRL3 (SAM_SCIF_BASE+SAM_SCIF_GCCTRL3_OFFSET) +#define SAM_SCIF_GCCTRL4 (SAM_SCIF_BASE+SAM_SCIF_GCCTRL4_OFFSET) +#define SAM_SCIF_GCCTRL5 (SAM_SCIF_BASE+SAM_SCIF_GCCTRL5_OFFSET) +#define SAM_SCIF_GCCTRL6 (SAM_SCIF_BASE+SAM_SCIF_GCCTRL6_OFFSET) +#define SAM_SCIF_GCCTRL7 (SAM_SCIF_BASE+SAM_SCIF_GCCTRL7_OFFSET) +#define SAM_SCIF_GCCTRL8 (SAM_SCIF_BASE+SAM_SCIF_GCCTRL8_OFFSET) +#define SAM_SCIF_GCCTRL9 (SAM_SCIF_BASE+SAM_SCIF_GCCTRL9_OFFSET) +#define SAM_SCIF_GCCTRL10 (SAM_SCIF_BASE+SAM_SCIF_GCCTRL10_OFFSET) +#define SAM_SCIF_GCCTRL11 (SAM_SCIF_BASE+SAM_SCIF_GCCTRL11_OFFSET) +#define SAM_SCIF_RCFASTVERSION (SAM_SCIF_BASE+SAM_SCIF_RCFASTVERSION_OFFSET) +#define SAM_SCIF_GCLKPRESCVERSION (SAM_SCIF_BASE+SAM_SCIF_GCLKPRESCVERSION_OFFSET) +#define SAM_SCIF_PLLIFAVERSION (SAM_SCIF_BASE+SAM_SCIF_PLLIFAVERSION_OFFSET) +#define SAM_SCIF_OSCIFAVERSION (SAM_SCIF_BASE+SAM_SCIF_OSCIFAVERSION_OFFSET) +#define SAM_SCIF_DFLLIFBVERSION (SAM_SCIF_BASE+SAM_SCIF_DFLLIFBVERSION_OFFSET) +#define SAM_SCIF_RCOSCIFAVERSION (SAM_SCIF_BASE+SAM_SCIF_RCOSCIFAVERSION_OFFSET) +#define SAM_SCIF_RC80MVERSION (SAM_SCIF_BASE+SAM_SCIF_RC80MVERSION_OFFSET) +#define SAM_SCIF_GCLKVERSION (SAM_SCIF_BASE+SAM_SCIF_GCLKVERSION_OFFSET) +#define SAM_SCIF_VERSION (SAM_SCIF_BASE+SAM_SCIF_VERSION_OFFSET) + +/* SCIF register bit definitions ********************************************************/ + +/* Interrupt Enable Register */ +/* Interrupt Disable Register */ +/* Interrupt Mask Register */ +/* Interrupt Status Register */ +/* Interrupt Clear Register */ +/* Power and Clocks Status Register */ + +#define SCIF_INT_OSC0RDY (1 << 0) /* Bit 0: OSC0 Ready */ +#define SCIF_INT_DFLL0LOCKC (1 << 1) /* Bit 1: DFLL0 Locked on Coarse Value */ +#define SCIF_INT_DFLL0LOCKF (1 << 2) /* Bit 2: DFLL0 Locked on Fine Value */ +#define SCIF_INT_DFLL0RDY (1 << 3) /* Bit 3: DFLL0 Synchronization Ready */ +#define SCIF_INT_DFLL0RCS (1 << 4) /* Bit 4: DFLL0 Reference Clock Stopped */ +#define SCIF_INT_PLL0LOCK (1 << 6) /* Bit 6: PLL0 Locked on Accurate value */ +#define SCIF_INT_PLL0LOCKLOST (1 << 7) /* Bit 7: PLL0 lock lost value */ +#define SCIF_INT_RCFASTLOCK (1 << 13) /* Bit 13: RCFAST Locked on Accurate value */ +#define SCIF_INT_RCFASTLOCKLOST (1 << 14) /* Bit 14: RCFAST lock lost value */ + +/* Unlock Register */ + +#define SCIF_UNLOCK_ADDR_SHIFT (0) /* Bits 0-9: Unlock Address */ +#define SCIF_UNLOCK_ADDR_MASK (0x3ff << SCIF_UNLOCK_ADDR_SHIFT) +# define SCIF_UNLOCK_ADDR(n) ((n) << SCIF_UNLOCK_ADDR_SHIFT) +#define SCIF_UNLOCK_KEY_SHIFT (24) /* Bits 24-31: Unlock Key */ +#define SCIF_UNLOCK_KEY_MASK (0xff << SCIF_UNLOCK_KEY_SHIFT) +# define SCIF_UNLOCK_KEY(n) ((n) << SCIF_UNLOCK_KEY_SHIFT) + +/* Chip Specific Configuration Register */ + +/* Oscillator Control Register */ + +#define SCIF_OSCCTRL0_MODE (1 << 0) /* Bit 0: Oscillator Mode */ +#define SCIF_OSCCTRL0_GAIN_SHIFT (1) /* Bits 1-2: Gain */ +#define SCIF_OSCCTRL0_GAIN_MASK (3 << SCIF_OSCCTRL0_GAIN_SHIFT) +# define SCIF_OSCCTRL0_GAIN(n) ((n) << SCIF_OSCCTRL0_GAIN_SHIFT) +#define SCIF_OSCCTRL0_AGC (1 << 3) /* Bit 3: Automatic Gain Control */ +#define SCIF_OSCCTRL0_STARTUP_SHIFT (9) /* Bits 8-11: Oscillator Start-up Time */ +#define SCIF_OSCCTRL0_STARTUP_MASK (15 << SCIF_OSCCTRL0_STARTUP_SHIFT) +# define SCIF_OSCCTRL0_STARTUP_0 (0 << SCIF_OSCCTRL0_STARTUP_SHIFT) +# define SCIF_OSCCTRL0_STARTUP_64 (1 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 64 557 us */ +# define SCIF_OSCCTRL0_STARTUP_128 (2 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 128 1.1 ms */ +# define SCIF_OSCCTRL0_STARTUP_2K (3 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 2048 18 ms */ +# define SCIF_OSCCTRL0_STARTUP_4K (4 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 4096 36 ms */ +# define SCIF_OSCCTRL0_STARTUP_8K (5 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 8192 71 ms */ +# define SCIF_OSCCTRL0_STARTUP_16K (6 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 16384 143 ms */ +# define SCIF_OSCCTRL0_STARTUP_32K (7 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 32768 285 ms */ +# define SCIF_OSCCTRL0_STARTUP_4 (8 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 4 35 us */ +# define SCIF_OSCCTRL0_STARTUP_8 (9 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 8 70 us */ +# define SCIF_OSCCTRL0_STARTUP_16 (10 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 16 139 us */ +# define SCIF_OSCCTRL0_STARTUP_32 (11 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 32 278 us */ +# define SCIF_OSCCTRL0_STARTUP_256 (12 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 256 2.2 ms */ +# define SCIF_OSCCTRL0_STARTUP_512 (13 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 512 4.5 ms */ +# define SCIF_OSCCTRL0_STARTUP_1K (14 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 1024 8.9 ms */ +# define SCIF_OSCCTRL0_STARTUP_32K2 (15 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 2768 285 ms */ +#define SCIF_OSCCTRL0_OSCEN (1 << 16) /* Bit 16: Oscillator Enable */ + +/* PLL0 Control Register */ + +#define SCIF_PLL0_PLLEN (1 << 0) /* Bit 0: PLL Enable */ +#define SCIF_PLL0_PLLOSC_SHIFT (1) /* Bits 1-2: PLL Oscillator Select */ +#define SCIF_PLL0_PLLOSC_MASK (3 << SCIF_PLL0_PLLOSC_SHIFT) +# define SCIF_PLL0_PLLOSC_OSC0 (0 << SCIF_PLL0_PLLOSC_SHIFT) /* Output clock from Oscillator0 */ +# define SCIF_PLL0_PLLOSC_GCLK9 (1 << SCIF_PLL0_PLLOSC_SHIFT) /* Generic clock 9 */ +#define SCIF_PLL0_PLLOPT_SHIFT (3) /* Bits 3-5: PLL Option */ +#define SCIF_PLL0_PLLOPT_MASK (7 << SCIF_PLL0_PLLOPT_SHIFT) +# define SCIF_PLL0_PLLOPT_FVO (1 << SCIF_PLL0_PLLOPT_SHIFT) /* Selects the VCO frequency range (fvco) */ +# define SCIF_PLL0_PLLOPT_DIV2 (2 << SCIF_PLL0_PLLOPT_SHIFT) /* Divides the output frequency by 2 */ +# define SCIF_PLL0_PLLOPT_WBM (4 << SCIF_PLL0_PLLOPT_SHIFT) /* Wide-Bandwidth mode */ +#define SCIF_PLL0_PLLDIV_SHIFT (8) /* Bits 8-11: PLL Division Factor */ +#define SCIF_PLL0_PLLDIV_MASK (15 << SCIF_PLL0_PLLDIV_SHIFT) +#define SCIF_PLL0_PLLMUL_SHIFT (16) /* Bits 16-19: PLL Multiply Factor */ +#define SCIF_PLL0_PLLMUL_MASK (15 << SCIF_PLL0_PLLMUL_SHIFT) +#define SCIF_PLL0_PLLCOUNT_SHIFT (24) /* Bits 24-24: PLL Count */ +#define SCIF_PLL0_PLLCOUNT_MASK (63 << SCIF_PLL0_PLLCOUNT_SHIFT) +# define SCIF_PLL0_PLLCOUNT_MAX (63 << SCIF_PLL0_PLLCOUNT_SHIFT) + +/* PLL0 operates in two frequency ranges as determined by SCIF_PLL0_PLLOPT_FVO: + * + * 0: 80MHz < fvco < 180MHz + * 1: 160MHz < fvco < 240MHz + * + * These ranges and recommend threshold value are defined below: + */ + +#define SCIF_PLL0_VCO_RANGE1_MINFREQ 160000000 +#define SCIF_PLL0_VCO_RANGE1_MAXFREQ 240000000 +#define SCIF_PLL0_VCO_RANGE0_MINFREQ 80000000 +#define SCIF_PLL0_VCO_RANGE0_MAXFREQ 180000000 + +#define SAM_PLL0_VCO_RANGE_THRESHOLD \ + ((SCIF_PLL0_VCO_RANGE1_MINFREQ + SCIF_PLL0_VCO_RANGE0_MAXFREQ) >> 1) + +/* DFLL0 Config Register */ + +#define SCIF_DFLL0CONF_EN (1 << 0) /* Bit 0: Enable */ +#define SCIF_DFLL0CONF_MODE (1 << 1) /* Bit 1: Mode Selection */ +#define SCIF_DFLL0CONF_STABLE (1 << 2) /* Bit 2: Stable DFLL Frequency */ +#define SCIF_DFLL0CONF_LLAW (1 << 3) /* Bit 3: Lose Lock After Wake */ +#define SCIF_DFLL0CONF_CCDIS (1 << 5) /* Bit 5: Chill Cycle Disable */ +#define SCIF_DFLL0CONF_QLDIS (1 << 6) /* Bit 6: Quick Lock Disable */ +#define SCIF_DFLL0CONF_RANGE_SHIFT (16) /* Bits 16-17: Range Value */ +#define SCIF_DFLL0CONF_RANGE_MASK (3 << SCIF_DFLL0CONF_RANGE_SHIFT) +# define SCIF_DFLL0CONF_RANGE(n) ((n) << SCIF_DFLL0CONF_RANGE_SHIFT) +# define SCIF_DFLL0CONF_RANGE0 (0 << SCIF_DFLL0CONF_RANGE_SHIFT) /* 96-150MHz */ +# define SCIF_DFLL0CONF_RANGE1 (1 << SCIF_DFLL0CONF_RANGE_SHIFT) /* 50-110MHz */ +# define SCIF_DFLL0CONF_RANGE2 (2 << SCIF_DFLL0CONF_RANGE_SHIFT) /* 25-55MHz */ +# define SCIF_DFLL0CONF_RANGE3 (3 << SCIF_DFLL0CONF_RANGE_SHIFT) /* 20-30MHz */ +#define SCIF_DFLL0CONF_FCD (1 << 23) /* Bit 23: Fuse Calibration Done */ +#define SCIF_DFLL0CONF_CALIB_SHIFT (24) /* Bits 24-27: Calibration Value */ +#define SCIF_DFLL0CONF_CALIB_MASK (15 << SCIF_DFLL0CONF_CALIB_SHIFT) + +/* Min/max frequencies for each DFLL0 range */ + +#define SCIF_DFLL0CONF_MAX_RANGE0 (150000000) +#define SCIF_DFLL0CONF_MIN_RANGE0 (96000000) +#define SCIF_DFLL0CONF_MAX_RANGE1 (110000000) +#define SCIF_DFLL0CONF_MIN_RANGE1 (50000000) +#define SCIF_DFLL0CONF_MAX_RANGE2 (55000000) +#define SCIF_DFLL0CONF_MIN_RANGE2 (25000000) +#define SCIF_DFLL0CONF_MAX_RANGE3 (30000000) +#define SCIF_DFLL0CONF_MIN_RANGE3 (20000000) + +/* DFLL Value Register */ + +#define SCIF_DFLL0VAL_FINE_SHIFT (0) /* Bits 0-7: Fine Value */ +#define SCIF_DFLL0VAL_FINE_MASK (0xff << SCIF_DFLL0VAL_FINE_SHIFT) +#define SCIF_DFLL0VAL_COARSE_SHIFT (16) /* Bits 16-20: Coarse value */ +#define SCIF_DFLL0VAL_COARSE_MASK (31 << SCIF_DFLL0VAL_COARSE_SHIFT) + +/* DFLL0 Multiplier Register */ + +#define SCIF_DFLL0MUL_MASK 0xffff + +/* DFLL0 Step Register */ + +#define SCIF_DFLL0STEP_FSTEP_SHIFT (0) /* Bits 0-7: Fine Maximum Step */ +#define SCIF_DFLL0STEP_FSTEP_MASK (0xff << SCIF_DFLL0STEP_FSTEP_SHIFT) +# define SCIF_DFLL0STEP_FSTEP(n) ((n) << SCIF_DFLL0STEP_FSTEP_SHIFT) +#define SCIF_DFLL0STEP_CSTEP_SHIFT (16) /* Bits 16-20: Coarse Maximum Step */ +#define SCIF_DFLL0STEP_CSTEP_MASK (31 << SCIF_DFLL0STEP_CSTEP_SHIFT) +# define SCIF_DFLL0STEP_CSTEP(n) ((n) << SCIF_DFLL0STEP_CSTEP_SHIFT) + +/* DFLL0 Spread Spectrum Generator Control Register */ + +#define SCIF_DFLL0SSG_EN (1 << 0) /* Bit 0: Enable */ +#define SCIF_DFLL0SSG_PRBS (1 << 1) /* Bit 1: Pseudo Random Bit Sequence */ +#define SCIF_DFLL0SSG_AMPLITUDE_SHIFT (8) /* Bits 8-12: SSG Amplitude */ +#define SCIF_DFLL0SSG_AMPLITUDE_MASK (31 << SCIF_DFLL0SSG_AMPLITUDE_SHIFT) +#define SCIF_DFLL0SSG_STEPSIZE_SHIFT (16) /* Bits 16-20: SSG Step Size */ +#define SCIF_DFLL0SSG_STEPSIZE_MASK (31 << SCIF_DFLL0SSG_STEPSIZE_SHIFT) + +/* DFLL0 Ratio Register */ + +#define SCIF_DFLL0RATIO_MASK 0xffff + +/* DFLL0 Synchronization Register */ + +#define SCIF_DFLL0SYNC_SYNC (1 << 0) /* Bit 0: Synchronization */ + +/* System RC Oscillator Calibration Register */ + +#define SCIF_RCCR_CALIB_SHIFT (0) /* Bits 0-9: Calibration Value */ +#define SCIF_RCCR_CALIB_MASK (0x3ff << SCIF_RCCR_CALIB_SHIFT) +#define SCIF_RCCR_FCD (1 << 16) /* Bit 16: Flash Calibration Done */ + +/* 4/8/12MHz RC Oscillator Configuration Register */ + +#define SCIF_RCFASTCFG_EN (1 << 0) /* Bit 0: Oscillator Enable */ +#define SCIF_RCFASTCFG_TUNEEN (1 << 1) /* Bit 1: Tuner Enable */ +#define SCIF_RCFASTCFG_JITMODE (1 << 2) /* Bit 2: Jitter Mode */ +#define SCIF_RCFASTCFG_NBPERIODS_SHIFT (4) /* Bits 4-6: Number of 32kHz Periods */ +#define SCIF_RCFASTCFG_NBPERIODS_MASK (7 << SCIF_RCFASTCFG_NBPERIODS_SHIFT) +#define SCIF_RCFASTCFG_FCD (1 << 7) /* Bit 7: RCFAST Fuse Calibration Done */ +#define SCIF_RCFASTCFG_FRANGE_SHIFT (8) /* Bits 8-9: Frequency Range */ +#define SCIF_RCFASTCFG_FRANGE_MASK (3 << SCIF_RCFASTCFG_FRANGE_SHIFT) +# define SCIF_RCFASTCFG_FRANGE_4MHZ (0 << SCIF_RCFASTCFG_FRANGE_SHIFT) /* 4MHz range selected */ +# define SCIF_RCFASTCFG_FRANGE_8MHZ (1 << SCIF_RCFASTCFG_FRANGE_SHIFT) /* 8MHz range selected */ +# define SCIF_RCFASTCFG_FRANGE_12MHZ (2 << SCIF_RCFASTCFG_FRANGE_SHIFT) /* 12MHz range selected */ +#define SCIF_RCFASTCFG_LOCKMARGIN_SHIFT (12) /* Bits 12-15: Accepted Count Error for Lock */ +#define SCIF_RCFASTCFG_LOCKMARGIN_MASK (15 << SCIF_RCFASTCFG_LOCKMARGIN_SHIFT) +#define SCIF_RCFASTCFG_CALIB_SHIFT (16) /* Bits 16-22: Oscillator Calibration Value */ +#define SCIF_RCFASTCFG_CALIB_MASK (0x7f << SCIF_RCFASTCFG_CALIB_SHIFT) + +/* 4/8/12MHz RC Oscillator Status Register */ + +#define SCIF_RCFASTSR_CURTRIM_SHIFT (0) /* Bits 0-6: Current Trim Value */ +#define SCIF_RCFASTSR_CURTRIM_MASK (0x7f << SCIF_RCFASTSR_CURTRIM_SHIFT) +#define SCIF_RCFASTSR_CNTERR_SHIFT (16) /* Bits 16-20: Current Count Error */ +#define SCIF_RCFASTSR_CNTERR_MASK (31 << SCIF_RCFASTSR_CNTERR_SHIFT) +#define SCIF_RCFASTSR_SIGN (1 << 21) /* Bit 21: Sign of Current Count Error */ +#define SCIF_RCFASTSR_LOCK (1 << 24) /* Bit 24: Lock */ +#define SCIF_RCFASTSR_LOCKLOST (1 << 25) /* Bit 25: Lock Lost */ +#define SCIF_RCFASTSR_UPDATED (1 << 31) /* Bit 31: Current Trim Value Updated */ + +/* 80MHz RC Oscillator Register */ + +#define SCIF_RC80MCR_EN (1 << 0) /* Bit 0: Enable */ +#define SCIF_RC80MCR_FCD (1 << 7) /* Bit 7: Flash Calibration Done */ +#define SCIF_RC80MCR_CALIB_SHIFT (16) /* Bits 16-17: Calibration Value */ +#define SCIF_RC80MCR_CALIB_MASK (3 << SCIF_RC80MCR_CALIB_SHIFT) + +/* High Resolution Prescaler Control Register */ + +#define SCIF_HRPCR_HRPEN (1 << 0) /* Bit 0: High Resolution Prescaler Enable */ +#define SCIF_HRPCR_CKSEL_SHIFT (1) /* Bits 1-3: Clock input selection */ +#define SCIF_HRPCR_CKSEL_MASK (7 << SCIF_HRPCR_CKSEL_SHIFT) +#define SCIF_HRPCR_HRCOUNT_SHIFT (8) /* Bits 8-31: High Resolution Counter */ +#define SCIF_HRPCR_HRCOUNT_MASK (0xffffff << SCIF_HRPCR_HRCOUNT_SHIFT) + +/* Fractional Prescaler Control Register */ + +#define SCIF_FPCR_FPEN (1 << 0) /* Bit 0: High Resolution Prescaler Enable */ +#define SCIF_FPCR_CKSEL_SHIFT (1) /* Bits 1-3: Clock input selection */ +#define SCIF_FPCR_CKSEL_MASK (7 << SCIF_FPCR_CKSEL_SHIFT) + +/* Fractional Prescaler Multiplier Register */ + +#define SCIF_FPMUL_MASK 0xffff + +/* Fractional Prescaler DIVIDER Register */ + +#define SCIF_FPDIV_MASK 0xffff + +/* Generic Clock Control0-11 */ + +#define SCIF_GCCTRL_CEN (1 << 0) /* Bit 0: Clock Enable */ +#define SCIF_GCCTRL_DIVEN (1 << 1) /* Bit 1: Divide Enable */ +#define SCIF_GCCTRL_OSCSEL_SHIFT (8) /* Bits 8-12: Oscillator Select */ +#define SCIF_GCCTRL_OSCSEL_MASK (31 << SCIF_GCCTRL_OSCSEL_SHIFT) +# define SCIF_GCCTRL_OSCSEL_RCSYS (0 << SCIF_GCCTRL_OSCSEL_SHIFT) /* System RC oscillator */ +# define SCIF_GCCTRL_OSCSEL_OSC32K (1 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Output from OSC32K */ +# define SCIF_GCCTRL_OSCSEL_DFLL0 (2 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Output from DFLL0 */ +# define SCIF_GCCTRL_OSCSEL_OSC0 (3 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Output from Oscillator0 */ +# define SCIF_GCCTRL_OSCSEL_RC80M (4 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Output from 80MHz RCOSC */ +# define SCIF_GCCTRL_OSCSEL_RCFAST (5 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Output from 4,8,12MHz RCFAST */ +# define SCIF_GCCTRL_OSCSEL_RC1M (6 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Output from 1MHz RC1M */ +# define SCIF_GCCTRL_OSCSEL_CPUCLK (7 << SCIF_GCCTRL_OSCSEL_SHIFT) /* The CPU clock */ +# define SCIF_GCCTRL_OSCSEL_HSBCLK (8 << SCIF_GCCTRL_OSCSEL_SHIFT) /* High Speed Bus clock */ +# define SCIF_GCCTRL_OSCSEL_PBACLK (9 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Peripheral Bus A clock */ +# define SCIF_GCCTRL_OSCSEL_PBBCLK (10 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Peripheral Bus B clock */ +# define SCIF_GCCTRL_OSCSEL_PBCCLK (11 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Peripheral Bus C clock */ +# define SCIF_GCCTRL_OSCSEL_PBDCLK (12 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Peripheral Bus D clock */ +# define SCIF_GCCTRL_OSCSEL_RC32K (13 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Output from 32kHz RCOSC */ +# define SCIF_GCCTRL_OSCSEL_1K (15 << SCIF_GCCTRL_OSCSEL_SHIFT) /* 1 kHz output from OSC32K */ +# define SCIF_GCCTRL_OSCSEL_PLL0 (16 << SCIF_GCCTRL_OSCSEL_SHIFT) /* PLL0 */ +# define SCIF_GCCTRL_OSCSEL_HRPCLK (17 << SCIF_GCCTRL_OSCSEL_SHIFT) /* High resolution prescaler */ +# define SCIF_GCCTRL_OSCSEL_FPCLK (18 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Fractional prescaler */ +# define SCIF_GCCTRL_OSCSEL_GCLKIN0 (19 << SCIF_GCCTRL_OSCSEL_SHIFT) /* GCLKIN0 */ +# define SCIF_GCCTRL_OSCSEL_GCLKIN1 (20 << SCIF_GCCTRL_OSCSEL_SHIFT) /* GCLKIN1 */ +# define SCIF_GCCTRL_OSCSEL_GCLK11 (21 << SCIF_GCCTRL_OSCSEL_SHIFT) /* GCLK11 */ +#define SCIF_GCCTRL_DIV_SHIFT (16) /* Bits 16-31: Division Factor */ +#define SCIF_GCCTRL_DIV_MASK (0xffff << SCIF_GCCTRL_DIV_SHIFT) +# define SCIF_GCCTRL_DIV(n) ((n) << SCIF_GCCTRL_DIV_SHIFT) + +/* 4/8/12MHz RC Oscillator Version Register */ +/* Generic Clock Prescaler Version Register */ +/* PLL Version Register */ +/* Oscillator0 Version Register */ +/* DFLL Version Register */ +/* System RC Oscillator Version Register */ +/* 80MHz RC Oscillator Version Register */ +/* Generic Clock Version Register */ +/* SCIF Version Register */ + +#define SCIF_VERSION_SHIFT (0) /* Bits 0-11: Version Number */ +#define SCIF_VERSION_MASK (0xfff << SCIF_VERSION_VERSION_SHIFT) +#define SCIF_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */ +#define SCIF_VARIANT_MASK (15 << SCIF_VARIANT_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_SCIF_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_usart.h b/nuttx/arch/arm/src/sam34/chip/sam4l_usart.h new file mode 100644 index 000000000..feaf4b48c --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_usart.h @@ -0,0 +1,447 @@ +/************************************************************************************************ + * arch/arm/src/sam34/chip/sam4l_uart.h + * Universal Synchronous Asynchronous Receiver Transmitter (USART) definitions for the SAM4L + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_UART_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_UART_H + +/************************************************************************************************ + * Included Files + ************************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ + +/* USART register offsets ***********************************************************************/ + +#define SAM_UART_CR_OFFSET 0x0000 /* Control Register */ +#define SAM_UART_MR_OFFSET 0x0004 /* Mode Register */ +#define SAM_UART_IER_OFFSET 0x0008 /* Interrupt Enable Register */ +#define SAM_UART_IDR_OFFSET 0x000c /* Interrupt Disable Register */ +#define SAM_UART_IMR_OFFSET 0x0010 /* Interrupt Mask Register */ +#define SAM_UART_SR_OFFSET 0x0014 /* Channel Status Register */ +#define SAM_UART_RHR_OFFSET 0x0018 /* Receive Holding Register */ +#define SAM_UART_THR_OFFSET 0x001c /* Transmit Holding Register */ +#define SAM_UART_BRGR_OFFSET 0x0020 /* Baud Rate Generator Register */ +#define SAM_UART_RTOR_OFFSET 0x0024 /* Receiver Time-out Register */ +#define SAM_UART_TTGR_OFFSET 0x0028 /* Transmitter Timeguard Register */ + /* 0x002c-0x003c: Reserved */ +#define SAM_UART_FIDI_OFFSET 0x0040 /* FI DI Ratio Register */ +#define SAM_UART_NER_OFFSET 0x0044 /* Number of Errors Register */ + /* 0x0048: Reserved */ +#define SAM_UART_IFR_OFFSET 0x004c /* IrDA Filter Register */ +#define SAM_UART_MAN_OFFSET 0x0050 /* Manchester Encoder Decoder Register */ +#define SAM_UART_LINMR_OFFSET 0x0054 /* LIN Mode Register */ +#define SAM_UART_LINIR_OFFSET 0x0058 /* LIN Identifier Register */ +#define SAM_UART_LINBR_OFFSET 0x005c /* LIN Baud Rate Register */ + /* 0x0060-0x00e0: Reserved */ +#define SAM_UART_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */ +#define SAM_UART_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */ + /* 0x005c-0xf008: Reserved */ +#define SAM_UART_VERSION_OFFSET 0x00fc /* Version Register */ + /* 0x0100-0x0124: PDC Area */ + +/* USART register adresses **********************************************************************/ + +#define SAM_USART_CR(n) (SAM_USARTN_BASE(n)+SAM_UART_CR_OFFSET) +#define SAM_USART_MR(n) (SAM_USARTN_BASE(n)+SAM_UART_MR_OFFSET) +#define SAM_USART_IER(n) (SAM_USARTN_BASE(n)+SAM_UART_IER_OFFSET) +#define SAM_USART_IDR(n) (SAM_USARTN_BASE(n)+SAM_UART_IDR_OFFSET) +#define SAM_USART_IMR(n) (SAM_USARTN_BASE(n)+SAM_UART_IMR_OFFSET) +#define SAM_USART_SR(n) (SAM_USARTN_BASE(n)+SAM_UART_SR_OFFSET) +#define SAM_USART_RHR(n) (SAM_USARTN_BASE(n)+SAM_UART_RHR_OFFSET) +#define SAM_USART_THR(n) (SAM_USARTN_BASE(n)+SAM_UART_THR_OFFSET) +#define SAM_USART_BRGR(n) (SAM_USARTN_BASE(n)+SAM_UART_BRGR_OFFSET) +#define SAM_USART_RTOR(n) (SAM_USARTN_BASE(n)+SAM_UART_RTOR_OFFSET) +#define SAM_USART_TTGR(n) (SAM_USARTN_BASE(n)+SAM_UART_TTGR_OFFSET) +#define SAM_USART_FIDI(n) (SAM_USARTN_BASE(n)+SAM_UART_FIDI_OFFSET) +#define SAM_USART_NER(n) (SAM_USARTN_BASE(n)+SAM_UART_NER_OFFSET) +#define SAM_USART_IFR(n) (SAM_USARTN_BASE(n)+SAM_UART_IFR_OFFSET) +#define SAM_USART_MAN(n) (SAM_USARTN_BASE(n)+SAM_UART_MAN_OFFSET) +#define SAM_USART_LINMR(n) (SAM_USARTN_BASE(n)+SAM_UART_LINMR_OFFSET) +#define SAM_USART_LINIR(n) (SAM_USARTN_BASE(n)+SAM_UART_LINIR_OFFSET) +#define SAM_USART_LINBR(n) (SAM_USARTN_BASE(n)+UART_LINBR_OFFSET) +#define SAM_USART_WPMR(n) (SAM_USARTN_BASE(n)+SAM_UART_WPMR_OFFSET) +#define SAM_USART_WPSR(n) (SAM_USARTN_BASE(n)+SAM_UART_WPSR_OFFSET) +#define SAM_USART_VERSION(n) (SAM_USARTN_BASE(n)+SAM_UART_VERSION_OFFSET) + +#define SAM_USART0_CR (SAM_USART0_BASE+SAM_UART_CR_OFFSET) +#define SAM_USART0_MR (SAM_USART0_BASE+SAM_UART_MR_OFFSET) +#define SAM_USART0_IER (SAM_USART0_BASE+SAM_UART_IER_OFFSET) +#define SAM_USART0_IDR (SAM_USART0_BASE+SAM_UART_IDR_OFFSET) +#define SAM_USART0_IMR (SAM_USART0_BASE+SAM_UART_IMR_OFFSET) +#define SAM_USART0_SR (SAM_USART0_BASE+SAM_UART_SR_OFFSET) +#define SAM_USART0_RHR (SAM_USART0_BASE+SAM_UART_RHR_OFFSET) +#define SAM_USART0_THR (SAM_USART0_BASE+SAM_UART_THR_OFFSET) +#define SAM_USART0_BRGR (SAM_USART0_BASE+SAM_UART_BRGR_OFFSET) +#define SAM_USART0_RTOR (SAM_USART0_BASE+SAM_UART_RTOR_OFFSET) +#define SAM_USART0_TTGR (SAM_USART0_BASE+SAM_UART_TTGR_OFFSET) +#define SAM_USART0_FIDI (SAM_USART0_BASE+SAM_UART_FIDI_OFFSET) +#define SAM_USART0_NER (SAM_USART0_BASE+SAM_UART_NER_OFFSET) +#define SAM_USART0_IFR (SAM_USART0_BASE+SAM_UART_IFR_OFFSET) +#define SAM_USART0_MAN (SAM_USART0_BASE+SAM_UART_MAN_OFFSET) +#define SAM_USART0_LINMR (SAM_USART0_BASE+SAM_UART_LINMR_OFFSET) +#define SAM_USART0_LINIR (SAM_USART0_BASE+SAM_UART_LINIR_OFFSET) +#define SAM_USART0_LINBR (SAM_USART0_BASE+UART_LINBR_OFFSET) +#define SAM_USART0_WPMR (SAM_USART0_BASE+SAM_UART_WPMR_OFFSET) +#define SAM_USART0_WPSR (SAM_USART0_BASE+SAM_UART_WPSR_OFFSET) +#define SAM_USART0_VERSION (SAM_USART0_BASE+SAM_UART_VERSION_OFFSET) + +#define SAM_USART1_CR (SAM_USART1_BASE+SAM_UART_CR_OFFSET) +#define SAM_USART1_MR (SAM_USART1_BASE+SAM_UART_MR_OFFSET) +#define SAM_USART1_IER (SAM_USART1_BASE+SAM_UART_IER_OFFSET) +#define SAM_USART1_IDR (SAM_USART1_BASE+SAM_UART_IDR_OFFSET) +#define SAM_USART1_IMR (SAM_USART1_BASE+SAM_UART_IMR_OFFSET) +#define SAM_USART1_SR (SAM_USART1_BASE+SAM_UART_SR_OFFSET) +#define SAM_USART1_RHR (SAM_USART1_BASE+SAM_UART_RHR_OFFSET) +#define SAM_USART1_THR (SAM_USART1_BASE+SAM_UART_THR_OFFSET) +#define SAM_USART1_BRGR (SAM_USART1_BASE+SAM_UART_BRGR_OFFSET) +#define SAM_USART1_RTOR (SAM_USART1_BASE+SAM_UART_RTOR_OFFSET) +#define SAM_USART1_TTGR (SAM_USART1_BASE+SAM_UART_TTGR_OFFSET) +#define SAM_USART1_FIDI (SAM_USART1_BASE+SAM_UART_FIDI_OFFSET) +#define SAM_USART1_NER (SAM_USART1_BASE+SAM_UART_NER_OFFSET) +#define SAM_USART1_IFR (SAM_USART1_BASE+SAM_UART_IFR_OFFSET) +#define SAM_USART1_MAN (SAM_USART1_BASE+SAM_UART_MAN_OFFSET) +#define SAM_USART1_LINMR (SAM_USART1_BASE+SAM_UART_LINMR_OFFSET) +#define SAM_USART1_LINIR (SAM_USART1_BASE+SAM_UART_LINIR_OFFSET) +#define SAM_USART1_LINBR (SAM_USART1_BASE+UART_LINBR_OFFSET) +#define SAM_USART1_WPMR (SAM_USART1_BASE+SAM_UART_WPMR_OFFSET) +#define SAM_USART1_WPSR (SAM_USART1_BASE+SAM_UART_WPSR_OFFSET) +#define SAM_USART1_VERSION (SAM_USART1_BASE+SAM_UART_VERSION_OFFSET) + +#define SAM_USART2_CR (SAM_USART2_BASE+SAM_UART_CR_OFFSET) +#define SAM_USART2_MR (SAM_USART2_BASE+SAM_UART_MR_OFFSET) +#define SAM_USART2_IER (SAM_USART2_BASE+SAM_UART_IER_OFFSET) +#define SAM_USART2_IDR (SAM_USART2_BASE+SAM_UART_IDR_OFFSET) +#define SAM_USART2_IMR (SAM_USART2_BASE+SAM_UART_IMR_OFFSET) +#define SAM_USART2_SR (SAM_USART2_BASE+SAM_UART_SR_OFFSET) +#define SAM_USART2_RHR (SAM_USART2_BASE+SAM_UART_RHR_OFFSET) +#define SAM_USART2_THR (SAM_USART2_BASE+SAM_UART_THR_OFFSET) +#define SAM_USART2_BRGR (SAM_USART2_BASE+SAM_UART_BRGR_OFFSET) +#define SAM_USART2_RTOR (SAM_USART2_BASE+SAM_UART_RTOR_OFFSET) +#define SAM_USART2_TTGR (SAM_USART2_BASE+SAM_UART_TTGR_OFFSET) +#define SAM_USART2_FIDI (SAM_USART2_BASE+SAM_UART_FIDI_OFFSET) +#define SAM_USART2_NER (SAM_USART2_BASE+SAM_UART_NER_OFFSET) +#define SAM_USART2_IFR (SAM_USART2_BASE+SAM_UART_IFR_OFFSET) +#define SAM_USART2_MAN (SAM_USART2_BASE+SAM_UART_MAN_OFFSET) +#define SAM_USART2_LINMR (SAM_USART2_BASE+SAM_UART_LINMR_OFFSET) +#define SAM_USART2_LINIR (SAM_USART2_BASE+SAM_UART_LINIR_OFFSET) +#define SAM_USART2_LINBR (SAM_USART2_BASE+UART_LINBR_OFFSET) +#define SAM_USART2_WPMR (SAM_USART2_BASE+SAM_UART_WPMR_OFFSET) +#define SAM_USART2_WPSR (SAM_USART2_BASE+SAM_UART_WPSR_OFFSET) +#define SAM_USART2_VERSION (SAM_USART2_BASE+SAM_UART_VERSION_OFFSET) + +#define SAM_USART3_CR (SAM_USART3_BASE+SAM_UART_CR_OFFSET) +#define SAM_USART3_MR (SAM_USART3_BASE+SAM_UART_MR_OFFSET) +#define SAM_USART3_IER (SAM_USART3_BASE+SAM_UART_IER_OFFSET) +#define SAM_USART3_IDR (SAM_USART3_BASE+SAM_UART_IDR_OFFSET) +#define SAM_USART3_IMR (SAM_USART3_BASE+SAM_UART_IMR_OFFSET) +#define SAM_USART3_SR (SAM_USART3_BASE+SAM_UART_SR_OFFSET) +#define SAM_USART3_RHR (SAM_USART3_BASE+SAM_UART_RHR_OFFSET) +#define SAM_USART3_THR (SAM_USART3_BASE+SAM_UART_THR_OFFSET) +#define SAM_USART3_BRGR (SAM_USART3_BASE+SAM_UART_BRGR_OFFSET) +#define SAM_USART3_RTOR (SAM_USART3_BASE+SAM_UART_RTOR_OFFSET) +#define SAM_USART3_TTGR (SAM_USART3_BASE+SAM_UART_TTGR_OFFSET) +#define SAM_USART3_FIDI (SAM_USART3_BASE+SAM_UART_FIDI_OFFSET) +#define SAM_USART3_NER (SAM_USART3_BASE+SAM_UART_NER_OFFSET) +#define SAM_USART3_IFR (SAM_USART3_BASE+SAM_UART_IFR_OFFSET) +#define SAM_USART3_MAN (SAM_USART3_BASE+SAM_UART_MAN_OFFSET) +#define SAM_USART3_LINMR (SAM_USART3_BASE+SAM_UART_LINMR_OFFSET) +#define SAM_USART3_LINIR (SAM_USART3_BASE+SAM_UART_LINIR_OFFSET) +#define SAM_USART3_LINBR (SAM_USART3_BASE+UART_LINBR_OFFSET) +#define SAM_USART3_WPMR (SAM_USART3_BASE+SAM_UART_WPMR_OFFSET) +#define SAM_USART3_WPSR (SAM_USART3_BASE+SAM_UART_WPSR_OFFSET) +#define SAM_USART3_VERSION (SAM_USART3_BASE+SAM_UART_VERSION_OFFSET) + +/* USART register bit definitions ***************************************************************/ + +/* USART Control Register */ + +#define UART_CR_RSTRX (1 << 2) /* Bit 2: Reset Receiver */ +#define UART_CR_RSTTX (1 << 3) /* Bit 3: Reset Transmitter */ +#define UART_CR_RXEN (1 << 4) /* Bit 4: Receiver Enable */ +#define UART_CR_RXDIS (1 << 5) /* Bit 5: Receiver Disable */ +#define UART_CR_TXEN (1 << 6) /* Bit 6: Transmitter Enable */ +#define UART_CR_TXDIS (1 << 7) /* Bit 7: Transmitter Disable */ +#define UART_CR_RSTSTA (1 << 8) /* Bit 8: Reset Status Bits */ +#define UART_CR_STTBRK (1 << 9) /* Bit 9: Start Break */ +#define UART_CR_STPBRK (1 << 10) /* Bit 10: Stop Break */ +#define UART_CR_STTTO (1 << 11) /* Bit 11: Start Time-out */ +#define UART_CR_SENDA (1 << 12) /* Bit 12: Send Address */ +#define UART_CR_RSTIT (1 << 13) /* Bit 13: Reset Iterations */ +#define UART_CR_RSTNACK (1 << 14) /* Bit 14: Reset Non Acknowledge */ +#define UART_CR_RETTO (1 << 15) /* Bit 15: Rearm Time-out */ +#define UART_CR_DTREN (1 << 16) /* Bit 16: Data Terminal Ready Enable */ +#define UART_CR_DTRDIS (1 << 17) /* Bit 17: Data Terminal Ready Disable */ +#define UART_CR_RTSEN (1 << 18) /* Bit 18: Request to Send Enable */ +#define UART_CR_FCS (1 << 18) /* Bit 18: Force SPI Chip Select */ +#define UART_CR_RTSDIS (1 << 19) /* Bit 19: Request to Send Disable */ +#define UART_CR_RCS (1 << 19) /* Bit 19: Release SPI Chip Select */ +#define UART_CR_LINABT (1 << 20) /* Bit 20: Abort LIN Transmission */ +#define UART_CR_LINWKUP (1 << 21) /* Bit 21: Send LIN Wakeup Signal */ + +/* USART Mode Register */ + +#define UART_MR_MODE_SHIFT (0) /* Bits 0-3: */ +#define UART_MR_MODE_MASK (15 << UART_MR_MODE_SHIFT) +# define UART_MR_MODE_NORMAL (0 << UART_MR_MODE_SHIFT) /* Normal */ +# define UART_MR_MODE_RS485 (1 << UART_MR_MODE_SHIFT) /* RS485 */ +# define UART_MR_MODE_HWHS (2 << UART_MR_MODE_SHIFT) /* Hardware Handshaking */ +# define UART_MR_MODE_ISO7816_0 (4 << UART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 0 */ +# define UART_MR_MODE_ISO7816_1 (6 << UART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 1 */ +# define UART_MR_MODE_IRDA (8 << UART_MR_MODE_SHIFT) /* IrDA */ +# define UART_MR_MODE_SPIMSTR (14 << UART_MR_MODE_SHIFT) /* SPI Master */ +# define UART_MR_MODE_SPISLV (15 << UART_MR_MODE_SHIFT) /* SPI Slave */ +#define UART_MR_USCLKS_SHIFT (4) /* Bits 4-5: Clock Selection */ +#define UART_MR_USCLKS_MASK (3 << UART_MR_USCLKS_SHIFT) +# define UART_MR_USCLKS_USART (0 << UART_MR_USCLKS_SHIFT) /* CLK_USART */ +# define UART_MR_USCLKS_USARTDIV (0 << UART_MR_USCLKS_SHIFT) /* CLK_USART/DIV(1) */ +# define UART_MR_USCLKS_CLK (0 << UART_MR_USCLKS_SHIFT) /* CLK */ +#define UART_MR_CHRL_SHIFT (6) /* Bits 6-7: Character Length */ +#define UART_MR_CHRL_MASK (3 << UART_MR_CHRL_SHIFT) +# define UART_MR_CHRL_5BITS (0 << UART_MR_CHRL_SHIFT) /* 5 bits */ +# define UART_MR_CHRL_6BITS (1 << UART_MR_CHRL_SHIFT) /* 6 bits */ +# define UART_MR_CHRL_7BITS (2 << UART_MR_CHRL_SHIFT) /* 7 bits */ +# define UART_MR_CHRL_8BITS (3 << UART_MR_CHRL_SHIFT) /* 8 bits */ +#define UART_MR_SYNC (1 << 8) /* Bit 8: Synchronous Mode Select */ +#define UART_MR_CPHA (1 << 8) /* Bit 8: SPI Clock Phase */ +#define UART_MR_PAR_SHIFT (9) /* Bits 9-11: Parity Type */ +#define UART_MR_PAR_MASK (7 << UART_MR_PAR_SHIFT) +# define UART_MR_PAR_EVEN (0 << UART_MR_PAR_SHIFT) /* Even parity */ +# define UART_MR_PAR_ODD (1 << UART_MR_PAR_SHIFT) /* Odd parity */ +# define UART_MR_PAR_SPACE (2 << UART_MR_PAR_SHIFT) /* Space: parity forced to 0 */ +# define UART_MR_PAR_MARK (3 << UART_MR_PAR_SHIFT) /* Mark: parity forced to 1 */ +# define UART_MR_PAR_NONE (4 << UART_MR_PAR_SHIFT) /* No parity */ +# define UART_MR_PAR_MULTIDROP (6 << UART_MR_PAR_SHIFT) /* Multidrop mode */ +#define UART_MR_NBSTOP_SHIFT (12) /* Bits 12-13: Number of Stop Bits */ +#define UART_MR_NBSTOP_MASK (3 << UART_MR_NBSTOP_SHIFT) +# define UART_MR_NBSTOP_1 (0 << UART_MR_NBSTOP_SHIFT) /* 1 stop bit 1 stop bit */ +# define UART_MR_NBSTOP_1p5 (1 << UART_MR_NBSTOP_SHIFT) /* 1.5 stop bits */ +# define UART_MR_NBSTOP_2 (2 << UART_MR_NBSTOP_SHIFT) /* 2 stop bits 2 stop bits */ +#define UART_MR_CHMODE_SHIFT (14) /* Bits 14-15: Channel Mode */ +#define UART_MR_CHMODE_MASK (3 << UART_MR_CHMODE_SHIFT) +# define UART_MR_CHMODE_NORMAL (0 << UART_MR_CHMODE_SHIFT) /* Normal Mode */ +# define UART_MR_CHMODE_ECHO (1 << UART_MR_CHMODE_SHIFT) /* Automatic Echo */ +# define UART_MR_CHMODE_LLPBK (2 << UART_MR_CHMODE_SHIFT) /* Local Loopback */ +# define UART_MR_CHMODE_RLPBK (3 << UART_MR_CHMODE_SHIFT) /* Remote Loopback */ +#define UART_MR_MSBF (1 << 16) /* Bit 16: Most Significant Bit first */ +#define UART_MR_CPOL (1 << 16) /* Bit 16: SPI Clock Polarity */ +#define UART_MR_MODE9 (1 << 17) /* Bit 17: 9-bit Character Length */ +#define UART_MR_CLKO (1 << 18) /* Bit 18: Clock Output Select */ +#define UART_MR_OVER (1 << 19) /* Bit 19: Oversampling Mode */ +#define UART_MR_INACK (1 << 20) /* Bit 20: Inhibit Non Acknowledge */ +#define UART_MR_DSNACK (1 << 21) /* Bit 21: Disable Successive NACK */ +#define UART_MR_VARSYNC (1 << 22) /* Bit 22: Variable Synchronization of Command/Data Sync Start Frame Delimiter */ +#define UART_MR_INVDATA (1 << 23) /* Bit 23: INverted Data */ +#define UART_MR_MAXITER_SHIFT (24) /* Bits 24-26: Max iterations (ISO7816 T=0 */ +#define UART_MR_MAXITER_MASK (7 << UART_MR_MAXITER_SHIFT) +#define UART_MR_FILTER (1 << 28) /* Bit 28: Infrared Receive Line Filter */ +#define UART_MR_MAN (1 << 29) /* Bit 29: Manchester Encoder/Decoder Enable */ +#define UART_MR_MODSYNC (1 << 30) /* Bit 30: Manchester Synchronization Mode */ +#define UART_MR_ONEBIT (1 << 31) /* Bit 31: Start Frame Delimiter Selector */ + +/* USART Interrupt Enable Register, USART Interrupt Disable Register, USART Interrupt Mask + * Register, and USART Status Register common bit field definitions. + * + * - Bits that provide interrupts with UART_INT_ + * - Bits unique to the USART status register begin with UART_SR_ + */ + +#define UART_INT_RXRDY (1 << 0) /* Bit 0: RXRDY Interrupt */ +#define UART_INT_TXRDY (1 << 1) /* Bit 1: TXRDY Interrupt */ +#define UART_INT_RXBRK (1 << 2) /* Bit 2: Break Received/End of Break */ +#define UART_INT_OVRE (1 << 5) /* Bit 5: Overrun Error Interrupt */ +#define UART_INT_FRAME (1 << 6) /* Bit 6: Framing Error Interrupt */ +#define UART_INT_PARE (1 << 7) /* Bit 7: Parity Error Interrupt */ +#define UART_INT_TIMEOUT (1 << 8) /* Bit 8: Time-out Interrupt */ +#define UART_INT_TXEMPTY (1 << 9) /* Bit 9: TXEMPTY Interrupt */ +#define UART_INT_ITER (1 << 10) /* Bit 10: Iteration Interrupt */ +#define UART_INT_UNRE (1 << 10) /* Bit 10: SPI Underrun Error Interrupt */ +#define UART_INT_RXBUFF (1 << 12) /* Bit 12: Buffer Full Interrupt */ +#define UART_INT_NACK (1 << 13) /* Bit 13: Non Acknowledge Interrupt */ +#define UART_INT_LINBK (1 << 13) /* Bit 13: LIN Break */ +#define UART_INT_LINID (1 << 14) /* Bit 14: LIN Identifier */ +#define UART_INT_LINTC (1 << 15) /* Bit 15: LIN Transfer Completed */ +#define UART_INT_RIIC (1 << 16) /* Bit 16: Ring Indicator Input Change Flag */ +#define UART_INT_DSRIC (1 << 17) /* Bit 17: DSR Input Change Flag */ +#define UART_INT_DCDIC (1 << 18) /* Bit 18: DCD Input Change Flag */ +#define UART_INT_CTSIC (1 << 19) /* Bit 19: CTS Input Change Interrupt */ +#define UART_SR_RI (1 << 20) /* Bit 20: Image of RI Input (Status only) */ +#define UART_SR_DSR (1 << 21) /* Bit 21: Image of DSR Input (Status only) */ +#define UART_SR_DCD (1 << 22) /* Bit 22: Image of DCD Input (Status only) */ +#define UART_SR_CTS (1 << 23) /* Bit 23: Image of CTS Input (Status only) */ +#define UART_SR_LINBLS (1 << 23) /* Bit 23: ILIN Bus Line Status (Status only) */ +#define UART_INT_MANE (1 << 24) /* Bit 24: Manchester Error Interrupt */ +#define UART_INT_LINBE (1 << 25) /* Bit 25: LIN Bit Error */ +#define UART_INT_LINISFE (1 << 26) /* Bit 26: LIN Inconsistent Sync Field Error */ +#define UART_INT_LINIPE (1 << 27) /* Bit 27: LIN Identifier Parity Error */ +#define UART_INT_LINCE (1 << 28) /* Bit 28: LIN Checksum Error */ +#define UART_INT_LINSNRE (1 << 29) /* Bit 29: LIN Slave Not Responding Error */ +#define UART_INT_LINSTE (1 << 30) /* Bit 30: LIN Sync Tolerance Error */ +#define UART_INT_LINHTE (1 << 31) /* Bit 31: LIN Header Time-out Error */ + +/* USART Receiver Holding Register */ + +#define UART_RHR_RXCHR_SHIFT (0) /* Bits 0-8: Received Character */ +#define UART_RHR_RXCHR_MASK (0x1ff << UART_RHR_RXCHR_SHIFT) +#define UART_RHR_RXSYNH (1 << 15) /* Bit 15: Received Sync */ + +/* USART Transmit Holding Register */ + +#define UART_THR_TXCHR_SHIFT (0) /* Bits 0-8: Character to be Transmitted */ +#define UART_THR_TXCHR_MASK (0x1ff << UART_THR_TXCHR_SHIFT) +#define UART_THR_TXSYNH (1 << 15) /* Bit 15: Sync Field to be tran */ + +/* USART Baud Rate Generator Register */ + +#define UART_BRGR_CD_SHIFT (0) /* Bits 0-15: Clock Divisor */ +#define UART_BRGR_CD_MASK (0xffff << UART_BRGR_CD_SHIFT) +#define UART_BRGR_FP_SHIFT (16) /* Bits 16-18: Fractional Part */ +#define UART_BRGR_FP_MASK (7 << UART_BRGR_FP_SHIFT) + +/* USART Receiver Time-out Register */ + +#define UART_RTOR_TO_SHIFT (0) /* Bits 0-16: Time-out Value */ +#define UART_RTOR_TO_MASK (0x1ffff << UART_RTOR_TO_SHIFT) + +/* USART Transmitter Timeguard Register */ + +#define UART_TTGR_TG_SHIFT (0) /* Bits 0-7: Timeguard Value */ +#define UART_TTGR_TG_MASK (0xff << UART_TTGR_TG_SHIFT) + +/* USART FI DI RATIO Register */ + +#define UART_FIDI_RATIO_SHIFT (0) /* Bits 0-10: FI Over DI Ratio Value */ +#define UART_FIDI_RATIO_MASK (0x7ff << UART_FIDI_RATIO_SHIFT) + +/* USART Number of Errors Register */ + +#define UART_NER_NBERRORS_SHIFT (0) /* Bits 0-7: Number of Errrors */ +#define UART_NER_NBERRORS_MASK (0xff << UART_NER_NBERRORS_SHIFT) + +/* USART IrDA FILTER Register */ + +#define UART_IFR_IRDAFILTER_SHIFT (0) /* Bits 0-7: IrDA Filter */ +#define UART_IFR_IRDAFILTER_MASK (0xff << UART_IFR_IRDAFILTER_SHIFT) + +/* USART Manchester Configuration Register */ + +#define UART_MAN_TXPL_SHIFT (0) /* Bits 0-3: Transmitter Preamble Length */ +#define UART_MAN_TXPL_MASK (15 << UART_MAN_TXPL_SHIFT) +#define UART_MAN_TXPP_SHIFT (8) /* Bits 8-9: Transmitter Preamble Pattern */ +#define UART_MAN_TXPP_MASK (3 << UART_MAN_TXPP_SHIFT) +# define UART_MAN_TXPP_ALLONE (0 << UART_MAN_TXPP_SHIFT) /* ALL_ONE */ +# define UART_MAN_TXPP_ALLZERO (1 << UART_MAN_TXPP_SHIFT) /* ALL_ZERO */ +# define UART_MAN_TXPP_ZEROONE (2 << UART_MAN_TXPP_SHIFT) /* ZERO_ONE */ +# define UART_MAN_TXPP_ONEZERO (3 << UART_MAN_TXPP_SHIFT) /* ONE_ZERO */ +#define UART_MAN_TXMPOL (1 << 12) /* Bit 12: Transmitter Manchester Polarity */ +#define UART_MAN_RXPL_SHIFT (16) /* Bits 16-19: Receiver Preamble Length */ +#define UART_MAN_RXPL_MASK (15 << UART_MAN_RXPL_SHIFT) +#define UART_MAN_RXPP_SHIFT (24) /* Bits 24-25: Receiver Preamble Pattern detected */ +#define UART_MAN_RXPP_MASK (3 << UART_MAN_RXPP_SHIFT) +# define UART_MAN_RXPP_ALLONE (0 << UART_MAN_RXPP_SHIFT) /* ALL_ONE */ +# define UART_MAN_RXPP_ALLZERO (1 << UART_MAN_RXPP_SHIFT) /* ALL_ZERO */ +# define UART_MAN_RXPP_ZEROONE (2 << UART_MAN_RXPP_SHIFT) /* ZERO_ONE */ +# define UART_MAN_RXPP_ONEZERO (3 << UART_MAN_RXPP_SHIFT) /* ONE_ZERO */ +#define UART_MAN_RXMPOL (1 << 28) /* Bit 28: Receiver Manchester Polarity */ +#define UART_MAN_DRIFT (1 << 30) /* Bit 30: Drift compensation */ + +/* USART LIN Mode Register */ + +#define UART_LINMR_NACT_SHIFT (0) /* Bits 0-1: LIN Node Action */ +#define UART_LINMR_NACT_MASK (3 << UART_LINMR_NACT_SHIFT) +# define UART_LINMR_NACT_PUBLISH (0 << UART_LINMR_NACT_SHIFT) /* USART transmits response */ +# define UART_LINMR_NACT_SUBSCRIBE (1 << UART_LINMR_NACT_SHIFT) /* USART receives response */ +# define UART_LINMR_NACT_IGNORE (2 << UART_LINMR_NACT_SHIFT) /* USART does neither */ +#define UART_LINMR_PARDIS (1 << 2) /* Bit 0: Parity Disable */ +#define UART_LINMR_CHKDIS (1 << 3) /* Bit 0: Checksum Disable */ +#define UART_LINMR_CHKTYP (1 << 4) /* Bit 0: Checksum Type */ +#define UART_LINMR_DLM (1 << 5) /* Bit 0: Data Length Mode */ +#define UART_LINMR_FSDIS (1 << 6) /* Bit 0: Frame Slot Mode Disable */ +#define UART_LINMR_WKUPTYP (1 << 7) /* Bit 0: Wakeup Signal Type */ +#define UART_LINMR_DLC_SHIFT (8) /* Bits 8-15: Data Length Control */ +#define UART_LINMR_DLC_MASK (0xff << UART_LINMR_DLC_SHIFT) +#define UART_LINMR_PDCM (1 << 16) /* Bit 16: Peripheral DMA Controller Mode */ +#define UART_LINMR_SYNCDIS (1 << 17) /* Bit 17: Synchronization Disable */ + +/* USART LIN Identifier Register */ + +#define UART_LINIR_MASK 0xff /* Bits 0-7: Identifer character */ + +/* USART LIN Baud Rate Register */ + +#define UART_LINBR_LINCD_SHIFT (0) /* Bit 0-15:LIN Clock Divider after Synchronization */ +#define UART_LINBR_LINCD_MASK (0xffff << UART_LINBR_LINCD_SHIFT) +#define UART_LINBR_LINFP_SHIFT (16) /* Bits 16-18: LIN Fractional Part after Synchronization */ +#define UART_LINBR_LINFP_MASK (7 << UART_LINBR_LINFP_SHIFT) + +/* USART Write Protect Mode Register */ + +#define UART_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ +#define UART_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ +#define UART_WPMR_WPKEY_MASK (0x00ffffff << UART_WPMR_WPKEY_SHIFT) + +/* USART Write Protect Status Register */ + +#define UART_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */ +#define UART_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ +#define UART_WPSR_WPVSRC_MASK (0xffff << UART_WPSR_WPVSRC_SHIFT) + +/* USART Version Register */ + +#define UART_VERSION_VERSION_SHIFT (0) /* Bits 0-11: Macrocell version number */ +#define UART_VERSION_VERSION_MASK (0xfff << UART_VERSION_VERSION_SHIFT) +#define UART_VERSION_MFN_SHIFT (16) /* Bits 16-18: Reserved */ +#define UART_VERSION_MFN_MASK (7 << UART_VERSION_MFN_SHIFT) + +/************************************************************************************************ + * Public Types + ************************************************************************************************/ + +/************************************************************************************************ + * Public Data + ************************************************************************************************/ + +/************************************************************************************************ + * Public Functions + ************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_UART_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_wdt.h b/nuttx/arch/arm/src/sam34/chip/sam4l_wdt.h new file mode 100644 index 000000000..638370614 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_wdt.h @@ -0,0 +1,137 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam4l_wdt.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_WDT_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_WDT_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* WDT register offsets ****************************************************************/ + +#define SAM_WDT_CTRL_OFFSET 0x0000 /* Control Register */ +#define SAM_WDT_CLR_OFFSET 0x0004 /* Clear Register */ +#define SAM_WDT_SR_OFFSET 0x0008 /* Status Register */ +#define SAM_WDT_IER_OFFSET 0x000c /* Interrupt Enable Register */ +#define SAM_WDT_IDR_OFFSET 0x0010 /* Interrupt Disable Register */ +#define SAM_WDT_IMR_OFFSET 0x0014 /* Interrupt Mask Register */ +#define SAM_WDT_ISR_OFFSET 0x0018 /* Interrupt Status Register */ +#define SAM_WDT_ICR_OFFSET 0x001c /* Interrupt Clear Register */ +#define SAM_WDT_VERSION_OFFSET 0x03fc /* Version Register */ + +/* WDT register adresses ***************************************************************/ + +#define SAM_WDT_CTRL (SAM_WDT_BASE+SAM_WDT_CTRL_OFFSET) +#define SAM_WDT_CLR (SAM_WDT_BASE+SAM_WDT_CLR_OFFSET) +#define SAM_WDT_SR (SAM_WDT_BASE+SAM_WDT_SR_OFFSET) +#define SAM_WDT_IER (SAM_WDT_BASE+SAM_WDT_IER_OFFSET) +#define SAM_WDT_IDR (SAM_WDT_BASE+SAM_WDT_IDR_OFFSET) +#define SAM_WDT_IMR (SAM_WDT_BASE+SAM_WDT_IMR_OFFSET) +#define SAM_WDT_ISR (SAM_WDT_BASE+SAM_WDT_ISR_OFFSET) +#define SAM_WDT_ICR (SAM_WDT_BASE+SAM_WDT_ICR_OFFSET) +#define SAM_WDT_VERSION (SAM_WDT_BASE+SAM_WDT_VERSION_OFFSET) + +/* WDT register bit definitions ********************************************************/ + +/* Control Register */ + +#define WDT_CTRL_EN (1 << 0) /* Bit 0: WDT Enable */ +#define WDT_CTRL_DAR (1 << 1) /* Bit 1: WDT Disable After Reset */ +#define WDT_CTRL_MODE (1 << 2) /* Bit 2: WDT Mode */ +#define WDT_CTRL_SFV (1 << 3) /* Bit 3: WDT Control Register Store Final Value */ +#define WDT_CTRL_IM (1 << 4) /* Bit 4: Interrupt Mode */ +#define WDT_CTRL_FCD (1 << 7) /* Bit 7: Flash Calibration Done */ +#define WDT_CTRL_PSEL_SHIFT (8) /* Bits 8-12: Time Out Prescale Select */ +#define WDT_CTRL_PSEL_MASK (31 << WDT_CTRL_PSEL_SHIFT) +#define WDT_CTRL_CEN (1 << 16) /* Bit 16: Clock Enable */ +#define WDT_CTRL_CSSEL (1 << 17) /* Bit 17: Clock Source Select */ +#define WDT_CTRL_TBAN_SHIFT (18) /* Bits 18-22: Time Ban Prescale Select */ +#define WDT_CTRL_TBAN_MASK (31 << WDT_CTRL_TBAN_SHIFT) +#define WDT_CTRL_KEY_SHIFT (24) /* Bits 24-31: Key */ +#define WDT_CTRL_KEY_MASK (0xff << WDT_CTRL_KEY_SHIFT) +# define WDT_CTRL_KEY_FIRST (0x55 << WDT_CTRL_KEY_SHIFT) +# define WDT_CTRL_KEY_SECOND (0xaa << WDT_CTRL_KEY_SHIFT) + +/* Clear Register */ + +#define WDT_CLR_WDTCLR (1 << 0) /* Bit 0: Watchdog Clear */ +#define WDT_CLR_KEY_SHIFT (24) /* Bits 24-31: Key */ +#define WDT_CLR_KEY_MASK (0xff << WDT_CLR_KEY_SHIFT) +# define WDT_CLR_KEY_FIRST (0x55 << WDT_CLR_KEY_SHIFT) +# define WDT_CLR_KEY_SECOND (0xaa << WDT_CLR_KEY_SHIFT) + +/* Status Register */ + +#define WDT_SR_WINDOW (1 << 0) /* Bit 0: Within Window */ +#define WDT_SR_CLEARED (1 << 1) /* Bit 1: WDT Counter Cleared */ + +/* Interrupt Enable Register */ +/* Interrupt Disable Register */ +/* Interrupt Mask Register */ +/* Interrupt Status Register */ +/* Interrupt Clear Register */ + +#define WDT_WINT (1 << 2) /* Bit 2: WINT */ + +/* Version Register */ + +#define WDT_VERSION_SHIFT (0) /* Bits 0-11: Version Number */ +#define WDT_VERSION_MASK (0xfff << WDT_VERSION_VERSION_SHIFT) +#define WDT_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */ +#define WDT_VARIANT_MASK (15 << WDT_VARIANT_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_WDT_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4s_memorymap.h b/nuttx/arch/arm/src/sam34/chip/sam4s_memorymap.h new file mode 100644 index 000000000..406b01dd9 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam4s_memorymap.h @@ -0,0 +1,153 @@ +/************************************************************************************************ + * arch/arm/src/sam34/chip/sam4s_memorymap.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_MEMORYMAP_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_MEMORYMAP_H + +/************************************************************************************************ + * Included Files + ************************************************************************************************/ + +#include <nuttx/config.h> +#include "chip.h" + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ + +/* Address regions */ + +#define SAM_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: Code space */ +#define SAM_INTSRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: Internal SRAM */ +#define SAM_PERIPHERALS_BASE 0x40000000 /* 0x40000000-0x5fffffff: Peripherals */ +#define SAM_EXTRAM_BASE 0x60000000 /* 0x60000000-0x9fffffff: External RAM */ +#define SAM_EXTDEV_BASE 0xa0000000 /* 0xa0000000-0xdfffffff: External device */ +#define SAM_SYSTEM_BASE 0xe0000000 /* 0xe0000000-0xffffffff: System */ + +/* Code memory region */ + +#define SAM_BOOTMEMORY_BASE 0x00000000 /* 0x00000000-0x003fffff: Boot Memory */ +#define SAM_INTFLASH_BASE 0x00400000 /* 0x00400000-0x007fffff: Internal FLASH */ +#define SAM_INTROM_BASE 0x00800000 /* 0x00180000-0x00bfffff: Internal ROM */ + /* 0x00c00000-0x1fffffff: Reserved */ +/* Internal SRAM memory region */ + +#define SAM_INTSRAM0_BASE 0x20000000 /* For SAM3U compatibility */ +#define SAM_BBSRAM_BASE 0x22000000 /* 0x22000000-0x23ffffff: 32MB bit-band region */ + /* 0x24000000-0x3fffffff: Undefined */ +/* Peripherals address region */ + +#define SAM_HSMCI_BASE 0x40000000 /* 0x40000000-0x400003ff: High Speed Multimedia Card Interface */ +#define SAM_SSC_BASE 0x40004000 /* 0x40004000-0x40007fff: Synchronous Serial Controller */ +#define SAM_SPI_BASE 0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface */ + /* 0x4000c000-0x4000ffff: Reserved */ +#define SAM_TC_BASE 0x40010000 /* 0x40010000-0x40017fff: Timer Counters */ +# define SAM_TC0_BASE 0x40080000 /* 0x40010000-0x4001003f: Timer Counter 0 */ +# define SAM_TC1_BASE 0x40080040 /* 0x40010040-0x4001007f: Timer Counter 1 */ +# define SAM_TC2_BASE 0x40080080 /* 0x40010080-0x400100bf: Timer Counter 2 */ + /* 0x400100c0-0x40013fff Reserved */ +# define SAM_TC3_BASE 0x40080000 /* 0x40014000-0x4001403f: Timer Counter 3 */ +# define SAM_TC4_BASE 0x40080040 /* 0x40014040-0x4001407f: Timer Counter 4 */ +# define SAM_TC5_BASE 0x40080080 /* 0x40014080-0x400140bf: Timer Counter 5 */ +#define SAM_TWI_BASE 0x40018000 /* 0x40018000-0x4001ffff: Two-Wire Interface */ +# define SAM_TWI0_BASE 0x40018000 /* 0x40018000-0x4001bfff: Two-Wire Interface 0 */ +# define SAM_TWI1_BASE 0x4001c000 /* 0x4001c000-0x4001ffff: Two-Wire Interface 1 */ +#define SAM_PWM_BASE 0x40020000 /* 0x40020000-0x4003ffff: Pulse Width Modulation */ +#define SAM_USART_BASE 0x40024000 /* 0x40024000-0x4002bfff: USART */ +# define SAM_USART0_BASE 0x40024000 /* 0x40024000-0x40023fff: USART0 */ +# define SAM_USART1_BASE 0x40028000 /* 0x40028000-0x4002bfff: USART1 */ + /* 0x4002C000-0x4002ffff: Reserved */ + /* 0x40030000-0x40033fff: Reserved */ +#define SAM_UDP_BASE 0x40034000 /* 0x40034000-0x40037fff: USB 2.0 Device */ +#define SAM_ADC_BASE 0x40038000 /* 0x40038000-0x4003bfff: Analog To Digital Converter */ +#define SAM_DACCBASE 0x400cC000 /* 0x4003c000-0x4003ffff: Digital To Analog Converter */ +#define SAM_ACC_BASE 0x40040000 /* 0x40040000-0x40043fff: Analog Comparator */ +#define SAM_CRCCU_BASE 0x40044000 /* 0x40040000-0x40047fff: CRC Calculation Unit */ + /* 0x40048000-0x400dffff: Reserved */ +#define SAM_SYSCTRLR_BASE 0x400e0000 /* 0x400e0000-0x400e25ff: System Controller */ + /* 0x400e2600-0x400fffff: Reserved */ + /* 0x40100000-0x4002ffff: Reserved */ +#define SAM_BBPERIPH_BASE 0x42000000 /* 0x42000000-0x43ffffff: 32MB bit-band region */ + /* 0x44000000-0x5fffffff: Reserved */ +/* System Controller Register Blocks: 0x400e0000-0x4007ffff */ + +#define SAM_SMC_BASE 0x400e0000 /* 0x400e0000-0x400e01ff: Static Memory Controller */ +#define SAM_MATRIX_BASE 0x400e0200 /* 0x400e0200-0x400e03ff: MATRIX */ +#define SAM_PMC_BASE 0x400e0400 /* 0x400e0400-0x400e05ff: Power Management Controller */ +#define SAM_UART0_BASE 0x400e0600 /* 0x400e0600-0x400e073f: UART 0 */ +#define SAM_CHIPID_BASE 0x400e0740 /* 0x400e0740-0x400e07ff: CHIP ID */ +#define SAM_UART1_BASE 0x400e0800 /* 0x400e0800-0x400e0bff: UART 1 */ +#define SAM_EEFC_BASE 0x400e0a00 /* 0x400e0a00-0x400e0bff: Enhanced Embedded Flash Controllers*/ +# define SAM_EEFC0_BASE 0x400e0a00 /* 0x400e0a00-0x400e0bff: Enhanced Embedded Flash Controller 0 */ +# define SAM_EEFC1_BASE 0x400e0c00 /* 0x400e0c00-0x400e0dff: Enhanced Embedded Flash Controller 1 */ +#define SAM_PIO_BASE 0x400e0e00 /* 0x400e0e00-0x400e13ff: Parallel I/O Controllers */ +# define SAM_PION_BASE(n) (0x400e0e00 + ((n) << 9)) +# define SAM_PIOA_BASE 0x400e0e00 /* 0x400e0e00-0x400e0fff: Parallel I/O Controller A */ +# define SAM_PIOB_BASE 0x400e1000 /* 0x400e1000-0x400e11ff: Parallel I/O Controller B */ +# define SAM_PIOC_BASE 0x400e1200 /* 0x400e1200-0x400e13ff: Parallel I/O Controller C */ +#define SAM_RSTC_BASE 0x400e1400 /* 0x400e1400-0x400e140f: Reset Controller */ +#define SAM_SUPC_BASE 0x400e1410 /* 0x400e1410-0x400e142f: Supply Controller */ +#define SAM_RTT_BASE 0x400e1430 /* 0x400e1430-0x400e144f: Real Time Timer */ +#define SAM_WDT_BASE 0x400e1450 /* 0x400e1250-0x400e145f: Watchdog Timer */ +#define SAM_RTC_BASE 0x400e1460 /* 0x400e1460-0x400e148f: Real Time Clock */ +#define SAM_GPBR_BASE 0x400e1490 /* 0x400e1490-0x400e15ff: GPBR */ + /* 0x400e1600-0x4007ffff: Reserved */ +/* External RAM memory region */ + +#define SAM_EXTCS_BASE 0x60000000 /* 0x60000000-0x63ffffff: Chip selects */ +# define SAM_EXTCSN_BASE(n) (0x60000000*((n)<<24)) +# define SAM_EXTCS0_BASE 0x60000000 /* 0x60000000-0x60ffffff: Chip select 0 */ +# define SAM_EXTCS1_BASE 0x61000000 /* 0x61000000-0x601fffff: Chip select 1 */ +# define SAM_EXTCS2_BASE 0x62000000 /* 0x62000000-0x62ffffff: Chip select 2 */ +# define SAM_EXTCS3_BASE 0x63000000 /* 0x63000000-0x63ffffff: Chip select 3 */ + /* 0x64000000-0x9fffffff: Reserved */ +/* System memory region */ + +#define SAM_PRIVPERIPH_BASE 0xe0000000 /* 0xe0000000-0xe00fffff: Private peripheral bus */ +#define SAM_VENDOR_BASE 0xe0100000 /* 0ex0100000-0xffffffff: Vendor-specific memory */ + +/************************************************************************************************ + * Public Types + ************************************************************************************************/ + +/************************************************************************************************ + * Public Data + ************************************************************************************************/ + +/************************************************************************************************ + * Public Functions + ************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_MEMORYMAP_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4s_pinmap.h b/nuttx/arch/arm/src/sam34/chip/sam4s_pinmap.h new file mode 100644 index 000000000..cb6d7eb18 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam4s_pinmap.h @@ -0,0 +1,314 @@ +/************************************************************************************ + * arch/arm/src/sam34/chip/sam4s_pinmap.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_PINMAP_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_PINMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "sam_gpio.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* GPIO pin definitions *************************************************************/ +/* Alternate Pin Functions. + * + * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. + * Drivers, however, will use the pin selection without the numeric suffix. + * Additional definitions are required in the board.h file. For example, if we + * wanted the programmable clock output PCK0 on PA6, then the following definition + * should appear in the board.h header file for that board: + * + * #define GPIO_PCK0 GPIO_PCK0_1 + * + * The driver will then automatically configre PA6 as the PCK0 pin. + */ + +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as frequency, + * open-drain/push-pull, and pull-up/down! Just the basics are defined for most + * pins in this file. + */ + +/* 12-bit Analog-to-Digital Conververt (ADC) */ + +#define GPIO_ADC0_AD0 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN17) +#define GPIO_ADC0_AD1 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN18) +#define GPIO_ADC0_AD2 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN19) +#define GPIO_ADC0_AD3 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN20) +#define GPIO_ADC0_AD4 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN0) +#define GPIO_ADC0_AD5 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN1) +#define GPIO_ADC0_AD6 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN2) +#define GPIO_ADC0_AD7 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN3) +#define GPIO_ADC0_AD8 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN21) +#define GPIO_ADC0_AD9 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22) +#define GPIO_ADC0_AD10 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN13) +#define GPIO_ADC0_AD11 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN15) +#define GPIO_ADC0_AD12 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN12) +#define GPIO_ADC0_AD13 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN29) +#define GPIO_ADC0_AD14 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN30) +#define GPIO_ADC0_ADTRG (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN8) + +/* Digital-to-Analog Convert (DAC) */ + +#define GPIO_DAC0 (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN13) +#define GPIO_DAC1 (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN14) +#define GPIO_DAC_DATRG (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN2) + +/* High-Speed Multimedia Card Interface (HSMCI) */ + +#define GPIO_MCI_CK (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN29) +#define GPIO_MCI_DA (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN28) +#define GPIO_MCI_DAT0 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN30) +#define GPIO_MCI_DAT1 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN31) +#define GPIO_MCI_DAT2 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN26) +#define GPIO_MCI_DAT3 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN27) + +/* Programmable Clock Output */ + +#define GPIO_PCK0_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN6) +#define GPIO_PCK0_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN13) +#define GPIO_PCK1_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN17) +#define GPIO_PCK1_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN21) +#define GPIO_PCK2_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN18) +#define GPIO_PCK2_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN31) +#define GPIO_PCK2_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN3) + +/* Pulse Width Modulation (PWM) */ + +#define GPIO_PWM0_FI (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN9) +#define GPIO_PWM0_H_1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN0) +#define GPIO_PWM0_H_2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN0) +#define GPIO_PWM0_H_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN11) +#define GPIO_PWM0_H_4 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23) +#define GPIO_PWM0_H_5 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN18) +#define GPIO_PWM0_L_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN19) +#define GPIO_PWM0_L_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN5) +#define GPIO_PWM0_L_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN0) +#define GPIO_PWM0_L_4 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN13) +#define GPIO_PWM1_H_1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN1) +#define GPIO_PWM1_H_2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN1) +#define GPIO_PWM1_H_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN12) +#define GPIO_PWM1_H_4 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN24) +#define GPIO_PWM1_H_5 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN19) +#define GPIO_PWM1_L_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN15) +#define GPIO_PWM1_L_2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN12) +#define GPIO_PWM1_L_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN20) +#define GPIO_PWM1_L_4 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN1) +#define GPIO_PWM2_H_1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN2) +#define GPIO_PWM2_H_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN13) +#define GPIO_PWM2_H_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN25) +#define GPIO_PWM2_H_4 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN4) +#define GPIO_PWM2_H_5 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN20) +#define GPIO_PWM2_L_1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN30) +#define GPIO_PWM2_L_2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN13) +#define GPIO_PWM2_L_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN2) +#define GPIO_PWM2_L_4 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN16) +#define GPIO_PWM3_H_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN14) +#define GPIO_PWM3_H_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN7) +#define GPIO_PWM3_H_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN14) +#define GPIO_PWM3_H_4 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN21) +#define GPIO_PWM3_H_5 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN17) +#define GPIO_PWM3_L_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN22) +#define GPIO_PWM3_L_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN3) +#define GPIO_PWM3_L_3 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN15) + +/* Static Memory Controller (SMC) */ + +#define GPIO_SMC_A0 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN18) +#define GPIO_SMC_A1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN19) +#define GPIO_SMC_A2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN20) +#define GPIO_SMC_A3 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN21) +#define GPIO_SMC_A4 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN22) +#define GPIO_SMC_A5 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN23) +#define GPIO_SMC_A6 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN24) +#define GPIO_SMC_A7 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN25) +#define GPIO_SMC_A8 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN26) +#define GPIO_SMC_A9 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN27) +#define GPIO_SMC_A10 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN28) +#define GPIO_SMC_A11 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN29) +#define GPIO_SMC_A12 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN30) +#define GPIO_SMC_A13 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN31) +#define GPIO_SMC_A14 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN18) +#define GPIO_SMC_A15 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN19) +#define GPIO_SMC_A16 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN20) +#define GPIO_SMC_A17 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN0) +#define GPIO_SMC_A18 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN1) +#define GPIO_SMC_A19 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23) +#define GPIO_SMC_A20 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN24) +#define GPIO_SMC_A21 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN16) +#define GPIO_SMC_A22 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN17) +#define GPIO_SMC_A23 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN25) +#define GPIO_SMC_D0 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN0) +#define GPIO_SMC_D1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN1) +#define GPIO_SMC_D2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN2) +#define GPIO_SMC_D3 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN3) +#define GPIO_SMC_D4 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN4) +#define GPIO_SMC_D5 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN5) +#define GPIO_SMC_D6 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN6) +#define GPIO_SMC_D7 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN7) +#define GPIO_SMC_NANDALE (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN16) +#define GPIO_SMC_NANDCLE (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN17) +#define GPIO_SMC_NANDOE (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN9) +#define GPIO_SMC_NANDWE (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN10) +#define GPIO_SMC_NCS0 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN14) +#define GPIO_SMC_NCS1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN15) +#define GPIO_SMC_NCS2 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22) +#define GPIO_SMC_NCS3 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN12) +#define GPIO_SMC_NRD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN11) +#define GPIO_SMC_NWAIT (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN13) +#define GPIO_SMC_NWE (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN8) + +/* Serial Peripheral Interface (SPI) */ + +#define GPIO_SPI0_MISO (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN12) +#define GPIO_SPI0_MOSI (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN13) +#define GPIO_SPI0_NPCS0 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN11) +#define GPIO_SPI0_NPCS1_1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN31) +#define GPIO_SPI0_NPCS1_2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN14) +#define GPIO_SPI0_NPCS1_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN9) +#define GPIO_SPI0_NPCS1_4 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN4) +#define GPIO_SPI0_NPCS2_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN10) +#define GPIO_SPI0_NPCS2_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN30) +#define GPIO_SPI0_NPCS2_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN2) +#define GPIO_SPI0_NPCS3_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22) +#define GPIO_SPI0_NPCS3_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN3) +#define GPIO_SPI0_NPCS3_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN5) +#define GPIO_SPI0_SPCK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN14) + +/* Synchronous Serial Controller (SSC) */ + +#define GPIO_SSC_RD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN18) +#define GPIO_SSC_RF (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN20) +#define GPIO_SSC_RK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN19) +#define GPIO_SSC_TD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN17) +#define GPIO_SSC_TF (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN15) +#define GPIO_SSC_TK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN16) + +/* Timer/Counters (TC) */ + +#define GPIO_TC0_TCLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN4) +#define GPIO_TC0_TIOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN0) +#define GPIO_TC0_TIOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN1) +#define GPIO_TC1_TCLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN28) +#define GPIO_TC1_TIOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN15) +#define GPIO_TC1_TIOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN16) +#define GPIO_TC2_TCLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN29) +#define GPIO_TC2_TIOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN26) +#define GPIO_TC2_TIOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN27) +#define GPIO_TC3_TCLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN25) +#define GPIO_TC3_TIOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN23) +#define GPIO_TC3_TIOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN24) +#define GPIO_TC4_TCLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN28) +#define GPIO_TC4_TIOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN26) +#define GPIO_TC4_TIOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN27) +#define GPIO_TC5_TCLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN31) +#define GPIO_TC5_TIOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN29) +#define GPIO_TC5_TIOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN30) + +/* Two Wire Interface (TWI) */ + +#define GPIO_TWI0_CK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN4) +#define GPIO_TWI0_D (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN3) +#define GPIO_TWI1_CK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN5) +#define GPIO_TWI1_D (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN4) + +/* Universal Asynchronous Receiver Transceiver (UART) */ + +#define GPIO_UART0_RXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN9) +#define GPIO_UART0_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN10) +#define GPIO_UART1_RXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN2) +#define GPIO_UART1_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN3) + +/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ + +#define GPIO_USART0_CTS (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN8) +#define GPIO_USART0_RTS (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN7) +#define GPIO_USART0_RXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN5) +#define GPIO_USART0_SCK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN2) +#define GPIO_USART0_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN6) + +#define GPIO_USART1_CTS (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN25) +#define GPIO_USART1_DCD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN26) +#define GPIO_USART1_DSR (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN28) +#define GPIO_USART1_DTR (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN27) +#define GPIO_USART1_RI (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN29) + +#define GPIO_USART1_RTS (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN24) +#define GPIO_USART1_RXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN21) +#define GPIO_USART1_SCK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23) +#define GPIO_USART1_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_PINMAP_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4s_pio.h b/nuttx/arch/arm/src/sam34/chip/sam4s_pio.h index c65d5dcbe..93111dddb 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam4s_pio.h +++ b/nuttx/arch/arm/src/sam34/chip/sam4s_pio.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam4s_pio.h + * Parallel Input/Output (PIO) Controller definitions for the SAM4S * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -57,7 +58,7 @@ /* 0x000c: Reserved */ #define SAM_PIO_OER_OFFSET 0x0010 /* Output Enable Register */ #define SAM_PIO_ODR_OFFSET 0x0014 /* Output Disable Register */ -#define SAM_PIO_OSR_OFFSET 0x0018 /* utput Status Register */ +#define SAM_PIO_OSR_OFFSET 0x0018 /* Output Status Register */ /* 0x001c: Reserved */ #define SAM_PIO_IFER_OFFSET 0x0020 /* Glitch Input Filter Enable Register */ #define SAM_PIO_IFDR_OFFSET 0x0024 /* Glitch Input Filter Disable Register */ @@ -82,13 +83,13 @@ #define SAM_PIO_ABCDSR1_OFFSET 0x0070 /* Peripheral Select Register 1 */ #define SAM_PIO_ABCDSR2_OFFSET 0x0074 /* Peripheral Select Register 2 */ /* 0x0078-0x007c: Reserved */ -#define SAM_PIO_IFSCDR_OFFSET 0x0080 /* SInput Filter Slow Clock Disable Register */ +#define SAM_PIO_IFSCDR_OFFSET 0x0080 /* Input Filter Slow Clock Disable Register */ #define SAM_PIO_IFSCER_OFFSET 0x0084 /* Input Filter Slow Clock Enable Register */ #define SAM_PIO_IFSCSR_OFFSET 0x0088 /* Input Filter Slow Clock Status Register */ #define SAM_PIO_SCDR_OFFSET 0x008c /* Slow Clock Divider Debouncing Register */ -#define SAM_PIO_PPDDR_OFFSET 0x0090 /* Pad Pull-down Enable Register */ -#define SAM_PIO_PPDER_OFFSET 0x0094 /* Pad Pull-down Status Register */ -#define SAM_PIO_PPDSR_OFFSET 0x0098 /* Input Filter Slow Clock Disable Register */ +#define SAM_PIO_PPDDR_OFFSET 0x0090 /* Pad Pull Down Disable Register */ +#define SAM_PIO_PPDER_OFFSET 0x0094 /* PIO Pad Pull Down Enable Register */ +#define SAM_PIO_PPDSR_OFFSET 0x0098 /* PIO Pad Pull Down Status Register */ /* 0x009c: Reserved */ #define SAM_PIO_OWER_OFFSET 0x00a0 /* Output Write Enable */ #define SAM_PIO_OWDR_OFFSET 0x00a4 /* Output Write Disable */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4s_vectors.h b/nuttx/arch/arm/src/sam34/chip/sam4s_vectors.h new file mode 100644 index 000000000..b2587cd12 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam4s_vectors.h @@ -0,0 +1,92 @@ +/************************************************************************************************ + * arch/arm/src/sam34/chip/sam42_vectors.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ +/* This file is included by sam_vectors.S. It provides the macro VECTOR that + * supplies ach SAM3U vector in terms of a (lower-case) ISR label and an + * (upper-case) IRQ number as defined in arch/arm/include/sam/sam3u_irq.h. + * sam_vectors.S will defined the VECTOR in different ways in order to generate + * the interrupt vectors and handlers in their final form. + */ + +/* If the common ARMv7-M vector handling is used, then all it needs is the following + * definition that provides the number of supported vectors. + */ + +#ifdef CONFIG_ARMV7M_CMNVECTOR + +/* Reserve 35 interrupt table entries for I/O interrupts. */ + +# define ARMV7M_PERIPHERAL_INTERRUPTS 35 + +#else + VECTOR(sam_supc, SAM_IRQ_SUPC) /* Vector 16+0: Supply Controller */ + VECTOR(sam_rstc, SAM_IRQ_RSTC) /* Vector 16+1: Reset Controller */ + VECTOR(sam_rtc, SAM_IRQ_RTC) /* Vector 16+2: Real Time Clock */ + VECTOR(sam_rtt, SAM_IRQ_RTT) /* Vector 16+3: Real Time Timer */ + VECTOR(sam_wdt, SAM_IRQ_WDT) /* Vector 16+4: Watchdog Timer */ + VECTOR(sam_pmc, SAM_IRQ_PMC) /* Vector 16+5: Power Management Controller */ + VECTOR(sam_eefc0, SAM_IRQ_EEFC0) /* Vector 16+6: Enhanced Embedded Flash Controller 0 */ + VECTOR(sam_eefc1, SAM_IRQ_EEFC1) /* Vector 16+7: Enhanced Embedded Flash Controller 1 */ + VECTOR(sam_uart0, SAM_IRQ_UART0) /* Vector 16+8: Universal Asynchronous Receiver Transmitter 0 */ + VECTOR(sam_uart1, SAM_IRQ_UART1) /* Vector 16+9: Universal Asynchronous Receiver Transmitter 1 */ + VECTOR(sam_smc, SAM_IRQ_SMC) /* Vector 16+10: Static Memory Controller */ + VECTOR(sam_pioa, SAM_IRQ_PIOA) /* Vector 16+11: Parallel I/O Controller A */ + VECTOR(sam_piob, SAM_IRQ_PIOB) /* Vector 16+12: Parallel I/O Controller B */ + VECTOR(sam_pioc, SAM_IRQ_PIOC) /* Vector 16+13: Parallel I/O Controller C */ + VECTOR(sam_usart0, SAM_IRQ_USART0) /* Vector 16+14: USART 0 */ + VECTOR(sam_usart1, SAM_IRQ_USART1) /* Vector 16+15: USART 1 */ + UNUSED(SAM_IRQ_RESERVED_16) /* Vector 16+16: Reserved */ + UNUSED(SAM_IRQ_RESERVED_17) /* Vector 16+17: Reserved */ + VECTOR(sam_hsmci, SAM_IRQ_HSMCI) /* Vector 16+18: High Speed Multimedia Card Interface */ + VECTOR(sam_twi0, SAM_IRQ_TWI0) /* Vector 16+19: Two-Wire Interface 0 */ + VECTOR(sam_twi1, SAM_IRQ_TWI1) /* Vector 16+20: Two-Wire Interface 1 */ + VECTOR(sam_spi, SAM_PID_SPI) /* Vector 16+21: Serial Peripheral Interface */ + VECTOR(sam_ssc, SAM_IRQ_SSC) /* Vector 16+22: Synchronous Serial Controller */ + VECTOR(sam_tc0, SAM_IRQ_TC0) /* Vector 16+23: Timer Counter 0 */ + VECTOR(sam_tc1, SAM_IRQ_TC1) /* Vector 16+24: Timer Counter 1 */ + VECTOR(sam_tc2, SAM_IRQ_TC2) /* Vector 16+25: Timer Counter 2 */ + VECTOR(sam_tc3, SAM_IRQ_TC3) /* Vector 16+26: Timer Counter 3 */ + VECTOR(sam_tc4, SAM_IRQ_TC4) /* Vector 16+27: Timer Counter 4 */ + VECTOR(sam_tc5, SAM_IRQ_TC5) /* Vector 16+28: Timer Counter 5 */ + VECTOR(sam_adc, SAM_IRQ_ADC) /* Vector 16+29: Analog To Digital Converter */ + VECTOR(sam_dacc, SAM_IRQ_DACC) /* Vector 16+30: Digital To Analog Converter */ + VECTOR(sam_pwm, SAM_IRQ_PWM) /* Vector 16+31: Pulse Width Modulation */ + VECTOR(sam_crccu, SAM_IRQ_CRCCU) /* Vector 16+32: CRC Calculation Unit */ + VECTOR(sam_acc, SAM_IRQ_ACC) /* Vector 16+33: Analog Comparator */ + VECTOR(sam_udp, SAM_IRQ_UDP) /* Vector 16+34: USB Device Port */ +#endif diff --git a/nuttx/arch/arm/src/sam34/chip/sam_chipid.h b/nuttx/arch/arm/src/sam34/chip/sam_chipid.h index c98130efe..fd5fc977a 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_chipid.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_chipid.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam_chipid.h + * CHIPID Register Definitions for the SAM3U, SAM4S, and SAM4L * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -100,10 +101,11 @@ #define CHIPID_CIDR_SRAMSIZ_MASK (15 << CHIPID_CIDR_SRAMSIZ_SHIFT) # define CHIPID_CIDR_SRAMSIZ_48KB (0 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 48K bytes */ # define CHIPID_CIDR_SRAMSIZ_1KB (1 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 1K bytes */ +# define CHIPID_CIDR_SRAMSIZ_192KB (1 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 192K bytes (SAM4S) */ # define CHIPID_CIDR_SRAMSIZ_2KB (2 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 2K bytes */ # define CHIPID_CIDR_SRAMSIZ_6KB (3 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 6K bytes */ # define CHIPID_CIDR_SRAMSIZ_112KB (4 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 112K bytes */ -# define CHIPID_CIDR_SRAMSIZ_24KB (4 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 24K bytes */ +# define CHIPID_CIDR_SRAMSIZ_24KB (4 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 24K bytes (SAM4S, SAM4L) */ # define CHIPID_CIDR_SRAMSIZ_4KB (5 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 4K bytes */ # define CHIPID_CIDR_SRAMSIZ_80KB (6 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 80K bytes */ # define CHIPID_CIDR_SRAMSIZ_160KB (7 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 160K bytes */ @@ -142,27 +144,32 @@ # define CHIPID_CIDR_ARCH_SAM3XXE (0x85 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3XxE Series (144-pin version) */ # define CHIPID_CIDR_ARCH_SAM3XXG (0x86 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3XxG Series (208/217-pin version) */ # define CHIPID_CIDR_ARCH_SAM3SXA (0x88 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SxA Series (48-pin version) */ +# define CHIPID_CIDR_ARCH_SAM4SXA (0x88 << CHIPID_CIDR_ARCH_SHIFT) /* SAM4SxA Series (48-pin version) */ # define CHIPID_CIDR_ARCH_SAM3SXB (0x89 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SxB Series (64-pin version) */ +# define CHIPID_CIDR_ARCH_SAM4SXB (0x89 << CHIPID_CIDR_ARCH_SHIFT) /* SAM34xB Series (64-pin version) */ # define CHIPID_CIDR_ARCH_SAM3SXC (0x8a << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SxC Series (100-pin version) */ +# define CHIPID_CIDR_ARCH_SAM4SXC (0x8a << CHIPID_CIDR_ARCH_SHIFT) /* SAM4SxC Series (100-pin version) */ # define CHIPID_CIDR_ARCH_AT91X92 (0x92 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x92 Series */ # define CHIPID_CIDR_ARCH_SAM3NXA (0x93 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3NxA Series (48-pin version) */ # define CHIPID_CIDR_ARCH_SAM3NXB (0x94 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3NxB Series (64-pin version) */ -# define CHIPID_CIDR_ARCH_SAM3NxC (0x95 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3NxC Series (100-pin version) */ -# define CHIPID_CIDR_ARCH_SAM3NXC (0x99 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SDxB SAM3SDxB Series (64-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3NXC (0x95 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3NxC Series (100-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3DXB (0x99 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SDxB SAM3SDxB Series (64-pin version) */ # define CHIPID_CIDR_ARCH_SAM3SDXC (0x9a << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SDxC Series (100-pin version) */ # define CHIPID_CIDR_ARCH_SAM5A (0xa5 << CHIPID_CIDR_ARCH_SHIFT) /* SAM5A */ -# define CHIPID_CIDR_ARCH_SAM4L (0xb0 << CHIPID_CIDR_ARCH_SHIFT) /* SAM4Lxx Series */ +# define CHIPID_CIDR_ARCH_SAM4LA (0xb0 << CHIPID_CIDR_ARCH_SHIFT) /* SAM4LxA Series */ +# define CHIPID_CIDR_ARCH_SAM4LB (0xb1 << CHIPID_CIDR_ARCH_SHIFT) /* SAM4LxB Series */ +# define CHIPID_CIDR_ARCH_SAM4LC (0xb2 << CHIPID_CIDR_ARCH_SHIFT) /* SAM4LxC Series */ # define CHIPID_CIDR_ARCH_AT75CXX (0xf0 << CHIPID_CIDR_ARCH_SHIFT) /* AT75Cxx Series */ #define CHIPID_CIDR_NVPTYP_SHIFT (28) /* Bits 28-30: Nonvolatile Program Memory Type */ #define CHIPID_CIDR_NVPTYP_MASK (7 << CHIPID_CIDR_NVPTYP_SHIFT) -# define CHIPID_CIDR_NVPTYP ROM (0 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM */ -# define CHIPID_CIDR_NVPTYP FLASH (1 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROMless or on-chip Flash */ -# define CHIPID_CIDR_NVPTYP SRAM (4 << CHIPID_CIDR_NVPTYP_SHIFT) /* SRAM emulating ROM */ -# define CHIPID_CIDR_NVPTYP EFLASH (2 << CHIPID_CIDR_NVPTYP_SHIFT) /* Embedded Flash Memory */ -# define CHIPID_CIDR_NVPTYP REFLASH (3 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM and Embedded Flash Memory */ +# define CHIPID_CIDR_NVPTYP_ROM (0 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM */ +# define CHIPID_CIDR_NVPTYP_FLASH (1 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROMless or on-chip Flash */ +# define CHIPID_CIDR_NVPTYP_SRAM (4 << CHIPID_CIDR_NVPTYP_SHIFT) /* SRAM emulating ROM */ +# define CHIPID_CIDR_NVPTYP_EFLASH (2 << CHIPID_CIDR_NVPTYP_SHIFT) /* Embedded Flash Memory */ +# define CHIPID_CIDR_NVPTYP_REFLASH (3 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM and Embedded Flash Memory */ #define CHIPID_CIDR_EXT (1 << 31) /* Bit 31: Extension Flag */ -/* Chip ID Extension Register */ +/* Chip ID Extension Register (32-bit value for SAM3U and SAM4S) */ #ifdef CONFIG_ARCH_CHIP_SAM4L # define CHIPID_EXID_AES (1 << 0) /* Bit 0: AES Option */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_hsmci.h b/nuttx/arch/arm/src/sam34/chip/sam_hsmci.h index dfee208c3..887d561ca 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_hsmci.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_hsmci.h @@ -70,13 +70,17 @@ #define SAM_HSMCI_IER_OFFSET 0x0044 /* Interrupt Enable Register */ #define SAM_HSMCI_IDR_OFFSET 0x0048 /* Interrupt Disable Register */ #define SAM_HSMCI_IMR_OFFSET 0x004c /* Interrupt Mask Register */ -#define SAM_HSMCI_DMA_OFFSET 0x0050 /* DMA Configuration Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_HSMCI_DMA_OFFSET 0x0050 /* DMA Configuration Register */ +#endif + #define SAM_HSMCI_CFG_OFFSET 0x0054 /* Configuration Register */ /* 0x0058-0x00e0: Reserved */ #define SAM_HSMCI_WPMR_OFFSET 0x00e4 /* Write Protection Mode Register */ #define SAM_HSMCI_WPSR_OFFSET 0x00e8 /* Write Protection Status Register */ /* 0x00ec-0x00fc: Reserved */ - /* 0x0100-0x0124: Reserved */ + /* 0x0100-0x0124: Reserved for PCD registers */ #define SAM_HSMCI_FIFO_OFFSET 0x0200 /* 0x0200-0x3ffc FIFO Memory Aperture */ /* HSMCI register adresses **************************************************************/ @@ -99,7 +103,11 @@ #define SAM_HSMCI_IER (SAM_MCI_BASE+SAM_HSMCI_IER_OFFSET) #define SAM_HSMCI_IDR (SAM_MCI_BASE+SAM_HSMCI_IDR_OFFSET) #define SAM_HSMCI_IMR (SAM_MCI_BASE+SAM_HSMCI_IMR_OFFSET) -#define SAM_HSMCI_DMA (SAM_MCI_BASE+SAM_HSMCI_DMA_OFFSET) + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_HSMCI_DMA (SAM_MCI_BASE+SAM_HSMCI_DMA_OFFSET) +#endif + #define SAM_HSMCI_CFG (SAM_MCI_BASE+SAM_HSMCI_CFG_OFFSET) #define SAM_HSMCI_WPMR (SAM_MCI_BASE+SAM_HSMCI_WPMR_OFFSET) #define SAM_HSMCI_WPSR (SAM_MCI_BASE+SAM_HSMCI_WPSR_OFFSET) @@ -126,8 +134,15 @@ #define HSMCI_MR_WRPROOF (1 << 12) /* Bit 12: Write Proof Enable */ #define HSMCI_MR_FBYTE (1 << 13) /* Bit 13: Force Byte Transfer */ #define HSMCI_MR_PADV (1 << 14) /* Bit 14: Padding Value */ -#define HSMCI_MR_BLKLEN_SHIFT (16) /* Bits 16-31: Data Block Length */ -#define HSMCI_MR_BLKLEN_MASK (0xffff << HSMCI_MR_BLKLEN_SHIFT) + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define HSMCI_MR_PDCMODE (1 << 15) /* Bit 15: PDC-oriented Mode */ +#endif + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define HSMCI_MR_BLKLEN_SHIFT (16) /* Bits 16-31: Data Block Length */ +# define HSMCI_MR_BLKLEN_MASK (0xffff << HSMCI_MR_BLKLEN_SHIFT) +#endif /* HSMCI Data Timeout Register */ @@ -157,6 +172,8 @@ # define HSMCI_SDCR_SDCBUS_4BIT (2 << HSMCI_SDCR_SDCBUS_SHIFT) # define HSMCI_SDCR_SDCBUS_8BIT (3 << HSMCI_SDCR_SDCBUS_SHIFT) +/* HSMCI Argument Register (32-bit value) */ + /* HSMCI Command Register */ #define HSMCI_CMDR_CMDNB_SHIFT (0) /* Bits 0-5: Command Number */ @@ -200,7 +217,7 @@ # define HSMCI_CMDR_IOSPCMD_SUSP (1 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Suspend Command */ # define HSMCI_CMDR_IOSPCMD_RESUME (2 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Resume Command */ #define HSMCI_CMDR_ATACS (1 << 26) /* Bit 26: ATA with Command Completion Signal */ -#define HSMCI_CMDR_BOOTACK (1 << 17) /* Bit 27: Boot Operation Acknowledge */ +#define HSMCI_CMDR_BOOTACK (1 << 27) /* Bit 27: Boot Operation Acknowledge */ /* HSMCI Block Register */ @@ -224,6 +241,10 @@ # define HSMCI_CSTOR_CSTOMUL_65536 (6 << HSMCI_CSTOR_CSTOMUL_SHIFT) # define HSMCI_CSTOR_CSTOMUL_1048576 (7 << HSMCI_CSTOR_CSTOMUL_SHIFT) +/* HSMCI Response Registers (32-bit data) */ +/* HSMCI Receive Data Registers (32-bit data) */ +/* HSMCI Transmit Data Registers (32-bit data) */ + /* HSMCI Status Register, HSMCI Interrupt Enable Register, HSMCI Interrupt Disable * Register, and HSMCI Interrupt Mask Register common bit-field definitions */ @@ -234,9 +255,21 @@ #define HSMCI_INT_BLKE (1 << 3) /* Bit 3: Data Block Ended */ #define HSMCI_INT_DTIP (1 << 4) /* Bit 4: Data Transfer in Progress */ #define HSMCI_INT_NOTBUSY (1 << 5) /* Bit 6: HSMCI Not Busy */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define HSMCI_INT_ENDRX (1 << 6) /* Bit 6: End of RX Buffer */ +# define HSMCI_INT_ENDTX (1 << 7) /* Bit 7: End of TX Buffer */ +#endif + #define HSMCI_INT_SDIOIRQA (1 << 8) /* Bit 8: SDIO Interrupt for Slot A */ #define HSMCI_INT_SDIOWAIT (1 << 12) /* Bit 12: SDIO Read Wait Operation Status */ #define HSMCI_INT_CSRCV (1 << 13) /* Bit 13: CE-ATA Completion Signal Received */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define HSMCI_INT_RXBUFF (1 << 14) /* Bit 14: RXBUFF: RX Buffer Full */ +# define HSMCI_INT_TXBUFE (1 << 15) /* Bit 15: TXBUFE: TX Buffer Empty */ +#endif + #define HSMCI_INT_RINDE (1 << 16) /* Bit 16: Response Index Error */ #define HSMCI_INT_RDIRE (1 << 17) /* Bit 17: Response Direction Error */ #define HSMCI_INT_RCRCE (1 << 18) /* Bit 18: Response CRC Error */ @@ -245,8 +278,12 @@ #define HSMCI_INT_DCRCE (1 << 21) /* Bit 21: Data CRC Error */ #define HSMCI_INT_DTOE (1 << 22) /* Bit 22: Data Time-out Error */ #define HSMCI_INT_CSTOE (1 << 23) /* Bit 23: Completion Signal Time-out Error */ -#define HSMCI_INT_BLKOVRE (1 << 24) /* Bit 24: DMA Block Overrun Error */ -#define HSMCI_INT_DMADONE (1 << 25) /* Bit 25: DMA Transfer done */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define HSMCI_INT_BLKOVRE (1 << 24) /* Bit 24: DMA Block Overrun Error */ +# define HSMCI_INT_DMADONE (1 << 25) /* Bit 25: DMA Transfer done */ +#endif + #define HSMCI_INT_FIFOEMPTY (1 << 26) /* Bit 26: FIFO empty flag */ #define HSMCI_INT_XFRDONE (1 << 27) /* Bit 27: Transfer Done flag */ #define HSMCI_INT_ACKRCV (1 << 28) /* Bit 28: Boot Operation Acknowledge Received */ @@ -256,11 +293,13 @@ /* HSMCI DMA Configuration Register */ -#define HSMCI_DMA_OFFSET_SHIFT (0) /* Bits 0-1: DMA Write Buffer Offset */ -#define HSMCI_DMA_OFFSET_MASK (3 << HSMCI_DMA_OFFSET_SHIFT) -#define HSMCI_DMA_CHKSIZE (1 << 4) /* Bit 4: DMA Channel Read and Write Chunk Size */ -#define HSMCI_DMA_DMAEN (1 << 8) /* Bit 8: DMA Hardware Handshaking Enable */ -#define HSMCI_DMA_ROPT (1 << 12) /* Bit 12: Read Optimization with padding */ +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define HSMCI_DMA_OFFSET_SHIFT (0) /* Bits 0-1: DMA Write Buffer Offset */ +# define HSMCI_DMA_OFFSET_MASK (3 << HSMCI_DMA_OFFSET_SHIFT) +# define HSMCI_DMA_CHKSIZE (1 << 4) /* Bit 4: DMA Channel Read and Write Chunk Size */ +# define HSMCI_DMA_DMAEN (1 << 8) /* Bit 8: DMA Hardware Handshaking Enable */ +# define HSMCI_DMA_ROPT (1 << 12) /* Bit 12: Read Optimization with padding */ +#endif /* HSMCI Configuration Register */ @@ -274,13 +313,18 @@ #define HSMCI_WPMR_WP_EN (1 << 0) /* Bit 0: Write Protection Enable */ #define HSMCI_WPMR_WP_KEY_SHIFT (8) /* Bits 8-31: Write Protection Key password */ #define HSMCI_WPMR_WP_KEY_MASK (0x00ffffff << HSMCI_WPMR_WP_KEY_SHIFT) +# define HSMCI_WPMR_WP_KEY (0x004d4349 << HSMCI_WPMR_WP_KEY_SHIFT) /* HSMCI Write Protect Status Register */ -#define HSMCI_WPSR_WP_VS_SHIFT (0) /* Bits 0-3: Write Protection Violation Status */ -#define HSMCI_WPSR_WP_VS_MASK (15 << HSMCI_WPSR_WP_VS_SHIFT) -#define HSMCI_WPSR_WP_VSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */ -#define HSMCI_WPSR_WP_VSRC_MASK (0xffff << HSMCI_WPSR_WP_VSRC_SHIFT) +#define HSMCI_WPSR_VS_SHIFT (0) /* Bits 0-3: Write Protection Violation Status */ +#define HSMCI_WPSR_VS_MASK (15 << HSMCI_WPSR_VS_SHIFT) +# define HSMCI_WPSR_VS_NONE (0 << HSMCI_WPSR_VS_SHIFT) +# define HSMCI_WPSR_VS_WRITE (1 << HSMCI_WPSR_VS_SHIFT) +# define HSMCI_WPSR_VS_RESET (2 << HSMCI_WPSR_VS_SHIFT) +# define HSMCI_WPSR_VS_BOTH (3 << HSMCI_WPSR_VS_SHIFT) +#define HSMCI_WPSR_VSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */ +#define HSMCI_WPSR_VSRC_MASK (0xffff << HSMCI_WPSR_VSRC_SHIFT) /**************************************************************************************** * Public Types diff --git a/nuttx/arch/arm/src/sam34/chip/sam_memorymap.h b/nuttx/arch/arm/src/sam34/chip/sam_memorymap.h index a1fe60382..05e53ec8e 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_memorymap.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_memorymap.h @@ -47,6 +47,8 @@ # include "chip/sam3u_memorymap.h" #elif defined(CONFIG_ARCH_CHIP_SAM4L) # include "chip/sam4l_memorymap.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# include "chip/sam4s_memorymap.h" #else # error Unrecognized SAM architecture #endif diff --git a/nuttx/arch/arm/src/sam34/chip/sam_pinmap.h b/nuttx/arch/arm/src/sam34/chip/sam_pinmap.h index 6adb547bf..74538cdaf 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_pinmap.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_pinmap.h @@ -45,6 +45,10 @@ #if defined(CONFIG_ARCH_CHIP_SAM3U) # include "chip/sam3u_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4L) +# include "chip/sam4l_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# include "chip/sam4s_pinmap.h" #else # error Unrecognized SAM architecture #endif diff --git a/nuttx/arch/arm/src/sam34/chip/sam_pmc.h b/nuttx/arch/arm/src/sam34/chip/sam_pmc.h deleted file mode 100644 index f6a98e3ee..000000000 --- a/nuttx/arch/arm/src/sam34/chip/sam_pmc.h +++ /dev/null @@ -1,315 +0,0 @@ -/**************************************************************************************** - * arch/arm/src/sam34/chip/sam_pmc.h - * - * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <gnutt@nuttx.org> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_PMC_H -#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_PMC_H - -/**************************************************************************************** - * Included Files - ****************************************************************************************/ - -#include <nuttx/config.h> - -#include "chip.h" -#include "chip/sam_memorymap.h" - -/**************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************/ - -/* PMC register offsets *****************************************************************/ - -#define SAM_PMC_SCER_OFFSET 0x0000 /* System Clock Enable Register */ -#define SAM_PMC_SCDR_OFFSET 0x0004 /* System Clock Disable Register */ -#define SAM_PMC_SCSR_OFFSET 0x0008 /* System Clock Status Register */ - /* 0x000c: Reserved */ -#define SAM_PMC_PCER_OFFSET 0x0010 /* Peripheral Clock Enable Register */ -#define SAM_PMC_PCDR_OFFSET 0x0014 /* Peripheral Clock Disable Register */ -#define SAM_PMC_PCSR_OFFSET 0x0018 /* Peripheral Clock Status Register */ -#define SAM_CKGR_UCKR_OFFSET 0x001c /* UTMI Clock Register */ -#define SAM_CKGR_MOR_OFFSET 0x0020 /* Main Oscillator Register */ -#define SAM_CKGR_MCFR_OFFSET 0x0024 /* Main Clock Frequency Register */ -#define SAM_CKGR_PLLAR_OFFSET 0x0028 /* PLLA Register */ - /* 0x002c: Reserved */ -#define SAM_PMC_MCKR_OFFSET 0x0030 /* Master Clock Register */ - /* 0x0034-0x003C Reserved */ -#define SAM_PMC_PCK_OFFSET(n) (0x0040+((n)<<2)) -#define SAM_PMC_PCK0_OFFSET 0x0040 /* Programmable Clock 0 Register */ -#define SAM_PMC_PCK1_OFFSET 0x0044 /* Programmable Clock 1 Register */ -#define SAM_PMC_PCK2_OFFSET 0x0048 /* Programmable Clock 2 Register */ - /* 0x004c-0x005c: Reserved */ -#define SAM_PMC_IER_OFFSET 0x0060 /* Interrupt Enable Register */ -#define SAM_PMC_IDR_OFFSET 0x0064 /* Interrupt Disable Register */ -#define SAM_PMC_SR_OFFSET 0x0068 /* Status Register */ -#define SAM_PMC_IMR_OFFSET 0x006c /* Interrupt Mask Register */ -#define SAM_PMC_FSMR_OFFSET 0x0070 /* Fast Startup Mode Register */ -#define SAM_PMC_FSPR_OFFSET 0x0074 /* Fast Startup Polarity Register */ -#define SAM_PMC_FOCR_OFFSET 0x0078 /* Fault Output Clear Register */ - /* 0x007c-0x00fc: Reserved */ -#define SAM_PMC_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */ -#define SAM_PMC_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */ - -/* PMC register adresses ****************************************************************/ - -#define SAM_PMC_SCER (SAM_PMC_BASE+SAM_PMC_SCER_OFFSET) -#define SAM_PMC_SCDR (SAM_PMC_BASE+SAM_PMC_SCDR_OFFSET) -#define SAM_PMC_SCSR (SAM_PMC_BASE+SAM_PMC_SCSR_OFFSET) -#define SAM_PMC_PCER (SAM_PMC_BASE+SAM_PMC_PCER_OFFSET) -#define SAM_PMC_PCDR (SAM_PMC_BASE+SAM_PMC_PCDR_OFFSET) -#define SAM_PMC_PCSR (SAM_PMC_BASE+SAM_PMC_PCSR_OFFSET) -#define SAM_CKGR_UCKR (SAM_PMC_BASE+SAM_CKGR_UCKR_OFFSET) -#define SAM_CKGR_MOR (SAM_PMC_BASE+SAM_CKGR_MOR_OFFSET) -#define SAM_CKGR_MCFR (SAM_PMC_BASE+SAM_CKGR_MCFR_OFFSET) -#define SAM_CKGR_PLLAR (SAM_PMC_BASE+SAM_CKGR_PLLAR_OFFSET) -#define SAM_PMC_MCKR (SAM_PMC_BASE+SAM_PMC_MCKR_OFFSET) -#define SAM_PMC_PCK(n) (SAM_PMC_BASE+SAM_PMC_PCK_OFFSET(n)) -#define SAM_PMC_PCK0 (SAM_PMC_BASE+SAM_PMC_PCK0_OFFSET) -#define SAM_PMC_PCK1 (SAM_PMC_BASE+SAM_PMC_PCK1_OFFSET) -#define SAM_PMC_PCK2 (SAM_PMC_BASE+SAM_PMC_PCK2_OFFSET) -#define SAM_PMC_IER (SAM_PMC_BASE+SAM_PMC_IER_OFFSET) -#define SAM_PMC_IDR (SAM_PMC_BASE+SAM_PMC_IDR_OFFSET) -#define SAM_PMC_SR (SAM_PMC_BASE+SAM_PMC_SR_OFFSET) -#define SAM_PMC_IMR (SAM_PMC_BASE+SAM_PMC_IMR_OFFSET) -#define SAM_PMC_FSMR (SAM_PMC_BASE+SAM_PMC_FSMR_OFFSET) -#define SAM_PMC_FSPR (SAM_PMC_BASE+SAM_PMC_FSPR_OFFSET) -#define SAM_PMC_FOCR (SAM_PMC_BASE+SAM_PMC_FOCR_OFFSET) -#define SAM_PMC_WPMR (SAM_PMC_BASE+SAM_PMC_WPMR_OFFSET) -#define SAM_PMC_WPSR (SAM_PMC_BASE+SAM_PMC_WPSR_OFFSET) - -/* PMC register bit definitions *********************************************************/ - -/* PMC System Clock Enable Register, PMC System Clock Disable Register, and PMC System - * Clock Status Register common bit-field definitions - */ - -#define PMC_PCK(n) (1 <<((n)+8) -#define PMC_PCK0 (1 << 8) /* Bit 8: Programmable Clock 0 Output Enable */ -#define PMC_PCK1 (1 << 9) /* Bit 9: Programmable Clock 1 Output Enable */ -#define PMC_PCK2 (1 << 10) /* Bit 10: Programmable Clock 2 Output Enable */ - -/* PMC Peripheral Clock Enable Register, PMC Peripheral Clock Disable Register, and PMC - * Peripheral Clock Status Register common bit-field definitions. - */ - -#define PMC_PID(n) (1<<(n)) -#define PMC_PID2 (1 << 2) /* Bit 2: Peripheral Clock 2 Enable */ -#define PMC_PID3 (1 << 3) /* Bit 3: Peripheral Clock 3 Enable */ -#define PMC_PID4 (1 << 4) /* Bit 4: Peripheral Clock 4 Enable */ -#define PMC_PID5 (1 << 5) /* Bit 5: Peripheral Clock 5 Enable */ -#define PMC_PID6 (1 << 6) /* Bit 6: Peripheral Clock 6 Enable */ -#define PMC_PID7 (1 << 7) /* Bit 7: Peripheral Clock 7 Enable */ -#define PMC_PID8 (1 << 8) /* Bit 8: Peripheral Clock 8 Enable */ -#define PMC_PID9 (1 << 9) /* Bit 9: Peripheral Clock 9 Enable */ -#define PMC_PID10 (1 << 10) /* Bit 10: Peripheral Clock 10 Enable */ -#define PMC_PID11 (1 << 11) /* Bit 11: Peripheral Clock 11 Enable */ -#define PMC_PID12 (1 << 12) /* Bit 12: Peripheral Clock 12 Enable */ -#define PMC_PID13 (1 << 13) /* Bit 13: Peripheral Clock 13 Enable */ -#define PMC_PID14 (1 << 14) /* Bit 14: Peripheral Clock 14 Enable */ -#define PMC_PID15 (1 << 15) /* Bit 15: Peripheral Clock 15 Enable */ -#define PMC_PID16 (1 << 16) /* Bit 16: Peripheral Clock 16 Enable */ -#define PMC_PID17 (1 << 17) /* Bit 17: Peripheral Clock 17 Enable */ -#define PMC_PID18 (1 << 18) /* Bit 18: Peripheral Clock 18 Enable */ -#define PMC_PID19 (1 << 19) /* Bit 19: Peripheral Clock 19 Enable */ -#define PMC_PID20 (1 << 20) /* Bit 20: Peripheral Clock 20 Enable */ -#define PMC_PID21 (1 << 21) /* Bit 21: Peripheral Clock 21 Enable */ -#define PMC_PID22 (1 << 22) /* Bit 22: Peripheral Clock 22 Enable */ -#define PMC_PID23 (1 << 23) /* Bit 23: Peripheral Clock 23 Enable */ -#define PMC_PID24 (1 << 24) /* Bit 24: Peripheral Clock 24 Enable */ -#define PMC_PID25 (1 << 25) /* Bit 25: Peripheral Clock 25 Enable */ -#define PMC_PID26 (1 << 26) /* Bit 26: Peripheral Clock 26 Enable */ -#define PMC_PID27 (1 << 27) /* Bit 27: Peripheral Clock 27 Enable */ -#define PMC_PID28 (1 << 28) /* Bit 28: Peripheral Clock 28 Enable */ -#define PMC_PID29 (1 << 29) /* Bit 29: Peripheral Clock 29 Enable */ -#define PMC_PID30 (1 << 30) /* Bit 30: Peripheral Clock 30 Enable */ -#define PMC_PID31 (1 << 31) /* Bit 31: Peripheral Clock 31 Enable */ - -/* PMC UTMI Clock Configuration Register */ - -#define CKGR_UCKR_UPLLEN (1 << 16) /* Bit 16: UTMI PLL Enable */ -#define CKGR_UCKR_UPLLCOUNT_SHIFT (20) /* Bits 20-23: UTMI PLL Start-up Time */ -#define CKGR_UCKR_UPLLCOUNT_MASK (15 << CKGR_UCKR_UPLLCOUNT_SHIFT) - -/* PMC Clock Generator Main Oscillator Register */ - -#define CKGR_MOR_MOSCXTEN (1 << 0) /* Bit 0: Main Crystal Oscillator Enable */ -#define CKGR_MOR_MOSCXTBY (1 << 1) /* Bit 1: Main Crystal Oscillator Bypass */ -#define CKGR_MOR_WAITMODE (1 << 2) /* Bit 2: Wait Mode Command */ -#define CKGR_MOR_MOSCRCEN (1 << 3) /* Bit 3: Main On-Chip RC Oscillator Enable */ -#define CKGR_MOR_MOSCRCF_SHIFT (4) /* Bits 4-6: Main On-Chip RC Oscillator Frequency Selection */ -#define CKGR_MOR_MOSCRCF_MASK (7 << CKGR_MOR_MOSCRCF_SHIFT) -#define CKGR_MOR_MOSCXTST_SHIFT (8) /* Bits 8-16: Main Crystal Oscillator Start-up Time */ -#define CKGR_MOR_MOSCXTST_MASK (0x1ff << CKGR_MOR_MOSCXTST_SHIFT) -#define CKGR_MOR_KEY_SHIFT (16) /* Bits 16-23: Password */ -#define CKGR_MOR_KEY_MASK (0xff << CKGR_MOR_KEY_SHIFT) -#define CKGR_MOR_MOSCSEL (1 << 24) /* Bit 24: Main Oscillator Selection */ -#define CKGR_MOR_CFDEN (1 << 25) /* Bit 25: Clock Failure Detector Enable */ - -/* PMC Clock Generator Main Clock Frequency Register */ - -#define CKGR_MCFR_MAINF_SHIFT (0) /* Bits 0-15: Main Clock Frequency */ -#define CKGR_MCFR_MAINF_MASK (0xffff << CKGR_MCFR_MAINF_SHIFT) -#define CKGR_MCFR_MAINFRDY (1 << 16) /* Bit 16: Main Clock Ready */ - -/* PMC Clock Generator PLLA Register */ - -#define CKGR_PLLAR_DIVA_SHIFT (0) /* Bits 0-7: Divider */ -#define CKGR_PLLAR_DIVA_MASK (0xff << CKGR_PLLAR_DIVA_SHIFT) -# define CKGR_PLLAR_DIVA_ZERO (0 << CKGR_PLLAR_DIVA_SHIFT) /* Divider output is 0 */ -# define CKGR_PLLAR_DIVA_BYPASS (1 << CKGR_PLLAR_DIVA_SHIFT) /* Divider is bypassed (DIVA=1) */ -# define CKGR_PLLAR_DIVA(n) ((n) << CKGR_PLLAR_DIVA_SHIFT) /* Divider output is DIVA=n, n=2..255 */ -#define CKGR_PLLAR_PLLACOUNT_SHIFT (8) /* Bits 8-13: PLLA Counter */ -#define CKGR_PLLAR_PLLACOUNT_MASK (63 << CKGR_PLLAR_PLLACOUNT_SHIFT) -#define CKGR_PLLAR_STMODE_SHIFT (14) /* Bits 14-15: Start Mode */ -#define CKGR_PLLAR_STMODE_MASK (3 << CKGR_PLLAR_STMODE_SHIFT) -# define CKGR_PLLAR_STMODE_FAST (0 << CKGR_PLLAR_STMODE_SHIFT) /* Fast Startup */ -# define CKGR_PLLAR_STMODE_NORMAL (2 << CKGR_PLLAR_STMODE_SHIFT) /* Normal Startup */ -#define CKGR_PLLAR_MULA_SHIFT (16) /* Bits 16-26: PLLA Multiplier */ -#define CKGR_PLLAR_MULA_MASK (0x7ff << CKGR_PLLAR_MULA_SHIFT) -#define CKGR_PLLAR_ONE (1 << 29) /* Bit 29: Always one */ - -/* PMC Master Clock Register */ - -#define PMC_MCKR_CSS_SHIFT (0) /* Bits 0-1: Master Clock Source Selection */ -#define PMC_MCKR_CSS_MASK (3 << PMC_MCKR_CSS_SHIFT) -# define PMC_MCKR_CSS_SLOW (0 << PMC_MCKR_CSS_SHIFT) /* Slow Clock */ -# define PMC_MCKR_CSS_MAIN (1 << PMC_MCKR_CSS_SHIFT) /* Main Clock */ -# define PMC_MCKR_CSS_PLLA (2 << PMC_MCKR_CSS_SHIFT) /* PLLA Clock */ -# define PMC_MCKR_CSS_UPLL (3 << PMC_MCKR_CSS_SHIFT) /* UPLL Clock */ -#define PMC_MCKR_PRES_SHIFT (4) /* Bits 4-6: Processor Clock Prescaler */ -#define PMC_MCKR_PRES_MASK (7 << PMC_MCKR_PRES_SHIFT) -# define PMC_MCKR_PRES_DIV1 (0 << PMC_MCKR_PRES_SHIFT) /* Selected clock */ -# define PMC_MCKR_PRES_DIV2 (1 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 2 */ -# define PMC_MCKR_PRES_DIV4 (2 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 4 */ -# define PMC_MCKR_PRES_DIV8 (3 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 8 */ -# define PMC_MCKR_PRES_DIV16 (4 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 16 */ -# define PMC_MCKR_PRES_DIV32K (5 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 32 */ -# define PMC_MCKR_PRES_DIV64 (6 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 64 */ -# define PMC_MCKR_PRES_DIV3 (7 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 3 */ -#define PMC_MCKR_UPLLDIV (1 << 13) /* Bit 13: UPLL Divider */ - -/* PMC Programmable Clock Register (0,1,2) */ - -#define PMC_PCK_CSS_SHIFT (0) /* Bits 0-2: Master Clock Source Selection */ -#define PMC_PCK_CSS_MASK (7 << PMC_PCK_CSS_MASK) -# define PMC_PCK_CSS_SLOW (0 << PMC_PCK_CSS_MASK) /* Slow Clock */ -# define PMC_PCK_CSS_MAIN (1 << PMC_PCK_CSS_MASK) /* Main Clock */ -# define PMC_PCK_CSS_PLLA (2 << PMC_PCK_CSS_MASK) /* PLLA Clock */ -# define PMC_PCK_CSS_UPLL (3 << PMC_PCK_CSS_MASK) /* UPLL Clock */ -# define PMC_PCK_CSS_MASTER (4 << PMC_PCK_CSS_MASK) /* Master Clock */ -#define PMC_PCK_PRES_SHIFT (4) /* Bits 4-6: Programmable Clock Prescaler */ -#define PMC_PCK_PRES_MASK (7 << PMC_PCK_PRES_SHIFT) -# define PMC_PCK_PRES_DIV1 (0 << PMC_PCK_PRES_SHIFT) /* Selected clock */ -# define PMC_PCK_PRES_DIV2 (1 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 2 */ -# define PMC_PCK_PRES_DIV4 (2 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 4 */ -# define PMC_PCK_PRES_DIV8 (3 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 8 */ -# define PMC_PCK_PRES_DIV16 (4 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 16 */ -# define PMC_PCK_PRES_DIV32K (5 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 32 */ -# define PMC_PCK_PRES_DIV64 (6 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 64 */ - -/* PMC Interrupt Enable Register, PMC Interrupt Disable Register, PMC Status Register, - * and PMC Interrupt Mask Register common bit-field definitions - */ - -#define PMC_INT_MOSCXTS (1 << 0) /* Bit 0: Main Crystal Oscillator Status Interrupt */ -#define PMC_INT_LOCKA (1 << 1) /* Bit 1: PLL A Lock Interrupt */ -#define PMC_INT_MCKRDY (1 << 3) /* Bit 3: Master Clock Ready Interrupt */ -#define PMC_INT_LOCKU (1 << 6) /* Bit 6: UTMI PLL Lock Interrupt */ -#define PMC_SR_OSCSELS (1 << 7) /* Bit 7: Slow Clock Oscillator Selection (SR only) */ -#define PMC_INT_PCKRDY(n) (1 << ((n)+8) -#define PMC_INT_PCKRDY0 (1 << 8) /* Bit 8: Programmable Clock Ready 0 Interrupt */ -#define PMC_INT_PCKRDY1 (1 << 9) /* Bit 9: Programmable Clock Ready 1 Interrupt */ -#define PMC_INT_PCKRDY2 (1 << 10) /* Bit 10: Programmable Clock Ready 2 Interrupt */ -#define PMC_INT_MOSCSELS (1 << 16) /* Bit 16: Main Oscillator Selection Status Interrupt */ -#define PMC_INT_MOSCRCS (1 << 17) /* Bit 17: Main On-Chip RC Status Interrupt */ -#define PMC_INT_CFDEV (1 << 18) /* Bit 18: Clock Failure Detector Event Interrupt */ -#define PMC_SR_CFDS (1 << 19) /* Bit 19: Clock Failure Detector Status (SR only) */ -#define PMC_SR_FOS (1 << 20) /* Bit 20: Clock Failure Detector Fault Output Status (SR only) */ - -/* PMC Fast Startup Mode Register and PMC Fast Startup Polarity Register common bit-field - * definitions - */ - -#define PMC_FSTI(n) (1 << (n)) -#define PMC_FSTI0 (1 << 0) /* Bit 0: Fast Startup Input 0 */ -#define PMC_FSTI1 (1 << 1) /* Bit 1: Fast Startup Input 1 */ -#define PMC_FSTI2 (1 << 2) /* Bit 2: Fast Startup Input 2 */ -#define PMC_FSTI3 (1 << 3) /* Bit 3: Fast Startup Input 3 */ -#define PMC_FSTI4 (1 << 4) /* Bit 4: Fast Startup Input 4 */ -#define PMC_FSTI5 (1 << 5) /* Bit 5: Fast Startup Input 5 */ -#define PMC_FSTI6 (1 << 6) /* Bit 6: Fast Startup Input 6 */ -#define PMC_FSTI7 (1 << 7) /* Bit 7: Fast Startup Input 7 */ -#define PMC_FSTI8 (1 << 8) /* Bit 8: Fast Startup Input 8 */ -#define PMC_FSTI9 (1 << 9) /* Bit 9: Fast Startup Input 9 */ -#define PMC_FSTI10 (1 << 10) /* Bit 10: Fast Startup Input 10 */ -#define PMC_FSTI11 (1 << 11) /* Bit 11: Fast Startup Input 11 */ -#define PMC_FSTI12 (1 << 12) /* Bit 12: Fast Startup Input 12 */ -#define PMC_FSTI13 (1 << 13) /* Bit 13: Fast Startup Input 13 */ -#define PMC_FSTI14 (1 << 14) /* Bit 14: Fast Startup Input 14 */ -#define PMC_FSTI15 (1 << 15) /* Bit 15: Fast Startup Input 15 */ - -#define PMC_FSMR_RTTAL (1 << 16) /* Bit 16: RTT Alarm Enable (MR only) */ -#define PMC_FSMR_RTCAL (1 << 17) /* Bit 17: RTC Alarm Enable (MR only) */ -#define PMC_FSMR_USBAL (1 << 18) /* Bit 18: USB Alarm Enable (MR only) */ -#define PMC_FSMR_LPM (1 << 20) /* Bit 20: Low Power Mode (MR only) */ - -/* PMC Fault Output Clear Register */ - -#define PMC_FOCLR (1 << 0) /* Bit 0: Fault Output Clear */ - -/* PMC Write Protect Mode Register */ - -#define PMC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ -#define PMC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ -#define PMC_WPMR_WPKEY_MASK (0x00ffffff << PMC_WPMR_WPKEY_SHIFT) - -/* PMC Write Protect Status Register */ - -#define PMC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */ -#define PMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ -#define PMC_WPSR_WPVSRC_MASK (0xffff << PMC_WPSR_WPVSRC_SHIFT) - -/**************************************************************************************** - * Public Types - ****************************************************************************************/ - -/**************************************************************************************** - * Public Data - ****************************************************************************************/ - -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_PMC_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_pwm.h b/nuttx/arch/arm/src/sam34/chip/sam_pwm.h index fe3bf04a1..d18ca291c 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_pwm.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_pwm.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam_pwm.h + * Pulse Width Modulation Controller (PWM) definitions for the SAM3U and SAM4S * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -83,6 +84,9 @@ #define SAM_PWM_EL0MR_OFFSET 0x07c /* PWM Event Line 0 Mode Register */ #define SAM_PWM_EL1MR_OFFSET 0x080 /* PWM Event Line 1 Mode Register */ /* 0x084-0x0ac: Reserved */ +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_PWM_SMMR_OFFSET 0x0b0 /* PWM Stepper Motor Mode Register */ +#endif /* 0x0b4-0x0e0: Reserved */ #define SAM_PWM_WPCR_OFFSET 0x0e4 /* PWM Write Protect Control Register */ #define SAM_PWM_WPSR_OFFSET 0x0e8 /* PWM Write Protect Status Register */ @@ -215,6 +219,10 @@ #define SAM_PWM_FPE (SAM_PWM_BASE+SAM_PWM_FPE_OFFSET) #define SAM_PWM_EL0MR (SAM_PWM_BASE+SAM_PWM_EL0MR_OFFSET) #define SAM_PWM_EL1MR (SAM_PWM_BASE+SAM_PWM_EL1MR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_PWM_SMMR_OFFSET 0x0b0 /* PWM Stepper Motor Mode Register */ +# define SAM_PWM_SMMR_OFFSET 0x0b0 /* PWM Stepper Motor Mode Register */ +#endif #define SAM_PWM_WPCR (SAM_PWM_BASE+SAM_PWM_WPCR_OFFSET) #define SAM_PWM_WPSR (SAM_PWM_BASE+SAM_PWM_WPSR_OFFSET) @@ -518,6 +526,12 @@ #define PWM_ELMR_CSEL6 (1 << 6) /* Bit 6: Comparison 6 Selection */ #define PWM_ELMR_CSEL7 (1 << 7) /* Bit 7: Comparison 7 Selection */ +/* PWM Stepper Motor Mode Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# warning SAM4S not yet integrated +#endif + /* PWM Write Protect Control Register */ #define PWM_WPCR_WPCMD_SHIFT (0) /* Bits 0-1: Write Protect Command */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_rstc.h b/nuttx/arch/arm/src/sam34/chip/sam_rstc.h index 3a620d7ef..3b278d45f 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_rstc.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_rstc.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam_rstc.h + * Reset Controller (RSTC) definitions for the SAM3U and SAM4S * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -68,6 +69,7 @@ #define RSTC_CR_EXTRST (1 << 3) /* Bit 3: External Reset */ #define RSTC_CR_KEY_SHIFT (24) /* Bits 24-31: Password */ #define RSTC_CR_KEY_MASK (0xff << RSTC_CR_KEY_SHIFT) +# define RSTC_CR_KEY (0xa5 << RSTC_CR_KEY_SHIFT) #define RSTC_SR_URSTS (1 << 0) /* Bit 0: User Reset Status */ #define RSTC_SR_RSTTYP_SHIFT (8) /* Bits 8-10: Reset Type */ @@ -86,6 +88,7 @@ #define RSTC_MR_ERSTL_MASK (15 << RSTC_MR_ERSTL_SHIFT) #define RSTC_MR_KEY_SHIFT (24) /* Bits 24-31: Password */ #define RSTC_MR_KEY_MASK (0xff << RSTC_CR_KEY_SHIFT) +# define RSTC_MR_KEY (0xa5 << RSTC_CR_KEY_SHIFT) /**************************************************************************************** * Public Types diff --git a/nuttx/arch/arm/src/sam34/chip/sam_rtc.h b/nuttx/arch/arm/src/sam34/chip/sam_rtc.h index 5c0a2e15e..4fe94a459 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_rtc.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_rtc.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam_rtc.h + * Real-time Clock (RTC) definitions for the SAM3U and SAM4S * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -81,6 +82,8 @@ /* RTC register bit definitions *********************************************************/ +/* RTC Control Register */ + #define RTC_CR_UPDTIM (1 << 0) /* Bit 0: Update Request Time Register */ #define RTC_CR_UPDCAL (1 << 1) /* Bit 1: Update Request Calendar Register */ #define RTC_CR_TIMEVSEL_SHIFT (8) /* Bits 8-9: Time Event Selection */ @@ -95,8 +98,56 @@ # define RTC_CR_CALEVSEL_MONTH (1 << RTC_CR_CALEVSEL_SHIFT) # define RTC_CR_CALEVSEL_YEAR (2 << RTC_CR_CALEVSEL_SHIFT) +/* RTC Mode Register */ + #define RTC_MR_HRMOD (1 << 0) /* Bit 0: 12-/24-hour Mode */ +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define RTC_MR_PERSIAN (1 << 1) /* Bit 1: PERSIAN Calendar */ +# define RTC_MR_NEGPPM (1 << 4) /* Bit 4: Negative PPM Correction */ +# define RTC_MR_CORRECTION_SHIFT (8) /* Bits 8-14: Slow Clock Correction */ +# define RTC_MR_CORRECTION_ +# define RTC_MR_HIGHPPM (1 << 15) /* Bit 15: HIGH PPM Correction */ +# define RTC_MR_OUT0_SHIFT (16) /* Bits 16-18: RTCOUT0 Output Source Selection */ +# define RTC_MR_OUT0_MASK (7 << RTC_MR_OUT0_SHIFT) +# define RTC_MR_OUT0_NOWAVE (0 << RTC_MR_OUT0_SHIFT) /* No waveform, stuck at 0 */ +# define RTC_MR_OUT0_FREQ1HZ (1 << RTC_MR_OUT0_SHIFT) /* 1Hz square wave */ +# define RTC_MR_OUT0_FREQ32HZ (2 << RTC_MR_OUT0_SHIFT) /* 32Hz square wave */ +# define RTC_MR_OUT0_FREQ64HZ (3 << RTC_MR_OUT0_SHIFT) /* 64Hz square wave */ +# define RTC_MR_OUT0_FREQ512HZ (4 << RTC_MR_OUT0_SHIFT) /* 512Hz square wave */ +# define RTC_MR_OUT0_ALARM_TOGGLE (5 << RTC_MR_OUT0_SHIFT) /* Output toggles when alarm flag rises */ +# define RTC_MR_OUT0_ALARM_FLAG (6 << RTC_MR_OUT0_SHIFT) /* Output is a copy of the alarm flag */ +# define RTC_MR_OUT0_PROG_PULSE (7 << RTC_MR_OUT0_SHIFT) /* Duty cycle programmable pulse */ +# define RTC_MR_OUT1_SHIFT (20) /* Bits 20-22: RTCOUT1 Output Source Selection */ +# define RTC_MR_OUT1_MASK (7 << RTC_MR_OUT1_SHIFT) +# define RTC_MR_OUT1_NOWAVE (0 << RTC_MR_OUT1_SHIFT) /* No waveform, stuck at 0 */ +# define RTC_MR_OUT1_FREQ1HZ (1 << RTC_MR_OUT1_SHIFT) /* 1Hz square wave */ +# define RTC_MR_OUT1_FREQ32HZ (2 << RTC_MR_OUT1_SHIFT) /* 32Hz square wave */ +# define RTC_MR_OUT1_FREQ64HZ (3 << RTC_MR_OUT1_SHIFT) /* 64Hz square wave */ +# define RTC_MR_OUT1_FREQ512HZ (4 << RTC_MR_OUT1_SHIFT) /* 512Hz square wave */ +# define RTC_MR_OUT1_ALARM_TOGGLE (5 << RTC_MR_OUT1_SHIFT) /* Output toggles when alarm flag rises */ +# define RTC_MR_OUT1_ALARM_FLAG (6 << RTC_MR_OUT1_SHIFT) /* Output is a copy of the alarm flag */ +# define RTC_MR_OUT1_PROG_PULSE (7 << RTC_MR_OUT1_SHIFT) /* Duty cycle programmable pulse */ +# define RTC_MR_THIGH_SHIFT (24) /* Bits 24-26: High Duration of the Output Pulse */ +# define RTC_MR_THIGH_MASK (7 << RTC_MR_THIGH_SHIFT) +# define RTC_MR_THIGH_ 31MS (0 << RTC_MR_THIGH_SHIFT) /* 31.2 ms */ +# define RTC_MR_THIGH_ 16MS (1 << RTC_MR_THIGH_SHIFT) /* 15.6 ms */ +# define RTC_MR_THIGH_ 4MS (2 << RTC_MR_THIGH_SHIFT) /* 3.91 ms */ +# define RTC_MR_THIGH_ 976US (3 << RTC_MR_THIGH_SHIFT) /* 976 µs */ +# define RTC_MR_THIGH_ 488US (4 << RTC_MR_THIGH_SHIFT) /* 488 µs */ +# define RTC_MR_THIGH_ 22US (5 << RTC_MR_THIGH_SHIFT) /* 122 µs */ +# define RTC_MR_THIGH_ 0US (6 << RTC_MR_THIGH_SHIFT) /* 30.5 µs */ +# define RTC_MR_THIGH_ 15US (7 << RTC_MR_THIGH_SHIFT) /* 15.2 µs */ +# define RTC_MR_TPERIOD_SHIFT (28) /* Bits 28-29: Period of the Output Pulse */ +# define RTC_MR_TPERIOD_MASK (3 << RTC_MR_TPERIOD_SHIFT) +# define RTC_MR_TPERIOD_ 1S (0 << RTC_MR_TPERIOD_SHIFT) /* 1 second */ +# define RTC_MR_TPERIOD_ 500MS (1 << RTC_MR_TPERIOD_SHIFT) /* 500 ms */ +# define RTC_MR_TPERIOD_ 250MS (2 << RTC_MR_TPERIOD_SHIFT) /* 250 ms */ +# define RTC_MR_TPERIOD_ 125MS (3 << RTC_MR_TPERIOD_SHIFT) /* 125 ms */ +#endif + +/* RTC Time Register */ + #define RTC_TIMR_SEC_SHIFT (0) /* Bits 0-6: Current Second */ #define RTC_TIMR_SEC_MASK (0x7f << RTC_TIMR_SEC_SHIFT) #define RTC_TIMR_MIN_SHIFT (8) /* Bits 8-14: Current Minute */ @@ -105,6 +156,8 @@ #define RTC_TIMR_HOUR_MASK (0x3f << RTC_TIMR_HOUR_SHIFT) #define RTC_TIMR_AMPM (1 << 22) /* Bit 22: Ante Meridiem Post Meridiem Indicator */ +/* RTC Calendar Register */ + #define RTC_CALR_CENT_SHIFT (0) /* Bits 0-6: Current Century */ #define RTC_CALR_CENT_MASK (0x7f << RTC_TIMR_HOUR_SHIFT) #define RTC_CALR_YEAR_SHIFT (8) /* Bits 8-15: Current Year */ @@ -116,6 +169,8 @@ #define RTC_CALR_DATE_SHIFT (24) /* Bits 24-29: Current Day in Current Month */ #define RTC_CALR_DATE_MASK (0x3f << RTC_CALR_DATE_SHIFT) +/* RTC Time Alarm Register */ + #define RTC_TIMALR_SEC_SHIFT (0) /* Bits 0-6: Second Alarm */ #define RTC_TIMALR_SEC_MASK (0x7f << RTC_TIMALR_SEC_SHIFT) #define RTC_TIMALR_SECEN (1 << 7) /* Bit 7: Second Alarm Enable */ @@ -127,43 +182,73 @@ #define RTC_TIMALR_AMPM (1 << 22) /* Bit 22: AM/PM Indicator */ #define RTC_TIMALR_HOUREN (1 << 23) /* Bit 23: Hour Alarm Enable */ +/* RTC Calendar Alarm Register */ + #define RTC_CALALR_MONTH_SHIFT (16) /* Bits 16-20: Month Alarm */ #define RTC_CALALR_MONTH_MASK (0x1f << RTC_CALALR_MONTH_SHIFT) #define RTC_CALALR_MTHEN (1 << 23) /* Bit 23: Month Alarm Enable */ #define RTC_CALALR_DATE_SHIFT (24) /* Bits 24-29: Date Alarm */ -#define RTC_CALALR_DATE_MASK (0x3c << RTC_CALALR_DATE_SHIFT) +#define RTC_CALALR_DATE_MASK (0x3f << RTC_CALALR_DATE_SHIFT) #define RTC_CALALR_DATEEN (1 << 31) /* Bit 31: Date Alarm Enable */ +/* RTC Status Register */ + #define RTC_SR_ACKUPD (1 << 0) /* Bit 0: Acknowledge for Update */ #define RTC_SR_ALARM (1 << 1) /* Bit 1: Alarm Flag */ #define RTC_SR_SEC (1 << 2) /* Bit 2: Second Event */ #define RTC_SR_TIMEV (1 << 3) /* Bit 3: Time Event */ #define RTC_SR_CALEV (1 << 4) /* Bit 4: Calendar Event */ +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define RTC_SR_TDERR (1 << 5) /* Bit 5: Time and/or Date Free Running Error */ +#endif + +/* RTC Status Clear Command Register */ + #define RTC_SCCR_ACKCLR (1 << 0) /* Bit 0: Acknowledge Clear */ #define RTC_SCCR_ALRCLR (1 << 1) /* Bit 1: Alarm Clear */ #define RTC_SCCR_SECCLR (1 << 2) /* Bit 2: Second Clear */ #define RTC_SCCR_TIMCLR (1 << 3) /* Bit 3: Time Clear */ #define RTC_SCCR_CALCLR (1 << 4) /* Bit 4: Calendar Clear */ +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define RTC_SR_TDERRCLR (1 << 5) /* Bit 5: Time and/or Date Free Running Error Clear */ +#endif + +/* RTC Interrupt Enable Register */ + #define RTC_IER_ACKEN (1 << 0) /* Bit 0: Acknowledge Update Interrupt Enable */ #define RTC_IER_ALREN (1 << 1) /* Bit 1: Alarm Interrupt Enable */ #define RTC_IER_SECEN (1 << 2) /* Bit 2: Second Event Interrupt Enable */ #define RTC_IER_TIMEN (1 << 3) /* Bit 3: Time Event Interrupt Enable */ #define RTC_IER_CALEN (1 << 4) /* Bit 4: Calendar Event Interrupt Enable */ +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define RTC_SR_TDERREN (1 << 5) /* Bit 5: Time and/or Date Error Interrupt Enable */ +#endif + +/* RTC Interrupt Disable Register */ + #define RTC_IDR_ACKDIS (1 << 0) /* Bit 0: Acknowledge Update Interrupt Disable */ #define RTC_IDR_ALRDIS (1 << 1) /* Bit 1: Alarm Interrupt Disable */ #define RTC_IDR_SECDIS (1 << 2) /* Bit 2: Second Event Interrupt Disable */ #define RTC_IDR_TIMDIS (1 << 3) /* Bit 3: Time Event Interrupt Disable */ #define RTC_IDR_CALDIS (1 << 4) /* Bit 4: Calendar Event Interrupt Disable */ +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define RTC_SR_TDERRDIS (1 << 5) /* Bit 5: Time and/or Date Error Interrupt Disable */ +#endif + +/* RTC Interrupt Mask Register */ + #define RTC_IMR_ACK (1 << 0) /* Bit 0: Acknowledge Update Interrupt Mask */ #define RTC_IMR_ALR (1 << 1) /* Bit 1: Alarm Interrupt Mask */ #define RTC_IMR_SEC (1 << 2) /* Bit 2: Second Event Interrupt Mask */ #define RTC_IMR_TIM (1 << 3) /* Bit 3: Time Event Interrupt Mask */ #define RTC_IMR_CAL (1 << 4) /* Bit 4: Calendar Event Interrupt Mask */ +/* RTC Valid Entry Register */ + #define RTC_VER_NVTIM (1 << 0) /* Bit 0: Non-valid Time */ #define RTC_VER_NVCAL (1 << 1) /* Bit 1: Non-valid Calendar */ #define RTC_VER_NVTIMALR (1 << 2) /* Bit 2: Non-valid Time Alarm */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_rtt.h b/nuttx/arch/arm/src/sam34/chip/sam_rtt.h index 75b0d361e..bd34ca814 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_rtt.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_rtt.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam_rtt.h + * Real-time Timer (RTT) definitions for the SAM3U and SAM4S * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -65,12 +66,24 @@ /* RTT register bit definitions ********************************************************/ +/* Real-time Timer Mode Register */ + #define RTT_MR_RTPRES_SHIFT (0) /* Bits 0-15: Real-time Timer Prescaler Value */ #define RTT_MR_RTPRES__MASK (0xffff << RTT_MR_RTPRES_SHIFT) #define RTT_MR_ALMIEN (1 << 16) /* Bit 16: Alarm Interrupt Enable */ #define RTT_MR_RTTINCIEN (1 << 17) /* Bit 17: Real-time Timer Increment Int Enable */ #define RTT_MR_RTTRST (1 << 18) /* Bit 18: Real-time Timer Restart */ +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define RTT_MR_RTTDIS (1 << 20) /* Bit 20: Real-time Timer Disable */ +# define RTT_MR_RTC1HZ (1 << 24) /* Bit 24: Real-Time Clock 1Hz Clock Selection */ +#endif + +/* Real-time Timer Alarm Register (32-bit alarm value) */ +/* Real-time Timer Value Register (32-bit timer value) */ + +/* Real-time Timer Status Register */ + #define RTT_SR_ALMS (1 << 0) /* Bit 0: Real-time Alarm Status */ #define RTT_SR_RTTINC (1 << 1) /* Bit 1: Real-time Timer Increment */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_smc.h b/nuttx/arch/arm/src/sam34/chip/sam_smc.h index ba67d6608..e729c1519 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_smc.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_smc.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam_smc.h + * Static Memory Controller (SMC) definitions for the SAM3U and SAM4S * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -51,369 +52,437 @@ /* SMC register offsets *****************************************************************/ -#define SAM_SMC_CFG_OFFSET 0x000 /* SMC NFC Configuration Register */ -#define SAM_SMC_CTRL_OFFSET 0x004 /* SMC NFC Control Register */ -#define SAM_SMC_SR_OFFSET 0x008 /* SMC NFC Status Register */ -#define SAM_SMC_IER_OFFSET 0x00c /* SMC NFC Interrupt Enable Register */ -#define SAM_SMC_IDR_OFFSET 0x010 /* SMC NFC Interrupt Disable Register */ -#define SAM_SMC_IMR_OFFSET 0x014 /* SMC NFC Interrupt Mask Register */ -#define SAM_SMC_ADDR_OFFSET 0x018 /* SMC NFC Address Cycle Zero Register */ -#define SAM_SMC_BANK_OFFSET 0x01c /* SMC Bank Address Register */ -#define SAM_SMC_ECCCTRL_OFFSET 0x020 /* SMC ECC Control Register */ -#define SAM_SMC_ECCMD_OFFSET 0x024 /* SMC ECC Mode Register */ -#define SAM_SMC_ECCSR1_OFFSET 0x028 /* SMC ECC Status 1 Register */ -#define SAM_SMC_ECCPR0_OFFSET 0x02c /* SMC ECC parity 0 Register */ -#define SAM_SMC_ECCPR1_OFFSET 0x030 /* SMC ECC parity 1 Register */ -#define SAM_SMC_ECCSR2_OFFSET 0x034 /* SMC ECC status 2 Register */ -#define SAM_SMC_ECCPR2_OFFSET 0x038 /* SMC ECC parity 2 Register */ -#define SAM_SMC_ECCPR3_OFFSET 0x03c /* SMC ECC parity 3 Register */ -#define SAM_SMC_ECCPR4_OFFSET 0x040 /* SMC ECC parity 4 Register */ -#define SAM_SMC_ECCPR5_OFFSET 0x044 /* SMC ECC parity 5 Register */ -#define SAM_SMC_ECCPR6_OFFSET 0x048 /* SMC ECC parity 6 Register */ -#define SAM_SMC_ECCPR7_OFFSET 0x04c /* SMC ECC parity 7 Register */ -#define SAM_SMC_ECCPR8_OFFSET 0x050 /* SMC ECC parity 8 Register */ -#define SAM_SMC_ECCPR9_OFFSET 0x054 /* SMC ECC parity 9 Register */ -#define SAM_SMC_ECCPR10_OFFSET 0x058 /* SMC ECC parity 10 Register */ -#define SAM_SMC_ECCPR11_OFFSET 0x05c /* SMC ECC parity 11 Register */ -#define SAM_SMC_ECCPR12_OFFSET 0x060 /* SMC ECC parity 12 Register */ -#define SAM_SMC_ECCPR13_OFFSET 0x064 /* SMC ECC parity 13 Register */ -#define SAM_SMC_ECCPR14_OFFSET 0x068 /* SMC ECC parity 14 Register */ -#define SAM_SMC_ECCPR15_OFFSET 0x06c /* SMC ECC parity 15 Register */ - -#define SAM_SMCCS_OFFSET(n) (0x070+((n)*0x014)) -#define SAM_SMCCS_SETUP_OFFSET 0x000 /* SMC SETUP Register */ -#define SAM_SMCCS_PULSE_OFFSET 0x004 /* SMC PULSE Register */ -#define SAM_SMCCS_CYCLE_OFFSET 0x008 /* SMC CYCLE Register */ -#define SAM_SMCCS_TIMINGS_OFFSET 0x00c /* SMC TIMINGS Register */ -#define SAM_SMCCS_MODE_OFFSET 0x010 /* SMC MODE Register */ - -#define SAM_SMC_OCMS_OFFSET 0x110 /* SMC OCMS MODE Register */ -#define SAM_SMC_KEY1_OFFSET 0x114 /* SMC KEY1 Register */ -#define SAM_SMC_KEY2_OFFSET 0x118 /* SMC KEY2 Register */ -#define SAM_SMC_WPCR_OFFSET 0x1e4 /* Write Protection Control Register */ -#define SAM_SMC_WPSR_OFFSET 0x1e8 /* Write Protection Status Register */ +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_SMC_CFG_OFFSET 0x0000 /* SMC NFC Configuration Register */ +# define SAM_SMC_CTRL_OFFSET 0x0004 /* SMC NFC Control Register */ +# define SAM_SMC_SR_OFFSET 0x0008 /* SMC NFC Status Register */ +# define SAM_SMC_IER_OFFSET 0x000c /* SMC NFC Interrupt Enable Register */ +# define SAM_SMC_IDR_OFFSET 0x0010 /* SMC NFC Interrupt Disable Register */ +# define SAM_SMC_IMR_OFFSET 0x0014 /* SMC NFC Interrupt Mask Register */ +# define SAM_SMC_ADDR_OFFSET 0x0018 /* SMC NFC Address Cycle Zero Register */ +# define SAM_SMC_BANK_OFFSET 0x001c /* SMC Bank Address Register */ +# define SAM_SMC_ECCCTRL_OFFSET 0x0020 /* SMC ECC Control Register */ +# define SAM_SMC_ECCMD_OFFSET 0x0024 /* SMC ECC Mode Register */ +# define SAM_SMC_ECCSR1_OFFSET 0x0028 /* SMC ECC Status 1 Register */ +# define SAM_SMC_ECCPR0_OFFSET 0x002c /* SMC ECC parity 0 Register */ +# define SAM_SMC_ECCPR1_OFFSET 0x0030 /* SMC ECC parity 1 Register */ +# define SAM_SMC_ECCSR2_OFFSET 0x0034 /* SMC ECC status 2 Register */ +# define SAM_SMC_ECCPR2_OFFSET 0x0038 /* SMC ECC parity 2 Register */ +# define SAM_SMC_ECCPR3_OFFSET 0x003c /* SMC ECC parity 3 Register */ +# define SAM_SMC_ECCPR4_OFFSET 0x0040 /* SMC ECC parity 4 Register */ +# define SAM_SMC_ECCPR5_OFFSET 0x0044 /* SMC ECC parity 5 Register */ +# define SAM_SMC_ECCPR6_OFFSET 0x0048 /* SMC ECC parity 6 Register */ +# define SAM_SMC_ECCPR7_OFFSET 0x004c /* SMC ECC parity 7 Register */ +# define SAM_SMC_ECCPR8_OFFSET 0x0050 /* SMC ECC parity 8 Register */ +# define SAM_SMC_ECCPR9_OFFSET 0x0054 /* SMC ECC parity 9 Register */ +# define SAM_SMC_ECCPR10_OFFSET 0x0058 /* SMC ECC parity 10 Register */ +# define SAM_SMC_ECCPR11_OFFSET 0x005c /* SMC ECC parity 11 Register */ +# define SAM_SMC_ECCPR12_OFFSET 0x0060 /* SMC ECC parity 12 Register */ +# define SAM_SMC_ECCPR13_OFFSET 0x0064 /* SMC ECC parity 13 Register */ +# define SAM_SMC_ECCPR14_OFFSET 0x0068 /* SMC ECC parity 14 Register */ +# define SAM_SMC_ECCPR15_OFFSET 0x006c /* SMC ECC parity 15 Register */ + +# define SAM_SMCCS_OFFSET(n) (0x0070+((n)*0x014)) +# define SAM_SMCCS_SETUP_OFFSET 0x0000 /* SMC Setup register */ +# define SAM_SMCCS_PULSE_OFFSET 0x0004 /* SMC Pulse Register */ +# define SAM_SMCCS_CYCLE_OFFSET 0x0008 /* SMC Cycle Register */ +# define SAM_SMCCS_TIMINGS_OFFSET 0x000c /* SMC Timings Register */ +# define SAM_SMCCS_MODE_OFFSET 0x0010 /* SMC Mode Register */ + +# define SAM_SMC_OCMS_OFFSET 0x0110 /* SMC OCMS Mode Register */ +# define SAM_SMC_KEY1_OFFSET 0x0114 /* SMC KEY1 Register */ +# define SAM_SMC_KEY2_OFFSET 0x0118 /* SMC KEY2 Register */ +# define SAM_SMC_WPCR_OFFSET 0x01e4 /* Write Protection Control Register */ +# define SAM_SMC_WPSR_OFFSET 0x01e8 /* Write Protection Status Register */ + +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_SMCCS_OFFSET(n) ((n) << 4) +# define SAM_SMCCS_SETUP_OFFSET 0x0000 /* SMC Setup Register */ +# define SAM_SMCCS_PULSE_OFFSET 0x0004 /* SMC Pulse Register */ +# define SAM_SMCCS_CYCLE_OFFSET 0x0008 /* SMC Cycle Register */ +# define SAM_SMCCS_MODE_OFFSET 0x000c /* SMC Mode Register */ + +# define SAM_SMC_OCMS_OFFSET 0x0080 /* SMC OCMS Mode Register */ +# define SAM_SMC_KEY1_OFFSET 0x0084 /* SMC KEY1 Register */ +# define SAM_SMC_KEY2_OFFSET 0x0088 /* SMC KEY2 Register */ +# define SAM_SMC_WPCR_OFFSET 0x00e4 /* Write Protection Control Register */ +# define SAM_SMC_WPSR_OFFSET 0x00e8 /* Write Protection Status Register */ + +#else +# error Unrecognized SAM architecture +#endif /* SMC register adresses ****************************************************************/ -#define SAM_SMC_CFG (SAM_SMC_BASE+SAM_SMC_CFG_OFFSET) -#define SAM_SMC_CTRL (SAM_SMC_BASE+SAM_SMC_CTRL_OFFSET) -#define SAM_SMC_SR (SAM_SMC_BASE+SAM_SMC_SR_OFFSET) -#define SAM_SMC_IER (SAM_SMC_BASE+SAM_SMC_IER_OFFSET) -#define SAM_SMC_IDR (SAM_SMC_BASE+SAM_SMC_IDR_OFFSET) -#define SAM_SMC_IMR (SAM_SMC_BASE+SAM_SMC_IMR_OFFSET) -#define SAM_SMC_ADDR (SAM_SMC_BASE+SAM_SMC_ADDR_OFFSET) -#define SAM_SMC_BANK (SAM_SMC_BASE+SAM_SMC_BANK_OFFSET) -#define SAM_SMC_ECCCTRL (SAM_SMC_BASE+SAM_SMC_ECCCTRL_OFFSET) -#define SAM_SMC_ECCMD (SAM_SMC_BASE+SAM_SMC_ECCMD_OFFSET) -#define SAM_SMC_ECCSR1 (SAM_SMC_BASE+SAM_SMC_ECCSR1_OFFSET) -#define SAM_SMC_ECCPR0 (SAM_SMC_BASE+SAM_SMC_ECCPR0_OFFSET) -#define SAM_SMC_ECCPR1 (SAM_SMC_BASE+SAM_SMC_ECCPR1_OFFSET) -#define SAM_SMC_ECCSR2 (SAM_SMC_BASE+SAM_SMC_ECCSR2_OFFSET) -#define SAM_SMC_ECCPR2 (SAM_SMC_BASE+SAM_SMC_ECCPR2_OFFSET) -#define SAM_SMC_ECCPR3 (SAM_SMC_BASE+SAM_SMC_ECCPR3_OFFSET) -#define SAM_SMC_ECCPR4 (SAM_SMC_BASE+SAM_SMC_ECCPR4_OFFSET) -#define SAM_SMC_ECCPR5 (SAM_SMC_BASE+SAM_SMC_ECCPR5_OFFSET) -#define SAM_SMC_ECCPR6 (SAM_SMC_BASE+SAM_SMC_ECCPR6_OFFSET) -#define SAM_SMC_ECCPR7 (SAM_SMC_BASE+SAM_SMC_ECCPR7_OFFSET) -#define SAM_SMC_ECCPR8 (SAM_SMC_BASE+SAM_SMC_ECCPR8_OFFSET) -#define SAM_SMC_ECCPR9 (SAM_SMC_BASE+SAM_SMC_ECCPR9_OFFSET) -#define SAM_SMC_ECCPR10 (SAM_SMC_BASE+SAM_SMC_ECCPR10_OFFSET) -#define SAM_SMC_ECCPR11 (SAM_SMC_BASE+SAM_SMC_ECCPR11_OFFSET) -#define SAM_SMC_ECCPR12 (SAM_SMC_BASE+SAM_SMC_ECCPR12_OFFSET) -#define SAM_SMC_ECCPR13 (SAM_SMC_BASE+SAM_SMC_ECCPR13_OFFSET) -#define SAM_SMC_ECCPR14 (SAM_SMC_BASE+SAM_SMC_ECCPR14_OFFSET) -#define SAM_SMC_ECCPR15 (SAM_SMC_BASE+SAM_SMC_ECCPR15_OFFSET) - -#define SAM_SMCCS_BASE(n) (SAM_SMC_BASE+SAM_SMCCS_OFFSET(n)) -# define SAM_SMC_CS0_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(0)) -# define SAM_SMC_CS1_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(1)) -# define SAM_SMC_CS2_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(2)) -# define SAM_SMC_CS3_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(3)) -#define SAM_SMCCS_SETUP(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_SETUP_OFFSET) -#define SAM_SMCCS_PULSE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_PULSE_OFFSET) -#define SAM_SMCCS_CYCLE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_CYCLE_OFFSET) -#define SAM_SMCCS_TIMINGS(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_TIMINGS_OFFSET) -#define SAM_SMCCS_MODE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_MODE_OFFSET) - -#define SAM_SMC_OCMS (SAM_SMC_BASE+SAM_SMC_OCMS_OFFSET) -#define SAM_SMC_KEY1 (SAM_SMC_BASE+SAM_SMC_KEY1_OFFSET) -#define SAM_SMC_KEY2 (SAM_SMC_BASE+SAM_SMC_KEY2_OFFSET) -#define SAM_SMC_WPCR (SAM_SMC_BASE+SAM_SMC_WPCR_OFFSET) -#define SAM_SMC_WPSR (SAM_SMC_BASE+SAM_SMC_WPSR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_SMC_CFG (SAM_SMC_BASE+SAM_SMC_CFG_OFFSET) +# define SAM_SMC_CTRL (SAM_SMC_BASE+SAM_SMC_CTRL_OFFSET) +# define SAM_SMC_SR (SAM_SMC_BASE+SAM_SMC_SR_OFFSET) +# define SAM_SMC_IER (SAM_SMC_BASE+SAM_SMC_IER_OFFSET) +# define SAM_SMC_IDR (SAM_SMC_BASE+SAM_SMC_IDR_OFFSET) +# define SAM_SMC_IMR (SAM_SMC_BASE+SAM_SMC_IMR_OFFSET) +# define SAM_SMC_ADDR (SAM_SMC_BASE+SAM_SMC_ADDR_OFFSET) +# define SAM_SMC_BANK (SAM_SMC_BASE+SAM_SMC_BANK_OFFSET) +# define SAM_SMC_ECCCTRL (SAM_SMC_BASE+SAM_SMC_ECCCTRL_OFFSET) +# define SAM_SMC_ECCMD (SAM_SMC_BASE+SAM_SMC_ECCMD_OFFSET) +# define SAM_SMC_ECCSR1 (SAM_SMC_BASE+SAM_SMC_ECCSR1_OFFSET) +# define SAM_SMC_ECCPR0 (SAM_SMC_BASE+SAM_SMC_ECCPR0_OFFSET) +# define SAM_SMC_ECCPR1 (SAM_SMC_BASE+SAM_SMC_ECCPR1_OFFSET) +# define SAM_SMC_ECCSR2 (SAM_SMC_BASE+SAM_SMC_ECCSR2_OFFSET) +# define SAM_SMC_ECCPR2 (SAM_SMC_BASE+SAM_SMC_ECCPR2_OFFSET) +# define SAM_SMC_ECCPR3 (SAM_SMC_BASE+SAM_SMC_ECCPR3_OFFSET) +# define SAM_SMC_ECCPR4 (SAM_SMC_BASE+SAM_SMC_ECCPR4_OFFSET) +# define SAM_SMC_ECCPR5 (SAM_SMC_BASE+SAM_SMC_ECCPR5_OFFSET) +# define SAM_SMC_ECCPR6 (SAM_SMC_BASE+SAM_SMC_ECCPR6_OFFSET) +# define SAM_SMC_ECCPR7 (SAM_SMC_BASE+SAM_SMC_ECCPR7_OFFSET) +# define SAM_SMC_ECCPR8 (SAM_SMC_BASE+SAM_SMC_ECCPR8_OFFSET) +# define SAM_SMC_ECCPR9 (SAM_SMC_BASE+SAM_SMC_ECCPR9_OFFSET) +# define SAM_SMC_ECCPR10 (SAM_SMC_BASE+SAM_SMC_ECCPR10_OFFSET) +# define SAM_SMC_ECCPR11 (SAM_SMC_BASE+SAM_SMC_ECCPR11_OFFSET) +# define SAM_SMC_ECCPR12 (SAM_SMC_BASE+SAM_SMC_ECCPR12_OFFSET) +# define SAM_SMC_ECCPR13 (SAM_SMC_BASE+SAM_SMC_ECCPR13_OFFSET) +# define SAM_SMC_ECCPR14 (SAM_SMC_BASE+SAM_SMC_ECCPR14_OFFSET) +# define SAM_SMC_ECCPR15 (SAM_SMC_BASE+SAM_SMC_ECCPR15_OFFSET) +#endif + +#define SAM_SMCCS_BASE(n) (SAM_SMC_BASE+SAM_SMCCS_OFFSET(n)) +# define SAM_SMC_CS0_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(0)) +# define SAM_SMC_CS1_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(1)) +# define SAM_SMC_CS2_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(2)) +# define SAM_SMC_CS3_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(3)) +#define SAM_SMCCS_SETUP(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_SETUP_OFFSET) +#define SAM_SMCCS_PULSE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_PULSE_OFFSET) +#define SAM_SMCCS_CYCLE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_CYCLE_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_SMCCS_TIMINGS(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_TIMINGS_OFFSET) +#endif +#define SAM_SMCCS_MODE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_MODE_OFFSET) + +#define SAM_SMC_OCMS (SAM_SMC_BASE+SAM_SMC_OCMS_OFFSET) +#define SAM_SMC_KEY1 (SAM_SMC_BASE+SAM_SMC_KEY1_OFFSET) +#define SAM_SMC_KEY2 (SAM_SMC_BASE+SAM_SMC_KEY2_OFFSET) +#define SAM_SMC_WPCR (SAM_SMC_BASE+SAM_SMC_WPCR_OFFSET) +#define SAM_SMC_WPSR (SAM_SMC_BASE+SAM_SMC_WPSR_OFFSET) /* SMC register bit definitions *********************************************************/ /* SMC NFC Configuration Register */ -#define SMC_CFG_PAGESIZE_SHIFT (0) /* Bits 0-1: Page size of NAND Flash device */ -#define SMC_CFG_PAGESIZE_MASK (3 << SMC_CFG_PAGESIZE_SHIFT) -# define SMC_CFG_PAGESIZE_16 BYTES (0 << SMC_CFG_PAGESIZE_SHIFT) /* 528 Bytes 16 byte */ -# define SMC_CFG_PAGESIZE_ 2 BYTES (1 << SMC_CFG_PAGESIZE_SHIFT) /* 1056 Bytes 32 bytes */ -# define SMC_CFG_PAGESIZE_64 BYTES (2 << SMC_CFG_PAGESIZE_SHIFT) /* 2112 Bytes 64 bytes */ -# define SMC_CFG_PAGESIZE_128 BYTES (3 << SMC_CFG_PAGESIZE_SHIFT) /* 4224 Bytes 128 bytes */ -#define SMC_CFG_WSPARE (1 << 8) /* Bit 8: Write Spare Area */ -#define SMC_CFG_RSPARE (1 << 9) /* Bit 9: Read Spare Area */ -#define SMC_CFG_EDGECTRL (1 << 12) /* Bit 12: Rising/Falling Edge Detection Control */ -#define SMC_CFG_RBEDGE (1 << 13) /* Bit 13: Ready/Busy Signal Edge Detection */ -#define SMC_CFG_DTOCYC_SHIFT (16) /* Bits 16-19: Data Timeout Cycle Number */ -#define SMC_CFG_DTOCYC_MASK (15 << SMC_CFG_DTOCYC_SHIFT) -#define SMC_CFG_DTOMUL_SHIFT (20) /* Bits 20-22: Data Timeout Multiplier */ -#define SMC_CFG_DTOMUL_MASK (7 << SMC_CFG_DTOMUL_SHIFT) -# define SMC_CFG_DTOMUL_1 (0 << SMC_CFG_DTOMUL_SHIFT) -# define SMC_CFG_DTOMUL_16 (1 << SMC_CFG_DTOMUL_SHIFT) -# define SMC_CFG_DTOMUL_128 (2 << SMC_CFG_DTOMUL_SHIFT) -# define SMC_CFG_DTOMUL_256 (3 << SMC_CFG_DTOMUL_SHIFT) -# define SMC_CFG_DTOMUL_1024 (4 << SMC_CFG_DTOMUL_SHIFT) -# define SMC_CFG_DTOMUL_4096 (5 << SMC_CFG_DTOMUL_SHIFT) -# define SMC_CFG_DTOMUL_65536 (6 << SMC_CFG_DTOMUL_SHIFT) -# define SMC_CFG_DTOMUL_1048576 (7 << SMC_CFG_DTOMUL_SHIFT) +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SMC_CFG_PAGESIZE_SHIFT (0) /* Bits 0-1: Page size of NAND Flash device */ +# define SMC_CFG_PAGESIZE_MASK (3 << SMC_CFG_PAGESIZE_SHIFT) +# define SMC_CFG_PAGESIZE_16 BYTES (0 << SMC_CFG_PAGESIZE_SHIFT) /* 528 Bytes 16 byte */ +# define SMC_CFG_PAGESIZE_ 2 BYTES (1 << SMC_CFG_PAGESIZE_SHIFT) /* 1056 Bytes 32 bytes */ +# define SMC_CFG_PAGESIZE_64 BYTES (2 << SMC_CFG_PAGESIZE_SHIFT) /* 2112 Bytes 64 bytes */ +# define SMC_CFG_PAGESIZE_128 BYTES (3 << SMC_CFG_PAGESIZE_SHIFT) /* 4224 Bytes 128 bytes */ +# define SMC_CFG_WSPARE (1 << 8) /* Bit 8: Write Spare Area */ +# define SMC_CFG_RSPARE (1 << 9) /* Bit 9: Read Spare Area */ +# define SMC_CFG_EDGECTRL (1 << 12) /* Bit 12: Rising/Falling Edge Detection Control */ +# define SMC_CFG_RBEDGE (1 << 13) /* Bit 13: Ready/Busy Signal Edge Detection */ +# define SMC_CFG_DTOCYC_SHIFT (16) /* Bits 16-19: Data Timeout Cycle Number */ +# define SMC_CFG_DTOCYC_MASK (15 << SMC_CFG_DTOCYC_SHIFT) +# define SMC_CFG_DTOMUL_SHIFT (20) /* Bits 20-22: Data Timeout Multiplier */ +# define SMC_CFG_DTOMUL_MASK (7 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_1 (0 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_16 (1 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_128 (2 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_256 (3 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_1024 (4 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_4096 (5 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_65536 (6 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_1048576 (7 << SMC_CFG_DTOMUL_SHIFT) +#endif /* SMC NFC Control Register */ -#define SMC_CTRL_NFCEN (1 << 0) /* Bit 0: NAND Flash Controller Enable */ -#define SMC_CTRL_NFCDIS (1 << 1) /* Bit 1: NAND Flash Controller Disable */ +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SMC_CTRL_NFCEN (1 << 0) /* Bit 0: NAND Flash Controller Enable */ +# define SMC_CTRL_NFCDIS (1 << 1) /* Bit 1: NAND Flash Controller Disable */ +#endif /* SMC NFC Status Register, SMC NFC Interrupt Enable Register, SMC NFC Interrupt * Disable Register, and SMC NFC Interrupt Mask Register common bit-field definitions */ -#define SMC_SR_SMCSTS (1 << 0) /* Bit 0: NAND Flash Controller status (SR only) */ -#define SMC_INT_RBRISE (1 << 4) /* Bit 4: Ready Busy Rising Edge Detection Interrupt */ -#define SMC_INT_RBFALL (1 << 5) /* Bit 5: Ready Busy Falling Edge Detection Interrupt */ -#define SMC_SR_NFCBUSY (1 << 8) /* Bit 8: NFC Busy (SR only) */ -#define SMC_SR_NFCWR (1 << 11) /* Bit 11: NFC Write/Read Operation (SR only) */ -#define SMC_SR_NFCSID (1 << 12) /* Bit 13: NFC Chip Select ID (SR only) */ -#define SMC_INT_XFRDONE (1 << 16) /* Bit 16: Transfer Done Interrupt */ -#define SMC_INT_CMDDONE (1 << 17) /* Bit 17: Command Done Interrupt */ -#define SMC_INT_DTOE (1 << 20) /* Bit 20: Data Timeout Error Interrupt */ -#define SMC_INT_UNDEF (1 << 21) /* Bit 21: Undefined Area Access Interrupt */ -#define SMC_INT_AWB (1 << 22) /* Bit 22: Accessing While Busy Interrupt */ -#define SMC_INT_NFCASE (1 << 23) /* Bit 23: NFC Access Size Error Interrupt */ -#define SMC_INT_RBEDGE(n) (1<<((n)+24)) -#define SMC_INT_RB_EDGE0 (1 << 24) /* Bit 24: Ready/Busy Line 0 Interrupt */ -#define SMC_INT_RB_EDGE1 (1 << 25) /* Bit 25: Ready/Busy Line 1 Interrupt */ -#define SMC_INT_RB_EDGE2 (1 << 26) /* Bit 26: Ready/Busy Line 2 Interrupt */ -#define SMC_INT_RB_EDGE3 (1 << 27) /* Bit 27: Ready/Busy Line 3 Interrupt */ -#define SMC_INT_RB_EDGE4 (1 << 28) /* Bit 28: Ready/Busy Line 4 Interrupt */ -#define SMC_INT_RB_EDGE5 (1 << 29) /* Bit 29: Ready/Busy Line 5 Interrupt */ -#define SMC_INT_RB_EDGE6 (1 << 30) /* Bit 30: Ready/Busy Line 6 Interrupt */ -#define SMC_INT_RB_EDGE7 (1 << 31) /* Bit 31: Ready/Busy Line 7 Interrupt */ +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SMC_SR_SMCSTS (1 << 0) /* Bit 0: NAND Flash Controller status (SR only) */ +# define SMC_INT_RBRISE (1 << 4) /* Bit 4: Ready Busy Rising Edge Detection Interrupt */ +# define SMC_INT_RBFALL (1 << 5) /* Bit 5: Ready Busy Falling Edge Detection Interrupt */ +# define SMC_SR_NFCBUSY (1 << 8) /* Bit 8: NFC Busy (SR only) */ +# define SMC_SR_NFCWR (1 << 11) /* Bit 11: NFC Write/Read Operation (SR only) */ +# define SMC_SR_NFCSID (1 << 12) /* Bit 13: NFC Chip Select ID (SR only) */ +# define SMC_INT_XFRDONE (1 << 16) /* Bit 16: Transfer Done Interrupt */ +# define SMC_INT_CMDDONE (1 << 17) /* Bit 17: Command Done Interrupt */ +# define SMC_INT_DTOE (1 << 20) /* Bit 20: Data Timeout Error Interrupt */ +# define SMC_INT_UNDEF (1 << 21) /* Bit 21: Undefined Area Access Interrupt */ +# define SMC_INT_AWB (1 << 22) /* Bit 22: Accessing While Busy Interrupt */ +# define SMC_INT_NFCASE (1 << 23) /* Bit 23: NFC Access Size Error Interrupt */ +# define SMC_INT_RBEDGE(n) (1<<((n)+24)) +# define SMC_INT_RB_EDGE0 (1 << 24) /* Bit 24: Ready/Busy Line 0 Interrupt */ +# define SMC_INT_RB_EDGE1 (1 << 25) /* Bit 25: Ready/Busy Line 1 Interrupt */ +# define SMC_INT_RB_EDGE2 (1 << 26) /* Bit 26: Ready/Busy Line 2 Interrupt */ +# define SMC_INT_RB_EDGE3 (1 << 27) /* Bit 27: Ready/Busy Line 3 Interrupt */ +# define SMC_INT_RB_EDGE4 (1 << 28) /* Bit 28: Ready/Busy Line 4 Interrupt */ +# define SMC_INT_RB_EDGE5 (1 << 29) /* Bit 29: Ready/Busy Line 5 Interrupt */ +# define SMC_INT_RB_EDGE6 (1 << 30) /* Bit 30: Ready/Busy Line 6 Interrupt */ +# define SMC_INT_RB_EDGE7 (1 << 31) /* Bit 31: Ready/Busy Line 7 Interrupt */ +#endif /* SMC NFC Address Cycle Zero Register */ -#define SMC_ADDR_ADDR_CYCLE0_SHIFT (3) /* Bits 0-7: NAND Flash Array Address cycle 0 */ -#define SMC_ADDR_ADDR_CYCLE0_SHIFT (3) /* Bits 0-7: NAND Flash Array Address cycle 0 */ +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SMC_ADDR_CYCLE0_SHIFT (3) /* Bits 0-7: NAND Flash Array Address cycle 0 */ +# define SMC_ADDR_CYCLE0_MASK (0xff << SMC_ADDR_CYCLE0_SHIFT) +#endif /* SMC NFC Bank Register */ -#define SMC_BANK_SHIFT (0) /* Bits 0-2: Bank identifier */ -#define SMC_BANK_MASK (7 << SMC_BANK_SHIFT) +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SMC_BANK_SHIFT (0) /* Bits 0-2: Bank identifier */ +# define SMC_BANK_MASK (7 << SMC_BANK_SHIFT) +#endif /* SMC ECC Control Register */ -#define SMC_ECCCTRL_RST (1 << 0) /* Bit 0: Reset ECC */ -#define SMC_ECCCTRL_SWRST (1 << 1) /* Bit 1: Software Reset */ +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SMC_ECCCTRL_RST (1 << 0) /* Bit 0: Reset ECC */ +# define SMC_ECCCTRL_SWRST (1 << 1) /* Bit 1: Software Reset */ +#endif /* SMC ECC MODE Register */ -#define SMC_ECCMD_ECC_PAGESIZE_SHIFT (0) /* Bits 0-1 */ -#define SMC_ECCMD_ECC_PAGESIZE_MASK (3 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) -# define SMC_ECCMD_ECC_PAGESIZE_528 (0 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) -# define SMC_ECCMD_ECC_PAGESIZE_1056 (1 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) -# define SMC_ECCMD_ECC_PAGESIZE_2112 (2 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) -# define SMC_ECCMD_ECC_PAGESIZE_4224 (3 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) -#define SMC_ECCMD_TYPCORREC_SHIFT (4) /* Bits 4-5: type of correction */ -#define SMC_ECCMD_TYPCORREC_MASK (3 << SMC_ECCMD_TYPCORREC_SHIFT) -# define SMC_ECCMD_TYPCORREC_PAGE (0 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for a page */ -# define SMC_ECCMD_TYPCORREC_256 (1 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for 256 bytes */ -# define SMC_ECCMD_TYPCORREC_512 (2 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for 512 bytes */ +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SMC_ECCMD_ECC_PAGESIZE_SHIFT (0) /* Bits 0-1 */ +# define SMC_ECCMD_ECC_PAGESIZE_MASK (3 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) +# define SMC_ECCMD_ECC_PAGESIZE_528 (0 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) +# define SMC_ECCMD_ECC_PAGESIZE_1056 (1 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) +# define SMC_ECCMD_ECC_PAGESIZE_2112 (2 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) +# define SMC_ECCMD_ECC_PAGESIZE_4224 (3 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) +# define SMC_ECCMD_TYPCORREC_SHIFT (4) /* Bits 4-5: type of correction */ +# define SMC_ECCMD_TYPCORREC_MASK (3 << SMC_ECCMD_TYPCORREC_SHIFT) +# define SMC_ECCMD_TYPCORREC_PAGE (0 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for a page */ +# define SMC_ECCMD_TYPCORREC_256 (1 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for 256 bytes */ +# define SMC_ECCMD_TYPCORREC_512 (2 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for 512 bytes */ +#endif /* SMC ECC Status Register 1 */ -#define _RECERR (0) /* Recoverable Error */ -#define _ECCERR (1) /* ECC Error */ -#define _MULERR (2) /* Multiple Error */ - -#define SMC_ECCSR1_RECERR(n) (1 << (((n)<<4)+_RECERR)) -#define SMC_ECCSR1_ECCERR(n) (1 << (((n)<<4)+_ECCERR)) -#define SMC_ECCSR1_MULERR(n) (1 << (((n)<<4)+_MULERR)) - -#define SMC_ECCSR1_RECERR0 SMC_ECCSR1_RECERR(0) -#define SMC_ECCSR1_ECCERR0 SMC_ECCSR1_ECCERR(0) -#define SMC_ECCSR1_MULERR0 SMC_ECCSR1_MULERR(0) -#define SMC_ECCSR1_RECERR1 SMC_ECCSR1_RECERR(1) -#define SMC_ECCSR1_ECCERR1 SMC_ECCSR1_ECCERR(1) -#define SMC_ECCSR1_MULERR1 SMC_ECCSR1_MULERR(1) -#define SMC_ECCSR1_RECERR2 SMC_ECCSR1_RECERR(2) -#define SMC_ECCSR1_ECCERR2 SMC_ECCSR1_ECCERR(2) -#define SMC_ECCSR1_MULERR2 SMC_ECCSR1_MULERR(2) -#define SMC_ECCSR1_RECERR3 SMC_ECCSR1_RECERR(3) -#define SMC_ECCSR1_ECCERR3 SMC_ECCSR1_ECCERR(3) -#define SMC_ECCSR1_MULERR3 SMC_ECCSR1_MULERR(3) -#define SMC_ECCSR1_RECERR4 SMC_ECCSR1_RECERR(4) -#define SMC_ECCSR1_ECCERR4 SMC_ECCSR1_ECCERR(4) -#define SMC_ECCSR1_MULERR4 SMC_ECCSR1_MULERR(4) -#define SMC_ECCSR1_RECERR5 SMC_ECCSR1_RECERR(5) -#define SMC_ECCSR1_ECCERR5 SMC_ECCSR1_ECCERR(5) -#define SMC_ECCSR1_MULERR5 SMC_ECCSR1_MULERR(5) -#define SMC_ECCSR1_RECERR6 SMC_ECCSR1_RECERR(6) -#define SMC_ECCSR1_ECCERR6 SMC_ECCSR1_ECCERR(6) -#define SMC_ECCSR1_MULERR6 SMC_ECCSR1_MULERR(6) -#define SMC_ECCSR1_RECERR7 SMC_ECCSR1_RECERR(7) -#define SMC_ECCSR1_ECCERR7 SMC_ECCSR1_ECCERR(7) -#define SMC_ECCSR1_MULERR7 SMC_ECCSR1_MULERR(7) +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define _RECERR (0) /* Recoverable Error */ +# define _ECCERR (1) /* ECC Error */ +# define _MULERR (2) /* Multiple Error */ + +# define SMC_ECCSR1_RECERR(n) (1 << (((n)<<4)+_RECERR)) +# define SMC_ECCSR1_ECCERR(n) (1 << (((n)<<4)+_ECCERR)) +# define SMC_ECCSR1_MULERR(n) (1 << (((n)<<4)+_MULERR)) + +# define SMC_ECCSR1_RECERR0 SMC_ECCSR1_RECERR(0) +# define SMC_ECCSR1_ECCERR0 SMC_ECCSR1_ECCERR(0) +# define SMC_ECCSR1_MULERR0 SMC_ECCSR1_MULERR(0) +# define SMC_ECCSR1_RECERR1 SMC_ECCSR1_RECERR(1) +# define SMC_ECCSR1_ECCERR1 SMC_ECCSR1_ECCERR(1) +# define SMC_ECCSR1_MULERR1 SMC_ECCSR1_MULERR(1) +# define SMC_ECCSR1_RECERR2 SMC_ECCSR1_RECERR(2) +# define SMC_ECCSR1_ECCERR2 SMC_ECCSR1_ECCERR(2) +# define SMC_ECCSR1_MULERR2 SMC_ECCSR1_MULERR(2) +# define SMC_ECCSR1_RECERR3 SMC_ECCSR1_RECERR(3) +# define SMC_ECCSR1_ECCERR3 SMC_ECCSR1_ECCERR(3) +# define SMC_ECCSR1_MULERR3 SMC_ECCSR1_MULERR(3) +# define SMC_ECCSR1_RECERR4 SMC_ECCSR1_RECERR(4) +# define SMC_ECCSR1_ECCERR4 SMC_ECCSR1_ECCERR(4) +# define SMC_ECCSR1_MULERR4 SMC_ECCSR1_MULERR(4) +# define SMC_ECCSR1_RECERR5 SMC_ECCSR1_RECERR(5) +# define SMC_ECCSR1_ECCERR5 SMC_ECCSR1_ECCERR(5) +# define SMC_ECCSR1_MULERR5 SMC_ECCSR1_MULERR(5) +# define SMC_ECCSR1_RECERR6 SMC_ECCSR1_RECERR(6) +# define SMC_ECCSR1_ECCERR6 SMC_ECCSR1_ECCERR(6) +# define SMC_ECCSR1_MULERR6 SMC_ECCSR1_MULERR(6) +# define SMC_ECCSR1_RECERR7 SMC_ECCSR1_RECERR(7) +# define SMC_ECCSR1_ECCERR7 SMC_ECCSR1_ECCERR(7) +# define SMC_ECCSR1_MULERR7 SMC_ECCSR1_MULERR(7) +#endif /* SMC ECC Status Register 2 */ -#define SMC_ECCSR2_RECERR(n) (1 << ((((n)-8)<<4)+_RECERR)) -#define SMC_ECCSR2_ECCERR(n) (1 << ((((n)-8)<<4)+_ECCERR)) -#define SMC_ECCSR2_MULERR(n) (1 << ((((n)-8)<<4)+_MULERR)) - -#define SMC_ECCSR2_RECERR8 SMC_ECCSR2_RECERR(8) -#define SMC_ECCSR2_ECCERR8 SMC_ECCSR2_ECCERR(8) -#define SMC_ECCSR2_MULERR8 SMC_ECCSR2_MULERR(8) -#define SMC_ECCSR2_RECERR9 SMC_ECCSR2_RECERR(9) -#define SMC_ECCSR2_ECCERR9 SMC_ECCSR2_ECCERR(9) -#define SMC_ECCSR2_MULERR9 SMC_ECCSR2_MULERR(9) -#define SMC_ECCSR2_RECERR10 SMC_ECCSR2_RECERR(10) -#define SMC_ECCSR2_ECCERR10 SMC_ECCSR2_ECCERR(10) -#define SMC_ECCSR2_MULERR10 SMC_ECCSR2_MULERR(10) -#define SMC_ECCSR2_RECERR11 SMC_ECCSR2_RECERR(11) -#define SMC_ECCSR2_ECCERR11 SMC_ECCSR2_ECCERR(11) -#define SMC_ECCSR2_MULERR11 SMC_ECCSR2_MULERR(11) -#define SMC_ECCSR2_RECERR12 SMC_ECCSR2_RECERR(12) -#define SMC_ECCSR2_ECCERR12 SMC_ECCSR2_ECCERR(12) -#define SMC_ECCSR2_MULERR12 SMC_ECCSR2_MULERR(12) -#define SMC_ECCSR2_RECERR13 SMC_ECCSR2_RECERR(13) -#define SMC_ECCSR2_ECCERR13 SMC_ECCSR2_ECCERR(13) -#define SMC_ECCSR2_MULERR13 SMC_ECCSR2_MULERR(13) -#define SMC_ECCSR1_RECERR14 SMC_ECCSR2_RECERR(14) -#define SMC_ECCSR1_ECCERR14 SMC_ECCSR2_ECCERR(14) -#define SMC_ECCSR1_MULERR14 SMC_ECCSR2_MULERR(14) -#define SMC_ECCSR1_RECERR15 SMC_ECCSR2_RECERR(15) -#define SMC_ECCSR1_ECCERR15 SMC_ECCSR2_ECCERR(15) -#define SMC_ECCSR1_MULERR15 SMC_ECCSR2_MULERR(15) +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SMC_ECCSR2_RECERR(n) (1 << ((((n)-8)<<4)+_RECERR)) +# define SMC_ECCSR2_ECCERR(n) (1 << ((((n)-8)<<4)+_ECCERR)) +# define SMC_ECCSR2_MULERR(n) (1 << ((((n)-8)<<4)+_MULERR)) + +# define SMC_ECCSR2_RECERR8 SMC_ECCSR2_RECERR(8) +# define SMC_ECCSR2_ECCERR8 SMC_ECCSR2_ECCERR(8) +# define SMC_ECCSR2_MULERR8 SMC_ECCSR2_MULERR(8) +# define SMC_ECCSR2_RECERR9 SMC_ECCSR2_RECERR(9) +# define SMC_ECCSR2_ECCERR9 SMC_ECCSR2_ECCERR(9) +# define SMC_ECCSR2_MULERR9 SMC_ECCSR2_MULERR(9) +# define SMC_ECCSR2_RECERR10 SMC_ECCSR2_RECERR(10) +# define SMC_ECCSR2_ECCERR10 SMC_ECCSR2_ECCERR(10) +# define SMC_ECCSR2_MULERR10 SMC_ECCSR2_MULERR(10) +# define SMC_ECCSR2_RECERR11 SMC_ECCSR2_RECERR(11) +# define SMC_ECCSR2_ECCERR11 SMC_ECCSR2_ECCERR(11) +# define SMC_ECCSR2_MULERR11 SMC_ECCSR2_MULERR(11) +# define SMC_ECCSR2_RECERR12 SMC_ECCSR2_RECERR(12) +# define SMC_ECCSR2_ECCERR12 SMC_ECCSR2_ECCERR(12) +# define SMC_ECCSR2_MULERR12 SMC_ECCSR2_MULERR(12) +# define SMC_ECCSR2_RECERR13 SMC_ECCSR2_RECERR(13) +# define SMC_ECCSR2_ECCERR13 SMC_ECCSR2_ECCERR(13) +# define SMC_ECCSR2_MULERR13 SMC_ECCSR2_MULERR(13) +# define SMC_ECCSR1_RECERR14 SMC_ECCSR2_RECERR(14) +# define SMC_ECCSR1_ECCERR14 SMC_ECCSR2_ECCERR(14) +# define SMC_ECCSR1_MULERR14 SMC_ECCSR2_MULERR(14) +# define SMC_ECCSR1_RECERR15 SMC_ECCSR2_RECERR(15) +# define SMC_ECCSR1_ECCERR15 SMC_ECCSR2_ECCERR(15) +# define SMC_ECCSR1_MULERR15 SMC_ECCSR2_MULERR(15) +#endif /* Registers for 1 ECC for a page of 512/1024/2048/4096 bytes */ /* SMC_ECC_PR0 */ -#define SMC_ECCPR0_BITADDR_SHIFT (0) /* Bits 0-3: Bit Address */ -#define SMC_ECCPR0_BITADDR_MASK (15 << SMC_ECCPR0_BITADDR_SHIFT) -#define SMC_ECCPR0_WORDADDR_SHIFT (4) /* Bits 4-15: Word Address */ -#define SMC_ECCPR0_WORDADDR_MASK (0xfff << SMC_ECCPR0_WORDADDR_SHIFT) +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SMC_ECCPR0_BITADDR_SHIFT (0) /* Bits 0-3: Bit Address */ +# define SMC_ECCPR0_BITADDR_MASK (15 << SMC_ECCPR0_BITADDR_SHIFT) +# define SMC_ECCPR0_WORDADDR_SHIFT (4) /* Bits 4-15: Word Address */ +# define SMC_ECCPR0_WORDADDR_MASK (0xfff << SMC_ECCPR0_WORDADDR_SHIFT) -#define SMC_ECCPR1_NPARITY_SHIFT (0) /* Bits 0-15 */ -#define SMC_ECCPR1_NPARITY_MASK (0xffff << SMC_ECCPR1_NPARITY_SHIFT) +# define SMC_ECCPR1_NPARITY_SHIFT (0) /* Bits 0-15 */ +# define SMC_ECCPR1_NPARITY_MASK (0xffff << SMC_ECCPR1_NPARITY_SHIFT) +#endif /* Registers for 1 ECC per 512 bytes for a page of 512/2048/4096 bytes, 8-bit word */ -#define SMC_ECCPR512_BITADDR_SHIFT (0) /* Bits 0-3: Bit Address */ -#define SMC_ECCPR512_BITADDR_MASK (15 << SMC_ECCPR512_BITADDR_SHIFT) -#define SMC_ECCPR512_WORDADDR_SHIFT (4) /* Bits 4-15: Word Address */ -#define SMC_ECCPR512_WORDADDR_MASK (0xfff << SMC_ECCPR512_WORDADDR_SHIFT) -#define SMC_ECCPR512_NPARITY_SHIFT (12) /* Bits 12-23 (or is it 31?) */ -#define SMC_ECCPR512_NPARITY_MASK (0xfff << SMC_ECCPR512_NPARITY_SHIFT) +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SMC_ECCPR512_BITADDR_SHIFT (0) /* Bits 0-3: Bit Address */ +# define SMC_ECCPR512_BITADDR_MASK (15 << SMC_ECCPR512_BITADDR_SHIFT) +# define SMC_ECCPR512_WORDADDR_SHIFT (4) /* Bits 4-15: Word Address */ +# define SMC_ECCPR512_WORDADDR_MASK (0xfff << SMC_ECCPR512_WORDADDR_SHIFT) +# define SMC_ECCPR512_NPARITY_SHIFT (12) /* Bits 12-23 (or is it 31?) */ +# define SMC_ECCPR512_NPARITY_MASK (0xfff << SMC_ECCPR512_NPARITY_SHIFT) +#endif /* Registers for 1 ECC per 256 bytes for a page of 512/2048/4096 bytes, 8-bit word */ -#define SMC_ECCPR256_BITADDR_SHIFT (0) /* Bits 0-2: Bit Address */ -#define SMC_ECCPR256_BITADDR_MASK (7 << SMC_ECCPR256_BITADDR_SHIFT) -#define SMC_ECCPR256_WORDADDR_SHIFT (4) /* Bits 4-10: Word Address */ -#define SMC_ECCPR256_WORDADDR_MASK (0x7f << SMC_ECCPR256_WORDADDR_SHIFT) -#define SMC_ECCPR256_NPARITY_SHIFT (12) /* Bits 12-22 */ -#define SMC_ECCPR256_NPARITY_MASK (0x7ff << SMC_ECCPR256_NPARITY_SHIFT) +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SMC_ECCPR256_BITADDR_SHIFT (0) /* Bits 0-2: Bit Address */ +# define SMC_ECCPR256_BITADDR_MASK (7 << SMC_ECCPR256_BITADDR_SHIFT) +# define SMC_ECCPR256_WORDADDR_SHIFT (4) /* Bits 4-10: Word Address */ +# define SMC_ECCPR256_WORDADDR_MASK (0x7f << SMC_ECCPR256_WORDADDR_SHIFT) +# define SMC_ECCPR256_NPARITY_SHIFT (12) /* Bits 12-22 */ +# define SMC_ECCPR256_NPARITY_MASK (0x7ff << SMC_ECCPR256_NPARITY_SHIFT) +#endif /* SMC Setup Register */ -#define SMCCS_SETUP_NWESETUP_SHIFT (0) /* Bits 0-5: NWE Setup length */ -#define SMCCS_SETUP_NWESETUP_MASK (63 << SMCCS_SETUP_NWESETUP_SHIFT) -#define SMCCS_SETUP_NCSWRSETUP_SHIFT (8) /* Bits 8-13: NCS Setup length in Write access */ -#define SMCCS_SETUP_NCSWRSETUP_MASK (63 << SMCCS_SETUP_NCSWRSETUP_SHIFT) -#define SMCCS_SETUP_NRDSETUP_SHIFT (16) /* Bits 16-21: NRD Setup length */ -#define SMCCS_SETUP_NRDSETUP_MASK (63 << SMCCS_SETUP_NRDSETUP_SHIFT) -#define SMCCS_SETUP_NCSRDSETUP_SHIFT (24) /* Bits 24-29: NCS Setup length in Read access */ -#define SMCCS_SETUP_NCSRDSETUP_MASK (63 << SMCCS_SETUP_NCSRDSETUP_SHIFT) +#define SMCCS_SETUP_NWESETUP_SHIFT (0) /* Bits 0-5: NWE Setup length */ +#define SMCCS_SETUP_NWESETUP_MASK (63 << SMCCS_SETUP_NWESETUP_SHIFT) +#define SMCCS_SETUP_NCSWRSETUP_SHIFT (8) /* Bits 8-13: NCS Setup length in Write access */ +#define SMCCS_SETUP_NCSWRSETUP_MASK (63 << SMCCS_SETUP_NCSWRSETUP_SHIFT) +#define SMCCS_SETUP_NRDSETUP_SHIFT (16) /* Bits 16-21: NRD Setup length */ +#define SMCCS_SETUP_NRDSETUP_MASK (63 << SMCCS_SETUP_NRDSETUP_SHIFT) +#define SMCCS_SETUP_NCSRDSETUP_SHIFT (24) /* Bits 24-29: NCS Setup length in Read access */ +#define SMCCS_SETUP_NCSRDSETUP_MASK (63 << SMCCS_SETUP_NCSRDSETUP_SHIFT) /* SMC Pulse Register */ -#define SMCCS_PULSE_NWEPULSE_SHIFT (0) /* Bits 0-5: NWE Pulse Length */ -#define SMCCS_PULSE_NWEPULSE_MASK (63 << SMCCS_PULSE_NWEPULSE_SHIFT) -#define SMCCS_PULSE_NCSWRPULSE_SHIFT (8) /* Bits 8-13: NCS Pulse Length in WRITE Access */ -#define SMCCS_PULSE_NCSWRPULSE_MASK (63 << SMCCS_PULSE_NCSWRPULSE_SHIFT) -#define SMCCS_PULSE_RDPULSE_SHIFT (16) /* Bits 16-21: NRD Pulse Length */ -#define SMCCS_PULSE_RDPULSE_MASK (63 << SMCCS_PULSE_RDPULSE_SHIFT) -#define SMCCS_PULSE_NCSRDPULSE_SHIFT (24) /* Bits 24-29: NCS Pulse Length in READ Access */ -#define SMCCS_PULSE_NCSRDPULSE_MASK (63 << SMCCS_PULSE_NCSRDPULSE_SHIFT) +#define SMCCS_PULSE_NWEPULSE_SHIFT (0) /* Bits 0-5: NWE Pulse Length */ +#define SMCCS_PULSE_NWEPULSE_MASK (63 << SMCCS_PULSE_NWEPULSE_SHIFT) +#define SMCCS_PULSE_NCSWRPULSE_SHIFT (8) /* Bits 8-13: NCS Pulse Length in WRITE Access */ +#define SMCCS_PULSE_NCSWRPULSE_MASK (63 << SMCCS_PULSE_NCSWRPULSE_SHIFT) +#define SMCCS_PULSE_NRDPULSE_SHIFT (16) /* Bits 16-21: NRD Pulse Length */ +#define SMCCS_PULSE_NRDPULSE_MASK (63 << SMCCS_PULSE_NRDPULSE_SHIFT) +#define SMCCS_PULSE_NCSRDPULSE_SHIFT (24) /* Bits 24-29: NCS Pulse Length in READ Access */ +#define SMCCS_PULSE_NCSRDPULSE_MASK (63 << SMCCS_PULSE_NCSRDPULSE_SHIFT) /* SMC Cycle Register */ -#define SMCCS_CYCLE_NWECYCLE_SHIFT (0) /* Bits 0-8: Total Write Cycle Length */ -#define SMCCS_CYCLE_NWECYCLE_MASK (0x1ff << SMCCS_CYCLE_NWECYCLE_SHIFT) -#define SMCCS_CYCLE_NRDCYCLE_SHIFT (16) /* Bits 16-24: Total Read Cycle Length */ -#define SMCCS_CYCLE_NRDCYCLE_MASK (0x1ff << SMCCS_CYCLE_NRDCYCLE_SHIFT) +#define SMCCS_CYCLE_NWECYCLE_SHIFT (0) /* Bits 0-8: Total Write Cycle Length */ +#define SMCCS_CYCLE_NWECYCLE_MASK (0x1ff << SMCCS_CYCLE_NWECYCLE_SHIFT) +#define SMCCS_CYCLE_NRDCYCLE_SHIFT (16) /* Bits 16-24: Total Read Cycle Length */ +#define SMCCS_CYCLE_NRDCYCLE_MASK (0x1ff << SMCCS_CYCLE_NRDCYCLE_SHIFT) /* SMC Timings Register */ -#define SMCCS_TIMINGS_TCLR_SHIFT (0) /* Bits 0-3: CLE to REN Low Delay */ -#define SMCCS_TIMINGS_TCLR_MASK (15 << SMCCS_TIMINGS_TCLR_SHIFT) -#define SMCCS_TIMINGS_TADL_SHIFT (4) /* Bits 4-7: ALE to Data Start */ -#define SMCCS_TIMINGS_TADL_MASK (15 << SMCCS_TIMINGS_TADL_SHIFT) -#define SMCCS_TIMINGS_TAR_SHIFT (8) /* Bits 8-11: ALE to REN Low Delay */ -#define SMCCS_TIMINGS_TAR_MASK (15 << SMCCS_TIMINGS_TAR_SHIFT) -#define SMCCS_TIMINGS_OCMS (1 << 12) /* Bit 12: Off Chip Memory Scrambling Enable */ -#define SMCCS_TIMINGS_TRR_SHIFT (16) /* Bits 16-19: Ready to REN Low Delay */ -#define SMCCS_TIMINGS_TRR_MASK (15 << SMCCS_TIMINGS_TRR_SHIFT) -#define SMCCS_TIMINGS_TWB_SHIFT (24) /* Bits 24-27: WEN High to REN to Busy */ -#define SMCCS_TIMINGS_TWB_MASK (15 << SMCCS_TIMINGS_TWB_SHIFT) -#define SMCCS_TIMINGS_RBNSEL_SHIFT (28) /* Bits 28-30: Ready/Busy Line Selection */ -#define SMCCS_TIMINGS_RBNSEL_MASK (7 << SMCCS_TIMINGS_RBNSEL_SHIFT) -#define SMCCS_TIMINGS_NFSEL (1 << 31) /* Bit 31: NAND Flash Selection */ +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SMCCS_TIMINGS_TCLR_SHIFT (0) /* Bits 0-3: CLE to REN Low Delay */ +# define SMCCS_TIMINGS_TCLR_MASK (15 << SMCCS_TIMINGS_TCLR_SHIFT) +# define SMCCS_TIMINGS_TADL_SHIFT (4) /* Bits 4-7: ALE to Data Start */ +# define SMCCS_TIMINGS_TADL_MASK (15 << SMCCS_TIMINGS_TADL_SHIFT) +# define SMCCS_TIMINGS_TAR_SHIFT (8) /* Bits 8-11: ALE to REN Low Delay */ +# define SMCCS_TIMINGS_TAR_MASK (15 << SMCCS_TIMINGS_TAR_SHIFT) +# define SMCCS_TIMINGS_OCMS (1 << 12) /* Bit 12: Off Chip Memory Scrambling Enable */ +# define SMCCS_TIMINGS_TRR_SHIFT (16) /* Bits 16-19: Ready to REN Low Delay */ +# define SMCCS_TIMINGS_TRR_MASK (15 << SMCCS_TIMINGS_TRR_SHIFT) +# define SMCCS_TIMINGS_TWB_SHIFT (24) /* Bits 24-27: WEN High to REN to Busy */ +# define SMCCS_TIMINGS_TWB_MASK (15 << SMCCS_TIMINGS_TWB_SHIFT) +# define SMCCS_TIMINGS_RBNSEL_SHIFT (28) /* Bits 28-30: Ready/Busy Line Selection */ +# define SMCCS_TIMINGS_RBNSEL_MASK (7 << SMCCS_TIMINGS_RBNSEL_SHIFT) +# define SMCCS_TIMINGS_NFSEL (1 << 31) /* Bit 31: NAND Flash Selection */ +#endif /* SMC Mode Register */ -#define SMCCS_MODE_READMODE (1 << 0) /* Bit 0: Read mode */ -#define SMCCS_MODE_WRITEMODE (1 << 1) /* Bit 1: Write mode */ -#define SMCCS_MODE_EXNWMODE_SHIFT (4) /* Bits 4-5: NWAIT Mode */ -#define SMCCS_MODE_EXNWMODE_MASK (3 << SMCCS_MODE_EXNWMODE_SHIFT) -# define SMCCS_EXNWMODE_DISABLED (0 << SMCCS_MODE_EXNWMODE_SHIFT) -# define SMCCS_EXNWMODE_FROZEN (2 << SMCCS_MODE_EXNWMODE_SHIFT) -# define SMCCS_EXNWMODE_READY (3 << SMCCS_MODE_EXNWMODE_SHIFT) -#define SMCCS_MODE_BAT (1 << 8) /* Bit 8: Byte Access Type */ -#define SMCCS_MODE_DBW_SHIFT (12) /* Bits 12-13: Data Bus Width */ -#define SMCCS_MODE_DBW_MASK (3 << SMCCS_MODE_DBW_SHIFT) -# define SMCCS_MODE_DBW_8BITS (0 << 12) /* 8 bits */ -# define SMCCS_MODE_DBW_16BITS (1 << 12) /* 16 bits */ -# define SMCCS_MODE_DBW_32BITS (2 << 12) /* 32 bits */ -#define SMCCS_MODE_TDFCYCLES_SHIFT (16) /* Bits 16-19: Data Float Time */ -#define SMCCS_MODE_TDFCYCLES_MASK (15 << SMCCS_MODE_TDFCYCLES_SHIFT) -#define SMCCS_MODE_TDFMODE (1 << 20) /* Bit 20: TDF Optimization */ -#define SMCCS_MODE_PMEN (1 << 24) /* Bit 24: Page Mode Enabled */ -#define SMCCS_MODE_PS_SHIFT (28) /* Bits 28-29: Page Size */ -#define SMCCS_MODE_PS_MASK (3 << SMCCS_MODE_PS_SHIFT) -# define SMCCS_MODE_PS_SIZE_4BYTES (0 << SMCCS_MODE_PS_SHIFT) /* 4 bytes */ -# define SMCCS_MODE_PS_SIZE_8BYTES (1 << SMCCS_MODE_PS_SHIFT) /* 8 bytes */ -# define SMCCS_MODE_PS_SIZE_16BYTES (2 << SMCCS_MODE_PS_SHIFT) /* 16 bytes */ -# define SMCCS_MODE_PS_SIZE_32BYTES (3 << SMCCS_MODE_PS_SHIFT) /* 32 bytes */ - -/* SMC OCMS Register */ - -#define SMC_OCMS_SMSE (1 << 0) /* Bit 0: Static Memory Controller Scrambling Enable */ -#define SMC_OCMS_SRSE (1 << 1) /* Bit 1: SRAM Scrambling Enable */ - -/* SMC Write Protection Control */ - -#define SMC_WPCR_WPPEN (1 << 9) /* Bit 9: Write Protection Enable */ -#define SMC_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protection KEY password */ -#define SMC_WPCR_WPKEY_MASK (0x00ffffff << SMC_WPCR_WPKEY_SHIFT) +#define SMCCS_MODE_READMODE (1 << 0) /* Bit 0: Read mode */ +#define SMCCS_MODE_WRITEMODE (1 << 1) /* Bit 1: Write mode */ +#define SMCCS_MODE_EXNWMODE_SHIFT (4) /* Bits 4-5: NWAIT Mode */ +#define SMCCS_MODE_EXNWMODE_MASK (3 << SMCCS_MODE_EXNWMODE_SHIFT) +# define SMCCS_EXNWMODE_DISABLED (0 << SMCCS_MODE_EXNWMODE_SHIFT) +# define SMCCS_EXNWMODE_FROZEN (2 << SMCCS_MODE_EXNWMODE_SHIFT) +# define SMCCS_EXNWMODE_READY (3 << SMCCS_MODE_EXNWMODE_SHIFT) + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SMCCS_MODE_BAT (1 << 8) /* Bit 8: Byte Access Type */ +# define SMCCS_MODE_DBW_SHIFT (12) /* Bits 12-13: Data Bus Width */ +# define SMCCS_MODE_DBW_MASK (3 << SMCCS_MODE_DBW_SHIFT) +# define SMCCS_MODE_DBW_8BITS (0 << 12) /* 8 bits */ +# define SMCCS_MODE_DBW_16BITS (1 << 12) /* 16 bits */ +# define SMCCS_MODE_DBW_32BITS (2 << 12) /* 32 bits */ +#endif + +#define SMCCS_MODE_TDFCYCLES_SHIFT (16) /* Bits 16-19: Data Float Time */ +#define SMCCS_MODE_TDFCYCLES_MASK (15 << SMCCS_MODE_TDFCYCLES_SHIFT) +#define SMCCS_MODE_TDFMODE (1 << 20) /* Bit 20: TDF Optimization */ +#define SMCCS_MODE_PMEN (1 << 24) /* Bit 24: Page Mode Enabled */ +#define SMCCS_MODE_PS_SHIFT (28) /* Bits 28-29: Page Size */ +#define SMCCS_MODE_PS_MASK (3 << SMCCS_MODE_PS_SHIFT) +# define SMCCS_MODE_PS_SIZE_4BYTES (0 << SMCCS_MODE_PS_SHIFT) /* 4 bytes */ +# define SMCCS_MODE_PS_SIZE_8BYTES (1 << SMCCS_MODE_PS_SHIFT) /* 8 bytes */ +# define SMCCS_MODE_PS_SIZE_16BYTES (2 << SMCCS_MODE_PS_SHIFT) /* 16 bytes */ +# define SMCCS_MODE_PS_SIZE_32BYTES (3 << SMCCS_MODE_PS_SHIFT) /* 32 bytes */ + +/* SMC OCMS Mode Register */ + +#define SMC_OCMS_SMSE (1 << 0) /* Bit 0: Static Memory Controller Scrambling Enable */ +#define SMC_OCMS_SRSE (1 << 1) /* Bit 1: SRAM Scrambling Enable */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SMC_OCMS_CSSE(n) (1 << ((n)+16)) /* Chip Select (n=0-3) Scrambling Enable */ +# define SMC_OCMS_CS0SE (1 << 16) /* Bit 16: Chip Select 0 Scrambling Enable */ +# define SMC_OCMS_CS1SE (1 << 17) /* Bit 17: Chip Select 1 Scrambling Enable */ +# define SMC_OCMS_CS2SE (1 << 18) /* Bit 18: Chip Select 2 Scrambling Enable */ +# define SMC_OCMS_CS3SE (1 << 19) /* Bit 19: Chip Select 3 Scrambling Enable */ +#endif + +/* SMC KEY1/2 Registers (32-bit data) */ + +/* SMC Write Protect Mode Register */ + +#define SMC_WPCR_WPPEN (1 << 9) /* Bit 9: Write Protection Enable */ +#define SMC_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protection KEY password */ +#define SMC_WPCR_WPKEY_MASK (0x00ffffff << SMC_WPCR_WPKEY_SHIFT) +# define SMC_WPCR_WPKEY (0x00534d43 << SMC_WPCR_WPKEY_SHIFT) /* SMC Write Protection Status */ -#define SMC_WPSR_PVS_SHIFT (0) /* Bits 0-3: Write Protection Violation Status */ -#define SMC_WPSR_PVS_MASK (15 << SMC_WPSR_PVS_SHIFT) -# define SMC_WPSR_PVS_NONE (0 << SMC_WPSR_PVS_SHIFT) /* No Write Protection Violation */ -# define SMC_WPSR_PVS_ RCREG (1 << SMC_WPSR_PVS_SHIFT) /* Attempt to write a control reg */ -# define SMC_WPSR_PVS_RESET (2 << SMC_WPSR_PVS_SHIFT) /* Software reset */ -# define SMC_WPSR_PVS_BOTH (3 << SMC_WPSR_PVS_SHIFT) /* Write + reset */ +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SMC_WPSR_PVS_SHIFT (0) /* Bits 0-3: Write Protection Violation Status */ +# define SMC_WPSR_PVS_MASK (15 << SMC_WPSR_PVS_SHIFT) +# define SMC_WPSR_PVS_NONE (0 << SMC_WPSR_PVS_SHIFT) /* No Write Protection Violation */ +# define SMC_WPSR_PVS_ RCREG (1 << SMC_WPSR_PVS_SHIFT) /* Attempt to write a control reg */ +# define SMC_WPSR_PVS_RESET (2 << SMC_WPSR_PVS_SHIFT) /* Software reset */ +# define SMC_WPSR_PVS_BOTH (3 << SMC_WPSR_PVS_SHIFT) /* Write + reset */ +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# define SMC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Source */ +#endif + #define SMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */ #define SMC_WPSR_WPVSRC_MASK (0xffff << SMC_WPSR_WPVSRC_SHIFT) diff --git a/nuttx/arch/arm/src/sam34/chip/sam_spi.h b/nuttx/arch/arm/src/sam34/chip/sam_spi.h index 91720647f..887b7f656 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_spi.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_spi.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam_spi.h + * Serial Peripheral Interface (SPI) definitions for the SAM3U and SAM4S * * Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -67,7 +68,8 @@ /* 0x40-0xe0: Reserved */ #define SAM_SPI_WPCR_OFFSET 0xe4 /* Write Protection Control Register */ #define SAM_SPI_WPSR_OFFSET 0xe8 /* Write Protection Status Register */ - /* 0xec-0xf8: Reserved*/ + /* 0xec-0xfc: Reserved */ + /* 0x100-0x124 Reserved for PDC Registers */ /* SPI register adresses ****************************************************************/ @@ -105,6 +107,10 @@ #define SPI_MR_LLB (1 << 7) /* Bit 7: Local Loopback Enable */ #define SPI_MR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */ #define SPI_MR_PCS_MASK (15 << SPI_MR_PCS_SHIFT) +# define SPI_MR_PCS0 (0 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1110 (w/PCSDEC=0) */ +# define SPI_MR_PCS1 (1 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1100 (w/PCSDEC=0) */ +# define SPI_MR_PCS2 (3 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1011 (w/PCSDEC=0) */ +# define SPI_MR_PCS3 (7 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 0111 (w/PCSDEC=0) */ #define SPI_MR_DLYBCS_SHIFT (24) /* Bits 24-31: Delay Between Chip Selects */ #define SPI_MR_DLYBCS_MASK (0xff << SPI_MR_DLYBCS_SHIFT) @@ -114,6 +120,10 @@ #define SPI_RDR_RD_MASK (0xffff << SPI_RDR_RD_SHIFT) #define SPI_RDR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */ #define SPI_RDR_PCS_MASK (15 << SPI_RDR_PCS_SHIFT) +# define SPI_RDR_PCS0 (0 << SPI_RDR_PCS_SHIFT) /* NPCS[3:0] = 1110 (w/PCSDEC=0) */ +# define SPI_RDR_PCS1 (1 << SPI_RDR_PCS_SHIFT) /* NPCS[3:0] = 1100 (w/PCSDEC=0) */ +# define SPI_RDR_PCS2 (3 << SPI_RDR_PCS_SHIFT) /* NPCS[3:0] = 1011 (w/PCSDEC=0) */ +# define SPI_RDR_PCS3 (7 << SPI_RDR_PCS_SHIFT) /* NPCS[3:0] = 0111 (w/PCSDEC=0) */ /* SPI Transmit Data Register */ @@ -121,6 +131,10 @@ #define SPI_TDR_TD_MASK (0xffff << SPI_TDR_TD_SHIFT) #define SPI_TDR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */ #define SPI_TDR_PCS_MASK (15 << SPI_TDR_PCS_SHIFT) +# define SPI_TDR_PCS0 (0 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1110 (w/PCSDEC=0) */ +# define SPI_TDR_PCS1 (1 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1100 (w/PCSDEC=0) */ +# define SPI_TDR_PCS2 (3 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1011 (w/PCSDEC=0) */ +# define SPI_TDR_PCS3 (7 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 0111 (w/PCSDEC=0) */ #define SPI_TDR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */ /* SPI Status Register, SPI Interrupt Enable Register, SPI Interrupt Disable Register, @@ -131,6 +145,14 @@ #define SPI_INT_TDRE (1 << 1) /* Bit 1: Transmit Data Register Empty Interrupt */ #define SPI_INT_MODF (1 << 2) /* Bit 2: Mode Fault Error Interrupt */ #define SPI_INT_OVRES (1 << 3) /* Bit 3: Overrun Error Interrupt */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SPI_INT_ENDRX (1 << 4) /* Bit 4: End of RX buffer */ +# define SPI_INT_ENDTX (1 << 5) /* Bit 5: End of TX buffer */ +# define SPI_INT_RXBUFF (1 << 6) /* Bit 6: RX Buffer Full */ +# define SPI_INT_TXBUFE (1 << 7) /* Bit 7: TX Buffer Empty */ +#endif + #define SPI_INT_NSSR (1 << 8) /* Bit 8: NSS Rising Interrupt */ #define SPI_INT_TXEMPTY (1 << 9) /* Bit 9: Transmission Registers Empty Interrupt */ #define SPI_INT_UNDES (1 << 10) /* Bit 10: Underrun Error Status Interrupt (slave) */ @@ -163,16 +185,17 @@ /* SPI Write Protection Control Register */ -#define SPI_WPCR_SPIWPEN (1 << 0) /* Bit 0: SPI Write Protection Enable */ -#define SPI_WPCR_SPIWPKEY_SHIFT (8) /* Bits 8-31: SPI Write Protection Key Password */ -#define SPI_WPCR_SPIWPKEY_MASK (0x00ffffff << SPI_WPCR_SPIWPKEY_SHIFT) +#define SPI_WPCR_WPEN (1 << 0) /* Bit 0: SPI Write Protection Enable */ +#define SPI_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: SPI Write Protection Key Password */ +#define SPI_WPCR_WPKEY_MASK (0x00ffffff << SPI_WPCR_WPKEY_SHIFT) +# define SPI_WPCR_WPKEY (0x00535049 << SPI_WPCR_WPKEY_SHIFT) /* SPI Write Protection Status Register */ -#define SPI_WPSR_SPIWPVS_SHIFT (0) /* Bits 0-2: SPI Write Protection Violation Status */ -#define SPI_WPSR_SPIWPVS_MASK (7 << SPI_WPSR_SPIWPVS_SHIFT) -#define SPI_WPSR_SPIWPVSRC_SHIFT (8) /* Bits 8-15: SPI Write Protection Violation Source */ -#define SPI_WPSR_SPIWPVSRC_MASK (0xff << SPI_WPSR_SPIWPVSRC_SHIFT) +#define SPI_WPSR_WPVS_SHIFT (0) /* Bits 0-2: SPI Write Protection Violation Status */ +#define SPI_WPSR_WPVS_MASK (7 << SPI_WPSR_WPVS_SHIFT) +#define SPI_WPSR_WPVSRC_SHIFT (8) /* Bits 8-15: SPI Write Protection Violation Source */ +#define SPI_WPSR_WPVSRC_MASK (0xff << SPI_WPSR_WPVSRC_SHIFT) /**************************************************************************************** * Public Types diff --git a/nuttx/arch/arm/src/sam34/chip/sam_ssc.h b/nuttx/arch/arm/src/sam34/chip/sam_ssc.h index 552659260..2b3755a1c 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_ssc.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_ssc.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam_ssc.h + * Synchronous Serial Controller (SSC) definitions for the SAM3U and SAM4S * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -74,7 +75,7 @@ #define SAM_SSC_WPMR_OFFSET 0x0e4 /* Write Protect Mode Register */ #define SAM_SSC_WPSR_OFFSET 0x0e8 /* Write Protect Status Register */ /* 0x050-0x0fc: Reserved */ - /* 0x100-0x124: Reserved */ + /* 0x100-0x124: Reserved for PDC registers */ /* SSC register adresses ****************************************************************/ @@ -121,7 +122,7 @@ # define SSC_RCMR_CKS_RK (2 << SSC_RCMR_CKS_SHIFT) /* RK pin */ #define SSC_RCMR_CKO_SHIFT (2) /* Bits 2-4: Receive Clock Output Mode Selection */ #define SSC_RCMR_CKO_MASK (7 << SSC_RCMR_CKO_SHIFT) -# define SSC_RCMR_CKO_ NONE (0 << SSC_RCMR_CKO_SHIFT) /* None */ +# define SSC_RCMR_CKO_NONE (0 << SSC_RCMR_CKO_SHIFT) /* None */ # define SSC_RCMR_CKO_CONTINUOUS (1 << SSC_RCMR_CKO_SHIFT) /* Continuous Receive Clock */ # define SSC_RCMR_CKO_XFERS (2 << SSC_RCMR_CKO_SHIFT) /* Receive Clock only during data transfers */ #define SSC_RCMR_CKI (1 << 5) /* Bit 5: Receive Clock Inversion */ @@ -142,12 +143,11 @@ # define SSC_RCMR_START_ANYEDGE (7 << SSC_RCMR_START_SHIFT) /* Any edge on RF signal */ # define SSC_RCMR_START_CMP0 (8 << SSC_RCMR_START_SHIFT) /* Compare 0 */ #define SSC_RCMR_STOP (1 << 12) /* Bit 12: Receive Stop Select */ -#define SSC_RCMR_STTDLY_SHIFT (15) /* Bits 16-23: Receive Start Delay */ +#define SSC_RCMR_STTDLY_SHIFT (16) /* Bits 16-23: Receive Start Delay */ #define SSC_RCMR_STTDLY_MASK (0xff << SSC_RCMR_STTDLY_SHIFT) #define SSC_RCMR_PERIOD_SHIFT (24) /* Bits 24-31: Receive Period Divider Selection */ #define SSC_RCMR_PERIOD_MASK (0xff << SSC_RCMR_PERIOD_SHIFT) - /* SSC Receive Frame Mode Register */ #define SSC_RFMR_DATLEN_SHIFT (0) /* Bits 0-4: Data Length */ @@ -162,7 +162,7 @@ #define SSC_RFMR_FSOS_MASK (7 << SSC_RFMR_FSOS_SHIFT) # define SSC_RFMR_FSOS_NONE (0 << SSC_RFMR_FSOS_SHIFT) /* None */ # define SSC_RFMR_FSOS_NEG (1 << SSC_RFMR_FSOS_SHIFT) /* 0x1 Negative Pulse */ -# define SSC_RFMR_FSOS_POW (2 << SSC_RFMR_FSOS_SHIFT) /* 0x2 Positive Pulse */ +# define SSC_RFMR_FSOS_POS (2 << SSC_RFMR_FSOS_SHIFT) /* 0x2 Positive Pulse */ # define SSC_RFMR_FSOS_LOW (3 << SSC_RFMR_FSOS_SHIFT) /* 0x3 Driven Low during data transfer */ # define SSC_RFMR_FSOS_HIGH (4 << SSC_RFMR_FSOS_SHIFT) /* 0x4 Driven High during data transfer */ # define SSC_RFMR_FSOS_TOGGLE (5 << SSC_RFMR_FSOS_SHIFT) /* 0x5 Toggling at each start of data transfer */ @@ -175,11 +175,11 @@ #define SSC_TCMR_CKS_SHIFT (0) /* Bits 0-1: Transmit Clock Selection */ #define SSC_TCMR_CKS_MASK (3 << SSC_TCMR_CKS_SHIFT) # define SSC_TCMR_CKS_DIVIDED (0 << SSC_TCMR_CKS_SHIFT) /* Divided Clock */ -# define SSC_TCMR_CKS_TK (1 << SSC_TCMR_CKS_SHIFT) /* TK Clock signal */ -# define SSC_TCMR_CKS_RK (2 << SSC_TCMR_CKS_SHIFT) /* RK pin */ +# define SSC_TCMR_CKS_RK (2 << SSC_TCMR_CKS_SHIFT) /* RK Clock signal */ +# define SSC_TCMR_CKS_TK (1 << SSC_TCMR_CKS_SHIFT) /* TK Pin */ #define SSC_TCMR_CKO_SHIFT (2) /* Bits 2-4: Transmit Clock Output Mode Selection */ #define SSC_TCMR_CKO_MASK (7 << SSC_TCMR_CKO_SHIFT) -# define SSC_TCMR_CKO_ NONE (0 << SSC_TCMR_CKO_SHIFT) /* None */ +# define SSC_TCMR_CKO_NONE (0 << SSC_TCMR_CKO_SHIFT) /* None */ # define SSC_TCMR_CKO_CONTINUOUS (1 << SSC_TCMR_CKO_SHIFT) /* Continuous Transmit Clock */ # define SSC_TCMR_CKO_XFERS (2 << SSC_TCMR_CKO_SHIFT) /* Transmit Clock only during data transfers */ #define SSC_TCMR_CKI (1 << 5) /* Bit 5: Transmit Clock Inversion */ @@ -217,7 +217,7 @@ #define SSC_TFMR_FSOS_MASK (7 << SSC_TFMR_FSOS_SHIFT) # define SSC_TFMR_FSOS_NONE (0 << SSC_TFMR_FSOS_SHIFT) /* None */ # define SSC_TFMR_FSOS_NEG (1 << SSC_TFMR_FSOS_SHIFT) /* 0x1 Negative Pulse */ -# define SSC_TFMR_FSOS_POW (2 << SSC_TFMR_FSOS_SHIFT) /* 0x2 Positive Pulse */ +# define SSC_TFMR_FSOS_POS (2 << SSC_TFMR_FSOS_SHIFT) /* 0x2 Positive Pulse */ # define SSC_TFMR_FSOS_LOW (3 << SSC_TFMR_FSOS_SHIFT) /* 0x3 Driven Low during data transfer */ # define SSC_TFMR_FSOS_HIGH (4 << SSC_TFMR_FSOS_SHIFT) /* 0x4 Driven High during data transfer */ # define SSC_TFMR_FSOS_TOGGLE (5 << SSC_TFMR_FSOS_SHIFT) /* 0x5 Toggling at each start of data transfer */ @@ -226,6 +226,8 @@ #define SSC_TFMR_FSLENEXT_SHIFT (28) /* Bits 28-31: FSLEN Field Extension */ #define SSC_TFMR_FSLENEXT_MASK (15 << SSC_TFMR_FSLENEXT_SHIFT) +/* SSC Receive/Transmit Holding Registers (32-bit data) */ + /* SSC Receive Synchronization Holding Register */ #define SSC_RSHR_RSDAT_SHIFT (0) /* Bits 0-15: Receive Synchronization Data */ @@ -270,6 +272,7 @@ #define SSC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ #define SSC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ #define SSC_WPMR_WPKEY_MASK (0x00ffffff << SSC_WPMR_WPKEY_SHIFT) +# define SSC_WPMR_WPKEY (0x00535343 << SSC_WPMR_WPKEY_SHIFT) /* SSC Write Protect Status Register */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_tc.h b/nuttx/arch/arm/src/sam34/chip/sam_tc.h index de2046852..779a5a2af 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_tc.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_tc.h @@ -1,5 +1,6 @@ /************************************************************************************************ * arch/arm/src/sam34/chip/sam_tc.h + * Timer Counter (TC) definitions for the SAM3U and SAM4S * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -56,7 +57,10 @@ #define SAM_TCN_OFFSET(n) (0x00 + ((n)<<6)) /* 0x00, 0x40, 0x80 */ #define SAM_TCN_CCR_OFFSET 0x00 /* Channel Control Register */ #define SAM_TCN_CMR_OFFSET 0x04 /* Channel Mode Register */ - /* 0x08 Reserved */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +#define SAM_TCN_SMMR_OFFSET 0x08 /* Stepper Motor Mode Register */ +#endif /* 0x0c Reserved */ #define SAM_TCN_CV_OFFSET 0x10 /* Counter Value */ #define SAM_TCN_RA_OFFSET 0x14 /* Register A */ @@ -75,8 +79,11 @@ #define SAM_TC_QIDR_OFFSET 0xcc /* QDEC Interrupt Disable Register */ #define SAM_TC_QIMR_OFFSET 0xd0 /* QDEC Interrupt Mask Register */ #define SAM_TC_QISR_OFFSET 0xd4 /* QDEC Interrupt Status Register */ - /* 0xd8 Reserved */ - /* 0xe4 Reserved */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TCN_FMR_OFFSET 0xd8 /* Fault Mode Register */ +# define SAM_TCN_WPMR_OFFSET 0xe4 /* Write Protect Mode Register */ +#endif /* TC register adresses *************************************************************************/ @@ -84,6 +91,9 @@ #define SAM_TC_CCR(n) (SAM_TCN_BASE(n)+SAM_TCN_CCR_OFFSET) #define SAM_TC_CMR(n) (SAM_TCN_BASE(n)+SAM_TCN_CMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TCN_SMMR(n) (SAM_TCN_BASE(n)+SAM_TCN_SMMR_OFFSET) +#endif #define SAM_TC_CV(n) (SAM_TCN_BASE(n)+SAM_TCN_CV_OFFSET) #define SAM_TC_RA(n) (SAM_TCN_BASE(n)+SAM_TCN_RA_OFFSET) #define SAM_TC_RB(n) (SAM_TCN_BASE(n)+SAM_TCN_RB_OFFSET) @@ -92,9 +102,16 @@ #define SAM_TC_IER(n) (SAM_TCN_BASE(n)+SAM_TCN_IER_OFFSET) #define SAM_TC_IDR(n) (SAM_TCN_BASE(n)+SAM_TCN_IDR_OFFSET) #define SAM_TC_IMR(n) (SAM_TCN_BASE(n)+SAM_TCN_IMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TCN_FMR(n) (SAM_TCN_BASE(n)+SAM_TCN_FMR_OFFSET) +# define SAM_TCN_WPMR(n) (SAM_TCN_BASE(n)+SAM_TCN_WPMR_OFFSET) +#endif #define SAM_TC0_CCR (SAM_TC0_BASE+SAM_TCN_CCR_OFFSET) #define SAM_TC0_CMR (SAM_TC0_BASE+SAM_TCN_CMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TC0_SMMR (SAM_TC0_BASE+SAM_TCN_SMMR_OFFSET) +#endif #define SAM_TC0_CV (SAM_TC0_BASE+SAM_TCN_CV_OFFSET) #define SAM_TC0_RA (SAM_TC0_BASE+SAM_TCN_RA_OFFSET) #define SAM_TC0_RB (SAM_TC0_BASE+SAM_TCN_RB_OFFSET) @@ -103,9 +120,16 @@ #define SAM_TC0_IER (SAM_TC0_BASE+SAM_TCN_IER_OFFSET) #define SAM_TC0_IDR (SAM_TC0_BASE+SAM_TCN_IDR_OFFSET) #define SAM_TC0_IMR (SAM_TC0_BASE+SAM_TCN_IMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TC0_FMR (SAM_TC0_BASE+SAM_TCN_FMR_OFFSET) +# define SAM_TC0_WPMR (SAM_TC0_BASE+SAM_TCN_WPMR_OFFSET) +#endif #define SAM_TC1_CCR (SAM_TC1_BASE+SAM_TCN_CCR_OFFSET) #define SAM_TC1_CMR (SAM_TC1_BASE+SAM_TCN_CMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TC1_SMMR (SAM_TC1_BASE+SAM_TCN_SMMR_OFFSET) +#endif #define SAM_TC1_CV (SAM_TC1_BASE+SAM_TCN_CV_OFFSET) #define SAM_TC1_RA (SAM_TC1_BASE+SAM_TCN_RA_OFFSET) #define SAM_TC1_RB (SAM_TC1_BASE+SAM_TCN_RB_OFFSET) @@ -114,9 +138,16 @@ #define SAM_TC1_IER (SAM_TC1_BASE+SAM_TCN_IER_OFFSET) #define SAM_TC1_IDR (SAM_TC1_BASE+SAM_TCN_IDR_OFFSET) #define SAM_TC1_IMR (SAM_TC1_BASE+SAM_TCN_IMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TC1_FMR (SAM_TC1_BASE+SAM_TCN_FMR_OFFSET) +# define SAM_TC1_WPMR (SAM_TC1_BASE+SAM_TCN_WPMR_OFFSET) +#endif #define SAM_TC2_CCR (SAM_TC2_BASE+SAM_TCN_CCR_OFFSET) #define SAM_TC2_CMR (SAM_TC2_BASE+SAM_TCN_CMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TC2_SMMR (SAM_TC2_BASE+SAM_TCN_SMMR_OFFSET) +#endif #define SAM_TC2_CV (SAM_TC2_BASE+SAM_TCN_CV_OFFSET) #define SAM_TC2_RA (SAM_TC2_BASE+SAM_TCN_RA_OFFSET) #define SAM_TC2_RB (SAM_TC2_BASE+SAM_TCN_RB_OFFSET) @@ -125,6 +156,64 @@ #define SAM_TC2_IER (SAM_TC2_BASE+SAM_TCN_IER_OFFSET) #define SAM_TC2_IDR (SAM_TC2_BASE+SAM_TCN_IDR_OFFSET) #define SAM_TC2_IMR (SAM_TC2_BASE+SAM_TCN_IMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TC2_FMR (SAM_TC2_BASE+SAM_TCN_FMR_OFFSET) +# define SAM_TC2_WPMR (SAM_TC2_BASE+SAM_TCN_WPMR_OFFSET) +#endif + +#define SAM_TC3_CCR (SAM_TC3_BASE+SAM_TCN_CCR_OFFSET) +#define SAM_TC3_CMR (SAM_TC3_BASE+SAM_TCN_CMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TC3_SMMR (SAM_TC3_BASE+SAM_TCN_SMMR_OFFSET) +#endif +#define SAM_TC3_CV (SAM_TC3_BASE+SAM_TCN_CV_OFFSET) +#define SAM_TC3_RA (SAM_TC3_BASE+SAM_TCN_RA_OFFSET) +#define SAM_TC3_RB (SAM_TC3_BASE+SAM_TCN_RB_OFFSET) +#define SAM_TC3_RC (SAM_TC3_BASE+SAM_TCN_RC_OFFSET) +#define SAM_TC3_SR (SAM_TC3_BASE+SAM_TCN_SR_OFFSET) +#define SAM_TC3_IER (SAM_TC3_BASE+SAM_TCN_IER_OFFSET) +#define SAM_TC3_IDR (SAM_TC3_BASE+SAM_TCN_IDR_OFFSET) +#define SAM_TC3_IMR (SAM_TC3_BASE+SAM_TCN_IMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TC3_FMR (SAM_TC3_BASE+SAM_TCN_FMR_OFFSET) +# define SAM_TC3_WPMR (SAM_TC3_BASE+SAM_TCN_WPMR_OFFSET) +#endif + +#define SAM_TC4_CCR (SAM_TC4_BASE+SAM_TCN_CCR_OFFSET) +#define SAM_TC4_CMR (SAM_TC4_BASE+SAM_TCN_CMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TC4_SMMR (SAM_TC4_BASE+SAM_TCN_SMMR_OFFSET) +#endif +#define SAM_TC4_CV (SAM_TC4_BASE+SAM_TCN_CV_OFFSET) +#define SAM_TC4_RA (SAM_TC4_BASE+SAM_TCN_RA_OFFSET) +#define SAM_TC4_RB (SAM_TC4_BASE+SAM_TCN_RB_OFFSET) +#define SAM_TC4_RC (SAM_TC4_BASE+SAM_TCN_RC_OFFSET) +#define SAM_TC4_SR (SAM_TC4_BASE+SAM_TCN_SR_OFFSET) +#define SAM_TC4_IER (SAM_TC4_BASE+SAM_TCN_IER_OFFSET) +#define SAM_TC4_IDR (SAM_TC4_BASE+SAM_TCN_IDR_OFFSET) +#define SAM_TC4_IMR (SAM_TC4_BASE+SAM_TCN_IMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TC4_FMR (SAM_TC4_BASE+SAM_TCN_FMR_OFFSET) +# define SAM_TC4_WPMR (SAM_TC4_BASE+SAM_TCN_WPMR_OFFSET) +#endif + +#define SAM_TC5_CCR (SAM_TC5_BASE+SAM_TCN_CCR_OFFSET) +#define SAM_TC5_CMR (SAM_TC5_BASE+SAM_TCN_CMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TC5_SMMR (SAM_TC5_BASE+SAM_TCN_SMMR_OFFSET) +#endif +#define SAM_TC5_CV (SAM_TC5_BASE+SAM_TCN_CV_OFFSET) +#define SAM_TC5_RA (SAM_TC5_BASE+SAM_TCN_RA_OFFSET) +#define SAM_TC5_RB (SAM_TC5_BASE+SAM_TCN_RB_OFFSET) +#define SAM_TC5_RC (SAM_TC5_BASE+SAM_TCN_RC_OFFSET) +#define SAM_TC5_SR (SAM_TC5_BASE+SAM_TCN_SR_OFFSET) +#define SAM_TC5_IER (SAM_TC5_BASE+SAM_TCN_IER_OFFSET) +#define SAM_TC5_IDR (SAM_TC5_BASE+SAM_TCN_IDR_OFFSET) +#define SAM_TC5_IMR (SAM_TC5_BASE+SAM_TCN_IMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_TC5_FMR (SAM_TC5_BASE+SAM_TCN_FMR_OFFSET) +# define SAM_TC5_WPMR (SAM_TC5_BASE+SAM_TCN_WPMR_OFFSET) +#endif /* Timer common registers */ @@ -308,6 +397,12 @@ # define TCN_CMR_BSWTRG_CLEAR (2 << TCN_CMR_BSWTRG_SHIFT) # define TCN_CMR_BSWTRG_TOGGLE (3 << TCN_CMR_BSWTRG_SHIFT) +/* Stepper Motor Mode Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# warning SAM4S not yet integrated +#endif + /* TC Counter Value Register */ #define TCN_CV_SHIFT (0) /* Bits 0-15: Counter Value */ @@ -332,6 +427,18 @@ #define TCN_SR_MTIOA (1 << 17) /* Bit 17: TIOA Mirror (SR only) */ #define TCN_SR_MTIOB (1 << 18) /* Bit 18: TIOB Mirror (SR only)*/ +/* Fault Mode Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# warning SAM4S not yet integrated +#endif + +/* Write Protect Mode Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# warning SAM4S not yet integrated +#endif + /************************************************************************************************ * Public Types ************************************************************************************************/ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_twi.h b/nuttx/arch/arm/src/sam34/chip/sam_twi.h index 056f1062e..091e98f34 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_twi.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_twi.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam_twi.h + * Two-wire Interface (TWI) definitions for the SAM3U and SAM4S * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -125,13 +126,13 @@ # define TWI_MMR_IADRSZ_3BYTE (2 << TWI_MMR_IADRSZ_SHIFT) /* Two-byte internal device address */ # define TWI_MMR_IADRSZ_3BYTE (3 << TWI_MMR_IADRSZ_SHIFT) /* Three-byte internal device address */ #define TWI_MMR_MREAD (1 << 12) /* Bit 12: Master Read Direction */ -#define TWI_MMR_DADR_SHIFT (16) /* Bits 16-23: Device Address */ -#define TWI_MMR_DADR_MASK (0xff << TWI_MMR_DADR_SHIFT) +#define TWI_MMR_DADR_SHIFT (16) /* Bits 16-22: Device Address */ +#define TWI_MMR_DADR_MASK (0x7f << TWI_MMR_DADR_SHIFT) /* TWI Slave Mode Register */ -#define TWI_SMR_SADR_SHIFT (16) /* Bits 16-23: Slave Address */ -#define TWI_SMR_SADR_MASK (0xff << TWI_SMR_SADR_SHIFT) +#define TWI_SMR_SADR_SHIFT (16) /* Bits 16-22: Slave Address */ +#define TWI_SMR_SADR_MASK (0x7f << TWI_SMR_SADR_SHIFT) /* TWI Internal Address Register */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_uart.h b/nuttx/arch/arm/src/sam34/chip/sam_uart.h deleted file mode 100644 index 4825435fd..000000000 --- a/nuttx/arch/arm/src/sam34/chip/sam_uart.h +++ /dev/null @@ -1,391 +0,0 @@ -/************************************************************************************************ - * arch/arm/src/sam34/chip/sam_uart.h - * - * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <gnutt@nuttx.org> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_UART_H -#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_UART_H - -/************************************************************************************************ - * Included Files - ************************************************************************************************/ - -#include <nuttx/config.h> - -#include "chip.h" -#include "chip/sam_memorymap.h" - -/************************************************************************************************ - * Pre-processor Definitions - ************************************************************************************************/ - -/* UART register offsets ************************************************************************/ - -#define SAM_UART_CR_OFFSET 0x0000 /* Control Register (Common) */ -#define SAM_UART_MR_OFFSET 0x0004 /* Mode Register (Common) */ -#define SAM_UART_IER_OFFSET 0x0008 /* Interrupt Enable Register (Common) */ -#define SAM_UART_IDR_OFFSET 0x000c /* Interrupt Disable Register (Common) */ -#define SAM_UART_IMR_OFFSET 0x0010 /* Interrupt Mask Register (Common) */ -#define SAM_UART_SR_OFFSET 0x0014 /* Status Register (Common) */ -#define SAM_UART_RHR_OFFSET 0x0018 /* Receive Holding Register (Common) */ -#define SAM_UART_THR_OFFSET 0x001c /* Transmit Holding Register (Common) */ -#define SAM_UART_BRGR_OFFSET 0x0020 /* Baud Rate Generator Register (Common) */ - /* 0x0024-0x003c: Reserved (UART) */ -#define SAM_USART_RTOR_OFFSET 0x0024 /* Receiver Time-out Register (USART only) */ -#define SAM_USART_TTGR_OFFSET 0x0028 /* Transmitter Timeguard Register (USART only) */ - /* 0x002c-0x003c: Reserved (UART) */ -#define SAM_USART_FIDI_OFFSET 0x0040 /* FI DI Ratio Register (USART only) */ -#define SAM_USART_NER_OFFSET 0x0044 /* Number of Errors Register ((USART only) */ - /* 0x0048: Reserved (USART) */ -#define SAM_USART_IF_OFFSET 0x004c /* IrDA Filter Register (USART only) */ -#define SAM_USART_MAN_OFFSET 0x0050 /* Manchester Encoder Decoder Register (USART only) */ -#define SAM_USART_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register (USART only) */ -#define SAM_USART_WPSR_OFFSET 0x00e8 /* Write Protect Status Register (USART only) */ - /* 0x005c-0xf008: Reserved (USART) */ -#define SAM_USART_VERSION_OFFSET 0x00fc /* Version Register (USART only) */ - /* 0x0100-0x0124: PDC Area (Common) */ - -/* UART register adresses ***********************************************************************/ - -#define SAM_UART_CR (SAM_UART_BASE+SAM_UART_CR_OFFSET) -#define SAM_UART_MR (SAM_UART_BASE+SAM_UART_MR_OFFSET) -#define SAM_UART_IER (SAM_UART_BASE+SAM_UART_IER_OFFSET) -#define SAM_UART_IDR (SAM_UART_BASE+SAM_UART_IDR_OFFSET) -#define SAM_UART_IMR (SAM_UART_BASE+SAM_UART_IMR_OFFSET) -#define SAM_UART_SR (SAM_UART_BASE+SAM_UART_SR_OFFSET) -#define SAM_UART_RHR (SAM_UART_BASE+SAM_UART_RHR_OFFSET) -#define SAM_UART_THR (SAM_UART_BASE+SAM_UART_THR_OFFSET) -#define SAM_UART_BRGR (SAM_UART_BASE+SAM_UART_BRGR_OFFSET) - -#define SAM_USART_CR(n) (SAM_USARTN_BASE(n)+SAM_UART_CR_OFFSET) -#define SAM_USART_MR(n) (SAM_USARTN_BASE(n)+SAM_UART_MR_OFFSET) -#define SAM_USART_IER(n) (SAM_USARTN_BASE(n)+SAM_UART_IER_OFFSET) -#define SAM_USART_IDR(n) (SAM_USARTN_BASE(n)+SAM_UART_IDR_OFFSET) -#define SAM_USART_IMR(n) (SAM_USARTN_BASE(n)+SAM_UART_IMR_OFFSET) -#define SAM_USART_SR(n) (SAM_USARTN_BASE(n)+SAM_UART_SR_OFFSET) -#define SAM_USART_RHR(n) (SAM_USARTN_BASE(n)+SAM_UART_RHR_OFFSET) -#define SAM_USART_THR(n) (SAM_USARTN_BASE(n)+SAM_UART_THR_OFFSET) -#define SAM_USART_BRGR(n) (SAM_USARTN_BASE(n)+SAM_UART_BRGR_OFFSET) -#define SAM_USART_RTOR(n) (SAM_USARTN_BASE(n)+SAM_USART_RTOR_OFFSET) -#define SAM_USART_TTGR(n) (SAM_USARTN_BASE(n)+SAM_USART_TTGR_OFFSET) -#define SAM_USART_FIDI(n) (SAM_USARTN_BASE(n)+SAM_USART_FIDI_OFFSET) -#define SAM_USART_NER(n) (SAM_USARTN_BASE(n)+SAM_USART_NER_OFFSET) -#define SAM_USART_IF(n) (SAM_USARTN_BASE(n)+SAM_USART_IF_OFFSET) -#define SAM_USART_MAN(n) (SAM_USARTN_BASE(n)+SAM_USART_MAN_OFFSET) -#define SAM_USART_WPMR(n) (SAM_USARTN_BASE(n)+SAM_USART_WPMR_OFFSET) -#define SAM_USART_WPSR(n) (SAM_USARTN_BASE(n)+SAM_USART_WPSR_OFFSET) -#define SAM_USART_VERSION(n) (SAM_USARTN_BASE(n)+SAM_USART_VERSION_OFFSET) - -#define SAM_USART0_CR (SAM_USART0_BASE+SAM_UART_CR_OFFSET) -#define SAM_USART0_MR_ (SAM_USART0_BASE+SAM_UART_MR_OFFSET) -#define SAM_USART0_IER (SAM_USART0_BASE+SAM_UART_IER_OFFSET) -#define SAM_USART0_IDR (SAM_USART0_BASE+SAM_UART_IDR_OFFSET) -#define SAM_USART0_IMR (SAM_USART0_BASE+SAM_UART_IMR_OFFSET) -#define SAM_USART0_SR (SAM_USART0_BASE+SAM_UART_SR_OFFSET) -#define SAM_USART0_RHR (SAM_USART0_BASE+SAM_UART_RHR_OFFSET) -#define SAM_USART0_THR (SAM_USART0_BASE+SAM_UART_THR_OFFSET) -#define SAM_USART0_BRGR (SAM_USART0_BASE+SAM_UART_BRGR_OFFSET) -#define SAM_USART0_RTOR (SAM_USART0_BASE+SAM_USART_RTOR_OFFSET) -#define SAM_USART0_TTGR (SAM_USART0_BASE+SAM_USART_TTGR_OFFSET) -#define SAM_USART0_FIDI (SAM_USART0_BASE+SAM_USART_FIDI_OFFSET) -#define SAM_USART0_NER (SAM_USART0_BASE+SAM_USART_NER_OFFSET) -#define SAM_USART0_IF (SAM_USART0_BASE+SAM_USART_IF_OFFSET) -#define SAM_USART0_MAN (SAM_USART0_BASE+SAM_USART_MAN_OFFSET) -#define SAM_USART0_WPMR (SAM_USART0_BASE+SAM_USART_WPMR_OFFSET) -#define SAM_USART0_WPSR (SAM_USART0_BASE+SAM_USART_WPSR_OFFSET) -#define SAM_USART0_VERSION (SAM_USART0_BASE+SAM_USART_VERSION_OFFSET) - -#define SAM_USART1_CR (SAM_USART1_BASE+SAM_UART_CR_OFFSET) -#define SAM_USART1_MR_ (SAM_USART1_BASE+SAM_UART_MR_OFFSET) -#define SAM_USART1_IER (SAM_USART1_BASE+SAM_UART_IER_OFFSET) -#define SAM_USART1_IDR (SAM_USART1_BASE+SAM_UART_IDR_OFFSET) -#define SAM_USART1_IMR (SAM_USART1_BASE+SAM_UART_IMR_OFFSET) -#define SAM_USART1_SR (SAM_USART1_BASE+SAM_UART_SR_OFFSET) -#define SAM_USART1_RHR (SAM_USART1_BASE+SAM_UART_RHR_OFFSET) -#define SAM_USART1_THR (SAM_USART1_BASE+SAM_UART_THR_OFFSET) -#define SAM_USART1_BRGR (SAM_USART1_BASE+SAM_UART_BRGR_OFFSET) -#define SAM_USART1_RTOR (SAM_USART1_BASE+SAM_USART_RTOR_OFFSET) -#define SAM_USART1_TTGR (SAM_USART1_BASE+SAM_USART_TTGR_OFFSET) -#define SAM_USART1_FIDI (SAM_USART1_BASE+SAM_USART_FIDI_OFFSET) -#define SAM_USART1_NER (SAM_USART1_BASE+SAM_USART_NER_OFFSET) -#define SAM_USART1_IF (SAM_USART1_BASE+SAM_USART_IF_OFFSET) -#define SAM_USART1_MAN (SAM_USART1_BASE+SAM_USART_MAN_OFFSET) -#define SAM_USART1_WPMR (SAM_USART1_BASE+SAM_USART_WPMR_OFFSET) -#define SAM_USART1_WPSR (SAM_USART1_BASE+SAM_USART_WPSR_OFFSET) -#define SAM_USART1_VERSION (SAM_USART1_BASE+SAM_USART_VERSION_OFFSET) - -#define SAM_USART2_CR (SAM_USART2_BASE+SAM_UART_CR_OFFSET) -#define SAM_USART2_MR_ (SAM_USART2_BASE+SAM_UART_MR_OFFSET) -#define SAM_USART2_IER (SAM_USART2_BASE+SAM_UART_IER_OFFSET) -#define SAM_USART2_IDR (SAM_USART2_BASE+SAM_UART_IDR_OFFSET) -#define SAM_USART2_IMR (SAM_USART2_BASE+SAM_UART_IMR_OFFSET) -#define SAM_USART2_SR (SAM_USART2_BASE+SAM_UART_SR_OFFSET) -#define SAM_USART2_RHR (SAM_USART2_BASE+SAM_UART_RHR_OFFSET) -#define SAM_USART2_THR (SAM_USART2_BASE+SAM_UART_THR_OFFSET) -#define SAM_USART2_BRGR (SAM_USART2_BASE+SAM_UART_BRGR_OFFSET) -#define SAM_USART2_RTOR (SAM_USART2_BASE+SAM_USART_RTOR_OFFSET) -#define SAM_USART2_TTGR (SAM_USART2_BASE+SAM_USART_TTGR_OFFSET) -#define SAM_USART2_FIDI (SAM_USART2_BASE+SAM_USART_FIDI_OFFSET) -#define SAM_USART2_NER (SAM_USART2_BASE+SAM_USART_NER_OFFSET) -#define SAM_USART2_IF (SAM_USART2_BASE+SAM_USART_IF_OFFSET) -#define SAM_USART2_MAN (SAM_USART2_BASE+SAM_USART_MAN_OFFSET) -#define SAM_USART2_WPMR (SAM_USART2_BASE+SAM_USART_WPMR_OFFSET) -#define SAM_USART2_WPSR (SAM_USART2_BASE+SAM_USART_WPSR_OFFSET) -#define SAM_USART2_VERSION (SAM_USART2_BASE+SAM_USART_VERSION_OFFSET) - -#define SAM_USART3_CR (SAM_USART3_BASE+SAM_UART_CR_OFFSET) -#define SAM_USART3_MR_ (SAM_USART3_BASE+SAM_UART_MR_OFFSET) -#define SAM_USART3_IER (SAM_USART3_BASE+SAM_UART_IER_OFFSET) -#define SAM_USART3_IDR (SAM_USART3_BASE+SAM_UART_IDR_OFFSET) -#define SAM_USART3_IMR (SAM_USART3_BASE+SAM_UART_IMR_OFFSET) -#define SAM_USART3_SR (SAM_USART3_BASE+SAM_UART_SR_OFFSET) -#define SAM_USART3_RHR (SAM_USART3_BASE+SAM_UART_RHR_OFFSET) -#define SAM_USART3_THR (SAM_USART3_BASE+SAM_UART_THR_OFFSET) -#define SAM_USART3_BRGR (SAM_USART3_BASE+SAM_UART_BRGR_OFFSET) -#define SAM_USART3_RTOR (SAM_USART3_BASE+SAM_USART_RTOR_OFFSET) -#define SAM_USART3_TTGR (SAM_USART3_BASE+SAM_USART_TTGR_OFFSET) -#define SAM_USART3_FIDI (SAM_USART3_BASE+SAM_USART_FIDI_OFFSET) -#define SAM_USART3_NER (SAM_USART3_BASE+SAM_USART_NER_OFFSET) -#define SAM_USART3_IF (SAM_USART3_BASE+SAM_USART_IF_OFFSET) -#define SAM_USART3_MAN (SAM_USART3_BASE+SAM_USART_MAN_OFFSET) -#define SAM_USART3_WPMR (SAM_USART3_BASE+SAM_USART_WPMR_OFFSET) -#define SAM_USART3_WPSR (SAM_USART3_BASE+SAM_USART_WPSR_OFFSET) -#define SAM_USART3_VERSION (SAM_USART3_BASE+SAM_USART_VERSION_OFFSET) - -/* UART register bit definitions ****************************************************************/ - -/* UART Control Register */ - -#define UART_CR_RSTRX (1 << 2) /* Bit 2: Reset Receiver (Common) */ -#define UART_CR_RSTTX (1 << 3) /* Bit 3: Reset Transmitter (Common) */ -#define UART_CR_RXEN (1 << 4) /* Bit 4: Receiver Enable (Common) */ -#define UART_CR_RXDIS (1 << 5) /* Bit 5: Receiver Disable (Common) */ -#define UART_CR_TXEN (1 << 6) /* Bit 6: Transmitter Enable (Common) */ -#define UART_CR_TXDIS (1 << 7) /* Bit 7: Transmitter Disable (Common) */ -#define UART_CR_RSTSTA (1 << 8) /* Bit 8: Reset Status Bits (Common) */ -#define USART_CR_STTBRK (1 << 9) /* Bit 9: Start Break (USART only) */ -#define USART_CR_STPBRK (1 << 10) /* Bit 10: Stop Break (USART only) */ -#define USART_CR_STTTO (1 << 11) /* Bit 11: Start Time-out (USART only) */ -#define USART_CR_SENDA (1 << 12) /* Bit 12: Send Address (USART only) */ -#define USART_CR_RSTIT (1 << 13) /* Bit 13: Reset Iterations (USART only) */ -#define USART_CR_RSTNACK (1 << 14) /* Bit 14: Reset Non Acknowledge (USART only) */ -#define USART_CR_RETTO (1 << 15) /* Bit 15: Rearm Time-out (USART only) */ -#define USART_CR_RTSEN (1 << 18) /* Bit 18: Request to Send Enable (USART only) */ -#define USART_CR_FCS (1 << 18) /* Bit 18: Force SPI Chip Select (USART only) */ -#define USART_CR_RTSDIS (1 << 19) /* Bit 19: Request to Send Disable (USART only) */ -#define USART_CR_RCS (1 << 19) /* Bit 19: Release SPI Chip Select (USART only) */ - -/* UART Mode Register */ - -#define USART_MR_MODE_SHIFT (0) /* Bits 0-3: (USART only) */ -#define USART_MR_MODE_MASK (15 << USART_MR_MODE_SHIFT) -# define USART_MR_MODE_NORMAL (0 << USART_MR_MODE_SHIFT) /* Normal */ -# define USART_MR_MODE_RS485 (1 << USART_MR_MODE_SHIFT) /* RS485 */ -# define USART_MR_MODE_HWHS (2 << USART_MR_MODE_SHIFT) /* Hardware Handshaking */ -# define USART_MR_MODE_ISO7816_0 (4 << USART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 0 */ -# define USART_MR_MODE_ISO7816_1 (6 << USART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 1 */ -# define USART_MR_MODE_IRDA (8 << USART_MR_MODE_SHIFT) /* IrDA */ -# define USART_MR_MODE_SPIMSTR (14 << USART_MR_MODE_SHIFT) /* SPI Master */ -# define USART_MR_MODE_SPISLV (15 << USART_MR_MODE_SHIFT) /* SPI Slave */ -#define USART_MR_USCLKS_SHIFT (4) /* Bits 4-5: Clock Selection (USART only) */ -#define USART_MR_USCLKS_MASK (3 << USART_MR_USCLKS_SHIFT) -# define USART_MR_USCLKS_MCK (0 << USART_MR_USCLKS_SHIFT) /* MCK */ -# define USART_MR_USCLKS_MCKDIV (1 << USART_MR_USCLKS_SHIFT) /* MCK/DIV (DIV = 8) */ -# define USART_MR_USCLKS_SCK (3 << USART_MR_USCLKS_SHIFT) /* SCK */ -#define USART_MR_CHRL_SHIFT (6) /* Bits 6-7: Character Length (USART only) */ -#define USART_MR_CHRL_MASK (3 << USART_MR_CHRL_SHIFT) -# define USART_MR_CHRL_5BITS (0 << USART_MR_CHRL_SHIFT) /* 5 bits */ -# define USART_MR_CHRL_6BITS (1 << USART_MR_CHRL_SHIFT) /* 6 bits */ -# define USART_MR_CHRL_7BITS (2 << USART_MR_CHRL_SHIFT) /* 7 bits */ -# define USART_MR_CHRL_8BITS (3 << USART_MR_CHRL_SHIFT) /* 8 bits */ -#define USART_MR_YNC (1 << 8) /* Bit 8: Synchronous Mode Select (USART only) */ -#define USART_MR_CPHA (1 << 8) /* Bit 8: SPI Clock Phase (USART only) */ -#define UART_MR_PAR_SHIFT (9) /* Bits 9-11: Parity Type (Common) */ -#define UART_MR_PAR_MASK (7 << UART_MR_PAR_SHIFT) -# define UART_MR_PAR_EVEN (0 << UART_MR_PAR_SHIFT) /* Even parity (Common) */ -# define UART_MR_PAR_ODD (1 << UART_MR_PAR_SHIFT) /* Odd parity (Common) */ -# define UART_MR_PAR_SPACE (2 << UART_MR_PAR_SHIFT) /* Space: parity forced to 0 (Common) */ -# define UART_MR_PAR_MARK (3 << UART_MR_PAR_SHIFT) /* Mark: parity forced to 1 (Common) */ -# define UART_MR_PAR_NONE (4 << UART_MR_PAR_SHIFT) /* No parity (Common) */ -# define UART_MR_PAR_MULTIDROP (6 << UART_MR_PAR_SHIFT) /* Multidrop mode (USART only) */ -#define USART_MR_NBSTOP_SHIFT (12) /* Bits 12-13: Number of Stop Bits (USART only) */ -#define USART_MR_NBSTOP_MASK (3 << USART_MR_NBSTOP_SHIFT) -# define USART_MR_NBSTOP_1 (0 << USART_MR_NBSTOP_SHIFT) /* 1 stop bit 1 stop bit */ -# define USART_MR_NBSTOP_1p5 (1 << USART_MR_NBSTOP_SHIFT) /* 1.5 stop bits */ -# define USART_MR_NBSTOP_2 (2 << USART_MR_NBSTOP_SHIFT) /* 2 stop bits 2 stop bits */ -#define UART_MR_CHMODE_SHIFT (14) /* Bits 14-15: Channel Mode (Common) */ -#define UART_MR_CHMODE_MASK (3 << UART_MR_CHMODE_SHIFT) -# define UART_MR_CHMODE_NORMAL (0 << UART_MR_CHMODE_SHIFT) /* Normal Mode */ -# define UART_MR_CHMODE_ECHO (1 << UART_MR_CHMODE_SHIFT) /* Automatic Echo */ -# define UART_MR_CHMODE_LLPBK (2 << UART_MR_CHMODE_SHIFT) /* Local Loopback */ -# define UART_MR_CHMODE_RLPBK (3 << UART_MR_CHMODE_SHIFT) /* Remote Loopback */ -#define USART_MR_MSBF (1 << 16) /* Bit 16: Bit Order or SPI Clock Polarity (USART only) */ -#define USART_MR_CPOL (1 << 16) -#define USART_MR_MODE9 (1 << 17) /* Bit 17: 9-bit Character Length (USART only) */ -#define USART_MR_CLKO (1 << 18) /* Bit 18: Clock Output Select (USART only) */ -#define USART_MR_OVER (1 << 19) /* Bit 19: Oversampling Mode (USART only) */ -#define USART_MR_INACK (1 << 20) /* Bit 20: Inhibit Non Acknowledge (USART only) */ -#define USART_MR_DSNACK (1 << 21) /* Bit 21: Disable Successive NACK (USART only) */ -#define USART_MR_VARSYNC (1 << 22) /* Bit 22: Variable Synchronization of Command/Data Sync Start Frame Delimiter (USART only) */ -#define USART_MR_INVDATA (1 << 23) /* Bit 23: INverted Data (USART only) */ -#define USART_MR_MAXITER_SHIFT (24) /* Bits 24-26: Max iterations (ISO7816 T=0 (USART only) */ -#define USART_MR_MAXITER_MASK (7 << USART_MR_MAXITER_SHIFT) -#define USART_MR_FILTER (1 << 28) /* Bit 28: Infrared Receive Line Filter (USART only) */ -#define USART_MR_MAN (1 << 29) /* Bit 29: Manchester Encoder/Decoder Enable (USART only) */ -#define USART_MR_MODSYNC (1 << 30) /* Bit 30: Manchester Synchronization Mode (USART only) */ -#define USART_MR_ONEBIT (1 << 31) /* Bit 31: Start Frame Delimiter Selector (USART only) */ - -/* UART Interrupt Enable Register, UART Interrupt Disable Register, UART Interrupt Mask - * Register, and UART Status Register common bit field definitions - */ - -#define UART_INT_RXRDY (1 << 0) /* Bit 0: RXRDY Interrupt (Common) */ -#define UART_INT_TXRDY (1 << 1) /* Bit 1: TXRDY Interrupt (Common) */ -#define UART_INT_RXBRK (1 << 2) /* Bit 2: Break Received/End of Break */ -#define UART_INT_ENDRX (1 << 3) /* Bit 3: End of Receive Transfer Interrupt (Common) */ -#define UART_INT_ENDTX (1 << 4) /* Bit 4: End of Transmit Interrupt (Common) */ -#define UART_INT_OVRE (1 << 5) /* Bit 5: Overrun Error Interrupt (Common) */ -#define UART_INT_FRAME (1 << 6) /* Bit 6: Framing Error Interrupt (Common) */ -#define UART_INT_PARE (1 << 7) /* Bit 7: Parity Error Interrupt (Common) */ -#define USART_INT_TIMEOUT (1 << 8) /* Bit 8: Time-out Interrupt (USART only) */ -#define UART_INT_TXEMPTY (1 << 9) /* Bit 9: TXEMPTY Interrupt (Common) */ -#define USART_INT_ITER (1 << 10) /* Bit 10: Iteration Interrupt (USART only) */ -#define USART_INT_UNRE (1 << 10) /* Bit 10: SPI Underrun Error Interrupt (USART only) */ -#define UART_INT_TXBUFE (1 << 11) /* Bit 11: Buffer Empty Interrupt (Common) */ -#define UART_INT_RXBUFF (1 << 12) /* Bit 12: Buffer Full Interrupt (Common) */ -#define USART_INT_NACK (1 << 13) /* Bit 13: Non Acknowledge Interrupt (USART only) */ -#define USART_INT_CTSIC (1 << 19) /* Bit 19: Clear to Send Input Change Interrupt (USART only) */ -#define USART_INT_MANE (1 << 24) /* Bit 24: Manchester Error Interrupt (USART only) */ - -/* UART Receiver Holding Register */ - -#define UART_RHR_RXCHR_SHIFT (0) /* Bits 0-7: Received Character (UART only) */ -#define UART_RHR_RXCHR_MASK (0xff << UART_RHR_RXCHR_SHIFT) -#define USART_RHR_RXCHR_SHIFT (0) /* Bits 0-8: Received Character (USART only) */ -#define USART_RHR_RXCHR_MASK (0x1ff << UART_RHR_RXCHR_SHIFT) -#define USART_RHR_RXSYNH (1 << 15) /* Bit 15: Received Sync (USART only) */ - -/* UART Transmit Holding Register */ - -#define UART_THR_TXCHR_SHIFT (0) /* Bits 0-7: Character to be Transmitted (UART only) */ -#define UART_THR_TXCHR_MASK (0xff << UART_THR_TXCHR_SHIFT) -#define USART_THR_TXCHR_SHIFT (0) /* Bits 0-8: Character to be Transmitted (USART only) */ -#define USART_THR_TXCHR_MASK (0x1ff << USART_THR_TXCHR_SHIFT) -#define USART_THR_TXSYNH (1 << 15) /* Bit 15: Sync Field to be tran (USART only) */ - -/* UART Baud Rate Generator Register */ - -#define UART_BRGR_CD_SHIFT (0) /* Bits 0-15: Clock Divisor (Common) */ -#define UART_BRGR_CD_MASK (0xffff << UART_BRGR_CD_SHIFT) -#define UART_BRGR_FP_SHIFT (16) /* Bits 16-18: Fractional Part (USART only) */ -#define UART_BRGR_FP_MASK (7 << UART_BRGR_FP_SHIFT) - -/* USART Receiver Time-out Register (USART only) */ - -#define USART_RTOR_TO_SHIFT (0) /* Bits 0-15: Time-out Value (USART only) */ -#define USART_RTOR_TO_MASK (0xffff << USART_RTOR_TO_SHIFT) - -/* USART Transmitter Timeguard Register (USART only) */ - -#define USART_TTGR_TG_SHIFT (0) /* Bits 0-7: Timeguard Value (USART only) */ -#define USART_TTGR_TG_MASK (0xff << USART_TTGR_TG_SHIFT) - -/* USART FI DI RATIO Register (USART only) */ - -#define USART_FIDI_RATIO_SHIFT (0) /* Bits 0-10: FI Over DI Ratio Value (USART only) */ -#define USART_FIDI_RATIO_MASK (0x7ff << USART_FIDI_RATIO_SHIFT) - -/* USART Number of Errors Register (USART only) */ - -#define USART_NER_NBERRORS_SHIFT (0) /* Bits 0-7: Number of Errrors (USART only) */ -#define USART_NER_NBERRORS_MASK (0xff << USART_NER_NBERRORS_SHIFT) - -/* USART IrDA FILTER Register (USART only) */ - -#define USART_IF_IRDAFILTER_SHIFT (0) /* Bits 0-7: IrDA Filter (USART only) */ -#define USART_IF_IRDAFILTER_MASK (0xff << USART_IF_IRDAFILTER_SHIFT) - -/* USART Manchester Configuration Register (USART only) */ - -#define USART_MAN_TXPL_SHIFT (0) /* Bits 0-3: Transmitter Preamble Length (USART only) */ -#define USART_MAN_TXPL_MASK (15 << USART_MAN_TXPL_SHIFT) -#define USART_MAN_TXPP_SHIFT (8) /* Bits 8-9: Transmitter Preamble Pattern (USART only) */ -#define USART_MAN_TXPP_MASK (3 << USART_MAN_TXPP_SHIFT) -# define USART_MAN_TXPP_ALLONE (0 << USART_MAN_TXPP_SHIFT) /* ALL_ONE */ -# define USART_MAN_TXPP_ALLZERO (1 << USART_MAN_TXPP_SHIFT) /* ALL_ZERO */ -# define USART_MAN_TXPP_ZEROONE (2 << USART_MAN_TXPP_SHIFT) /* ZERO_ONE */ -# define USART_MAN_TXPP_ONEZERO (3 << USART_MAN_TXPP_SHIFT) /* ONE_ZERO */ -#define USART_MAN_TXMPOL (1 << 12) /* Bit 12: Transmitter Manchester Polarity (USART only) */ -#define USART_MAN_RXPL_SHIFT (16) /* Bits 16-19: Receiver Preamble Length (USART only) */ -#define USART_MAN_RXPL_MASK (15 << USART_MAN_RXPL_SHIFT) -#define USART_MAN_RXPP_SHIFT (24) /* Bits 24-25: Receiver Preamble Pattern detected (USART only) */ -#define USART_MAN_RXPP_MASK (3 << USART_MAN_RXPP_SHIFT) -# define USART_MAN_RXPP_ALLONE (0 << USART_MAN_RXPP_SHIFT) /* ALL_ONE */ -# define USART_MAN_RXPP_ALLZERO (1 << USART_MAN_RXPP_SHIFT) /* ALL_ZERO */ -# define USART_MAN_RXPP_ZEROONE (2 << USART_MAN_RXPP_SHIFT) /* ZERO_ONE */ -# define USART_MAN_RXPP_ONEZERO (3 << USART_MAN_RXPP_SHIFT) /* ONE_ZERO */ -#define USART_MAN_RXMPOL (1 << 28) /* Bit 28: Receiver Manchester Polarity (USART only) */ -#define USART_MAN_DRIFT (1 << 30) /* Bit 30: Drift compensation (USART only) */ - -/* USART Write Protect Mode Register (USART only) */ - -#define USART_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable (USART only) */ -#define USART_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY (USART only) */ -#define USART_WPMR_WPKEY_MASK (0x00ffffff << USART_WPMR_WPKEY_SHIFT) - -/* USART Write Protect Status Register (USART only) */ - -#define USART_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status (USART only) */ -#define USART_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source (USART only) */ -#define USART_WPSR_WPVSRC_MASK (0xffff << USART_WPSR_WPVSRC_SHIFT) - -/* USART Version Register */ - -#define USART_VERSION_VERSION_SHIFT (0) /* Bits 0-11: Macrocell version number (USART only) */ -#define USART_VERSION_VERSION_MASK (0xfff << USART_VERSION_VERSION_SHIFT) -#define USART_VERSION_MFN_SHIFT (16) /* Bits 16-18: Reserved (USART only) */ -#define USART_VERSION_MFN_MASK (7 << USART_VERSION_MFN_SHIFT) - -/************************************************************************************************ - * Public Types - ************************************************************************************************/ - -/************************************************************************************************ - * Public Data - ************************************************************************************************/ - -/************************************************************************************************ - * Public Functions - ************************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_UART_H */ diff --git a/nuttx/arch/arm/src/sam34/sam3u_clockconfig.c b/nuttx/arch/arm/src/sam34/sam3u_clockconfig.c index 374e4868a..71d918b8c 100644 --- a/nuttx/arch/arm/src/sam34/sam3u_clockconfig.c +++ b/nuttx/arch/arm/src/sam34/sam3u_clockconfig.c @@ -49,11 +49,11 @@ #include "up_internal.h" #include "sam_clockconfig.h" -#include "chip/sam_pmc.h" +#include "chip/sam3u_pmc.h" #include "chip/sam3u_eefc.h" -#include "chip/sam_wdt.h" +#include "chip/sam3u_wdt.h" #include "chip/sam3u_supc.h" -#include "chip/sam_matrix.h" +#include "chip/sam3u_matrix.h" /**************************************************************************** * Pre-processor Definitions @@ -63,21 +63,22 @@ * in board.h */ -#define CKGR_MOR_KEY (0x37 << CKGR_MOR_KEY_SHIFT) -#define SUPR_CR_KEY (0xa5 << SUPC_CR_KEY_SHIFT) +#define BOARD_CKGR_MOR (PMC_CKGR_MOR_KEY | BOARD_CKGR_MOR_MOSCXTST | \ + PMC_CKGR_MOR_MOSCRCEN | PMC_CKGR_MOR_MOSCXTEN) -#define BOARD_CKGR_MOR (CKGR_MOR_KEY|BOARD_CKGR_MOR_MOSCXTST|\ - CKGR_MOR_MOSCRCEN|CKGR_MOR_MOSCXTEN) - -#define BOARD_CKGR_PLLAR (CKGR_PLLAR_ONE|BOARD_CKGR_PLLAR_MULA|\ - BOARD_CKGR_PLLAR_STMODE|BOARD_CKGR_PLLAR_PLLACOUNT|\ - BOARD_CKGR_PLLAR_DIVA) - -#define BOARD_PMC_MCKR_FAST (BOARD_PMC_MCKR_PRES|PMC_MCKR_CSS_MAIN) -#define BOARD_PMC_MCKR (BOARD_PMC_MCKR_PRES|BOARD_PMC_MCKR_CSS) +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define BOARD_CKGR_PLLAR (PMC_CKGR_PLLAR_ONE | BOARD_CKGR_PLLAR_MUL | \ + BOARD_CKGR_PLLAR_STMODE | BOARD_CKGR_PLLAR_COUNT | \ + BOARD_CKGR_PLLAR_DIV) +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# define BOARD_CKGR_PLLAR (PMC_CKGR_PLLAR_ONE | BOARD_CKGR_PLLAR_MUL | \ + BOARD_CKGR_PLLAR_COUNT | BOARD_CKGR_PLLAR_DIV) +#endif -#define BOARD_CKGR_UCKR (BOARD_CKGR_UCKR_UPLLCOUNT|CKGR_UCKR_UPLLEN) +#define BOARD_PMC_MCKR_FAST (BOARD_PMC_MCKR_PRES | PMC_MCKR_CSS_MAIN) +#define BOARD_PMC_MCKR (BOARD_PMC_MCKR_PRES | BOARD_PMC_MCKR_CSS) +#define BOARD_CKGR_UCKR (BOARD_CKGR_UCKR_UPLLCOUNT | PMC_CKGR_UCKR_UPLLEN) /**************************************************************************** * Public Data @@ -101,8 +102,8 @@ static inline void sam_efcsetup(void) { - putreg32((2 << EEFC_FMR_FWS_SHIFT), SAM_EEFC0_FMR); - putreg32((2 << EEFC_FMR_FWS_SHIFT), SAM_EEFC1_FMR); + putreg32((BOARD_FWS << EEFC_FMR_FWS_SHIFT), SAM_EEFC0_FMR); + putreg32((BOARD_FWS << EEFC_FMR_FWS_SHIFT), SAM_EEFC1_FMR); } /**************************************************************************** @@ -170,7 +171,7 @@ static inline void sam_pmcsetup(void) /* Enable main oscillator (if it has not already been selected) */ - if ((getreg32(SAM_CKGR_MOR) & CKGR_MOR_MOSCSEL) == 0) + if ((getreg32(SAM_PMC_CKGR_MOR) & PMC_CKGR_MOR_MOSCSEL) == 0) { /* "When the MOSCXTEN bit and the MOSCXTCNT are written in CKGR_MOR to * enable the main oscillator, the MOSCXTS bit in the Power Management @@ -180,7 +181,7 @@ static inline void sam_pmcsetup(void) * indicating that the main clock is valid." */ - putreg32(BOARD_CKGR_MOR, SAM_CKGR_MOR); + putreg32(BOARD_CKGR_MOR, SAM_PMC_CKGR_MOR); sam_pmcwait(PMC_INT_MOSCXTS); } @@ -196,7 +197,7 @@ static inline void sam_pmcsetup(void) * 1 = Selection is in progress */ - putreg32((BOARD_CKGR_MOR|CKGR_MOR_MOSCSEL), SAM_CKGR_MOR); + putreg32((BOARD_CKGR_MOR | PMC_CKGR_MOR_MOSCSEL), SAM_PMC_CKGR_MOR); sam_pmcwait(PMC_INT_MOSCSELS); /* "Select the master clock. "The Master Clock selection is made by writing @@ -214,17 +215,17 @@ static inline void sam_pmcsetup(void) putreg32(regval, SAM_PMC_MCKR); sam_pmcwait(PMC_INT_MCKRDY); - /* Settup PLLA and wait for LOCKA */ + /* Setup PLLA and wait for LOCKA */ - putreg32(BOARD_CKGR_PLLAR, SAM_CKGR_PLLAR); + putreg32(BOARD_CKGR_PLLAR, SAM_PMC_CKGR_PLLAR); sam_pmcwait(PMC_INT_LOCKA); /* Setup UTMI for USB and wait for LOCKU */ #ifdef CONFIG_USBDEV - regval = getreg32(SAM_CKGR_UCKR); + regval = getreg32(SAM_PMC_CKGR_UCKR); regval |= BOARD_CKGR_UCKR; - putreg32(regval, SAM_CKGR_UCKR); + putreg32(regval, SAM_PMC_CKGR_UCKR); sam_pmcwait(PMC_INT_LOCKU); #endif diff --git a/nuttx/arch/arm/src/sam34/sam3u_gpio.c b/nuttx/arch/arm/src/sam34/sam3u_gpio.c index 271bb2f9b..a59878a3d 100644 --- a/nuttx/arch/arm/src/sam34/sam3u_gpio.c +++ b/nuttx/arch/arm/src/sam34/sam3u_gpio.c @@ -1,5 +1,6 @@ /**************************************************************************** * arch/arm/src/sam34/sam3u_gpio.c + * General Purpose Input/Output (GPIO) logic for the SAM3U and SAM4S * * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -52,7 +53,14 @@ #include "chip.h" #include "sam_gpio.h" -#include "chip/sam_pio.h" + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# include "chip/sam3u_pio.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# include "chip/sam4s_pio.h" +#else +# error Unrecognized SAM architecture +#endif /**************************************************************************** * Definitions @@ -111,6 +119,10 @@ static inline int sam_gpiopin(gpio_pinset_t cfgset) static inline int sam_configinput(uintptr_t base, uint32_t pin, gpio_pinset_t cfgset) { +#ifdef GPIO_HAVE_SCHMITT + uint32_t regval; +#endif + /* Disable interrupts on the pin */ putreg32(pin, base + SAM_PIO_IDR_OFFSET); @@ -126,6 +138,19 @@ static inline int sam_configinput(uintptr_t base, uint32_t pin, putreg32(pin, base + SAM_PIO_PUDR_OFFSET); } +#ifdef GPIO_HAVE_PULLDOWN + /* Enable/disable the pull-down as requested */ + + if ((cfgset & GPIO_CFG_PULLDOWN) != 0) + { + putreg32(pin, base + SAM_PIO_PPDER_OFFSET); + } + else + { + putreg32(pin, base + SAM_PIO_PPDDR_OFFSET); + } +#endif + /* Check if filtering should be enabled */ if ((cfgset & GPIO_CFG_DEGLITCH) != 0) @@ -137,14 +162,29 @@ static inline int sam_configinput(uintptr_t base, uint32_t pin, putreg32(pin, base + SAM_PIO_IFDR_OFFSET); } +#ifdef GPIO_HAVE_SCHMITT + /* Enable/disable the Schmitt trigger */ + + regval = getreg32(base + SAM_PIO_SCHMITT_OFFSET); + if ((cfgset & GPIO_CFG_PULLDOWN) != 0) + { + regval |= pin; + } + else + { + regval &= ~pin; + } + putreg32(regval, base + SAM_PIO_SCHMITT_OFFSET); +#endif + /* Configure the pin as an input and enable the GPIO function */ putreg32(pin, base + SAM_PIO_ODR_OFFSET); putreg32(pin, base + SAM_PIO_PER_OFFSET); /* To-Do: If DEGLITCH is selected, need to configure DIFSR, SCIFSR, and - * registers. This would probably best be done with another, new - * API... perhaps sam_configfilter() + * IFDGSR registers. This would probably best be done with + * another, new API... perhaps sam_configfilter() */ return OK; @@ -176,6 +216,19 @@ static inline int sam_configoutput(uintptr_t base, uint32_t pin, putreg32(pin, base + SAM_PIO_PUDR_OFFSET); } +#ifdef GPIO_HAVE_PULLDOWN + /* Enable/disable the pull-down as requested */ + + if ((cfgset & GPIO_CFG_PULLDOWN) != 0) + { + putreg32(pin, base + SAM_PIO_PPDER_OFFSET); + } + else + { + putreg32(pin, base + SAM_PIO_PPDDR_OFFSET); + } +#endif + /* Enable the open drain driver if requrested */ if ((cfgset & GPIO_CFG_OPENDRAIN) != 0) @@ -234,7 +287,58 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin, putreg32(pin, base + SAM_PIO_PUDR_OFFSET); } - /* Configure pin, depending upon the peripheral A or B*/ +#ifdef GPIO_HAVE_PULLDOWN + /* Enable/disable the pull-down as requested */ + + if ((cfgset & GPIO_CFG_PULLDOWN) != 0) + { + putreg32(pin, base + SAM_PIO_PPDER_OFFSET); + } + else + { + putreg32(pin, base + SAM_PIO_PPDDR_OFFSET); + } +#endif + +#ifdef GPIO_HAVE_PERIPHCD + /* Configure pin, depending upon the peripheral A, B, C or D + * + * PERIPHA: ABCDSR1[n] = 0 ABCDSR2[n] = 0 + * PERIPHB: ABCDSR1[n] = 1 ABCDSR2[n] = 0 + * PERIPHC: ABCDSR1[n] = 0 ABCDSR2[n] = 1 + * PERIPHD: ABCDSR1[n] = 1 ABCDSR2[n] = 1 + */ + + regval = getreg32(base + SAM_PIO_ABCDSR1_OFFSET); + if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA || + (cfgset & GPIO_MODE_MASK) == GPIO_PERIPHC) + { + regval &= ~pin; + } + else + { + regval |= pin; + } + putreg32(regval, base + SAM_PIO_ABCDSR1_OFFSET); + + regval = getreg32(base + SAM_PIO_ABCDSR2_OFFSET); + if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA || + (cfgset & GPIO_MODE_MASK) == GPIO_PERIPHB) + { + regval &= ~pin; + } + else + { + regval |= pin; + } + putreg32(regval, base + SAM_PIO_ABCDSR2_OFFSET); + +#else + /* Configure pin, depending upon the peripheral A or B: + * + * PERIPHA: ABSR[n] = 0 + * PERIPHB: ABSR[n] = 1 + */ regval = getreg32(base + SAM_PIO_ABSR_OFFSET); if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA) @@ -246,6 +350,7 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin, regval |= pin; } putreg32(regval, base + SAM_PIO_ABSR_OFFSET); +#endif /* Disable PIO functionality */ @@ -375,11 +480,17 @@ int sam_dumpgpio(uint32_t pinset, const char *msg) lldbg(" PDSR: %08x IMR: %08x ISR: %08x MDSR: %08x\n", getreg32(base + SAM_PIO_PDSR_OFFSET), getreg32(base + SAM_PIO_IMR_OFFSET), getreg32(base + SAM_PIO_ISR_OFFSET), getreg32(base + SAM_PIO_MDSR_OFFSET)); - lldbg(" PUSR: %08x ABSR: %08x SCIFSR: %08x DIFSR: %08x\n", - getreg32(base + SAM_PIO_PUSR_OFFSET), getreg32(base + SAM_PIO_ABSR_OFFSET), - getreg32(base + SAM_PIO_SCIFSR_OFFSET), getreg32(base + SAM_PIO_DIFSR_OFFSET)); - lldbg(" IFDGSR: %08x SCDR: %08x OWSR: %08x AIMMR: %08x\n", - getreg32(base + SAM_PIO_IFDGSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET), +#if defined(CONFIG_ARCH_CHIP_ATSAM3U) + lldbg(" ABSR: %08x SCIFSR: %08x DIFSR: %08x IFDGSR: %08x\n", + getreg32(base + SAM_PIO_ABSR_OFFSET), getreg32(base + SAM_PIO_SCIFSR_OFFSET), + getreg32(base + SAM_PIO_DIFSR_OFFSET), getreg32(base + SAM_PIO_IFDGSR_OFFSET)); +#elif defined(CONFIG_ARCH_CHIP_ATSAM4S) + lldbg(" ABCDSR: %08x %08x IFSCSR: %08x PPDSR: %08x\n", + getreg32(base + SAM_PIO_ABCDSR1_OFFSET), getreg32(base + SAM_PIO_ABCDSR2_OFFSET), + getreg32(base + SAM_PIO_IFSCSR_OFFSET), getreg32(base + SAM_PIOC_PPDSR)); +#endif + lldbg(" PUSR: %08x SCDR: %08x OWSR: %08x AIMMR: %08x\n", + getreg32(base + SAM_PIO_PUSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET), getreg32(base + SAM_PIO_OWSR_OFFSET), getreg32(base + SAM_PIO_AIMMR_OFFSET)); lldbg(" ESR: %08x LSR: %08x ELSR: %08x FELLSR: %08x\n", getreg32(base + SAM_PIO_ESR_OFFSET), getreg32(base + SAM_PIO_LSR_OFFSET), @@ -387,6 +498,13 @@ int sam_dumpgpio(uint32_t pinset, const char *msg) lldbg(" FRLHSR: %08x LOCKSR: %08x WPMR: %08x WPSR: %08x\n", getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET), getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET)); +#if defined(CONFIG_ARCH_CHIP_ATSAM4S) + lldbg(" PCMR: %08x PCIMR: %08x PCISR: %08x PCRHR: %08x\n", + getreg32(base + SAM_PIO_PCMR_OFFSET), getreg32(base + SAM_PIO_PCIMR_OFFSET), + getreg32(base + SAM_PIO_PCISR_OFFSET), getreg32(base + SAM_PIO_PCRHR_OFFSET)); + lldbg("SCHMITT: %08x\n", + getreg32(base + SAM_PIO_SCHMITT_OFFSET)); +#endif irqrestore(flags); return OK; } diff --git a/nuttx/arch/arm/src/sam34/sam3u_gpio.h b/nuttx/arch/arm/src/sam34/sam3u_gpio.h index 7a9fea1ca..84f543056 100644 --- a/nuttx/arch/arm/src/sam34/sam3u_gpio.h +++ b/nuttx/arch/arm/src/sam34/sam3u_gpio.h @@ -1,5 +1,6 @@ /************************************************************************************ * arch/arm/src/sam34/sam3u_gpio.h + * General Purpose Input/Output (GPIO) definitions for the SAM3U * * Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -45,16 +46,22 @@ /************************************************************************************ * Definitions ************************************************************************************/ +/* Configuration ********************************************************************/ + +#undef GPIO_HAVE_PULLDOWN +#undef GPIO_HAVE_PERIPHCD +#undef GPIO_HAVE_SCHMITT /* Bit-encoded input to sam_configgpio() ********************************************/ /* 16-bit Encoding: - * MMCC CII. VPPB BBBB + * + * MMCC CII. VPPB BBBB */ /* Input/Output mode: * - * MM.. .... .... .... + * MM.. .... .... .... */ #define GPIO_MODE_SHIFT (14) /* Bits 14-15: GPIO mode */ @@ -65,7 +72,8 @@ # define GPIO_PERIPHB (3 << GPIO_MODE_SHIFT) /* Controlled by periph B signal */ /* These bits set the configuration of the pin: - * ..CC C... .... .... + * + * ..CC C... .... .... */ #define GPIO_CFG_SHIFT (11) /* Bits 11-13: GPIO configuration bits */ @@ -76,10 +84,11 @@ # define GPIO_CFG_OPENDRAIN (4 << GPIO_CFG_SHIFT) /* Bit 13: Open drain */ /* Additional interrupt modes: - * .... .II. .... .... + * + * .... .II. .... .... */ -#define GPIO_INT_SHIFT (9) /* Bits 9-10: GPIO configuration bits */ +#define GPIO_INT_SHIFT (9) /* Bits 9-10: GPIO interrupt bits */ #define GPIO_INT_MASK (3 << GPIO_INT_SHIFT) # define GPIO_INT_LEVEL (1 << 10) /* Bit 10: Level detection interrupt */ # define GPIO_INT_EDGE (0) /* (vs. Edge detection interrupt) */ @@ -89,14 +98,16 @@ # define GPIO_INT_FALLING (0) /* (vs. Falling edge detection interrupt) */ /* If the pin is an GPIO output, then this identifies the initial output value: - * .... .... V... .... + * + * .... .... V... .... */ #define GPIO_OUTPUT_SET (1 << 7) /* Bit 7: Inital value of output */ #define GPIO_OUTPUT_CLEAR (0) /* This identifies the GPIO port: - * .... .... .PP. .... + * + * .... .... .PP. .... */ #define GPIO_PORT_SHIFT (5) /* Bit 5-6: Port number */ @@ -106,10 +117,11 @@ # define GPIO_PORT_PIOC (2 << GPIO_PORT_SHIFT) /* This identifies the bit in the port: - * .... .... ...B BBBB + * + * .... .... ...B BBBB */ -#define GPIO_PIN_SHIFT 0 /* Bits 0-4: GPIO number: 0-31 */ +#define GPIO_PIN_SHIFT 0 /* Bits 0-4: GPIO number: 0-31 */ #define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT) #define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) #define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) diff --git a/nuttx/arch/arm/src/sam34/sam3u_periphclks.h b/nuttx/arch/arm/src/sam34/sam3u_periphclks.h new file mode 100644 index 000000000..09c1abb4d --- /dev/null +++ b/nuttx/arch/arm/src/sam34/sam3u_periphclks.h @@ -0,0 +1,149 @@ +/************************************************************************************ + * arch/arm/src/sam34/sam3u_periphclks.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_SAM3U_PERIPHCLKS_H +#define __ARCH_ARM_SRC_SAM34_SAM3U_PERIPHCLKS_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> +#include <stdint.h> +#include <arch/irq.h> +#include "chip/sam3u_pmc.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Helper macros */ + +#define sam_enableperipheral(s) putreg32((1 << (s)), SAM_PMC_PCER) +#define sam_disableperipheral(s) putreg32((1 << (s)), SAM_PMC_PDER) + +#define sam_supc_enableclk() sam_enableperipheral(SAM_PID_SUPC) +#define sam_rstc_enableclk() sam_enableperipheral(SAM_PID_RSTC) +#define sam_rtc_enableclk() sam_enableperipheral(SAM_PID_RTC) +#define sam_rtt_enableclk() sam_enableperipheral(SAM_PID_RTT) +#define sam_wdt_enableclk() sam_enableperipheral(SAM_PID_WDT) +#define sam_pmc_enableclk() sam_enableperipheral(SAM_PID_PMC) +#define sam_eefc0_enableclk() sam_enableperipheral(SAM_PID_EEFC0) +#define sam_eefc1_enableclk() sam_enableperipheral(SAM_PID_EEFC1) +#define sam_uart0_enableclk() sam_enableperipheral(SAM_PID_UART0) +#define sam_smc_enableclk() sam_enableperipheral(SAM_PID_SMC) +#define sam_pioa_enableclk() sam_enableperipheral(SAM_PID_PIOA) +#define sam_piob_enableclk() sam_enableperipheral(SAM_PID_PIOB) +#define sam_pioc_enableclk() sam_enableperipheral(SAM_PID_PIOC) +#define sam_usart0_enableclk() sam_enableperipheral(SAM_PID_USART0) +#define sam_usart1_enableclk() sam_enableperipheral(SAM_PID_USART1) +#define sam_usart2_enableclk() sam_enableperipheral(SAM_PID_USART2) +#define sam_usart3_enableclk() sam_enableperipheral(SAM_PID_USART3) +#define sam_hsmci_enableclk() sam_enableperipheral(SAM_PID_HSMCI) +#define sam_twi0_enableclk() sam_enableperipheral(SAM_PID_TWI0) +#define sam_twi1_enableclk() sam_enableperipheral(SAM_PID_TWI1) +#define sam_spi_enableclk() sam_enableperipheral(SAM_PID_SPI) +#define sam_ssc_enableclk() sam_enableperipheral(SAM_PID_SSC) +#define sam_tc0_enableclk() sam_enableperipheral(SAM_PID_TC0) +#define sam_tc1_enableclk() sam_enableperipheral(SAM_PID_TC1) +#define sam_tc2_enableclk() sam_enableperipheral(SAM_PID_TC2) +#define sam_pwm_enableclk() sam_enableperipheral(SAM_PID_PWM) +#define sam_adc12b_enableclk() sam_enableperipheral(SAM_PID_ADC12B) +#define sam_dmac_enableclk() sam_enableperipheral(SAM_PID_DMAC) +#define sam_udphs_enableclk() sam_enableperipheral(SAM_PID_UDPHS) + +#define sam_supc_disableclk() sam_disableperipheral(SAM_PID_SUPC) +#define sam_rstc_disableclk() sam_disableperipheral(SAM_PID_RSTC) +#define sam_rtc_disableclk() sam_disableperipheral(SAM_PID_RTC) +#define sam_rtt_disableclk() sam_disableperipheral(SAM_PID_RTT) +#define sam_wdt_disableclk() sam_disableperipheral(SAM_PID_WDT) +#define sam_pmc_disableclk() sam_disableperipheral(SAM_PID_PMC) +#define sam_eefc0_disableclk() sam_disableperipheral(SAM_PID_EEFC0) +#define sam_eefc1_disableclk() sam_disableperipheral(SAM_PID_EEFC1) +#define sam_uart0_disableclk() sam_disableperipheral(SAM_PID_UART0) +#define sam_smc_disableclk() sam_disableperipheral(SAM_PID_SMC) +#define sam_pioa_disableclk() sam_disableperipheral(SAM_PID_PIOA) +#define sam_piob_disableclk() sam_disableperipheral(SAM_PID_PIOB) +#define sam_pioc_disableclk() sam_disableperipheral(SAM_PID_PIOC) +#define sam_usart0_disableclk() sam_disableperipheral(SAM_PID_USART0) +#define sam_usart1_disableclk() sam_disableperipheral(SAM_PID_USART1) +#define sam_usart2_disableclk() sam_disableperipheral(SAM_PID_USART2) +#define sam_usart3_disableclk() sam_disableperipheral(SAM_PID_USART3) +#define sam_hsmci_disableclk() sam_disableperipheral(SAM_PID_HSMCI) +#define sam_twi0_disableclk() sam_disableperipheral(SAM_PID_TWI0) +#define sam_twi1_disableclk() sam_disableperipheral(SAM_PID_TWI1) +#define sam_spi_disableclk() sam_disableperipheral(SAM_PID_SPI) +#define sam_ssc_disableclk() sam_disableperipheral(SAM_PID_SSC) +#define sam_tc0_disableclk() sam_disableperipheral(SAM_PID_TC0) +#define sam_tc1_disableclk() sam_disableperipheral(SAM_PID_TC1) +#define sam_tc2_disableclk() sam_disableperipheral(SAM_PID_TC2) +#define sam_pwm_disableclk() sam_disableperipheral(SAM_PID_PWM) +#define sam_adc12b_disableclk() sam_disableperipheral(SAM_PID_ADC12B) +#define sam_dmac_disableclk() sam_disableperipheral(SAM_PID_DMAC) +#define sam_udphs_disableclk() sam_disableperipheral(SAM_PID_UDPHS) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_SAM34_SAM3U_PERIPHCLKS_H */ diff --git a/nuttx/arch/arm/src/sam34/sam4l_clockconfig.c b/nuttx/arch/arm/src/sam34/sam4l_clockconfig.c index 2857c7fb1..59bd62bf0 100644 --- a/nuttx/arch/arm/src/sam34/sam4l_clockconfig.c +++ b/nuttx/arch/arm/src/sam34/sam4l_clockconfig.c @@ -41,6 +41,9 @@ #include <nuttx/config.h> +#include <stdint.h> +#include <stdbool.h> + #include <arch/irq.h> #include <arch/board/board.h> @@ -48,24 +51,390 @@ #include "up_internal.h" #include "chip/sam4l_pm.h" +#include "chip/sam4l_scif.h" +#include "chip/sam4l_bpm.h" +#include "chip/sam4l_bscif.h" #include "chip/sam4l_flashcalw.h" +#include "sam4l_periphclks.h" #include "sam_clockconfig.h" /**************************************************************************** - * Private Definitions + * Pre-processor Definitions ****************************************************************************/ +/* Configuration ************************************************************/ + +#ifndef CONFIG_ARCH_RAMFUNCS +# error "CONFIG_ARCH_RAMFUNCS must be defined" +#endif + +/* Board/Clock Setup *******************************************************/ +/* Verify dividers */ + +#if ((BOARD_CPU_SHIFT > BOARD_PBA_SHIFT) || (BOARD_CPU_SHIFT > BOARD_PBB_SHIFT) || \ + (BOARD_CPU_SHIFT > BOARD_PBC_SHIFT) || (BOARD_CPU_SHIFT > BOARD_PBD_SHIFT)) +# error BOARD_PBx_SHIFT must be greater than or equal to BOARD_CPU_SHIFT +#endif + +/* Nominal frequencies in on-chip RC oscillators. These may frequencies + * may vary with temperature changes. + */ + +#define SAM_RCSYS_FREQUENCY 115000 /* Nominal frequency of RCSYS (Hz) */ +#define SAM_RC32K_FREQUENCY 32768 /* Nominal frequency of RC32K (Hz) */ +#define SAM_RC80M_FREQUENCY 80000000 /* Nominal frequency of RC80M (Hz) */ +#define SAM_RCFAST4M_FREQUENCY 4000000 /* Nominal frequency of RCFAST4M (Hz) */ +#define SAM_RCFAST8M_FREQUENCY 8000000 /* Nominal frequency of RCFAST8M (Hz) */ +#define SAM_RCFAST12M_FREQUENCY 12000000 /* Nominal frequency of RCFAST12M (Hz) */ +#define SAM_RC1M_FREQUENCY 1000000 /* Nominal frequency of RC1M (Hz) */ + +/* Oscillator 0. This might be the system clock or the source clock for + * either PLL0 or DFPLL. It might also be needed if OSC0 is the source + * clock for GCLK9. + * + * By selecting CONFIG_SAM34_OSC0, you can also force the clock to be enabled + * at boot time. + */ + +#if defined(CONFIG_SAM34_OSC0) || defined(BOARD_SYSCLK_SOURCE_OSC0) || \ + defined(BOARD_DFLL0_SOURCE_OSC0) || defined(BOARD_PLL0_SOURCE_OSC0) || \ + defined(BOARD_GLCK9_SOURCE_OSC0) +# define NEED_OSC0 1 +#endif + +#ifdef NEED_OSC0 +# if !defined(BOARD_OSC0_STARTUP_US) +# error BOARD_OSC0_STARTUP_US is not defined +# elif BOARD_OSC0_STARTUP_US == 0 +# define SAM_OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_0 +# define SAM_OSC0_STARTUP_TIMEOUT 8 +# elif BOARD_OSC0_STARTUP_US <= 557 +# define SAM_OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_64 +# define SAM_OSC0_STARTUP_TIMEOUT 80 +# elif BOARD_OSC0_STARTUP_US <= 1100 +# define SAM_OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_128 +# define SAM_OSC0_STARTUP_TIMEOUT 160 +# elif BOARD_OSC0_STARTUP_US <= 18000 +# define SAM_OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_2K +# define SAM_OSC0_STARTUP_TIMEOUT 2560 +# elif BOARD_OSC0_STARTUP_US <= 36000 +# define SAM_OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_4K +# define SAM_OSC0_STARTUP_TIMEOUT 5120 +# elif BOARD_OSC0_STARTUP_US <= 71000 +# define SAM_OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_8K +# define SAM_OSC0_STARTUP_TIMEOUT 10240 +# elif BOARD_OSC0_STARTUP_US <= 143000 +# define SAM_OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_16K +# define SAM_OSC0_STARTUP_TIMEOUT 20480 +# elif BOARD_OSC0_STARTUP_US <= 285000 +# define SAM_OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_32K +# define SAM_OSC0_STARTUP_TIMEOUT 40960 +# else +# error BOARD_OSC0_STARTUP_US is out of range +# endif + +# ifdef BOARD_OSC0_ISXTAL +# define SAM_OSC0_MODE_VALUE SCIF_OSCCTRL0_MODE +# if BOARD_OSC0_FREQUENCY < 2000000 +# define SAM_OSC0_GAIN_VALUE SCIF_OSCCTRL0_GAIN(0) +# elif BOARD_OSC0_FREQUENCY < 4000000 +# define SAM_OSC0_GAIN_VALUE SCIF_OSCCTRL0_GAIN(1) +# elif BOARD_OSC0_FREQUENCY < 8000000 +# define SAM_OSC0_GAIN_VALUE SCIF_OSCCTRL0_GAIN(2) +# elif BOARD_OSC0_FREQUENCY < 16000000 +# define SAM_OSC0_GAIN_VALUE SCIF_OSCCTRL0_GAIN(3) +# else +# define SAM_OSC0_GAIN_VALUE ((0x1u << 4) | SCIF_OSCCTRL0_GAIN(0)) +# endif +# else +# define SAM_OSC0_MODE_VALUE 0 +# define SAM_OSC0_GAIN_VALUE 0 +# endif +#endif + +/* OSC32. The 32K oscillator may be the source clock for DFPLL0 or + * the source clock for GLK9 that might be used to driver PLL0. + * + * By selecting CONFIG_SAM34_OSC32K, you can also force the clock to be + * enabled at boot time. OSC32 may needed by other devices as well + * (AST, WDT, PICUART, RTC). + */ + +#if defined(CONFIG_SAM34_OSC32K) || defined(BOARD_DFLL0_SOURCE_OSC32K) || \ + defined(BOARD_GLCK9_SOURCE_OSC32K) +# define NEED_OSC32K 1 +#endif -#if defined(SAM_CLOCK_OSC0) || \ - (defined (SAM_CLOCK_PLL0) && defined(SAM_CLOCK_PLL0_OSC0)) || \ - (defined (SAM_CLOCK_PLL1) && defined(SAM_CLOCK_PLL1_OSC0)) -# define NEED_OSC0 +#ifdef NEED_OSC32K +# if !defined(BOARD_OSC32_STARTUP_US) +# error BOARD_OSC32_STARTUP_US is not defined +# elif BOARD_OSC32_STARTUP_US == 0 +# define SAM_OSC32_STARTUP_VALUE BSCIF_OSCCTRL32_STARTUP_0 +# elif BOARD_OSC32_STARTUP_US <= 1100 +# define SAM_OSC32_STARTUP_VALUE BSCIF_OSCCTRL32_STARTUP_128 +# elif BOARD_OSC32_STARTUP_US <= 72300 +# define SAM_OSC32_STARTUP_VALUE BSCIF_OSCCTRL32_STARTUP_8K +# elif BOARD_OSC32_STARTUP_US <= 143000 +# define SAM_OSC32_STARTUP_VALUE BSCIF_OSCCTRL32_STARTUP_16K +# elif BOARD_OSC32_STARTUP_US <= 570000 +# define SAM_OSC32_STARTUP_VALUE BSCIF_OSCCTRL32_STARTUP_64K +# elif BOARD_OSC32_STARTUP_US <= 1100000 +# define SAM_OSC32_STARTUP_VALUE BSCIF_OSCCTRL32_STARTUP_128K +# elif BOARD_OSC32_STARTUP_US <= 2300000 +# define SAM_OSC32_STARTUP_VALUE BSCIF_OSCCTRL32_STARTUP_256K +# elif BOARD_OSC32_STARTUP_US <= 4600000 +# define SAM_OSC32_STARTUP_VALUE BSCIF_OSCCTRL32_STARTUP_512K +# else +# error BOARD_OSC32_STARTUP_US is out of range +# endif + +# ifdef BOARD_OSC32_ISXTAL +# define SAM_OSC32_MODE_VALUE BSCIF_OSCCTRL32_MODE_XTAL +# else +# define SAM_OSC32_MODE_VALUE BSCIF_OSCCTRL32_MODE_EXTCLK +# endif + +# ifndef BOARD_OSC32_SELCURR +# define BOARD_OSC32_SELCURR BSCIF_OSCCTRL32_SELCURR_300 +# endif #endif -#if defined(SAM_CLOCK_OSC1) || \ - (defined (SAM_CLOCK_PLL0) && defined(SAM_CLOCK_PLL0_OSC1)) || \ - (defined (SAM_CLOCK_PLL1) && defined(SAM_CLOCK_PLL1_OSC1)) -# define NEED_OSC1 +/* RC80M. This might be the system clock or the source clock for the DFPLL + * or it could be the source for GCLK9 that drives PLL0. + * + * By selecting CONFIG_SAM34_RC80M, you can also force the clock to be enabled + * at boot time. + */ + +#if defined(CONFIG_SAM34_RC80M) || defined(BOARD_SYSCLK_SOURCE_RC80M) || \ + defined(BOARD_DFLL0_SOURCE_RC80M) || BOARD_GLCK9_SOURCE_RC80M +# define NEED_RC80M 1 +#endif + +/* RCFAST. The 12/8/4 fast RC oscillator may be used as the system clock + * or as the source for GLCK9 that drives PLL0. + * If not then, it may be enabled by setting the CONFIG_SAM34_RCFASTxM + * configuration variable. + */ + +#if defined(CONFIG_SAM34_RCFAST12M) +# undef CONFIG_SAM34_RCFAST8M +# undef CONFIG_SAM34_RCFAST4M +#elif defined(CONFIG_SAM34_RCFAST8M) +# undef CONFIG_SAM34_RCFAST4M +#endif + +#if defined(BOARD_SYSCLK_SOURCE_FCFAST12M) +# if defined(CONFIG_SAM34_RCFAST8M) || defined(CONFIG_SAM34_RCFAST4M) +# error BOARD_SYSCLK_SOURCE_FCFAST12M inconsistent with CONFIG_SAM34_RCFAST8/4M +# endif +# define NEED_RCFAST 1 +# define SAM_RCFAST_RANGE SCIF_RCFASTCFG_FRANGE_12MHZ +# define SAM_RCFAST_FREQUENCY SAM_RCFAST12M_FREQUENCY +#elif defined(BOARD_SYSCLK_SOURCE_FCFAST8M) +# if defined(CONFIG_SAM34_RCFAST12M) || defined(CONFIG_SAM34_RCFAST4M) +# error BOARD_SYSCLK_SOURCE_FCFAST8M inconsistent with CONFIG_SAM34_RCFAST12/4M +# endif +# define NEED_RCFAST 1 +# define SAM_RCFAST_RANGE SCIF_RCFASTCFG_FRANGE_8MHZ +# define SAM_RCFAST_FREQUENCY SAM_RCFAST8M_FREQUENCY +#elif defined(BOARD_SYSCLK_SOURCE_FCFAST4M) +# if defined(CONFIG_SAM34_RCFAST12M) || defined(CONFIG_SAM34_RCFAST8M) +# error BOARD_SYSCLK_SOURCE_FCFAST4M inconsistent with CONFIG_SAM34_RCFAST12/8M +# endif +# define NEED_RCFAST 1 +# define SAM_RCFAST_RANGE SCIF_RCFASTCFG_FRANGE_4MHZ +# define SAM_RCFAST_FREQUENCY SAM_RCFAST4M_FREQUENCY +#elif defined(CONFIG_SAM34_RCFAST12M) +# define NEED_RCFAST 1 +# define SAM_RCFAST_RANGE SCIF_RCFASTCFG_FRANGE_12MHZ +# define SAM_RCFAST_FREQUENCY SAM_RCFAST12M_FREQUENCY +#elif defined(CONFIG_SAM34_RCFAST8M) +# define NEED_RCFAST 1 +# define SAM_RCFAST_RANGE SCIF_RCFASTCFG_FRANGE_8MHZ +# define SAM_RCFAST_FREQUENCY SAM_RCFAST8M_FREQUENCY +#elif defined(CONFIG_SAM34_RCFAST4M) +# define NEED_RCFAST 1 +# define SAM_RCFAST_RANGE SCIF_RCFASTCFG_FRANGE_4MHZ +# define SAM_RCFAST_FREQUENCY SAM_RCFAST4M_FREQUENCY +#endif + +/* RC1M. The 1M RC oscillator may be used as the system block or + * may be the source clock for GLCK9 that drives PLL0 + * + * By selecting CONFIG_SAM34_RC1M, you can also force the clock to be + * enabled at boot time. + */ + +#if defined(CONFIG_SAM34_RC1M) || defined(BOARD_SYSCLK_SOURCE_RC1M) || \ + defined(BOARD_GLCK9_SOURCE_RC1M) +# define NEED_RC1M 1 +#endif + +/* RC32K. The 32KHz RC oscillator may be used as the input to DFLL0 + * or as the input to GCLK9 that drives PLL0. + * + * By selecting CONFIG_SAM34_RC32K, you can also force the clock to be + * enabled at boot time. + */ + +#if defined(CONFIG_SAM34_RC32K) || defined(BOARD_DFLL0_SOURCE_RC32K) || \ + defined(BOARD_GLCK9_SOURCE_RC32K) +# define NEED_RC32K 1 +#endif + +/* GCLK9. May used as a source clock for PLL0 */ + +#ifdef BOARD_PLL0_SOURCE_GCLK9 +# define NEED_GLCK9 1 +#endif + +#ifdef NEED_GLCK9 +# if defined(BOARD_GLCK9_SOURCE_RCSYS) +# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_RCSYS +# define SAM_GCLK9_FREQUENCY SAM_RCSYS_FREQUENCY +# elif defined(BOARD_GLCK9_SOURCE_OSC32K) +# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_OSC32K +# define SAM_GCLK9_FREQUENCY BOARD_OSC32_FREQUENCY +# elif defined(BOARD_GLCK9_SOURCE_DFLL0) +# error BOARD_GLCK9_SOURCE_DFLL0 is not supported +# elif defined(BOARD_GLCK9_SOURCE_OSC0) +# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_OSC0 +# define SAM_GCLK9_FREQUENCY BOARD_OSC0_FREQUENCY +# elif defined(BOARD_GLCK9_SOURCE_RC80M) +# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_RC80M +# define SAM_GCLK9_FREQUENCY SAM_RC80M_FREQUENCY +# elif defined(BOARD_GLCK9_SOURCE_RCFAST) +# error BOARD_GLCK9_SOURCE_RCFAST is not supported (needs RCFAST configuration) +# elif defined(BOARD_GLCK9_SOURCE_RC1M) +# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_RC1M +# define SAM_GCLK9_FREQUENCY SAM_RCFAST_FREQUENCY +# elif defined(BOARD_GLCK9_SOURCE_CPUCLK) +# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_CPUCLK +# define SAM_GCLK9_FREQUENCY BOARD_CPU_FREQUENCY +# elif defined(BOARD_GLCK9_SOURCE_HSBCLK) +# error BOARD_GLCK9_SOURCE_HSBCLK is not supported (REVISIT) +# elif defined(BOARD_GLCK9_SOURCE_PBACLK) +# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_PBACLK +# define SAM_GCLK9_FREQUENCY BOARD_PBA_FREQUENCY +# elif defined(BOARD_GLCK9_SOURCE_PBBCLK) +# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_PBBCLK +# define SAM_GCLK9_FREQUENCY BOARD_PBB_FREQUENCY +# elif defined(BOARD_GLCK9_SOURCE_PBCCLK) +# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_PBCCLK +# define SAM_GCLK9_FREQUENCY BOARD_PBC_FREQUENCY +# elif defined(BOARD_GLCK9_SOURCE_PBDCLK) +# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_PBDCLK +# define SAM_GCLK9_FREQUENCY BOARD_PBD_FREQUENCY +# elif defined(BOARD_GLCK9_SOURCE_RC32K) +# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_RC32K +# define SAM_GCLK9_FREQUENCY SAM_RC32K_FREQUENCY +# else +# error Missing GCLK9 source +# endif +#endif + +/* PLL0 */ + +#ifdef BOARD_SYSCLK_SOURCE_PLL0 +/* PLL0 source */ + +# if defined(BOARD_PLL0_SOURCE_OSC0) +# define SAM_PLL0_SOURCE SCIF_PLL0_PLLOSC_OSC0 +# define SAM_PLL0_SOURCE_FREQUENCY BOARD_OSC0_FREQUENCY +# elif defined(BOARD_PLL0_SOURCE_GCLK9) +# define SAM_PLL0_SOURCE SCIF_PLL0_PLLOSC_GCLK9 +# define SAM_PLL0_SOURCE_FREQUENCY SAM_GCLK9_FREQUENCY +# else +# error Missing PLL0 source +# endif + +/* PLL0 Multipler and Divider */ + +# if !defined(BOARD_PLL0_MUL) +# error BOARD_PLL0_MUL is not defined +# elif BOARD_PLL0_MUL <= 2 || BOARD_PLL0_MUL > 16 +# error BOARD_PLL0_MUL is out of range +# endif + +# if !defined(BOARD_PLL0_DIV) +# error BOARD_PLL0_DIV is not defined +# elif BOARD_PLL0_DIV < 1 || BOARD_PLL0_DIV > 15 +# error BOARD_PLL0_DIV is out of range +# endif + +/* PLL0 frequency ranges */ + +# define SAM_PLL0_MIN_FREQUENCY 40000000 +# define SAM_PLL0_MAX_FREQUENCY 240000000 + +/* PLL0 VCO frequency */ + +# define SAM_PLL0_VCO_DIV1_FREQUENCY \ + (SAM_PLL0_SOURCE_FREQUENCY * BOARD_PLL0_MUL / BOARD_PLL0_DIV) + +# if (SAM_PLL0_VCO_DIV1_FREQUENCY < SAM_PLL0_MIN_FREQUENCY) || \ + (SAM_PLL0_VCO_DIV1_FREQUENCY > SAM_PLL0_MAX_FREQUENCY) +# error PLL0 VCO frequency is out of range +# endif + +/* PLL0 Options: + * + * PLL0 supports an option to divide the frequency output by 2. We + * will do this division to bring the internal VCO frequency up to the + * minimum value + * + * PLL0 operates in two frequency ranges as determined by + * SCIF_PLL0_PLLOPT_FVO: + * + * 0: 80MHz < fvco < 180MHz + * 1: 160MHz < fvco < 240MHz + * + * Select the correct frequncy range using the recommended threshold + * value. + */ + +# if SAM_PLL0_VCO_DIV1_FREQUENCY < (2*SAM_PLL0_MIN_FREQUENCY) && BOARD_PLL0_MUL <= 8 +# define SAM_PLL0_VCO_FREQUENCY (2 * SAM_PLL0_VCO_DIV1_FREQUENCY) +# define SAM_PLL0_MUL (2 * BOARD_PLL0_MUL) + +# if SAM_PLL0_VCO_FREQUENCY > (SAM_PLL0_VCO_RANGE_THRESHOLD / 2) +# define SAM_PLL0_OPTIONS (SCIF_PLL0_PLLOPT_DIV2 | SCIF_PLL0_PLLOPT_FVO) +# else +# define SAM_PLL0_OPTIONS SCIF_PLL0_PLLOPT_DIV2 +# endif + +# else +# define SAM_PLL0_VCO_FREQUENCY SAM_PLL0_VCO_DIV1_FREQUENCY +# define SAM_PLL0_MUL BOARD_PLL0_MUL + +# if SAM_PLL0_VCO_FREQUENCY > SAM_PLL0_VCO_RANGE_THRESHOLD +# define SAM_PLL0_OPTIONS SCIF_PLL0_PLLOPT_FVO +# else +# define SAM_PLL0_OPTIONS 0 +# endif +# endif +#endif + +/* DFLL0 */ + +#ifdef BOARD_SYSCLK_SOURCE_DFLL0 +/* DFLL0 reference clock */ + +# if defined(BOARD_DFLL0_SOURCE_RCSYS) +# define SAM_DFLLO_REFCLK SCIF_GCCTRL_OSCSEL_RCSYS +# elif defined(BOARD_DFLL0_SOURCE_OSC32K) +# define SAM_DFLLO_REFCLK SCIF_GCCTRL_OSCSEL_OSC32K +# elif define(BOARD_DFLL0_SOURCE_OSC0) +# define SAM_DFLLO_REFCLK SCIF_GCCTRL_OSCSEL_OSC0 +# elif define(BOARD_DFLL0_SOURCE_RC80M) +# define SAM_DFLLO_REFCLK SCIF_GCCTRL_OSCSEL_RC80M +# elif define(BOARD_DFLL0_SOURCE_RC32K) +# define SAM_DFLLO_REFCLK SCIF_GCCTRL_OSCSEL_RC32K +# else +# error No DFLL0 source for reference clock defined +# endif + #endif /**************************************************************************** @@ -96,7 +465,7 @@ * ****************************************************************************/ -#ifdef CONFIG_SAM_PICOCACHE +#ifdef CONFIG_SAM34_PICOCACHE static inline void sam_picocache(void) { /* Enable clocking to the PICOCACHE */ @@ -114,230 +483,369 @@ static inline void sam_picocache(void) #endif /**************************************************************************** + * Name: sam_enableosc0 + * + * Description: + * Initialiaze OSC0 settings per the definitions in the board.h file. + * + ****************************************************************************/ + +#ifdef NEED_OSC0 +static inline void sam_enableosc0(void) +{ + uint32_t regval; + + /* Enable and configure OSC0 */ + + regval = SAM_OSC0_STARTUP_VALUE | SAM_OSC0_GAIN_VALUE | SAM_OSC0_MODE_VALUE | + SCIF_OSCCTRL0_OSCEN; + putreg32(SCIF_UNLOCK_KEY(0xaa) | SCIF_UNLOCK_ADDR(SAM_SCIF_OSCCTRL0_OFFSET), + SAM_SCIF_UNLOCK); + putreg32(regval, SAM_SCIF_OSCCTRL0); + + /* Wait for OSC0 to be ready */ + + while (getreg32(SAM_SCIF_PCLKSR) & SCIF_INT_OSC0RDY) == 0); +} +#endif + +/**************************************************************************** * Name: sam_enableosc32 * * Description: - * Initialiaze the 32KHz oscillator. This oscillator is used by the RTC - * logic to provide the sysem timer. + * Initialiaze the 32KHz oscillator per settings in the board.h header + * file. * ****************************************************************************/ -#ifdef SAM_CLOCK_OSC32 +#ifdef NEED_OSC32K static inline void sam_enableosc32(void) { uint32_t regval; - /* Select the 32KHz oscillator crystal */ + /* Set up the OSCCTRL32 register using settings from the board.h file. + * Also enable the oscillator and provide bother the 32KHz and 1KHz output. + */ - regval = getreg32(SAM_PM_OSCCTRL32); - regval &= ~PM_OSCCTRL32_MODE_MASK; - regval |= PM_OSCCTRL32_MODE_XTAL; - putreg32(regval, SAM_PM_OSCCTRL32); + regval = SAM_OSC32_STARTUP_VALUE | BOARD_OSC32_SELCURR | SAM_OSC32_MODE_VALUE | + BSCIF_OSCCTRL32_EN1K | BSCIF_OSCCTRL32_EN32K | + BSCIF_OSCCTRL32_OSC32EN; - /* Enable the 32-kHz clock */ + putreg32(BSCIF_UNLOCK_KEY(0xaa) | BSCIF_UNLOCK_ADDR(SAM_BSCIF_OSCCTRL32_OFFSET), + SAM_BSCIF_UNLOCK); + putreg32(regval, SAM_BSCIF_OSCCTRL32); - regval = getreg32(SAM_PM_OSCCTRL32); - regval &= ~PM_OSCCTRL32_STARTUP_MASK; - regval |= PM_OSCCTRL32_EN|(SAM_OSC32STARTUP << PM_OSCCTRL32_STARTUP_SHIFT); - putreg32(regval, SAM_PM_OSCCTRL32); + /* Wait for OSC32 to be ready */ + + while ((getreg32(SAM_BSCIF_PCLKSR) & BSCIF_INT_OSC32RDY) == 0); } #endif /**************************************************************************** - * Name: sam_enableosc0 + * Name: sam_enablerc80m * * Description: - * Initialiaze OSC0 settings per the definitions in the board.h file. + * Initialiaze the 80 MHz RC oscillator per settings in the board.h header + * file. * ****************************************************************************/ -#ifdef NEED_OSC0 -static inline void sam_enableosc0(void) +#ifdef NEED_RC80M +static inline void sam_enablerc80m(void) { uint32_t regval; - /* Enable OSC0 in the correct crystal mode by setting the mode value in OSCCTRL0 */ + /* Configure and enable RC80M */ - regval = getreg32(SAM_PM_OSCCTRL0); - regval &= ~PM_OSCCTRL_MODE_MASK; -#if SAM_FOSC0 < 900000 - regval |= PM_OSCCTRL_MODE_XTALp9; /* Crystal XIN 0.4-0.9MHz */ -#elif SAM_FOSC0 < 3000000 - regval |= PM_OSCCTRL_MODE_XTAL3; /* Crystal XIN 0.9-3.0MHz */ -#elif SAM_FOSC0 < 8000000 - regval |= PM_OSCCTRL_MODE_XTAL8; /* Crystal XIN 3.0-8.0MHz */ -#else - regval |= PM_OSCCTRL_MODE_XTALHI; /* Crystal XIN above 8.0MHz */ + regval = getreg32(SAM_SCIF_RC80MCR); + putreg32(SCIF_UNLOCK_KEY(0xaa) | SCIF_UNLOCK_ADDR(SAM_SCIF_RC80MCR_OFFSET), + SAM_SCIF_UNLOCK); + putreg32(regval | SCIF_RC80MCR_EN, SAM_SCIF_RC80MCR); + + /* Wait for OSC32 to be ready */ + + while (getreg32(SAM_SCIF_RC80MCR) & SCIF_RC80MCR_EN) == 0); +} #endif - putreg32(regval, SAM_PM_OSCCTRL0); - /* Enable OSC0 using the startup time provided in board.h. This startup time - * is critical and depends on the characteristics of the crystal. - */ +/**************************************************************************** + * Name: sam_enablerc80m + * + * Description: + * Initialiaze the 12/8/4 RC fast oscillator per settings in the board.h + * header file. + * + ****************************************************************************/ - regval = getreg32(SAM_PM_OSCCTRL0); - regval &= ~PM_OSCCTRL_STARTUP_MASK; - regval |= (SAM_OSC0STARTUP << PM_OSCCTRL_STARTUP_SHIFT); - putreg32(regval, SAM_PM_OSCCTRL0); +#ifdef NEED_RCFAST +static inline void sam_enablercfast(void) +{ + uint32_t regval; - /* Enable OSC0 */ + /* Configure and enable RCFAST */ - regval = getreg32(SAM_PM_MCCTRL); - regval |= PM_MCCTRL_OSC0EN; - putreg32(regval, SAM_PM_MCCTRL); + regval = getreg32(SAM_SCIF_RCFASTCFG); + regval &= ~SCIF_RCFASTCFG_FRANGE_MASK; + regval |= (SAM_RCFAST_RANGE | SCIF_RCFASTCFG_EN); - /* Wait for OSC0 to be ready */ + putreg32(SCIF_UNLOCK_KEY(0xaa) | SCIF_UNLOCK_ADDR(SAM_SCIF_RCFASTCFG_OFFSET), + SAM_SCIF_UNLOCK); + putreg32(regval, SAM_SCIF_RCFASTCFG); + + /* Wait for RCFAST to be ready */ - while ((getreg32(SAM_PM_POSCSR) & PM_POSCSR_OSC0RDY) == 0); + while (getreg32(SAM_SCIF_RCFASTCFG) & SCIF_RCFASTCFG_EN) == 0); } #endif /**************************************************************************** - * Name: sam_enableosc1 + * Name: sam_enablerc1m * * Description: - * Initialiaze OSC0 settings per the definitions in the board.h file. + * Initialiaze the 1M RC oscillator per settings in the board.h header + * file. * ****************************************************************************/ -#ifdef NEED_OSC1 -static inline void sam_enableosc1(void) +#ifdef NEED_RC1M +static inline void sam_enablerc1m(void) { uint32_t regval; - /* Enable OSC1 in the correct crystal mode by setting the mode value in OSCCTRL1 */ + /* Configure and enable RC1M */ - regval = getreg32(SAM_PM_OSCCTRL1); - regval &= ~PM_OSCCTRL_MODE_MASK; -#if SAM_FOSC1 < 900000 - regval |= PM_OSCCTRL_MODE_XTALp9; /* Crystal XIN 0.4-0.9MHz */ -#elif SAM_FOSC1 < 3000000 - regval |= PM_OSCCTRL_MODE_XTAL3; /* Crystal XIN 0.9-3.0MHz */ -#elif SAM_FOSC1 < 8000000 - regval |= PM_OSCCTRL_MODE_XTAL8; /* Crystal XIN 3.0-8.0MHz */ -#else - regval |= PM_OSCCTRL_MODE_XTALHI; /* Crystal XIN above 8.0MHz */ + regval = getreg32(SAM_BSCIF_RC1MCR); + regval &= ~BSCIF_RCFASTCFG_FRANGE_MASK; + regval |= (SAM_RCFAST_RANGE | BSCIF_RCFASTCFG_EN); + + putreg32(BSCIF_UNLOCK_KEY(0xaa) | BSCIF_UNLOCK_ADDR(SAM_BSCIF_RC1MCR_OFFSET), + SAM_BSCIF_UNLOCK); + putreg32(regval | BSCIF_RC1MCR_CLKOEN, SAM_BSCIF_RC1MCR); + + /* Wait for RCFAST to be ready */ + + while (getreg32(SAM_BSCIF_RC1MCR) & BSCIF_RC1MCR_CLKOEN) == 0); +} #endif - putreg32(regval, SAM_PM_OSCCTRL1); - /* Enable OSC1 using the startup time provided in board.h. This startup time - * is critical and depends on the characteristics of the crystal. - */ +/**************************************************************************** + * Name: sam_enablerc32k + * + * Description: + * Initialiaze the 23KHz RC oscillator per settings in the board.h header + * file. + * + ****************************************************************************/ - regval = getreg32(SAM_PM_OSCCTRL1); - regval &= ~PM_OSCCTRL_STARTUP_MASK; - regval |= (SAM_OSC1STARTUP << PM_OSCCTRL_STARTUP_SHIFT); - putreg32(regval, SAM_PM_OSCCTRL1); +#ifdef NEED_RC32K +static inline void sam_enablerc32k(void) +{ + uint32_t regval; - /* Enable OSC1 */ + /* Configure and enable RC32K */ - regval = getreg32(SAM_PM_MCCTRL); - regval |= PM_MCCTRL_OSC1EN; - putreg32(regval, SAM_PM_MCCTRL); + regval = getreg32(SAM_BSCIF_RC32KCR); + putreg32(BSCIF_UNLOCK_KEY(0xaa) | BSCIF_UNLOCK_ADDR(SAM_BSCIF_RC32KCR_OFFSET), + SAM_BSCIF_UNLOCK); + putreg32(regval | BSCIF_RC32KCR_EN32K | BSCIF_RC32KCR_EN, SAM_BSCIF_RC32KCR); - /* Wait for OSC1 to be ready */ + /* Wait for RCFAST to be ready */ - while ((getreg32(SAM_PM_POSCSR) & PM_POSCSR_OSC1RDY) == 0); + while (getreg32(SAM_BSCIF_RC32KCR) & BSCIF_RC32KCR_EN) == 0); } #endif /**************************************************************************** - * Name: sam_enablepll0 + * Name: sam_enableglck9 + * + * Description: + * Enable GLCK9. + * + ****************************************************************************/ + +#ifdef NEED_GLCK9 +static inline void sam_enableglck9(void) +{ + /* Enable the generic clock using the source specified in the board.h + * file. No division is used so that the GCLK9 frequency is the same + * as the source frequency. + */ + + putreg32(SAM_GCLK9_SOURCE_VALUE | SCIF_GCCTRL_CEN, SAM_SCIF_GCCTRL9); +} +#endif + +/**************************************************************************** + * Name: sam_enablepll0 (and its helper sam_pll0putreg()) * * Description: * Initialiaze PLL0 settings per the definitions in the board.h file. * ****************************************************************************/ -#ifdef SAM_CLOCK_PLL0 +#ifdef BOARD_SYSCLK_SOURCE_PLL0 +static inline void sam_pll0putreg(uint32_t regval, uint32_t regaddr, + uint32_t regoffset) +{ + putreg32(SCIF_UNLOCK_KEY(0xaa) | SCIF_UNLOCK_ADDR(regoffset), + SAM_SCIF_UNLOCK); + putreg32(regval, regaddr); +} + static inline void sam_enablepll0(void) { - /* Setup PLL0 */ + uint32_t regval; - regval = (SAM_PLL0_DIV << PM_PLL_PLLDIV_SHIFT) | (SAM_PLL0_MUL << PM_PLL_PLLMUL_SHIFT) | (16 << PM_PLL_PLLCOUNT_SHIFT) + /* Clear the PLL0 control register */ - /* Select PLL0/1 oscillator */ + sam_pll0putreg(0, SAM_SCIF_PLL0, SAM_SCIF_PLL0_OFFSET); -#if SAM_CLOCK_PLL_OSC1 - regval |= PM_PLL_PLLOSC; -#endif + /* Write the selected options */ - putreg32(regval, SAM_PM_PLL0); + regval = getreg32(SAM_SCIF_PLL0); + regval &= SCIF_PLL0_PLLOPT_MASK; + regval |= SAM_PLL0_OPTIONS; + sam_pll0putreg(regval, SAM_SCIF_PLL0, SAM_SCIF_PLL0_OFFSET); - /* Set PLL0 options */ + /* Set up the multiers and dividers */ - regval = getreg32(SAM_PM_PLL0); - regval &= ~PM_PLL_PLLOPT_MASK -#if SAM_PLL0_FREQ < 160000000 - regval |= PM_PLL_PLLOPT_VCO; -#endif -#if SAM_PLL0_DIV2 != 0 - regval |= PM_PLL_PLLOPT_XTRADIV; -#endif -#if SAM_PLL0_WBWM != 0 - regval |= PM_PLL_PLLOPT_WBWDIS; -#endif - putreg32(regval, SAM_PM_PLL0) + regval = getreg32(SAM_SCIF_PLL0); + regval &= ~(SCIF_PLL0_PLLOSC_MASK | SCIF_PLL0_PLLDIV_MASK | SCIF_PLL0_PLLMUL_MASK); + regval |= ((SAM_PLL0_MUL - 1) << SCIF_PLL0_PLLMUL_SHIFT) | + (BOARD_DFLL0_DIV << SCIF_PLL0_PLLDIV_SHIFT) | + SCIF_PLL0_PLLCOUNT_MAX | SAM_PLL0_SOURCE; + sam_pll0putreg(regval, SAM_SCIF_PLL0, SAM_SCIF_PLL0_OFFSET); - /* Enable PLL0 */ + /* And, finally, enable PLL0 */ - regval = getreg32(SAM_PM_PLL0); - regval |= PM_PLL_PLLEN; - putreg32(regval, SAM_PM_PLL0) + regval = getreg32(SAM_SCIF_PLL0); + regval |= SCIF_PLL_PLLEN; + sam_pll0putreg(regval, SAM_SCIF_PLL0, SAM_SCIF_PLL0_OFFSET); - /* Wait for PLL0 locked. */ + /* Wait for PLL0 to become locked */ - while ((getreg32(SAM_PM_POSCSR) & PM_POSCSR_LOCK0) == 0); + while ((getreg32(SAM_SCIF_PCLKSR) & SCIF_INT_PLL0LOCK) == 0); } #endif /**************************************************************************** - * Name: sam_enablepll1 + * Name: sam_enabledfll0 (and its helper sam_dfll0_putreg32()) * * Description: - * Initialiaze PLL1 settings per the definitions in the board.h file. + * Initialiaze DFLL0 settings per the definitions in the board.h file. * ****************************************************************************/ -#ifdef SAM_CLOCK_PLL1 -static inline void sam_enablepll1(void) +#ifdef BOARD_SYSCLK_SOURCE_DFLL0 +static inline void sam_dfll0_putreg32(uint32_t regval, uint32_t regaddr, + uint32_t regoffset) { - /* Setup PLL1 */ + /* Wait until DFLL0 is completes the last setting */ - regval = (SAM_PLL1_DIV << PM_PLL_PLLDIV_SHIFT) | (SAM_PLL1_MUL << PM_PLL_PLLMUL_SHIFT) | (16 << PM_PLL_PLLCOUNT_SHIFT) + while ((getreg32(SAM_SCIF_PCLKSR) & SCIF_INT_DFLL0RDY) == 0); - /* Select PLL0/1 oscillator */ + /* Then unlock the register and write the next value */ -#if SAM_CLOCK_PLL_OSC1 - regval |= PM_PLL_PLLOSC; -#endif + putreg32(SCIF_UNLOCK_KEY(0xaa) | SCIF_UNLOCK_ADDR(regoffset), + SAM_SCIF_UNLOCK); + putreg32(regval, regaddr); +} - putreg32(regval, SAM_PM_PLL1); +static inline void sam_enabledfll0(void) +{ + uint32_t regval; + uint32_t conf; - /* Set PLL1 options */ + /* Set up generic clock source with specified reference clock + * and divider. + */ - regval = getreg32(SAM_PM_PLL1); - regval &= ~PM_PLL_PLLOPT_MASK -#if SAM_PLL1_FREQ < 160000000 - regval |= PM_PLL_PLLOPT_VCO; -#endif -#if SAM_PLL1_DIV2 != 0 - regval |= PM_PLL_PLLOPT_XTRADIV; + putreg32(0, SAM_SCIF_GCCTRL0); + + /* Set the generic clock 0 source */ + + regval = getreg32(SAM_SCIF_GCCTRL0); + regval &= ~SCIF_GCCTRL_OSCSEL_MASK; + regval |= SAM_DFLLO_REFCLK; + putreg32(regval, SAM_SCIF_GCCTRL0); + + /* Get the generic clock 0 divider */ + + regval = getreg32(SAM_SCIF_GCCTRL0); + regval &= ~(SCIF_GCCTRL_DIVEN | SCIF_GCCTRL_DIV_MASK); + +#if BOARD_DFLL0_DIV > 1 + regval |= SCIF_GCCTRL_DIVEN; + regval |= SCIF_GCCTRL_DIV(((BOARD_DFLL0_DIV + 1) / 2) - 1); #endif -#if SAM_PLL1_WBWM != 0 - regval |= PM_PLL_PLLOPT_WBWDIS; + + putreg32(regval, SAM_SCIF_GCCTRL0); + + /* Sync before reading a dfll conf register */ + + putreg32(SCIF_DFLL0SYNC_SYNC, SAM_SCIF_DFLL0SYNC); + while ((getreg32(SAM_SCIF_PCLKSR) & SCIF_INT_DFLL0RDY) == 0); + + /* Select Closed Loop Mode */ + + conf = getreg32(SAM_SCIF_DFLL0CONF); + conf &= ~SCIF_DFLL0CONF_RANGE_MASK; + conf |= SCIF_DFLL0CONF_MODE; + + /* Select the DFLL0 Frequency Range */ + +#if BOARD_DFLL0_FREQUENCY < SCIF_DFLL0CONF_MAX_RANGE3 + conf |= SCIF_DFLL0CONF_RANGE3; +#elif BOARD_DFLL0_FREQUENCY < SCIF_DFLL0CONF_MAX_RANGE2 + conf |= SCIF_DFLL0CONF_RANGE2; +#elif BOARD_DFLL0_FREQUENCY < SCIF_DFLL0CONF_MAX_RANGE1 + conf |= SCIF_DFLL0CONF_RANGE1; +#else + conf |= SCIF_DFLL0CONF_RANGE0; #endif - putreg32(regval, SAM_PM_PLL1) - /* Enable PLL1 */ + /* Enable the reference generic clock 0 */ + + regval = getreg32(SAM_SCIF_GCCTRL0); + regval |= SCIF_GCCTRL_CEN; + putreg32(regval, SAM_SCIF_GCCTRL0); + + /* Enable DFLL0. Here we assume DFLL0RDY because the DFLL was disabled + * before this function was called. + */ + + putreg32(SCIF_UNLOCK_KEY(0xaa) | SCIF_UNLOCK_ADDR(SAM_SCIF_DFLL0CONF_OFFSET), + SAM_SCIF_UNLOCK); + putreg32(SCIF_DFLL0CONF_EN, SAM_SCIF_DFLL0CONF); + + /* Configure DFLL0. Note that now we do have to wait for DFLL0RDY before + * every write. + * + * Set the initial coarse and fine step lengths to 4. If this is set + * too high, DFLL0 may fail to lock. + */ + + sam_dfll0_putreg32(SCIF_DFLL0STEP_CSTEP(4) | SCIF_DFLL0STEP_FSTEP(4), + SAM_SCIF_DFLL0STEP, + SAM_SCIF_DFLL0STEP_OFFSET); + + /* Set the DFLL0 multipler register */ - regval = getreg32(SAM_PM_PLL1); - regval |= PM_PLL_PLLEN; - putreg32(regval, SAM_PM_PLL1) + sam_dfll0_putreg32(BOARD_DFLL0_MUL, SAM_SCIF_DFLL0MUL, + SAM_SCIF_DFLL0MUL_OFFSET); - /* Wait for PLL1 locked. */ + /* Set the multipler and spread spectrum generator control registers */ - while ((getreg32(SAM_PM_POSCSR) & PM_POSCSR_LOCK1) == 0); + sam_dfll0_putreg32(0, SAM_SCIF_DFLL0SSG, SAM_SCIF_DFLL0SSG_OFFSET); + + /* Finally, set the DFLL0 configuration */ + + sam_dfll0_putreg32(conf | SCIF_DFLL0CONF_EN, + SAM_SCIF_DFLL0CONF, SAM_SCIF_DFLL0CONF_OFFSET); + + /* Wait until we are locked on the fine value */ + + while ((getreg32(SAM_SCIF_PCLKSR) & SCIF_INT_DFLL0LOCKF) == 0); } #endif @@ -349,49 +857,47 @@ static inline void sam_enablepll1(void) * ****************************************************************************/ -static inline void sam_setdividers(uint32_t cpudiv, uint32_t pbadiv, - uint32_t pbbdiv, uint32_t pbcdiv, - uint32_t pbddiv) +static inline void sam_setdividers(void) { - irqstate_t flags; - uint32_t cpusel = 0; - uint32_t pbasel = 0; - uint32_t pbbsel = 0; - uint32_t pbcsel = 0; - uint32_t pbdsel = 0; + uint32_t cpusel; + uint32_t pbasel; + uint32_t pbbsel; + uint32_t pbcsel; + uint32_t pbdsel; /* Get the register setting for each divider value */ - if (cpudiv > 0) - { - cpusel = (PM_CPUSEL(cpudiv - 1)) | PM_CPUSEL_DIV; - } - - if (pbadiv > 0) - { - pbasel = (PM_PBSEL(pbadiv - 1)) | PM_PBSEL_DIV; - } +#if BOARD_CPU_SHIFT > 0 + cpusel = (PM_CPUSEL(BOARD_CPU_SHIFT - 1)) | PM_CPUSEL_DIV; +#else + cpusel = 0; +#endif - if (pbbdiv > 0) - { - pbbsel = (PM_PBSEL(pbbdiv - 1)) | PM_PBSEL_DIV; - } +#if BOARD_PBA_SHIFT > 0 + pbasel = (PM_PBSEL(BOARD_PBA_SHIFT - 1)) | PM_PBSEL_DIV; +#else + pbasel = 0; +#endif - if (pbcdiv > 0) - { - pbcsel = (PM_PBSEL(pbcdiv - 1)) | PM_PBSEL_DIV; - } +#if BOARD_PBB_SHIFT >0 + pbbsel = (PM_PBSEL(BOARD_PBB_SHIFT - 1)) | PM_PBSEL_DIV; +#else + pbbsel = 0; +#endif - if (pbddiv > 0) - { - pbdsel = (PM_PBSEL(pbddiv - 1)) | PM_PBSEL_DIV; - } +#if BOARD_PBC_SHIFT > 0 + pbcsel = (PM_PBSEL(BOARD_PBC_SHIFT - 1)) | PM_PBSEL_DIV; +#else + pbcsel = 0; +#endif - /* Then set the divider values. The following operations need to be atomic - * for the unlock-write sequeuences. - */ +#if BOARD_PBD_SHIFT > 0 + pbdsel = (PM_PBSEL(BOARD_PBD_SHIFT - 1)) | PM_PBSEL_DIV; +#else + pbdsel = 0; +#endif - flags = irqsave(); + /* Then set the divider values. */ putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_CPUSEL_OFFSET), SAM_PM_UNLOCK); putreg32(cpusel, SAM_PM_CPUSEL); @@ -407,24 +913,46 @@ static inline void sam_setdividers(uint32_t cpudiv, uint32_t pbadiv, putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBDSEL_OFFSET), SAM_PM_UNLOCK); putreg32(pbdsel, SAM_PM_PBDSEL); +} + +/**************************************************************************** + * Name: sam_enable_fastwakeup + * + * Description: + * Enable FLASH fast wakeup mode. + * + ****************************************************************************/ + +static inline void sam_enable_fastwakeup(void) +{ + uint32_t regval; - irqrestore(flags); + regval = getreg32(SAM_BPM_PMCON); + regval |= BPM_PMCON_FASTWKUP; + putreg32(BPM_UNLOCK_KEY(0xaa) | BPM_UNLOCK_ADDR(SAM_BPM_PMCON_OFFSET), + SAM_BPM_UNLOCK); + putreg32(regval, SAM_BPM_PMCON); } /**************************************************************************** - * Name: sam_fws + * Name: set_flash_waitstate * * Description: - * Setup FLASH wait states. + * Setup one or two FLASH wait states. * ****************************************************************************/ -static void sam_fws(uint32_t cpuclock) +static inline void set_flash_waitstate(bool waitstate) { uint32_t regval; + /* Set or clear the FLASH wait state (FWS) bit in the FLASH control + * register (FCR). + */ + regval = getreg32(SAM_FLASHCALW_FCR); - if (cpuclock > SAM_FLASHCALW_FWS0_MAXFREQ) + + if (waitstate) { regval |= FLASHCALW_FCR_FWS; } @@ -437,6 +965,157 @@ static void sam_fws(uint32_t cpuclock) } /**************************************************************************** + * Name: sam_flash_readmode + * + * Description: + * Send a FLASH command to enable to disable high speed FLASH read mode. + * + ****************************************************************************/ + +static inline void sam_flash_readmode(uint32_t command) +{ + uint32_t regval; + + /* Make sure that any previous FLASH operation is completed */ + + while ((getreg32(SAM_FLASHCALW_FSR) & FLASHCALW_FSR_FRDY) == 0); + + /* Write the specified FLASH command to the FCMD register */ + + regval = getreg32(SAM_FLASHCALW_FCMD); + regval &= ~FLASHCALW_FCMD_CMD_MASK; + regval |= (FLASHCALW_FCMD_KEY | command); + putreg32(regval, SAM_FLASHCALW_FCMD); + + /* Wait for this FLASH operation to complete */ + + while ((getreg32(SAM_FLASHCALW_FSR) & FLASHCALW_FSR_FRDY) == 0); +} + +/**************************************************************************** + * Name: sam_flash_config + * + * Description: + * Configure FLASH read mode and wait states. + * + * Maximum CPU frequency for 0 and 1 FLASH wait states (FWS) in various modes + * (Table 42-30 in the big data sheet). + * + * ------- ------------------- ---------- ---------- + * Power Flash Read Mode Flash Maximum + * Sclaing Wait Operating + * Mode HSEN HSDIS FASTWKUP States Frequency + * ------- ---- ----- -------- ---------- ---------- + * PS0 X X 1 12MHz + * " " X 0 18MHz + * " " X 1 36MHz + * PS1 X X 1 12MHz + * " " X 0 8MHz + * " " X 1 12MHz + * PS2 X 0 24Mhz + * " " X 1 48MHz + * ------- ---- ----- -------- ---------- ---------- + * + ****************************************************************************/ + +static inline void sam_flash_config(uint32_t cpuclock, uint32_t psm, bool fastwkup) +{ + bool waitstate; + uint32_t command; + +#ifdef CONFIG_SAM34_FLASH_HSEN + /* High speed flash read mode (with power scaling mode == 2). Set one + * wait state if the CPU clock frequency exceeds the threshold value + * and enable high speed read mode. + */ + + waitstate = (cpuclock > FLASH_MAXFREQ_PS2_HSEN_FWS0); + command = FLASHCALW_FCMD_CMD_HSEN; +#else + /* Assume that we will select no wait states and that we will disable high- + * speed read mode. + */ + + waitstate = false; + command = FLASHCALW_FCMD_CMD_HSDIS; + + /* Handle power scaling mode == 0 FLASH configuration */ + + if (psm == 0) + { + /* Power scaling mode 0. We need to set wait state the CPU clock if + * the CPU frequency exceeds a threshold. + */ + + if (cpuclock > FLASH_MAXFREQ_PS0_HSDIS_FWS0) + { + /* Set one wait state */ + + waitstate = true; + + /* Enable high speed read mode if the frequency exceed the maximum + * for the low speed configuration. This mode is not documented + * in the data sheet, but I see that they do this in some Atmel + * code examples. + */ + + if (cpuclock > FLASH_MAXFREQ_PS0_HSDIS_FWS1) + { + /* Enable high speed read mode. */ + + command = FLASHCALW_FCMD_CMD_HSEN; + } + } + + /* The is below the threshold that requires one wait state. But we + * have to check a few more things. + */ + + else + { + /* If FLASH wake-up mode is selected and the we are in the lower + * operating frequency for this mode, then set 1 waitate and + * disable high speed read mode. + */ + + if ((fastwkup == true) && + (cpuclock <= FLASH_MAXFREQ_PS1_HSDIS_FASTWKUP_FWS1)) + { + /* Set one wait state */ + + waitstate = true; + } + } + } + + /* Otherwise, this is power scaling mode 1 */ + + else /* if (psm == 1) */ + { + /* If we are in the lower operating frequency range, then select + * zero wait states. Otherwise, select one wait state. + */ + + if (cpuclock > FLASH_MAXFREQ_PS1_HSDIS_FWS0) + { + /* Set one wait state */ + + waitstate = true; + } + } + +#endif + + /* Set 0 or 1 waitstates */ + + set_flash_waitstate(waitstate); + + /* Enable/disable the high-speed read mode. */ + + sam_flash_readmode(command); +} + +/**************************************************************************** * Name: sam_mainclk * * Description: @@ -451,10 +1130,51 @@ static inline void sam_mainclk(uint32_t mcsel) regval = getreg32(SAM_PM_MCCTRL); regval &= ~PM_MCCTRL_MCSEL_MASK; regval |= mcsel; + + putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_MCCTRL_OFFSET), + SAM_PM_UNLOCK); putreg32(regval, SAM_PM_MCCTRL); } /**************************************************************************** + * Name: sam_setpsm (and its helper, sam_instantiatepsm()) + * + * Description: + * Switch to the selected power scaling mode. + * + ****************************************************************************/ + +static __ramfunc__ void sam_instantiatepsm(uint32_t regval) +{ + /* Set the BMP PCOM register (containing the new power scaling mode) */ + + putreg32(BPM_UNLOCK_KEY(0xaa) | BPM_UNLOCK_ADDR(SAM_BPM_PMCON_OFFSET), + SAM_BPM_UNLOCK); + putreg32(regval, SAM_BPM_PMCON); + + /* Wait for new power scaling mode to become active. There should be + * timeout on this wait. + */ + + while ((getreg32(SAM_BPM_SR) & BPM_INT_PSOK) == 0); +} + +static inline void sam_setpsm(uint32_t psm) +{ + uint32_t regval; + + /* Setup the PMCON register content fo the new power scaling mode */ + + regval = getreg32(SAM_BPM_PMCON); + regval &= ~BPM_PMCON_PS_MASK; + regval |= (psm | BPM_PMCON_PSCM | BPM_PMCON_PSCREQ); + + /* Then call the RAMFUNC sam_setpsm() to set the new power scaling mode */ + + sam_instantiatepsm(regval); +} + +/**************************************************************************** * Name: sam_usbclock * * Description: @@ -505,67 +1225,210 @@ static inline void sam_usbclock(void) void sam_clockconfig(void) { + uint32_t psm; + bool fastwkup; + /* Enable clocking to the PICOCACHE */ sam_picocache(); - /* Configure dividers derived clocks. These divider definitions must be - * provided in the board.h header file. + /* Configure dividers for derived clocks. These divider definitions must + * be provided in the board.h header file. */ - sam_setdividers(BOARD_SYSCLK_CPU_DIV, BOARD_SYSCLK_PBA_DIV, - BOARD_SYSCLK_PBB_DIV, BOARD_SYSCLK_PBC_DIV, - BOARD_SYSCLK_PBD_DIV); + sam_setdividers(); + + /* Select a power scaling mode and possible fast wakeup so that we get the + * best possible flash performance. The following table shows the maximum + * CPU frequency for 0 and 1 FLASH wait states (FWS) in various modes + * (Table 42-30 in the big data sheet). + * + * ------- ------------------- ---------- ---------- + * Power Flash Read Mode Flash Maximum + * Sclaing Wait Operating + * Mode HSEN HSDIS FASTWKUP States Frequency + * ------- ---- ----- -------- ---------- ---------- + * PS0 X X 1 12MHz + * " " X 0 18MHz + * " " X 1 36MHz + * PS1 X X 1 12MHz + * " " X 0 8MHz + * " " X 1 12MHz + * PS2 X 0 24Mhz + * " " X 1 48MHz + * ------- ---- ----- -------- ---------- ---------- + */ -#ifdef SAM_CLOCK_OSC32 - /* Enable the 32KHz oscillator (need by the RTC module) */ +#ifdef CONFIG_SAM34_FLASH_HSEN + /* The high speed FLASH mode has been enabled. Select power scaling + * mode 2, no fast wakeup. + */ - sam_enableosc32(); + psm = BPM_PMCON_PS2; + fastwkup = false; + +#elif BOARD_CPU_FREQUENCY <= FLASH_MAXFREQ_PS1_HSDIS_FWS1 + /* Not high speed mode and frequency is below the thrshold. We can go to + * power scaling mode 1. + */ + + psm = BPM_PMCON_PS1; + +# if BOARD_CPU_FREQUENCY > FLASH_MAXFREQ_PS1_HSDIS_FWS0 + /* We need to enable fast wakeup */ + + sam_enable_fastwakeup() + fastwkup = true; +# endif +#else + /* Power scaling mode 0, disable high speed mode, no fast wakeup */ + + psm = BPM_PMCON_PS0; + fastwkup = false; #endif -#ifdef NEED_OSC0 + /* Enable clock sources: + * + * OSC0: Might by the system clock or the source clock for PLL0 or DFLL0 + * OSC32: Might be source clock for DFLL0 + */ + +#if NEED_OSC0 /* Enable OSC0 using the settings in board.h */ sam_enableosc0(); +#endif - /* Set up FLASH wait states */ +#ifdef NEED_OSC32K + /* Enable the 32KHz oscillator using the settings in board.h */ - sam_fws(SAM_FOSC0); + sam_enableosc32(); +#endif - /* Then switch the main clock to OSC0 */ +#ifdef NEED_RC80M + /* Enable the 32KHz oscillator using the settings in board.h */ - sam_mainclk(PM_MCCTRL_MCSEL_OSC0); + sam_enablerc80m(); +#endif + +#ifdef NEED_RCFAST + /* Enable the 12/8/4MHz RC fast oscillator using the settings in board.h */ + + sam_enablercrcfast(); +#endif + +#ifdef NEED_RC1M + /* Enable the 1MHz RC oscillator using the settings in board.h */ + + sam_enablerc1m(); +#endif + +#ifdef NEED_RC32K + /* Enable the 32KHz RC oscillator using the settings in board.h */ + + sam_enablerc32k(); #endif -#ifdef NEED_OSC1 - /* Enable OSC1 using the settings in board.h */ +#ifdef NEED_GLCK9 + /* Enable the GLCK9 */ - sam_enableosc1(); + sam_enableglck9(); #endif -#ifdef SAM_CLOCK_PLL0 + /* Switch to the system clock selected by the settings in the board.h + * header file. + */ + +#if defined(BOARD_SYSCLK_SOURCE_RCSYS) + /* Since this function only executes at power up, we know that we are + * already running from RCSYS. + */ + + // sam_mainclk(PM_MCCTRL_MCSEL_RCSYS); +#elif defined(BOARD_SYSCLK_SOURCE_OSC0) + + /* Configure FLASH read mode and wait states */ + + sam_flash_config(BOARD_CPU_FREQUENCY, psm, fastwkup); + + /* Then switch the main clock to OSC0 */ + + sam_mainclk(PM_MCCTRL_MCSEL_OSC0); + +#elif defined(BOARD_SYSCLK_SOURCE_PLL0) + /* Enable PLL0 using the settings in board.h */ sam_enablepll0(); - /* Set up FLASH wait states */ + /* Configure FLASH read mode and wait states */ - sam_fws(SAM_CPU_CLOCK); + sam_flash_config(BOARD_CPU_FREQUENCY, psm, fastwkup); /* Then switch the main clock to PLL0 */ - sam_mainclk(PM_MCCTRL_MCSEL_PLL0); -#endif + sam_mainclk(PM_MCCTRL_MCSEL_PLL); + +#elif defined(BOARD_SYSCLK_SOURCE_DFLL0) + + /* Enable PLL0 using the settings in board.h */ + + sam_enabledfll0(); + + /* Configure FLASH read mode and wait states */ + + sam_flash_config(BOARD_CPU_FREQUENCY, psm, fastwkup); -#ifdef SAM_CLOCK_PLL1 - /* Enable PLL1 using the settings in board.h */ + /* Then switch the main clock to DFLL0 */ - sam_enablepll1(); + sam_mainclk(PM_MCCTRL_MCSEL_DFLL); + +#elif defined(BOARD_SYSCLK_SOURCE_RC80M) + + /* Configure FLASH read mode and wait states */ + + sam_flash_config(BOARD_CPU_FREQUENCY, psm, fastwkup); + + /* Then switch the main clock to RCM80 */ + + sam_mainclk(PM_MCCTRL_MCSEL_RC80M); + +#elif defined(BOARD_SYSCLK_SOURCE_FCFAST12M) || defined(BOARD_SYSCLK_SOURCE_FCFAST8M) || \ + defined(BOARD_SYSCLK_SOURCE_FCFAST4M) + + /* Configure FLASH read mode and wait states */ + + sam_flash_config(BOARD_CPU_FREQUENCY, psm, fastwkup); + + /* Then switch the main clock to RCFAST */ + + sam_mainclk(PM_MCCTRL_MCSEL_RCFAST); + +#elif defined(BOARD_SYSCLK_SOURCE_RC1M) + + /* Configure FLASH read mode and wait states */ + + sam_flash_config(BOARD_CPU_FREQUENCY, psm, fastwkup); + + /* Then switch the main clock to RC1M */ + + sam_mainclk(PM_MCCTRL_MCSEL_RC1M); + +#else +# error "No SYSCLK source provided" #endif - /* Set up the USBB GCLK */ + /* Switch to the selected power scaling mode */ + + sam_setpsm(psm); + + /* Enable all selected peripheral cloks */ + + sam_init_periphclks(); + + /* Configure clocking to the USB controller */ #ifdef CONFIG_USBDEV - void sam_usbclock(); + sam_usbc_enableclk(); #endif } diff --git a/nuttx/arch/arm/src/sam34/sam4l_periphclks.c b/nuttx/arch/arm/src/sam34/sam4l_periphclks.c index abd766695..2c55ab6b0 100644 --- a/nuttx/arch/arm/src/sam34/sam4l_periphclks.c +++ b/nuttx/arch/arm/src/sam34/sam4l_periphclks.c @@ -52,8 +52,23 @@ #include "sam4l_periphclks.h" /**************************************************************************** - * Private Definitions + * Pre-processor Definitions ****************************************************************************/ +/* USBC source clock selection */ + +#ifdef CONFIG_SAM34_USBC +# if defined(BOARD_USBC_SRC_OSC0) +# define SAM_USBC_GCLK_SOURCE SCIF_GCCTRL_OSCSEL_OSC0 +# elif defined(BOARD_USBC_SRC_PLL0) +# define SAM_USBC_GCLK_SOURCE SCIF_GCCTRL_OSCSEL_PLL0 +# elif defined(BOARD_USBC_SRC_DFLL) +# define SAM_USBC_GCLK_SOURCE SCIF_GCCTRL_OSCSEL_DFLL0 +# elif defined(BOARD_USBC_SRC_GCLKIN0) +# define SAM_USBC_GCLK_SOURCE SCIF_GCCTRL_OSCSEL_GCLKIN0 +# else +# error No USBC GCLK7 source clock defined +# endif +#endif /**************************************************************************** * Private Types @@ -76,10 +91,328 @@ ****************************************************************************/ /**************************************************************************** + * Name: sam_init_cpumask + * + * Description: + * Called during boot to enable clocking on selected peripherals in the + * CPU mask register. + * + ****************************************************************************/ + +static inline void sam_init_cpumask(void) +{ + uint32_t mask = 0; + + /* OR in the user selected peripherals */ + +#ifdef CONFIG_SAM32_RESET_PERIPHCLKS +#ifdef CONFIG_SAM34_OCD + mask |= PM_CPUMASK_OCD; /* On-Chip Debug */ +#endif +#endif + + /* Save the new CPU mask */ + + putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_CPUMASK_OFFSET), + SAM_PM_UNLOCK); + putreg32(mask, SAM_PM_CPUMASK); +} + +/**************************************************************************** + * Name: sam_init_hsbmask + * + * Description: + * Called during boot to enable clocking on selected peripherals in the + * HSB mask register. + * + ****************************************************************************/ + +static inline void sam_init_hsbmask(void) +{ + /* Select the non-optional peripherals */ + + uint32_t mask = (PM_HSBMASK_FLASHCALW | PM_HSBMASK_APBB | + PM_HSBMASK_APBC | PM_HSBMASK_APBD); + + /* OR in the user selected peripherals */ + +#ifdef CONFIG_SAM32_RESET_PERIPHCLKS +#ifdef CONFIG_SAM34_PDCA + mask |= PM_HSBMASK_PDCA; /* PDCA */ +#endif +#ifdef CONFIG_SAM34_HRAMC1 + mask |= PM_HSBMASK_HRAMC1; /* HRAMC1 (picoCache RAM) */ +#endif +#ifdef CONFIG_SAM34_USBC + mask |= PM_HSBMASK_USBC; /* USBC */ +#endif +#ifdef CONFIG_SAM34_CRCCU + mask |= PM_HSBMASK_CRCCU; /* CRCCU */ +#endif +#ifdef CONFIG_SAM34_APBA + mask |= PM_HSBMASK_APBA; /* APBA bridge */ +#endif +#ifdef CONFIG_SAM34_AESA + mask |= PM_HSBMASK_AESA; /* AESA */ +#endif +#endif + + /* Save the new HSB mask */ + + putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_HSBMASK_OFFSET), + SAM_PM_UNLOCK); + putreg32(mask, SAM_PM_HSBMASK); +} + +/**************************************************************************** + * Name: sam_init_pbamask + * + * Description: + * Called during boot to enable clocking on selected peripherals in the + * PBA mask register. + * + ****************************************************************************/ + +static inline void sam_init_pbamask(void) +{ + /* Select the non-optional peripherals */ + + uint32_t mask = 0; + uint32_t divmask = 0; + + /* OR in the user selected peripherals */ + +#ifdef CONFIG_SAM32_RESET_PERIPHCLKS +#ifdef CONFIG_SAM34_IISC + mask |= PM_PBAMASK_IISC; /* IISC */ +#endif +#ifdef CONFIG_SAM34_SPI + mask |= PM_PBAMASK_SPI; /* SPI */ +#endif +#ifdef CONFIG_SAM34_TC0 + mask |= PM_PBAMASK_TC0; /* TC0 */ + divmask |= PM_PBADIVMASK_TIMER_CLOCKS; +#endif +#ifdef CONFIG_SAM34_TC1 + mask |= PM_PBAMASK_TC1; /* TC1 */ + divmask |= PM_PBADIVMASK_TIMER_CLOCKS; +#endif +#ifdef CONFIG_SAM34_TWIM0 + mask |= PM_PBAMASK_TWIM0; /* TWIM0 */ +#endif +#ifdef CONFIG_SAM34_TWIS0 + mask |= PM_PBAMASK_TWIS0; /* TWIS0 */ +#endif +#ifdef CONFIG_SAM34_TWIM1 + mask |= PM_PBAMASK_TWIM1; /* TWIM1 */ +#endif +#ifdef CONFIG_SAM34_TWIS1 + mask |= PM_PBAMASK_TWIS1; /* TWIS1 */ +#endif +#ifdef CONFIG_SAM34_USART0 + mask |= PM_PBAMASK_USART0; /* USART0 */ + divmask |= PM_PBADIVMASK_CLK_USART; +#endif +#ifdef CONFIG_SAM34_USART1 + mask |= PM_PBAMASK_USART1; /* USART1 */ + divmask |= PM_PBADIVMASK_CLK_USART; +#endif +#ifdef CONFIG_SAM34_USART2 + mask |= PM_PBAMASK_USART2; /* USART2 */ + divmask |= PM_PBADIVMASK_CLK_USART; +#endif +#ifdef CONFIG_SAM34_USART3 + mask |= PM_PBAMASK_USART3; /* USART3 */ + divmask |= PM_PBADIVMASK_CLK_USART; +#endif +#ifdef CONFIG_SAM34_ADCIFE + mask |= PM_PBAMASK_ADCIFE; /* ADCIFE */ +#endif +#ifdef CONFIG_SAM34_DACC + mask |= PM_PBAMASK_DACC; /* DACC */ +#endif +#ifdef CONFIG_SAM34_ACIFC + mask |= PM_PBAMASK_ACIFC; /* ACIFC */ +#endif +#ifdef CONFIG_SAM34_GLOC + mask |= PM_PBAMASK_GLOC; /* GLOC */ +#endif +#ifdef CONFIG_SAM34_ABDACB + mask |= PM_PBAMASK_ABDACB; /* ABDACB */ +#endif +#ifdef CONFIG_SAM34_TRNG + mask |= PM_PBAMASK_TRNG; /* TRNG */ +#endif +#ifdef CONFIG_SAM34_PARC + mask |= PM_PBAMASK_PARC; /* PARC */ +#endif +#ifdef CONFIG_SAM34_CATB + mask |= PM_PBAMASK_CATB; /* CATB */ +#endif +#ifdef CONFIG_SAM34_TWIM2 + mask |= PM_PBAMASK_TWIM2; /* TWIM2 */ +#endif +#ifdef CONFIG_SAM34_TWIM3 + mask |= PM_PBAMASK_TWIM3; /* TWIM3 */ +#endif +#ifdef CONFIG_SAM34_LCDCA + mask |= PM_PBAMASK_LCDCA; /* LCDCA*/ +#endif +#endif + + /* Save the new PBA mask */ + + putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBAMASK_OFFSET), + SAM_PM_UNLOCK); + putreg32(mask, SAM_PM_PBAMASK); + + /* Set the peripheral divider mask as necessary */ + + putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBADIVMASK_OFFSET), + SAM_PM_UNLOCK); + putreg32(divmask, SAM_PM_PBADIVMASK); +} + +/**************************************************************************** + * Name: sam_init_pbbmask + * + * Description: + * Called during boot to enable clocking on selected peripherals in the + * PBB mask register. + * + ****************************************************************************/ + +static inline void sam_init_pbbmask(void) +{ + /* Select the non-optional peripherals */ + + uint32_t mask = PM_PBBMASK_FLASHCALW; + + /* OR in the user selected peripherals */ + +#ifdef CONFIG_SAM32_RESET_PERIPHCLKS +#ifdef CONFIG_SAM34_HRAMC1 + mask |= PM_PBBMASK_HRAMC1; /* HRAMC1 */ +#endif +#ifdef CONFIG_SAM34_HMATRIX + mask |= PM_PBBMASK_HMATRIX; /* HMATRIX */ +#endif +#ifdef CONFIG_SAM34_PDCA + mask |= PM_PBBMASK_PDCA; /* PDCA */ +#endif +#ifdef CONFIG_SAM34_CRCCU + mask |= PM_PBBMASK_CRCCU; /* CRCCU */ +#endif +#ifdef CONFIG_SAM34_USBC + mask |= PM_PBBMASK_USBC; /* USBC */ +#endif +#ifdef CONFIG_SAM34_PEVC + mask |= PM_PBBMASK_PEVC; /* PEVC */ +#endif +#endif + + /* Save the new PBB mask */ + + putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBBMASK_OFFSET), + SAM_PM_UNLOCK); + putreg32(mask, SAM_PM_PBBMASK); +} + +/**************************************************************************** + * Name: sam_init_pbcmask + * + * Description: + * Called during boot to enable clocking on selected peripherals in the + * PBC mask register. + * + ****************************************************************************/ + +static inline void sam_init_pbcmask(void) +{ + /* Select the non-optional peripherals */ + + uint32_t mask = (PM_PBCMASK_PM | PM_PBCMASK_SCIF | PM_PBCMASK_GPIO); + + /* OR in the user selected peripherals */ + +#ifdef CONFIG_SAM32_RESET_PERIPHCLKS +#ifdef CONFIG_SAM34_CHIPID + mask |= PM_PBCMASK_CHIPID; /* CHIPID */ +#endif +#ifdef CONFIG_SAM34_FREQM + mask |= PM_PBCMASK_FREQM; /* FREQM */ +#endif +#endif + + /* Save the new PBC mask */ + + putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBCMASK_OFFSET), + SAM_PM_UNLOCK); + putreg32(mask, SAM_PM_PBCMASK); +} + +/**************************************************************************** + * Name: sam_init_pbdmask + * + * Description: + * Called during boot to enable clocking on selected peripherals in the + * PBD mask register. + * + ****************************************************************************/ + +static inline void sam_init_pbdmask(void) +{ + /* Select the non-optional peripherals */ + + uint32_t mask = (PM_PBDMASK_BPM | PM_PBDMASK_BSCIF); + + /* OR in the user selected peripherals */ + +#ifdef CONFIG_SAM32_RESET_PERIPHCLKS +#ifdef CONFIG_SAM34_AST + mask |= PM_PBDMASK_AST; /* AST */ +#endif +#ifdef CONFIG_SAM34_WDT + mask |= PM_PBDMASK_WDT; /* WDT */ +#endif +#ifdef CONFIG_SAM34_EIC + mask |= PM_PBDMASK_EIC; /* EIC */ +#endif +#ifdef CONFIG_SAM34_PICOUART + mask |= PM_PBDMASK_PICOUART; /* PICOUART */ +#endif +#endif + + /* Save the new PBD mask */ + + putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBDMASK_OFFSET), + SAM_PM_UNLOCK); + putreg32(mask, SAM_PM_PBDMASK); +} + +/**************************************************************************** * Public Functions ****************************************************************************/ /**************************************************************************** + * Name: sam_init_periphclks + * + * Description: + * Called during boot to enable clocking on all selected peripherals. + * + ****************************************************************************/ + +void sam_init_periphclks(void) +{ + sam_init_cpumask(); + sam_init_hsbmask(); + sam_init_pbamask(); + sam_init_pbbmask(); + sam_init_pbcmask(); + sam_init_pbdmask(); +} + +/**************************************************************************** * Name: sam_modifyperipheral * * Description: @@ -88,7 +421,8 @@ * ****************************************************************************/ -void sam_modifyperipheral(uintptr_t regaddr, uint32_t clrbits, uint32_t setbits) +void sam_modifyperipheral(uintptr_t regaddr, uint32_t clrbits, + uint32_t setbits) { irqstate_t flags; uint32_t regval; @@ -102,7 +436,8 @@ void sam_modifyperipheral(uintptr_t regaddr, uint32_t clrbits, uint32_t setbits) regval = getreg32(regaddr); regval &= ~clrbits; regval |= setbits; - putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(regaddr - SAM_PM_BASE), SAM_PM_UNLOCK); + putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(regaddr - SAM_PM_BASE), + SAM_PM_UNLOCK); putreg32(regval, regaddr); irqrestore(flags); @@ -131,7 +466,8 @@ void sam_pba_modifydivmask(uint32_t clrbits, uint32_t setbits) regval = getreg32(SAM_PM_PBADIVMASK); regval &= ~clrbits; regval |= setbits; - putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBADIVMASK_OFFSET), SAM_PM_UNLOCK); + putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBADIVMASK_OFFSET), + SAM_PM_UNLOCK); putreg32(regval, SAM_PM_PBADIVMASK); irqrestore(flags); @@ -270,3 +606,86 @@ void sam_pbb_disableperipheral(uint32_t bitset) irqrestore(flags); } + +/**************************************************************************** + * Name: sam_usbc_enableclk + * + * Description: + * Enable clocking for the USBC using settings from the board.h header files. + * + * "The USBC has two bus clocks connected: One High Speed Bus clock + * (CLK_USBC_AHB) and one Peripheral Bus clock (CLK_USBC_APB). These clocks + * are generated by the Power Manager. Both clocks are enabled at reset + * and can be disabled by the Power Manager. It is recommended to disable + * the USBC before disabling the clocks, to avoid freezing the USBC in + * an undefined state. + * + * "To follow the usb data rate at 12Mbit/s in full-speed mode, the + * CLK_USBC_AHB clock should be at minimum 12MHz. + * + * "The 48MHz USB clock is generated by a dedicated generic clock from + * the SCIF module. Before using the USB, the user must ensure that the + * USB generic clock (GCLK_USBC) is enabled at 48MHz in the SCIF module." + * + ****************************************************************************/ + +#ifdef CONFIG_SAM34_USBC +void sam_usbc_enableclk(void) +{ + irqstate_t flags; + uint32_t regval; + + /* Enable USBC clocking (possibly along with the PBB peripheral bridge) */ + + flags = irqsave(); + sam_hsb_enableperipheral(PM_HSBMASK_USBC); + sam_pbb_enableperipheral(PM_PBBMASK_USBC); + + /* Reset generic clock 7 */ + + putreg32(0, SAM_SCIF_GCCTRL7); + + /* Set the generic clock source */ + + regval = getreg32(SAM_SCIF_GCCTRL7); + regval &= ~SCIF_GCCTRL_OSCSEL_MASK; + regval |= SAM_USBC_GCLK_SOURCE; + putreg32(regval, SAM_SCIF_GCCTRL7); + + /* Set the generic clock divider */ + + regval = getreg32(SAM_SCIF_GCCTRL7); + regval &= ~(SCIF_GCCTRL_DIVEN | SCIF_GCCTRL_DIV_MASK); + +#if BOARD_USBC_GCLK_DIV > 1 + regval |= SCIF_GCCTRL_DIVEN; + regval |= SCIF_GCCTRL_DIV(((divider + 1) / 2) - 1); +#endif + + putreg32(regval, SAM_SCIF_GCCTRL7); + + /* Enable the generic clock */ + + regval = getreg32(SAM_SCIF_GCCTRL7); + regval |= SCIF_GCCTRL_CEN; + putreg32(regval, SAM_SCIF_GCCTRL7); + irqrestore(flags); +} +#endif /* CONFIG_SAM34_USBC */ + +/**************************************************************************** + * Name: sam_usbc_disableclk + * + * Description: + * Disable clocking to the USBC. + * + ****************************************************************************/ + +#ifdef CONFIG_SAM34_USBC +void sam_usbc_disableclk(void) +{ + putreg32(0, SAM_SCIF_GCCTRL7); + sam_pbb_enableperipheral(PM_PBBMASK_USBC); + sam_hsb_enableperipheral(PM_HSBMASK_USBC); +} +#endif /* CONFIG_SAM34_USBC */ diff --git a/nuttx/arch/arm/src/sam34/sam4l_periphclks.h b/nuttx/arch/arm/src/sam34/sam4l_periphclks.h index 895556e5d..f7509e278 100644 --- a/nuttx/arch/arm/src/sam34/sam4l_periphclks.h +++ b/nuttx/arch/arm/src/sam34/sam4l_periphclks.h @@ -42,6 +42,10 @@ #include <nuttx/config.h> +#include "chip/sam4l_pm.h" + +#ifdef CONFIG_ARCH_CHIP_SAM4L + /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ @@ -90,13 +94,13 @@ #define sam_usart0_enableclk() \ do { \ sam_pba_enableperipheral(PM_PBAMASK_USART0); \ - sam_pba_enabledivmask(PBA_DIVMASK_CLK_USART); \ + sam_pba_enabledivmask(PM_PBADIVMASK_CLK_USART); \ } while (0) #define sam_usart1_enableclk() \ do { \ sam_pba_enableperipheral(PM_PBAMASK_USART1); \ - sam_pba_enabledivmask(PBA_DIVMASK_CLK_USART); \ + sam_pba_enabledivmask(PM_PBADIVMASK_CLK_USART); \ } while (0) #define sam_usart2_enableclk() \ @@ -149,12 +153,6 @@ sam_pbb_enableperipheral(PM_PBBMASK_CRCCU); \ } while (0) -#define sam_usbc_enableclk() \ - do { \ - sam_hsb_enableperipheral(PM_HSBMASK_USBC); \ - sam_pbb_enableperipheral(PM_PBBMASK_USBC); \ - } while (0) - #define sam_pevc_enableclk() sam_pbb_enableperipheral(PM_PBBMASK_PEVC) #define sam_pm_enableclk() sam_pbc_enableperipheral(PM_PBCMASK_PM) #define sam_chipid_enableclk() sam_pbc_enableperipheral(PM_PBCMASK_CHIPID) @@ -216,12 +214,6 @@ sam_pbb_disableperipheral(PM_PBBMASK_CRCCU); \ } while (0) -#define sam_usbc_disableclk() \ - do { \ - sam_hsb_disableperipheral(PM_HSBMASK_USBC); \ - sam_pbb_disableperipheral(PM_PBBMASK_USBC); \ - } while (0) - #define sam_pevc_disableclk() sam_pbb_disableperipheral(PM_PBBMASK_PEVC) #define sam_pm_disableclk() sam_pbc_disableperipheral(PM_PBCMASK_PM) #define sam_chipid_disableclk() sam_pbc_disableperipheral(PM_PBCMASK_CHIPID) @@ -262,82 +254,114 @@ extern "C" * Public Function Prototypes ************************************************************************************/ -/**************************************************************************** +/************************************************************************************ + * Name: sam_init_periphclks + * + * Description: + * Called during boot to enable clocking on all selected peripherals. + * + ************************************************************************************/ + +void sam_init_periphclks(void); + +/************************************************************************************ * Name: sam_modifyperipheral * * Description: - * This is a convenience function that is intended to be used to enable - * or disable module clocking. + * This is a convenience function that is intended to be used to enable or disable + * module clocking. * - ****************************************************************************/ + ************************************************************************************/ -#ifdef CONFIG_ARCH_CHIP_SAM4L void sam_modifyperipheral(uintptr_t regaddr, uint32_t clrbits, uint32_t setbits); -#endif -/**************************************************************************** +/************************************************************************************ * Name: sam_pba_modifydivmask * * Description: - * This is a convenience function that is intended to be used to modify - * bits in the PBA divided clock (DIVMASK) register. + * This is a convenience function that is intended to be used to modify bits in + * the PBA divided clock (DIVMASK) register. * - ****************************************************************************/ + ************************************************************************************/ -#ifdef CONFIG_ARCH_CHIP_SAM4L void sam_pba_modifydivmask(uint32_t clrbits, uint32_t setbits); -#endif -/**************************************************************************** +/************************************************************************************ * Name: sam_pba_enableperipheral * * Description: - * This is a convenience function to enable a peripheral on the APBA - * bridge. + * This is a convenience function to enable a peripheral on the APBA bridge. * - ****************************************************************************/ + ************************************************************************************/ -#ifdef CONFIG_ARCH_CHIP_SAM4L void sam_pba_enableperipheral(uint32_t bitset); -#endif -/**************************************************************************** +/************************************************************************************ * Name: sam_pba_disableperipheral * * Description: - * This is a convenience function to disable a peripheral on the APBA - * bridge. + * This is a convenience function to disable a peripheral on the APBA bridge. * - ****************************************************************************/ + ************************************************************************************/ -#ifdef CONFIG_ARCH_CHIP_SAM4L void sam_pba_disableperipheral(uint32_t bitset); -#endif -/**************************************************************************** +/************************************************************************************ * Name: sam_pbb_enableperipheral * * Description: - * This is a convenience function to enable a peripheral on the APBB - * bridge. + * This is a convenience function to enable a peripheral on the APBB bridge. * - ****************************************************************************/ + ************************************************************************************/ -#ifdef CONFIG_ARCH_CHIP_SAM4L void sam_pbb_enableperipheral(uint32_t bitset); -#endif -/**************************************************************************** +/************************************************************************************ * Name: sam_pbb_disableperipheral * * Description: - * This is a convenience function to disable a peripheral on the APBA - * bridge. + * This is a convenience function to disable a peripheral on the APBA bridge. * - ****************************************************************************/ + ************************************************************************************/ -#ifdef CONFIG_ARCH_CHIP_SAM4L void sam_pbb_disableperipheral(uint32_t bitset); + +/************************************************************************************ + * Name: sam_usbc_enableclk + * + * Description: + * Enable clocking for the USBC using settings from the board.h header files. + * + * "The USBC has two bus clocks connected: One High Speed Bus clock + * (CLK_USBC_AHB) and one Peripheral Bus clock (CLK_USBC_APB). These clocks + * are generated by the Power Manager. Both clocks are enabled at reset + * and can be disabled by the Power Manager. It is recommended to disable + * the USBC before disabling the clocks, to avoid freezing the USBC in + * an undefined state. + * + * "To follow the usb data rate at 12Mbit/s in full-speed mode, the + * CLK_USBC_AHB clock should be at minimum 12MHz. + * + * "The 48MHz USB clock is generated by a dedicated generic clock from + * the SCIF module. Before using the USB, the user must ensure that the + * USB generic clock (GCLK_USBC) is enabled at 48MHz in the SCIF module." + * + ************************************************************************************/ + +#ifdef CONFIG_SAM34_USBC +void sam_usbc_enableclk(void); +#endif + +/************************************************************************************ + * Name: sam_usbc_disableclk + * + * Description: + * Disable clocking to the USBC. + * + ************************************************************************************/ + +#ifdef CONFIG_SAM34_USBC +void sam_usbc_disableclk(void); #endif #undef EXTERN @@ -346,4 +370,5 @@ void sam_pbb_disableperipheral(uint32_t bitset); #endif #endif /* __ASSEMBLY__ */ +#endif /* CONFIG_ARCH_CHIP_SAM4L */ #endif /* __ARCH_ARM_SRC_SAM34_SAM4L_PERIPHCLKS_H */ diff --git a/nuttx/arch/arm/src/sam34/sam4s_gpio.h b/nuttx/arch/arm/src/sam34/sam4s_gpio.h new file mode 100644 index 000000000..2d9fd8bb5 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/sam4s_gpio.h @@ -0,0 +1,201 @@ +/************************************************************************************ + * arch/arm/src/sam34/sam4s_gpio.h + * General Purpose Input/Output (GPIO) definitions for the SAM4S + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_SAM3U_GPIO_H +#define __ARCH_ARM_SRC_SAM34_SAM3U_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +/************************************************************************************ + * Definitions + ************************************************************************************/ +/* Configuration ********************************************************************/ + +#define GPIO_HAVE_PULLDOWN 1 +#define GPIO_HAVE_PERIPHCD 1 +#define GPIO_HAVE_SCHMITT 1 + +/* Bit-encoded input to sam_configgpio() ********************************************/ + +/* 32-bit Encoding: + * + * MMMC CCCC II.. VPPB BBBB + */ + +/* Input/Output mode: + * + * MMM. .... .... .... .... + */ + +#define GPIO_MODE_SHIFT (17) /* Bits 17-23: GPIO mode */ +#define GPIO_MODE_MASK (7 << GPIO_MODE_SHIFT) +# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input */ +# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* Output */ +# define GPIO_PERIPHA (2 << GPIO_MODE_SHIFT) /* Controlled by periph A signal */ +# define GPIO_PERIPHB (3 << GPIO_MODE_SHIFT) /* Controlled by periph B signal */ +# define GPIO_PERIPHC (4 << GPIO_MODE_SHIFT) /* Controlled by periph C signal */ +# define GPIO_PERIPHD (5 << GPIO_MODE_SHIFT) /* Controlled by periph D signal */ + +/* These bits set the configuration of the pin: + * NOTE: No definitions for parallel capture mode + * + * ...C CCCC .... .... .... + */ + +#define GPIO_CFG_SHIFT (12) /* Bits 12-16: GPIO configuration bits */ +#define GPIO_CFG_MASK (31 << GPIO_CFG_SHIFT) +# define GPIO_CFG_DEFAULT (0 << GPIO_CFG_SHIFT) /* Default, no attribute */ +# define GPIO_CFG_PULLUP (1 << GPIO_CFG_SHIFT) /* Bit 11: Internal pull-up */ +# define GPIO_CFG_PULLDOWN (2 << GPIO_CFG_SHIFT) /* Bit 11: Internal pull-down */ +# define GPIO_CFG_DEGLITCH (4 << GPIO_CFG_SHIFT) /* Bit 12: Internal glitch filter */ +# define GPIO_CFG_OPENDRAIN (8 << GPIO_CFG_SHIFT) /* Bit 13: Open drain */ +# define GPIO_CFG_SCHMITT (16 << GPIO_CFG_SHIFT) /* Bit 13: Schmitt trigger */ + +/* Additional interrupt modes: + * + * .... .... II.. .... .... + */ + +#define GPIO_INT_SHIFT (10) /* Bits 10-11: GPIO interrupt bits */ +#define GPIO_INT_MASK (3 << GPIO_INT_SHIFT) +# define GPIO_INT_LEVEL (1 << 10) /* Bit 10: Level detection interrupt */ +# define GPIO_INT_EDGE (0) /* (vs. Edge detection interrupt) */ +# define GPIO_INT_HIGHLEVEL (1 << 9) /* Bit 9: High level detection interrupt */ +# define GPIO_INT_LOWLEVEL (0) /* (vs. Low level detection interrupt) */ +# define GPIO_INT_RISING (1 << 9) /* Bit 9: Rising edge detection interrupt */ +# define GPIO_INT_FALLING (0) /* (vs. Falling edge detection interrupt) */ + +/* If the pin is an GPIO output, then this identifies the initial output value: + * + * .... .... .... V... .... + */ + +#define GPIO_OUTPUT_SET (1 << 7) /* Bit 7: Inital value of output */ +#define GPIO_OUTPUT_CLEAR (0) + +/* This identifies the GPIO port: + * + * .... .... .... .PP. .... + */ + +#define GPIO_PORT_SHIFT (5) /* Bit 5-6: Port number */ +#define GPIO_PORT_MASK (3 << GPIO_PORT_SHIFT) +# define GPIO_PORT_PIOA (0 << GPIO_PORT_SHIFT) +# define GPIO_PORT_PIOB (1 << GPIO_PORT_SHIFT) +# define GPIO_PORT_PIOC (2 << GPIO_PORT_SHIFT) + +/* This identifies the bit in the port: + * + * .... .... .... ...B BBBB + */ + +#define GPIO_PIN_SHIFT (0) /* Bits 0-4: GPIO number: 0-31 */ +#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT) +#define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) +#define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) +#define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) +#define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) +#define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) +#define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) +#define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) +#define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) +#define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) +#define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) +#define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) +#define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) +#define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) +#define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) +#define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) +#define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) +#define GPIO_PIN16 (16 << GPIO_PIN_SHIFT) +#define GPIO_PIN17 (17 << GPIO_PIN_SHIFT) +#define GPIO_PIN18 (18 << GPIO_PIN_SHIFT) +#define GPIO_PIN19 (19 << GPIO_PIN_SHIFT) +#define GPIO_PIN20 (20 << GPIO_PIN_SHIFT) +#define GPIO_PIN21 (21 << GPIO_PIN_SHIFT) +#define GPIO_PIN22 (22 << GPIO_PIN_SHIFT) +#define GPIO_PIN23 (23 << GPIO_PIN_SHIFT) +#define GPIO_PIN24 (24 << GPIO_PIN_SHIFT) +#define GPIO_PIN25 (25 << GPIO_PIN_SHIFT) +#define GPIO_PIN26 (26 << GPIO_PIN_SHIFT) +#define GPIO_PIN27 (27 << GPIO_PIN_SHIFT) +#define GPIO_PIN28 (28 << GPIO_PIN_SHIFT) +#define GPIO_PIN29 (29 << GPIO_PIN_SHIFT) +#define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) +#define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/* Must be big enough to hold the 32-bit encoding */ + +typedef uint32_t gpio_pinset_t; + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + + #undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_SAM34_SAM3U_GPIO_H */ diff --git a/nuttx/arch/arm/src/sam34/sam4s_periphclks.h b/nuttx/arch/arm/src/sam34/sam4s_periphclks.h new file mode 100644 index 000000000..071d475eb --- /dev/null +++ b/nuttx/arch/arm/src/sam34/sam4s_periphclks.h @@ -0,0 +1,157 @@ +/************************************************************************************ + * arch/arm/src/sam34/sam4s_periphclks.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_SAM4S_PERIPHCLKS_H +#define __ARCH_ARM_SRC_SAM34_SAM4S_PERIPHCLKS_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> +#include <stdint.h> +#include <arch/irq.h> +#include "chip/sam3u_pmc.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Helper macros */ + +#define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0) +#define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1) +#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PDER0) +#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PDER1) + +#define sam_supc_enableclk() sam_enableperiph0(SAM_PID_SUPC) +#define sam_rstc_enableclk() sam_enableperiph0(SAM_PID_RSTC) +#define sam_rtc_enableclk() sam_enableperiph0(SAM_PID_RTC) +#define sam_rtt_enableclk() sam_enableperiph0(SAM_PID_RTT) +#define sam_wdt_enableclk() sam_enableperiph0(SAM_PID_WDT) +#define sam_pmc_enableclk() sam_enableperiph0(SAM_PID_PMC) +#define sam_eefc0_enableclk() sam_enableperiph0(SAM_PID_EEFC0) +#define sam_eefc1_enableclk() sam_enableperiph0(SAM_PID_EEFC1) +#define sam_uart0_enableclk() sam_enableperiph0(SAM_PID_UART0) +#define sam_uart1_enableclk() sam_enableperiph0(SAM_PID_UART1) +#define sam_smc_enableclk() sam_enableperiph0(SAM_PID_SMC) +#define sam_pioa_enableclk() sam_enableperiph0(SAM_PID_PIOA) +#define sam_piob_enableclk() sam_enableperiph0(SAM_PID_PIOB) +#define sam_pioc_enableclk() sam_enableperiph0(SAM_PID_PIOC) +#define sam_usart0_enableclk() sam_enableperiph0(SAM_PID_USART0) +#define sam_usart1_enableclk() sam_enableperiph0(SAM_PID_USART1) +#define sam_hsmci_enableclk() sam_enableperiph0(SAM_PID_HSMCI) +#define sam_twi0_enableclk() sam_enableperiph0(SAM_PID_TWI0) +#define sam_twi1_enableclk() sam_enableperiph0(SAM_PID_TWI1) +#define sam_ssc_enableclk() sam_enableperiph0(SAM_PID_SSC) +#define sam_tc0_enableclk() sam_enableperiph0(SAM_PID_TC0) +#define sam_tc1_enableclk() sam_enableperiph0(SAM_PID_TC1) +#define sam_tc2_enableclk() sam_enableperiph0(SAM_PID_TC2) +#define sam_tc3_enableclk() sam_enableperiph0(SAM_PID_TC3) +#define sam_tc4_enableclk() sam_enableperiph0(SAM_PID_TC4) +#define sam_tc5_enableclk() sam_enableperiph0(SAM_PID_TC5) +#define sam_adc12b_enableclk() sam_enableperiph0(SAM_PID_ADC12B) +#define sam_dacc_enableclk() sam_enableperiph0(SAM_PID_DACC) +#define sam_pwm_enableclk() sam_enableperiph0(SAM_PID_PWM) +#define sam_crccu_enableclk() sam_enableperiph1(SAM_PID_CRCCU) +#define sam_acc_enableclk() sam_enableperiph1(SAM_PID_ACC) +#define sam_udp_enableclk() sam_enableperiph1(SAM_PID_UDP) + +#define sam_supc_disableclk() sam_disableperiph0(SAM_PID_SUPC) +#define sam_rstc_disableclk() sam_disableperiph0(SAM_PID_RSTC) +#define sam_rtc_disableclk() sam_disableperiph0(SAM_PID_RTC) +#define sam_rtt_disableclk() sam_disableperiph0(SAM_PID_RTT) +#define sam_wdt_disableclk() sam_disableperiph0(SAM_PID_WDT) +#define sam_pmc_disableclk() sam_disableperiph0(SAM_PID_PMC) +#define sam_eefc0_disableclk() sam_disableperiph0(SAM_PID_EEFC0) +#define sam_eefc1_disableclk() sam_disableperiph0(SAM_PID_EEFC1) +#define sam_uart0_disableclk() sam_disableperiph0(SAM_PID_UART0) +#define sam_uart1_disableclk() sam_disableperiph0(SAM_PID_UART1) +#define sam_smc_disableclk() sam_disableperiph0(SAM_PID_SMC) +#define sam_pioa_disableclk() sam_disableperiph0(SAM_PID_PIOA) +#define sam_piob_disableclk() sam_disableperiph0(SAM_PID_PIOB) +#define sam_pioc_disableclk() sam_disableperiph0(SAM_PID_PIOC) +#define sam_usart0_disableclk() sam_disableperiph0(SAM_PID_USART0) +#define sam_usart1_disableclk() sam_disableperiph0(SAM_PID_USART1) +#define sam_hsmci_disableclk() sam_disableperiph0(SAM_PID_HSMCI) +#define sam_twi0_disableclk() sam_disableperiph0(SAM_PID_TWI0) +#define sam_twi1_disableclk() sam_disableperiph0(SAM_PID_TWI1) +#define sam_ssc_disableclk() sam_disableperiph0(SAM_PID_SSC) +#define sam_tc0_disableclk() sam_disableperiph0(SAM_PID_TC0) +#define sam_tc1_disableclk() sam_disableperiph0(SAM_PID_TC1) +#define sam_tc2_disableclk() sam_disableperiph0(SAM_PID_TC2) +#define sam_tc3_disableclk() sam_disableperiph0(SAM_PID_TC3) +#define sam_tc4_disableclk() sam_disableperiph0(SAM_PID_TC4) +#define sam_tc5_disableclk() sam_disableperiph0(SAM_PID_TC5) +#define sam_adc12b_disableclk() sam_disableperiph0(SAM_PID_ADC) +#define sam_dacc_disableclk() sam_disableperiph0(SAM_PID_DACC) +#define sam_pwm_disableclk() sam_disableperiph0(SAM_PID_PWM) +#define sam_crccu_disableclk() sam_disableperiph1(SAM_PID_CRCCU) +#define sam_acc_disableclk() sam_disableperiph1(SAM_PID_ACC) +#define sam_udp_disableclk() sam_disableperiph1(SAM_PID_UDP) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_SAM34_SAM4S_PERIPHCLKS_H */ diff --git a/nuttx/arch/arm/src/sam34/sam_allocateheap.c b/nuttx/arch/arm/src/sam34/sam_allocateheap.c index 390234b71..edacfc617 100644 --- a/nuttx/arch/arm/src/sam34/sam_allocateheap.c +++ b/nuttx/arch/arm/src/sam34/sam_allocateheap.c @@ -57,7 +57,7 @@ * Private Definitions ****************************************************************************/ -#if CONFIG_MM_REGIONS < 2 +#if CONFIG_MM_REGIONS < 2 && SAM34_SRAM1_SIZE > 0 # warning "CONFIG_MM_REGIONS < 2: SRAM1 not included in HEAP" #endif @@ -66,16 +66,16 @@ #endif #if CONFIG_MM_REGIONS > 2 && defined(CONFIG_SAM34_NAND) -# error "CONFIG_MM_REGIONS > 3 but cannot used NFC SRAM" +# error "CONFIG_MM_REGIONS > 2 but cannot use NFC SRAM" # undef CONFIG_MM_REGIONS # define CONFIG_MM_REGIONS 2 #endif -#if CONFIG_DRAM_END > (SAM_INTSRAM0_BASE+CONFIG_SAM34_SRAM0_SIZE) +#if CONFIG_DRAM_END > (SAM_INTSRAM0_BASE+SAM34_SRAM0_SIZE) # error "CONFIG_DRAM_END is beyond the end of SRAM0" # undef CONFIG_DRAM_END -# define CONFIG_DRAM_END (SAM_INTSRAM0_BASE+CONFIG_SAM34_SRAM0_SIZE) -#elif CONFIG_DRAM_END < (SAM_INTSRAM0_BASE+CONFIG_SAM34_SRAM0_SIZE) +# define CONFIG_DRAM_END (SAM_INTSRAM0_BASE+SAM34_SRAM0_SIZE) +#elif CONFIG_DRAM_END < (SAM_INTSRAM0_BASE+SAM34_SRAM0_SIZE) # warning "CONFIG_DRAM_END is before end of SRAM0... not all of SRAM0 used" #endif @@ -224,25 +224,25 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size) #if CONFIG_MM_REGIONS > 1 void up_addregion(void) { -#if CONFIG_SAM34_SRAM1_SIZE > 0 +#if SAM34_SRAM1_SIZE > 0 /* Allow user access to the heap memory */ - sam_mpu_uheap(SAM_INTSRAM1_BASE, CONFIG_SAM34_SRAM1_SIZE); + sam_mpu_uheap(SAM_INTSRAM1_BASE, SAM34_SRAM1_SIZE); /* Add the region */ - kumm_addregion((FAR void*)SAM_INTSRAM1_BASE, CONFIG_SAM34_SRAM1_SIZE); + kumm_addregion((FAR void*)SAM_INTSRAM1_BASE, SAM34_SRAM1_SIZE); -#if CONFIG_MM_REGIONS > 2 && CONFIG_SAM34_NFCSRAM_SIZE > 0 +#if CONFIG_MM_REGIONS > 2 && SAM34_NFCSRAM_SIZE > 0 /* Allow user access to the heap memory */ - sam_mpu_uheap(SAM_NFCSRAM_BASE, CONFIG_SAM34_NFCSRAM_SIZE); + sam_mpu_uheap(SAM_NFCSRAM_BASE, SAM34_NFCSRAM_SIZE); /* Add the region */ - kumm_addregion((FAR void*)SAM_NFCSRAM_BASE, CONFIG_SAM34_NFCSRAM_SIZE); + kumm_addregion((FAR void*)SAM_NFCSRAM_BASE, SAM34_NFCSRAM_SIZE); -#endif /* CONFIG_MM_REGIONS > 2 && CONFIG_SAM34_NFCSRAM_SIZE > 0 */ -#endif /* CONFIG_SAM34_SRAM1_SIZE > 0 */ +#endif /* CONFIG_MM_REGIONS > 2 && SAM34_NFCSRAM_SIZE > 0 */ +#endif /* SAM34_SRAM1_SIZE > 0 */ } #endif /* CONFIG_MM_REGIONS > 1 */ diff --git a/nuttx/arch/arm/src/sam34/sam_dmac.c b/nuttx/arch/arm/src/sam34/sam_dmac.c index b11199fb1..4f6ede437 100644 --- a/nuttx/arch/arm/src/sam34/sam_dmac.c +++ b/nuttx/arch/arm/src/sam34/sam_dmac.c @@ -56,7 +56,7 @@ #include "chip.h" #include "sam_dmac.h" -#include "chip/sam_pmc.h" +#include "chip/sam3u_pmc.h" #include "chip/sam_dmac.h" /**************************************************************************** @@ -1160,7 +1160,7 @@ void weak_function up_dmainitialize(void) { /* Enable peripheral clock */ - putreg32((1 << SAM_PID_DMAC), SAM_PMC_PCER); + sam_dmac_enableclk(); /* Disable all DMA interrupts */ diff --git a/nuttx/arch/arm/src/sam34/sam_gpio.h b/nuttx/arch/arm/src/sam34/sam_gpio.h index 53f36c8fb..fd4e88fd1 100644 --- a/nuttx/arch/arm/src/sam34/sam_gpio.h +++ b/nuttx/arch/arm/src/sam34/sam_gpio.h @@ -51,6 +51,8 @@ # include "sam3u_gpio.h" #elif defined(CONFIG_ARCH_CHIP_SAM4L) # include "sam4l_gpio.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# include "sam4s_gpio.h" #else # error Unrecognized SAM architecture #endif diff --git a/nuttx/arch/arm/src/sam34/sam_gpioirq.c b/nuttx/arch/arm/src/sam34/sam_gpioirq.c index e5f0364cd..b7c7ead27 100644 --- a/nuttx/arch/arm/src/sam34/sam_gpioirq.c +++ b/nuttx/arch/arm/src/sam34/sam_gpioirq.c @@ -54,8 +54,9 @@ #include "up_internal.h" #include "sam_gpio.h" -#include "chip/sam_pio.h" -#include "chip/sam_pmc.h" +#include "sam_periphclks.h" +#include "chip/sam3u_pio.h" +#include "chip/sam3u_pmc.h" #ifdef CONFIG_GPIO_IRQ @@ -209,15 +210,12 @@ static int up_gpiocinterrupt(int irq, void *context) void sam_gpioirqinitialize(void) { - uint32_t pcer; - /* Configure GPIOA interrupts */ #ifdef CONFIG_GPIOA_IRQ /* Enable GPIOA clocking */ - pcer |= (1 << SAM_PID_PIOA); - putreg32(pcer, SAM_PMC_PCER); + sam_pioa_enableclk(); /* Clear and disable all GPIOA interrupts */ @@ -235,8 +233,7 @@ void sam_gpioirqinitialize(void) #ifdef CONFIG_GPIOB_IRQ /* Enable GPIOB clocking */ - pcer |= (1 << SAM_PID_PIOB); - putreg32(pcer, SAM_PMC_PCER); + sam_piob_enableclk(); /* Clear and disable all GPIOB interrupts */ @@ -254,8 +251,7 @@ void sam_gpioirqinitialize(void) #ifdef CONFIG_GPIOC_IRQ /* Enable GPIOC clocking */ - pcer |= (1 << SAM_PID_PIOC); - putreg32(pcer, SAM_PMC_PCER); + sam_pioc_enableclk(); /* Clear and disable all GPIOC interrupts */ diff --git a/nuttx/arch/arm/src/sam34/sam_hsmci.c b/nuttx/arch/arm/src/sam34/sam_hsmci.c index f9ee665a8..f44d9fbba 100644 --- a/nuttx/arch/arm/src/sam34/sam_hsmci.c +++ b/nuttx/arch/arm/src/sam34/sam_hsmci.c @@ -64,7 +64,7 @@ #include "sam_dmac.h" #include "sam_hsmci.h" #include "chip/sam_dmac.h" -#include "chip/sam_pmc.h" +#include "chip/sam3u_pmc.h" #include "chip/sam_hsmci.h" #include "chip/sam_pinmap.h" @@ -644,7 +644,7 @@ static inline void sam_disable(void) { /* Disable the MCI peripheral clock */ - putreg32((1 << SAM_PID_HSMCI), SAM_PMC_PCDR); + sam_hsmci_disableclk(); /* Disable the MCI */ @@ -667,7 +667,7 @@ static inline void sam_enable(void) { /* Enable the MCI peripheral clock */ - putreg32((1 << SAM_PID_HSMCI), SAM_PMC_PCER); + sam_hsmci_enableclk(); /* Enable the MCI and the Power Saving */ @@ -1223,8 +1223,7 @@ static void sam_reset(FAR struct sdio_dev_s *dev) /* Enable the MCI clock */ flags = irqsave(); - putreg32((1 << SAM_PID_HSMCI), SAM_PMC_PCER); - fdbg("PCSR: %08x\n", getreg32(SAM_PMC_PCSR)); + sam_hsmci_enableclk(); /* Reset the MCI */ diff --git a/nuttx/arch/arm/src/sam34/sam_irq.c b/nuttx/arch/arm/src/sam34/sam_irq.c index f21274211..00c88a7c1 100644 --- a/nuttx/arch/arm/src/sam34/sam_irq.c +++ b/nuttx/arch/arm/src/sam34/sam_irq.c @@ -221,18 +221,51 @@ static inline void sam_prioritize_syscall(int priority) static int sam_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit) { + unsigned int extint = irq - SAM_IRQ_EXTINT; + DEBUGASSERT(irq >= SAM_IRQ_NMI && irq < NR_IRQS); /* Check for external interrupt */ if (irq >= SAM_IRQ_EXTINT) { - if (irq < SAM_IRQ_NIRQS) +#if SAM_IRQ_NEXTINT <= 32 + if (extint < SAM_IRQ_NEXTINT) + { + *regaddr = NVIC_IRQ0_31_ENABLE; + *bit = 1 << extint; + } + else +#elif SAM_IRQ_NEXTINT <= 64 + if (extint < 32) + { + *regaddr = NVIC_IRQ0_31_ENABLE; + *bit = 1 << extint; + } + else if (extint < SAM_IRQ_NEXTINT) + { + *regaddr = NVIC_IRQ32_63_ENABLE; + *bit = 1 << (extint - 32); + } + else +#elif SAM_IRQ_NEXTINT <= 96 + if (extint < 32) { *regaddr = NVIC_IRQ0_31_ENABLE; - *bit = 1 << (irq - SAM_IRQ_EXTINT); + *bit = 1 << extint; + } + else if (extint < 64) + { + *regaddr = NVIC_IRQ32_63_ENABLE; + *bit = 1 << (extint - 32); + } + else if (extint < SAM_IRQ_NEXTINT) + { + *regaddr = NVIC_IRQ64_95_ENABLE; + *bit = 1 << (extint - 64); } else +#endif { return ERROR; /* Invalid interrupt */ } @@ -279,9 +312,35 @@ static int sam_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit) void up_irqinitialize(void) { - /* Disable all interrupts */ + uintptr_t regaddr; +#if defined(CONFIG_DEBUG_SYMBOLS) && !defined(CONFIG_ARMV7M_USEBASEPRI) + uint32_t regval; +#endif + int nintlines; + int i; - putreg32(0, NVIC_IRQ0_31_ENABLE); + /* The NVIC ICTR register (bits 0-4) holds the number of of interrupt + * lines that the NVIC supports, defined in groups of 32. That is, + * the total number of interrupt lines is up to (32*(INTLINESNUM+1)). + * + * 0 -> 32 interrupt lines, 1 enable register, 8 priority registers + * 1 -> 64 " " " ", 2 enable registers, 16 priority registers + * 2 -> 96 " " " ", 3 enable regsiters, 24 priority registers + * ... + */ + + nintlines = (getreg32(NVIC_ICTR) & NVIC_ICTR_INTLINESNUM_MASK) + 1; + + /* Disable all interrupts. There are nintlines interrupt enable + * registers. + */ + + for (i = nintlines, regaddr = NVIC_IRQ0_31_ENABLE; + i > 0; + i--, regaddr += 4) + { + putreg32(0, regaddr); + } /* Set up the vector table address. * @@ -291,24 +350,26 @@ void up_irqinitialize(void) #if defined(CONFIG_ARCH_RAMVECTORS) up_ramvec_initialize(); -#elif defined(CONFIG_STM32_DFU) +#elif defined(CONFIG_SAM_BOOTLOADER) putreg32((uint32_t)sam_vectors, NVIC_VECTAB); #endif - /* Set all interrrupts (and exceptions) to the default priority */ + /* Set all interrupts (and exceptions) to the default priority */ putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY); + /* Now set all of the interrupt lines to the default priority. There are + * nintlines * 8 priority registers. + */ + + for (i = (nintlines << 3), regaddr = NVIC_IRQ0_3_PRIORITY; + i > 0; + i--, regaddr += 4) + { + putreg32(0, regaddr); + } /* currents_regs is non-NULL only while processing an interrupt */ @@ -357,8 +418,18 @@ void up_irqinitialize(void) sam_dumpnvic("initial", SAM_IRQ_NIRQS); -#ifndef CONFIG_SUPPRESS_INTERRUPTS + /* If a debugger is connected, try to prevent it from catching hardfaults. + * If CONFIG_ARMV7M_USEBASEPRI, no hardfaults are expected in normal + * operation. + */ + +#if defined(CONFIG_DEBUG_SYMBOLS) && !defined(CONFIG_ARMV7M_USEBASEPRI) + regval = getreg32(NVIC_DEMCR); + regval &= ~NVIC_DEMCR_VCHARDERR; + putreg32(regval, NVIC_DEMCR); +#endif +#ifndef CONFIG_SUPPRESS_INTERRUPTS /* Initialize logic to support a second level of interrupt decoding for * GPIO pins. */ diff --git a/nuttx/arch/arm/src/sam34/sam_lowputc.c b/nuttx/arch/arm/src/sam34/sam_lowputc.c index 00a3d3a89..55ab7555b 100644 --- a/nuttx/arch/arm/src/sam34/sam_lowputc.c +++ b/nuttx/arch/arm/src/sam34/sam_lowputc.c @@ -48,9 +48,19 @@ #include "up_arch.h" #include "sam_gpio.h" +#include "sam_periphclks.h" #include "sam_lowputc.h" -#include "chip/sam_pmc.h" -#include "chip/sam_uart.h" + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# include "chip/sam3u_uart.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4L) +# include "chip/sam4l_usart.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# include "chip/sam3u_uart.h" +#else +# error Unknown UART +#endif + #include "chip/sam_pinmap.h" /************************************************************************** @@ -76,40 +86,54 @@ # undef CONFIG_SAM34_USART3 #endif -/* Is there a serial console? It could be on the UART, or USARTn */ +/* Is there a serial console? It could be on UART0-1 or USART0-3 */ -#if defined(CONFIG_UART_SERIAL_CONSOLE) && defined(CONFIG_SAM34_UART) +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_SAM34_UART0) +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_SAM34_UART1) +# undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #elif defined(CONFIG_USART0_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART0) -# undef CONFIG_USART_SERIAL_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART1) -# undef CONFIG_USART_SERIAL_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART2) -# undef CONFIG_USART_SERIAL_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART3) -# undef CONFIG_USART_SERIAL_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #else -# undef CONFIG_USART_SERIAL_CONSOLE +# warning "No valid CONFIG_USARTn_SERIAL_CONSOLE Setting" +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -117,14 +141,37 @@ # undef HAVE_CONSOLE #endif +/* Select MCU-specific settings + * + * For the SAM3U, the USARTs are driven by the main clock. + * For the SAM4L, the USARTs are driven by CLK_USART (undivided) which is + * selected by the PBADIVMASK register. + */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_MR_USCLKS UART_MR_USCLKS_MCK /* Source = Main clock */ +# define SAM_USART_CLOCK BOARD_MCK_FREQUENCY /* Frequency of the main clock */ +#elif defined(CONFIG_ARCH_CHIP_SAM4L) +# define SAM_MR_USCLKS UART_MR_USCLKS_USART /* Source = USART_CLK (undefined) */ +# define SAM_USART_CLOCK BOARD_PBA_FREQUENCY /* PBA frequency is undivided */ +#else +# error Unrecognized SAM architecture +#endif + /* Select USART parameters for the selected console */ -#if defined(CONFIG_UART_SERIAL_CONSOLE) -# define SAM_CONSOLE_BASE SAM_UART_BASE -# define SAM_CONSOLE_BAUD CONFIG_UART_BAUD -# define SAM_CONSOLE_BITS CONFIG_UART_BITS -# define SAM_CONSOLE_PARITY CONFIG_UART_PARITY -# define SAM_CONSOLE_2STOP CONFIG_UART_2STOP +#if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define SAM_CONSOLE_BASE SAM_UART0_BASE +# define SAM_CONSOLE_BAUD CONFIG_UART0_BAUD +# define SAM_CONSOLE_BITS CONFIG_UART0_BITS +# define SAM_CONSOLE_PARITY CONFIG_UART0_PARITY +# define SAM_CONSOLE_2STOP CONFIG_UART0_2STOP +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define SAM_CONSOLE_BASE SAM_UART1_BASE +# define SAM_CONSOLE_BAUD CONFIG_UART1_BAUD +# define SAM_CONSOLE_BITS CONFIG_UART1_BITS +# define SAM_CONSOLE_PARITY CONFIG_UART1_PARITY +# define SAM_CONSOLE_2STOP CONFIG_UART1_2STOP #elif defined(CONFIG_USART0_SERIAL_CONSOLE) # define SAM_CONSOLE_BASE SAM_USART0_BASE # define SAM_CONSOLE_BAUD CONFIG_USART0_BAUD @@ -156,15 +203,16 @@ /* Select the settings for the mode register */ #if SAM_CONSOLE_BITS == 5 -# define MR_CHRL_VALUE USART_MR_CHRL_5BITS /* 5 bits */ +# define MR_CHRL_VALUE UART_MR_CHRL_5BITS /* 5 bits */ #elif SAM_CONSOLE_BITS == 6 -# define MR_CHRL_VALUE USART_MR_CHRL_6BITS /* 6 bits */ +# define MR_CHRL_VALUE UART_MR_CHRL_6BITS /* 6 bits */ #elif SAM_CONSOLE_BITS == 7 -# define MR_CHRL_VALUE USART_MR_CHRL_7BITS /* 7 bits */ +# define MR_CHRL_VALUE UART_MR_CHRL_7BITS /* 7 bits */ #elif SAM_CONSOLE_BITS == 8 -# define MR_CHRL_VALUE USART_MR_CHRL_8BITS /* 8 bits */ -#elif SAM_CONSOLE_BITS == 9 && !defined(CONFIG_UART_SERIAL_CONSOLE) -# define MR_CHRL_VALUE USART_MR_MODE9 +# define MR_CHRL_VALUE UART_MR_CHRL_8BITS /* 8 bits */ +#elif SAM_CONSOLE_BITS == 9 && !defined(CONFIG_UART0_SERIAL_CONSOLE) && \ + !defined(CONFIG_UART1_SERIAL_CONSOLE) +# define MR_CHRL_VALUE UART_MR_MODE9 #else # error "Invlaid number of bits" #endif @@ -178,12 +226,12 @@ #endif #if SAM_CONSOLE_2STOP != 0 -# define MR_NBSTOP_VALUE USART_MR_NBSTOP_2 +# define MR_NBSTOP_VALUE UART_MR_NBSTOP_2 #else -# define MR_NBSTOP_VALUE USART_MR_NBSTOP_1 +# define MR_NBSTOP_VALUE UART_MR_NBSTOP_1 #endif -#define MR_VALUE (USART_MR_MODE_NORMAL | USART_MR_USCLKS_MCK | \ +#define MR_VALUE (UART_MR_MODE_NORMAL | SAM_MR_USCLKS | \ MR_CHRL_VALUE | MR_PAR_VALUE | MR_NBSTOP_VALUE) /************************************************************************** @@ -241,69 +289,81 @@ void up_lowputc(char ch) void sam_lowsetup(void) { - uint32_t regval; - /* Enable clocking for all selected UART/USARTs */ - regval = 0; -#ifdef CONFIG_SAM34_UART - regval |= (1 << SAM_PID_UART); +#ifdef CONFIG_SAM34_UART0 + sam_uart0_enableclk(); +#endif +#ifdef CONFIG_SAM34_UART1 + sam_uart1_enableclk(); #endif #ifdef CONFIG_SAM34_USART0 - regval |= (1 << SAM_PID_USART0); + sam_usart0_enableclk(); #endif #ifdef CONFIG_SAM34_USART1 - regval |= (1 << SAM_PID_USART1); + sam_usart1_enableclk(); #endif #ifdef CONFIG_SAM34_USART2 - regval |= (1 << SAM_PID_USART2); + sam_usart2_enableclk(); #endif #ifdef CONFIG_SAM34_USART3 - regval |= (1 << SAM_PID_USART3); + sam_usart3_enableclk(); #endif - putreg32(regval, SAM_PMC_PCER); /* Configure UART pins for all selected UART/USARTs */ -#ifdef CONFIG_SAM34_UART - (void)sam_configgpio(GPIO_UART_RXD); - (void)sam_configgpio(GPIO_UART_TXD); +#ifdef CONFIG_SAM34_UART0 + (void)sam_configgpio(GPIO_UART0_RXD); + (void)sam_configgpio(GPIO_UART0_TXD); #endif + +#ifdef CONFIG_SAM34_UART1 + (void)sam_configgpio(GPIO_UART1_RXD); + (void)sam_configgpio(GPIO_UART1_TXD); +#endif + #ifdef CONFIG_SAM34_USART0 (void)sam_configgpio(GPIO_USART0_RXD); (void)sam_configgpio(GPIO_USART0_TXD); +#ifdef CONFIG_USART0_OFLOWCONTROL (void)sam_configgpio(GPIO_USART0_CTS); +#endif +#ifdef CONFIG_USART0_IFLOWCONTROL (void)sam_configgpio(GPIO_USART0_RTS); #endif +#endif + #ifdef CONFIG_SAM34_USART1 (void)sam_configgpio(GPIO_USART1_RXD); (void)sam_configgpio(GPIO_USART1_TXD); +#ifdef CONFIG_USART1_OFLOWCONTROL (void)sam_configgpio(GPIO_USART1_CTS); +#endif +#ifdef CONFIG_USART1_IFLOWCONTROL (void)sam_configgpio(GPIO_USART1_RTS); #endif +#endif + #ifdef CONFIG_SAM34_USART2 (void)sam_configgpio(GPIO_USART2_RXD); (void)sam_configgpio(GPIO_USART2_TXD); +#ifdef CONFIG_USART2_OFLOWCONTROL (void)sam_configgpio(GPIO_USART2_CTS); +#endif +#ifdef CONFIG_USART2_IFLOWCONTROL (void)sam_configgpio(GPIO_USART2_RTS); #endif +#endif + #ifdef CONFIG_SAM34_USART3 (void)sam_configgpio(GPIO_USART3_RXD); (void)sam_configgpio(GPIO_USART3_TXD); +#ifdef CONFIG_USART3_OFLOWCONTROL (void)sam_configgpio(GPIO_USART3_CTS); - (void)sam_configgpio(GPIO_USART3_RTS); #endif - -#ifdef GPIO_CONSOLE_RXD -#endif -#ifdef GPIO_CONSOLE_TXD - (void)sam_configgpio(GPIO_CONSOLE_TXD); -#endif -#ifdef GPIO_CONSOLE_CTS - (void)sam_configgpio(GPIO_CONSOLE_CTS); +#ifdef CONFIG_USART3_IFLOWCONTROL + (void)sam_configgpio(GPIO_USART3_RTS); #endif -#ifdef GPIO_CONSOLE_RTS - (void)sam_configgpio(GPIO_CONSOLE_RTS); #endif /* Configure the console (only) */ @@ -321,9 +381,11 @@ void sam_lowsetup(void) putreg32(MR_VALUE, SAM_CONSOLE_BASE + SAM_UART_MR_OFFSET); - /* Configure the console baud */ + /* Configure the console baud. NOTE: Oversampling by 8 is not supported. + * This may limit BAUD rates for lower USART clocks. + */ - putreg32(((SAM_MCK_FREQUENCY + (SAM_CONSOLE_BAUD << 3))/(SAM_CONSOLE_BAUD << 4)), + putreg32(((SAM_USART_CLOCK + (SAM_CONSOLE_BAUD << 3)) / (SAM_CONSOLE_BAUD << 4)), SAM_CONSOLE_BASE + SAM_UART_BRGR_OFFSET); /* Enable receiver & transmitter */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_pio.h b/nuttx/arch/arm/src/sam34/sam_periphclks.h index e2596475d..43fb6dc89 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_pio.h +++ b/nuttx/arch/arm/src/sam34/sam_periphclks.h @@ -1,5 +1,5 @@ -/**************************************************************************************** - * arch/arm/src/sam34/chip/sam_pio.h +/************************************************************************************ + * arch/arm/src/sam34/sam_periphclks.h * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -31,41 +31,62 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************************/ + ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_PIO_H -#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_PIO_H +#ifndef __ARCH_ARM_SRC_SAM34_SAM_PERIPHCLKS_H +#define __ARCH_ARM_SRC_SAM34_SAM_PERIPHCLKS_H -/**************************************************************************************** +/************************************************************************************ * Included Files - ****************************************************************************************/ + ************************************************************************************/ #include <nuttx/config.h> -#include "chip.h" - #if defined(CONFIG_ARCH_CHIP_SAM3U) -# include "chip/sam3u_vectors.h" +# include "sam3u_periphclks.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4L) +# include "sam4l_periphclks.h" #elif defined(CONFIG_ARCH_CHIP_SAM4S) -# include "chip/sam4s_vectors.h" +# include "sam4s_periphclks.h" #else -# error Unrecognized SAM architecture +# error Unknown SAM chip #endif -/**************************************************************************************** +/************************************************************************************ * Pre-processor Definitions - ****************************************************************************************/ + ************************************************************************************/ -/**************************************************************************************** +/************************************************************************************ * Public Types - ****************************************************************************************/ + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ -/**************************************************************************************** +#ifndef __ASSEMBLY__ + +/************************************************************************************ * Public Data - ****************************************************************************************/ + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif -#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_PIO_H */ +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_SAM34_SAM_PERIPHCLKS_H */ diff --git a/nuttx/arch/arm/src/sam34/sam_serial.c b/nuttx/arch/arm/src/sam34/sam_serial.c index fb7d69cba..2afc302e5 100644 --- a/nuttx/arch/arm/src/sam34/sam_serial.c +++ b/nuttx/arch/arm/src/sam34/sam_serial.c @@ -60,7 +60,13 @@ #include "os_internal.h" #include "chip.h" -#include "chip/sam_uart.h" +#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4S) +# include "chip/sam3u_uart.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4L) +# include "chip/sam4l_usart.h" +#else +# error Unknown UART +#endif /**************************************************************************** * Definitions @@ -87,9 +93,9 @@ /* Is there a USART/USART enabled? */ -#if !defined(CONFIG_SAM34_UART) && !defined(CONFIG_SAM34_USART0) && \ - !defined(CONFIG_SAM34_USART1) && !defined(CONFIG_SAM34_USART2) && \ - !defined(CONFIG_SAM34_USART3) +#if !defined(CONFIG_SAM34_UART0) && !defined(CONFIG_SAM34_UART1) && \ + !defined(CONFIG_SAM34_USART0) && !defined(CONFIG_SAM34_USART1) && \ + !defined(CONFIG_SAM34_USART2) && !defined(CONFIG_SAM34_USART3) # error "No USARTs enabled" #endif @@ -98,41 +104,54 @@ # define HAVE_USART #endif -/* Is there a serial console? */ +/* Is there a serial console? It could be on UART0-1 or USART0-3 */ -#if defined(CONFIG_UART_SERIAL_CONSOLE) && defined(CONFIG_SAM34_UART) +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_SAM34_UART0) +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_SAM34_UART1) +# undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #elif defined(CONFIG_USART0_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART0) -# undef CONFIG_UART_SERIAL_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART1) -# undef CONFIG_UART_SERIAL_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART2) -# undef CONFIG_UART_SERIAL_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART3) -# undef CONFIG_UART_SERIAL_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #else # warning "No valid CONFIG_USARTn_SERIAL_CONSOLE Setting" -# undef CONFIG_UART_SERIAL_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -146,405 +165,165 @@ #ifdef USE_SERIALDRIVER -/* Which UART/USART with be tty0/console and which tty1? tty2? tty3? tty4? */ - -#if defined(CONFIG_UART_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uartport /* UART=console */ -# define TTYS0_DEV g_uartport /* UART=ttyS0 */ -# ifdef CONFIG_SAM34_USART0 -# define TTYS1_DEV g_usart0port /* UART=ttyS0;USART0=ttyS1 */ -# ifdef CONFIG_SAM34_USART1 -# define TTYS2_DEV g_usart1port /* UART=ttyS0;USART0=ttyS1;USART1=ttyS2 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS3_DEV g_usart2port /* UART=ttyS0;USART0=ttyS1;USART1=ttyS2;USART2=ttyS3 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS4_DEV g_usart3port /* UART=ttyS0;USART0=ttyS1;USART1=ttyS2;USART2=ttyS3;USART3=ttyS4 */ -# else -# undef TTYS4_DEV /* UART=ttyS0;USART0=ttyS1;USART1=ttyS2;USART2=ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* UART=ttyS0;USART0=ttyS1;USART1=ttyS;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* UART=ttyS0;USART0=ttyS1;USART1=ttyS;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS2_DEV g_usart2port /* UART=ttyS0;USART0=ttyS1;USART2=ttys2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* UART=ttyS0;USART0=ttyS1;USART2=ttys2;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* UART=ttyS0;USART0=ttyS1;USART2=ttys2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* UART=ttyS0;USART0=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* UART=ttyS0;USART0=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# endif -# else -# ifdef CONFIG_SAM34_USART1 -# define TTYS1_DEV g_usart1port /* UART=ttyS0;USART1=ttyS1;No ttyS4 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS2_DEV g_usart2port /* UART=ttyS0;USART1=ttyS1;USART2=ttyS2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* UART=ttyS0;USART1=ttyS1;USART2=ttyS2;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* UART=ttyS0;USART1=ttyS1;USART2=ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* UART=ttyS0;USART1=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* UART=ttyS0;USART1=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS1_DEV g_usart2port /* UART=ttyS0;USART2=ttyS1;No ttyS3;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* UART=ttyS0;USART2=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* UART=ttyS0;USART2=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS1_DEV g_usart3port /* UART=ttyS0;USART3=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS1_DEV /* UART=ttyS0;No ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS2_DEV /* No ttyS2 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# endif +/* Which UART/USART with be tty0/console and which tty1? tty2? tty3? tty4? tty5? */ + +/* First pick the console and ttys0. This could be any of UART0-1, USART0-3 */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart0port /* UART0 is console */ +# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ +# define UART0_ASSIGNED 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port /* UART1 is console */ +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# define UART1_ASSIGNED 1 #elif defined(CONFIG_USART0_SERIAL_CONSOLE) -# define CONSOLE_DEV g_usart0port /* USART0=console */ -# define TTYS0_DEV g_usart0port /* USART0=ttyS0 */ -# ifdef CONFIG_SAM34_UART -# define TTYS1_DEV g_uartport /* USART0=ttyS0;UART=ttyS1 */ -# ifdef CONFIG_SAM34_USART1 -# define TTYS2_DEV g_usart1port /* USART0=ttyS0;UART=ttyS1;USART1=ttyS2 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS3_DEV g_usart2port /* USART0=ttyS0;UART=ttyS1;USART1=ttyS2;USART2=ttyS3 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS4_DEV g_usart3port /* USART0=ttyS0;UART=ttyS1;USART1=ttyS2;USART2=ttyS3;USART3=ttyS4 */ -# else -# undef TTYS4_DEV /* USART0=ttyS0;UART=ttyS1;USART1=ttyS2;USART2=ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* USART0=ttyS0;UART=ttyS1;USART1=ttyS;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART0=ttyS0;UART=ttyS1;USART1=ttyS;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS2_DEV g_usart2port /* USART0=ttyS0;UART=ttyS1;USART2=ttys2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* USART0=ttyS0;UART=ttyS1;USART2=ttys2;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART0=ttyS0;UART=ttyS1;USART2=ttys2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* USART0=ttyS0;UART=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART0=ttyS0;UART=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# endif -# else -# ifdef CONFIG_SAM34_USART1 -# define TTYS1_DEV g_usart1port /* USART0=ttyS0;USART1=ttyS1;No ttyS4 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS2_DEV g_usart2port /* USART0=ttyS0;USART1=ttyS1;USART2=ttyS2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* USART0=ttyS0;USART1=ttyS1;USART2=ttyS2;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART0=ttyS0;USART1=ttyS1;USART2=ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* USART0=ttyS0;USART1=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART0=ttyS0;USART1=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS1_DEV g_usart2port /* USART0=ttyS0;USART2=ttyS1;No ttyS3;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* USART0=ttyS0;USART2=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART0=ttyS0;USART2=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS1_DEV g_usart3port /* USART0=ttyS0;USART3=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS1_DEV /* USART0=ttyS0;No ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS2_DEV /* No ttyS2 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# endif +# define CONSOLE_DEV g_usart0port /* USART0 is console */ +# define TTYS0_DEV g_usart0port /* USART0 is ttyS0 */ +# define USART0_ASSIGNED 1 #elif defined(CONFIG_USART1_SERIAL_CONSOLE) -# define CONSOLE_DEV g_usart1port /* USART1=console */ -# define TTYS0_DEV g_usart1port /* USART1=ttyS0 */ -# ifdef CONFIG_SAM34_UART -# define TTYS1_DEV g_uartport /* USART1=ttyS0;UART=ttyS1 */ -# ifdef CONFIG_SAM34_USART0 -# define TTYS2_DEV g_usart0port /* USART1=ttyS0;UART=ttyS1;USART0=ttyS2 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS3_DEV g_usart2port /* USART1=ttyS0;UART=ttyS1;USART0=ttyS2;USART2=ttyS3 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS4_DEV g_usart3port /* USART1=ttyS0;UART=ttyS1;USART0=ttyS2;USART2=ttyS3;USART3=ttyS4 */ -# else -# undef TTYS4_DEV /* USART1=ttyS0;UART=ttyS1;USART0=ttyS2;USART2=ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* USART1=ttyS0;UART=ttyS1;USART0=ttyS;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART1=ttyS0;UART=ttyS1;USART0=ttyS;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS2_DEV g_usart2port /* USART1=ttyS0;UART=ttyS1;USART2=ttys2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* USART1=ttyS0;UART=ttyS1;USART2=ttys2;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART1=ttyS0;UART=ttyS1;USART2=ttys2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* USART1=ttyS0;UART=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART1=ttyS0;UART=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# endif -# else -# ifdef CONFIG_SAM34_USART0 -# define TTYS1_DEV g_usart0port /* USART1=ttyS0;USART0=ttyS1;No ttyS4 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS2_DEV g_usart2port /* USART1=ttyS0;USART0=ttyS1;USART2=ttyS2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* USART1=ttyS0;USART0=ttyS1;USART2=ttyS2;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART1=ttyS0;USART0=ttyS1;USART2=ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* USART1=ttyS0;USART0=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART1=ttyS0;USART0=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS1_DEV g_usart2port /* USART1=ttyS0;USART2=ttyS1;No ttyS3;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* USART1=ttyS0;USART2=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART1=ttyS0;USART2=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS1_DEV g_usart3port /* USART1=ttyS0;USART3=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS1_DEV /* USART1=ttyS0;No ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS2_DEV /* No ttyS2 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# endif +# define CONSOLE_DEV g_usart1port /* USART1 is console */ +# define TTYS0_DEV g_usart1port /* USART1 is ttyS0 */ +# define USART1_ASSIGNED 1 #elif defined(CONFIG_USART2_SERIAL_CONSOLE) -# define CONSOLE_DEV g_usart2port /* USART2=console */ -# define TTYS0_DEV g_usart2port /* USART2=ttyS0 */ -# ifdef CONFIG_SAM34_UART -# define TTYS1_DEV g_uartport /* USART2=ttyS0;UART=ttyS1 */ -# ifdef CONFIG_SAM34_USART0 -# define TTYS2_DEV g_usart0port /* USART2=ttyS0;UART=ttyS1;USART0=ttyS2 */ -# ifdef CONFIG_SAM34_USART1 -# define TTYS3_DEV g_usart1port /* USART2=ttyS0;UART=ttyS1;USART0=ttyS2;USART1=ttyS3 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS4_DEV g_usart3port /* USART2=ttyS0;UART=ttyS1;USART0=ttyS2;USART1=ttyS3;USART3=ttyS4 */ -# else -# undef TTYS4_DEV /* USART2=ttyS0;UART=ttyS1;USART0=ttyS2;USART1=ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* USART2=ttyS0;UART=ttyS1;USART0=ttyS;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART2=ttyS0;UART=ttyS1;USART0=ttyS;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART1 -# define TTYS2_DEV g_usart1port /* USART2=ttyS0;UART=ttyS1;USART1=ttys2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* USART2=ttyS0;UART=ttyS1;USART1=ttys2;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART2=ttyS0;UART=ttyS1;USART1=ttys2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* USART2=ttyS0;UART=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART2=ttyS0;UART=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# endif -# else -# ifdef CONFIG_SAM34_USART0 -# define TTYS1_DEV g_usart0port /* USART2=ttyS0;USART0=ttyS1;No ttyS4 */ -# ifdef CONFIG_SAM34_USART1 -# define TTYS2_DEV g_usart1port /* USART2=ttyS0;USART0=ttyS1;USART1=ttyS2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* USART2=ttyS0;USART0=ttyS1;USART1=ttyS2;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART2=ttyS0;USART0=ttyS1;USART1=ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* USART2=ttyS0;USART0=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART2=ttyS0;USART0=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# else -# ifdef CONFIG_SAM34_USART1 -# define TTYS1_DEV g_usart1port /* USART2=ttyS0;USART1=ttyS1;No ttyS3;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* USART2=ttyS0;USART1=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART2=ttyS0;USART1=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS1_DEV g_usart3port /* USART2=ttyS0;USART3=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS1_DEV /* USART2=ttyS0;No ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS2_DEV /* No ttyS2 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# endif +# define CONSOLE_DEV g_usart2port /* USART2 is console */ +# define TTYS0_DEV g_usart2port /* USART2 is ttyS0 */ +# define USART2_ASSIGNED 1 #elif defined(CONFIG_USART3_SERIAL_CONSOLE) -# define CONSOLE_DEV g_usart3port /* USART3=console */ -# define TTYS0_DEV g_usart3port /* USART3=ttyS0 */ -# ifdef CONFIG_SAM34_UART -# define TTYS1_DEV g_uartport /* USART3=ttyS0;UART=ttyS1 */ -# ifdef CONFIG_SAM34_USART0 -# define TTYS2_DEV g_usart0port /* USART3=ttyS0;UART=ttyS1;USART0=ttyS2 */ -# ifdef CONFIG_SAM34_USART1 -# define TTYS3_DEV g_usart1port /* USART3=ttyS0;UART=ttyS1;USART0=ttyS2;USART1=ttyS3 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS4_DEV g_usart2port /* USART3=ttyS0;UART=ttyS1;USART0=ttyS2;USART1=ttyS3;USART2=ttyS4 */ -# else -# undef TTYS4_DEV /* USART3=ttyS0;UART=ttyS1;USART0=ttyS2;USART1=ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS3_DEV g_usart2port /* USART3=ttyS0;UART=ttyS1;USART0=ttyS;USART2=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART3=ttyS0;UART=ttyS1;USART0=ttyS;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART1 -# define TTYS2_DEV g_usart1port /* USART3=ttyS0;UART=ttyS1;USART1=ttys2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS3_DEV g_usart2port /* USART3=ttyS0;UART=ttyS1;USART1=ttys2;USART2=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART3=ttyS0;UART=ttyS1;USART1=ttys2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS2_DEV g_usart2port /* USART3=ttyS0;UART=ttyS1;USART2=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART3=ttyS0;UART=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# endif -# else -# ifdef CONFIG_SAM34_USART0 -# define TTYS1_DEV g_usart0port /* USART3=ttyS0;USART0=ttyS1;No ttyS4 */ -# ifdef CONFIG_SAM34_USART1 -# define TTYS2_DEV g_usart1port /* USART3=ttyS0;USART0=ttyS1;USART1=ttyS2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS3_DEV g_usart2port /* USART3=ttyS0;USART0=ttyS1;USART1=ttyS2;USART2=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART3=ttyS0;USART0=ttyS1;USART1=ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS2_DEV g_usart2port /* USART3=ttyS0;USART0=ttyS1;USART2=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART3=ttyS0;USART0=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# else -# ifdef CONFIG_SAM34_USART1 -# define TTYS1_DEV g_usart1port /* USART3=ttyS0;USART1=ttyS1;No ttyS3;No ttyS4 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS2_DEV g_EEEEport /* USART3=ttyS0;USART1=ttyS1;USART2=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART3=ttyS0;USART1=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS1_DEV g_usart2port /* USART3=ttyS0;USART2=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS1_DEV /* USART3=ttyS0;No ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS2_DEV /* No ttyS2 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ +# define CONSOLE_DEV g_usart3port /* USART3 is console */ +# define TTYS5_DEV g_usart3port /* USART3 is ttyS0 */ +#else +# undef CONSOLE_DEV /* No console */ +# if defined(CONFIG_SAM34_UART0) +# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ +# define UART0_ASSIGNED 1 +# elif defined(CONFIG_SAM34_UART1) +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# define UART1_ASSIGNED 1 +# elif defined(CONFIG_SAM34_USART0) +# define TTYS0_DEV g_usart0port /* USART0 is ttyS0 */ +# define USART0_ASSIGNED 1 +# elif defined(CONFIG_SAM34_USART1) +# define TTYS0_DEV g_usart1port /* USART1 is ttyS0 */ +# define USART1_ASSIGNED 1 +# elif defined(CONFIG_SAM34_USART2) +# define TTYS0_DEV g_usart2port /* USART2 is ttyS0 */ +# define USART2_ASSIGNED 1 +# elif defined(CONFIG_SAM34_USART3) +# define TTYS0_DEV g_usart3port /* USART3 is ttyS0 */ +# define USART3_ASSIGNED 1 # endif #endif +/* Pick ttys1. This could be any of UART0-1, USART0-3 excluding the console UART. */ + +#if defined(CONFIG_SAM34_UART0) && !defined(UART0_ASSIGNED) +# define TTYS1_DEV g_uart0port /* UART0 is ttyS1 */ +# define UART0_ASSIGNED 1 +#elif defined(CONFIG_SAM34_UART1) && !defined(UART1_ASSIGNED) +# define TTYS1_DEV g_uart1port /* UART1 is ttyS1 */ +# define UART1_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART0) && !defined(USART0_ASSIGNED) +# define TTYS1_DEV g_usart0port /* USART0 is ttyS1 */ +# define USART0_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART1) && !defined(USART1_ASSIGNED) +# define TTYS1_DEV g_usart1port /* USART1 is ttyS1 */ +# define USART1_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART2) && !defined(USART2_ASSIGNED) +# define TTYS1_DEV g_usart2port /* USART2 is ttyS1 */ +# define USART2_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART3) && !defined(USART3_ASSIGNED) +# define TTYS1_DEV g_usart3port /* USART3 is ttyS1 */ +# define USART3_ASSIGNED 1 +#endif + +/* Pick ttys2. This could be one of UART1 or USART0-3. It can't be UART0 + * because that was either assigned as ttyS0 or ttys1. One of these + * could also be the console. + */ + +#if defined(CONFIG_SAM34_UART1) && !defined(UART1_ASSIGNED) +# define TTYS2_DEV g_uart1port /* UART1 is ttyS2 */ +# define UART1_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART0) && !defined(USART0_ASSIGNED) +# define TTYS2_DEV g_usart0port /* USART0 is ttyS2 */ +# define USART0_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART1) && !defined(USART1_ASSIGNED) +# define TTYS2_DEV g_usart1port /* USART1 is ttyS2 */ +# define USART1_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART2) && !defined(USART2_ASSIGNED) +# define TTYS2_DEV g_usart2port /* USART2 is ttyS2 */ +# define USART2_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART3) && !defined(USART3_ASSIGNED) +# define TTYS2_DEV g_usart3port /* USART3 is ttyS2 */ +# define USART3_ASSIGNED 1 +#endif + +/* Pick ttys3. This could be one of USART0-3. It can't be UART0-1 because + * those have already been assigned to ttsyS0, 1, or 2. One of + * USART0-3 could also be the console. + */ + +#if defined(CONFIG_SAM34_USART0) && !defined(USART0_ASSIGNED) +# define TTYS3_DEV g_usart0port /* USART0 is ttyS3 */ +# define USART0_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART1) && !defined(USART1_ASSIGNED) +# define TTYS3_DEV g_usart1port /* USART1 is ttyS3 */ +# define USART1_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART2) && !defined(USART2_ASSIGNED) +# define TTYS3_DEV g_usart2port /* USART2 is ttyS3 */ +# define USART2_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART3) && !defined(USART3_ASSIGNED) +# define TTYS3_DEV g_usart3port /* USART3 is ttyS3 */ +# define USART3_ASSIGNED 1 +#endif + +/* Pick ttys4. This could be one of USART1-3. It can't be UART0-1 or USART0 + * because those have already been assigned to ttsyS0, 1, 2 or 3. One of + * USART1-3 could also be the console. + */ + +#if defined(CONFIG_SAM34_USART1) && !defined(USART1_ASSIGNED) +# define TTYS4_DEV g_usart1port /* USART1 is ttyS4 */ +# define USART1_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART2) && !defined(USART2_ASSIGNED) +# define TTYS4_DEV g_usart2port /* USART2 is ttyS4 */ +# define USART2_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART3) && !defined(USART3_ASSIGNED) +# define TTYS4_DEV g_usart3port /* USART3 is ttyS4 */ +# define USART3_ASSIGNED 1 +#endif + +/* Pick ttys5. This could be one of USART2-3. It can't be UART0-1 or + * USART0-1 because those have already been assigned to ttsyS0, 1, 2, + * 3 or 4. One of USART2-3 could also be the console. + */ + +#if defined(CONFIG_SAM34_USART2) && !defined(USART2_ASSIGNED) +# define TTYS5_DEV g_usart2port /* USART2 is ttyS5 */ +# define USART2_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART3) && !defined(USART3_ASSIGNED) +# define TTYS5_DEV g_usart3port /* USART3 is ttyS5 */ +# define USART3_ASSIGNED 1 +#endif + +/* Select MCU-specific settings + * + * For the SAM3U, the USARTs are driven by the main clock. + * For the SAM4L, the USARTs are driven by CLK_USART (undivided) which is + * selected by the PBADIVMASK register. + */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_MR_USCLKS UART_MR_USCLKS_MCK /* Source = Main clock */ +# define SAM_USART_CLOCK BOARD_MCK_FREQUENCY /* Frequency of the main clock */ +#elif defined(CONFIG_ARCH_CHIP_SAM4L) +# define SAM_MR_USCLKS UART_MR_USCLKS_USART /* Source = USART_CLK (undefined) */ +# define SAM_USART_CLOCK BOARD_PBA_FREQUENCY /* PBA frequency is undivided */ +#else +# error Unrecognized SAM architecture +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -601,9 +380,13 @@ static const struct uart_ops_s g_uart_ops = /* I/O buffers */ -#ifdef CONFIG_SAM34_UART -static char g_uartrxbuffer[CONFIG_UART_RXBUFSIZE]; -static char g_uarttxbuffer[CONFIG_UART_TXBUFSIZE]; +#ifdef CONFIG_SAM34_UART0 +static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; +static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; +#endif +#ifdef CONFIG_SAM34_UART1 +static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE]; +static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; #endif #ifdef CONFIG_SAM34_USART0 static char g_usart0rxbuffer[CONFIG_USART0_RXBUFSIZE]; @@ -622,33 +405,63 @@ static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; #endif -/* This describes the state of the UART port. */ +/* This describes the state of the UART0 port. */ -#ifdef CONFIG_SAM34_UART -static struct up_dev_s g_uartpriv = +#ifdef CONFIG_SAM34_UART0 +static struct up_dev_s g_uart0priv = { - .usartbase = SAM_UART_BASE, - .baud = CONFIG_UART_BAUD, - .irq = SAM_IRQ_UART, - .parity = CONFIG_UART_PARITY, - .bits = CONFIG_UART_BITS, - .stopbits2 = CONFIG_UART_2STOP, + .usartbase = SAM_UART0_BASE, + .baud = CONFIG_UART0_BAUD, + .irq = SAM_IRQ_UART0, + .parity = CONFIG_UART0_PARITY, + .bits = CONFIG_UART0_BITS, + .stopbits2 = CONFIG_UART0_2STOP, }; -static uart_dev_t g_uartport = +static uart_dev_t g_uart0port = { .recv = { - .size = CONFIG_UART_RXBUFSIZE, - .buffer = g_uartrxbuffer, + .size = CONFIG_UART0_RXBUFSIZE, + .buffer = g_uart0rxbuffer, }, .xmit = { - .size = CONFIG_UART_TXBUFSIZE, - .buffer = g_uarttxbuffer, + .size = CONFIG_UART0_TXBUFSIZE, + .buffer = g_uart0txbuffer, }, .ops = &g_uart_ops, - .priv = &g_uartpriv, + .priv = &g_uart0priv, +}; +#endif + +/* This describes the state of the UART1 port. */ + +#ifdef CONFIG_SAM34_UART1 +static struct up_dev_s g_uart1priv = +{ + .usartbase = SAM_UART1_BASE, + .baud = CONFIG_UART1_BAUD, + .irq = SAM_IRQ_UART1, + .parity = CONFIG_UART1_PARITY, + .bits = CONFIG_UART1_BITS, + .stopbits2 = CONFIG_UART1_2STOP, +}; + +static uart_dev_t g_uart1port = +{ + .recv = + { + .size = CONFIG_UART1_RXBUFSIZE, + .buffer = g_uart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART1_TXBUFSIZE, + .buffer = g_uart1txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart1priv, }; #endif @@ -873,37 +686,38 @@ static int up_setup(struct uart_dev_s *dev) * as the timing source */ - regval = (USART_MR_MODE_NORMAL|USART_MR_USCLKS_MCK); + regval = (UART_MR_MODE_NORMAL | SAM_MR_USCLKS); /* OR in settings for the selected number of bits */ if (priv->bits == 5) { - regval |= USART_MR_CHRL_5BITS; /* 5 bits */ + regval |= UART_MR_CHRL_5BITS; /* 5 bits */ } else if (priv->bits == 6) { - regval |= USART_MR_CHRL_6BITS; /* 6 bits */ + regval |= UART_MR_CHRL_6BITS; /* 6 bits */ } else if (priv->bits == 7) { - regval |= USART_MR_CHRL_7BITS; /* 7 bits */ + regval |= UART_MR_CHRL_7BITS; /* 7 bits */ } #ifdef HAVE_USART -#ifdef CONFIG_SAM34_UART - /* UART does not support 9bit mode */ - - else if (priv->bits == 9 && priv->usartbase != SAM_UART_BASE) -#else - else if (priv->bits == 9) /* Only USARTS */ + else if (priv->bits == 9 +#if defined(CONFIG_SAM34_UART0) + && priv->usartbase != SAM_UART0_BASE #endif +#if defined(CONFIG_SAM34_UART1) + && priv->usartbase != SAM_UART1_BASE +#endif + ) { - regval |= USART_MR_MODE9; /* 9 bits */ + regval |= UART_MR_MODE9; /* 9 bits */ } #endif else /* if (priv->bits == 8) */ { - regval |= USART_MR_CHRL_8BITS; /* 8 bits (default) */ + regval |= UART_MR_CHRL_8BITS; /* 8 bits (default) */ } /* OR in settings for the selected parity */ @@ -925,20 +739,22 @@ static int up_setup(struct uart_dev_s *dev) if (priv->stopbits2) { - regval |= USART_MR_NBSTOP_2; + regval |= UART_MR_NBSTOP_2; } else { - regval |= USART_MR_NBSTOP_1; + regval |= UART_MR_NBSTOP_1; } /* And save the new mode register value */ up_serialout(priv, SAM_UART_MR_OFFSET, regval); - /* Configure the console baud */ + /* Configure the console baud. NOTE: Oversampling by 8 is not supported. + * This may limit BAUD rates for lower USART clocks. + */ - regval = (SAM_MCK_FREQUENCY + (priv->baud << 3))/(priv->baud << 4); + regval = (SAM_USART_CLOCK + (priv->baud << 3))/(priv->baud << 4); up_serialout(priv, SAM_UART_BRGR_OFFSET, regval); /* Enable receiver & transmitter */ @@ -1042,10 +858,17 @@ static int up_interrupt(int irq, void *context) int passes; bool handled; -#ifdef CONFIG_SAM34_UART - if (g_uartpriv.irq == irq) +#ifdef CONFIG_SAM34_UART0 + if (g_uart0priv.irq == irq) { - dev = &g_uartport; + dev = &g_uart0port; + } + else +#endif +#ifdef CONFIG_SAM34_UART1 + if (g_uart1priv.irq == irq) + { + dev = &g_uart1port; } else #endif @@ -1094,7 +917,7 @@ static int up_interrupt(int irq, void *context) /* Get the UART/USART status (we are only interested in the unmasked interrupts). */ priv->sr = up_serialin(priv, SAM_UART_SR_OFFSET); /* Save for error reporting */ - pending = priv->sr & priv->imr; /* Mask out disabled interrupt sources */ + pending = priv->sr & priv->imr; /* Mask out disabled interrupt sources */ /* Handle an incoming, receive byte. RXRDY: At least one complete character * has been received and US_RHR has not yet been read. @@ -1285,6 +1108,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable) priv->imr &= ~UART_INT_TXRDY; up_disableint(priv); } + irqrestore(flags); } diff --git a/nuttx/arch/arm/src/sam34/sam_spi.c b/nuttx/arch/arm/src/sam34/sam_spi.c index 10395ec90..2143a5c15 100644 --- a/nuttx/arch/arm/src/sam34/sam_spi.c +++ b/nuttx/arch/arm/src/sam34/sam_spi.c @@ -57,7 +57,8 @@ #include "chip.h" #include "sam_gpio.h" #include "sam_spi.h" -#include "chip/sam_pmc.h" +#include "sam_periphclks.h" +#include "chip/sam3u_pmc.h" #include "chip/sam_spi.h" #include "chip/sam_pinmap.h" @@ -66,6 +67,19 @@ /**************************************************************************** * Definitions ****************************************************************************/ +/* Select MCU-specific settings + * + * For the SAM3U, SPI is driven by the main clock. + * For the SAM4L, SPI driven by CLK_SPI which is the PBB clock. + */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_SPI_CLOCK BOARD_MCK_FREQUENCY /* Frequency of the main clock */ +#elif defined(CONFIG_ARCH_CHIP_SAM4L) +# define SAM_SPI_CLOCK BOARD_PBB_FREQUENCY /* PBB frequency */ +#else +# error Unrecognized SAM architecture +#endif /* Check if SPI debut is enabled (non-standard.. no support in * include/debug.h @@ -461,7 +475,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) * SPCK frequency = MCK / SCBR, or SCBR = MCK / frequency */ - scbr = SAM_MCK_FREQUENCY / frequency; + scbr = SAM_SPI_CLOCK / frequency; if (scbr < 8) { @@ -493,7 +507,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) * DLYBS = MCK * 0.000002 = MCK / 500000 */ - dlybs = SAM_MCK_FREQUENCY / 500000; + dlybs = SAM_SPI_CLOCK / 500000; regval |= dlybs << SPI_CSR_DLYBS_SHIFT; /* DLYBCT: Delay Between Consecutive Transfers. This field defines the delay @@ -508,13 +522,13 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) * DLYBCT = MCK * 0.000005 / 32 = MCK / 200000 / 32 */ - dlybct = SAM_MCK_FREQUENCY / 200000 / 32; + dlybct = SAM_SPI_CLOCK / 200000 / 32; regval |= dlybct << SPI_CSR_DLYBCT_SHIFT; putreg32(regval, regaddr); /* Calculate the new actual frequency */ - actual = SAM_MCK_FREQUENCY / scbr; + actual = SAM_SPI_CLOCK / scbr; spivdbg("csr[%08x]=%08x actual=%d\n", regaddr, regval, actual); /* Save the frequency setting */ @@ -886,7 +900,6 @@ FAR struct spi_dev_s *up_spiinitialize(int port) { FAR struct sam_spidev_s *priv = &g_spidev; irqstate_t flags; - uint32_t regval; /* The SAM3U has only a single SPI port */ @@ -897,15 +910,9 @@ FAR struct spi_dev_s *up_spiinitialize(int port) priv->cs = 0xff; - /* Apply power to the SPI block */ + /* Enable clocking to the SPI block */ - flags = irqsave(); - regval = getreg32(SAM_PMC_PCER); - regval |= (1 << SAM_PID_SPI); -#ifdef CONFIG_SAM34_SPIINTERRUPT - regval |= (1 << SAM_IRQ_SPI); -#endif - putreg32(regval, SAM_PMC_PCER); + sam_spi_enableclk(); /* Configure multiplexed pins as connected on the board. Chip select pins * must be configured by board-specific logic. diff --git a/nuttx/arch/arm/src/sam34/sam_start.c b/nuttx/arch/arm/src/sam34/sam_start.c index a3fc49fa2..6324617f3 100644 --- a/nuttx/arch/arm/src/sam34/sam_start.c +++ b/nuttx/arch/arm/src/sam34/sam_start.c @@ -54,8 +54,11 @@ #include "sam_userspace.h" /**************************************************************************** - * Private Definitions + * Pre-processor Definitions ****************************************************************************/ +#if defined(CONFIG_WDT_ENABLED_ON_RESET) && defined(CONFIG_WDT_DISABLE_ON_RESET) +# define NEED_WDT_DISABLE +#endif /**************************************************************************** * Private Data @@ -100,12 +103,6 @@ void __start(void) const uint32_t *src; uint32_t *dest; - /* Configure the uart so that we can get debug output as soon as possible */ - - sam_clockconfig(); - sam_lowsetup(); - showprogress('A'); - /* Clear .bss. We'll do this inline (vs. calling memset) just to be * certain that there are no issues with the state of global variables. */ @@ -114,7 +111,6 @@ void __start(void) { *dest++ = 0; } - showprogress('B'); /* Move the intialized data section from his temporary holding spot in * FLASH into the correct place in SRAM. The correct place in SRAM is @@ -126,14 +122,38 @@ void __start(void) { *dest++ = *src++; } - showprogress('C'); + +#ifdef NEED_WDT_DISABLE + /* Disable the watchdog timer */ +# warning Missing logic +#endif + + /* Copy any necessary code sections from FLASH to RAM. The correct + * destination in SRAM is geive by _sramfuncs and _eramfuncs. The + * temporary location is in flash after the data initalization code + * at _framfuncs. This must be done before sam_clockconfig() can be + * called (at least for the SAM4L family). + */ + +#ifdef CONFIG_ARCH_RAMFUNCS + for (src = &_framfuncs, dest = &_sramfuncs; dest < &_eramfuncs; ) + { + *dest++ = *src++; + } +#endif + + /* Configure the uart so that we can get debug output as soon as possible */ + + sam_clockconfig(); + sam_lowsetup(); + showprogress('A'); /* Perform early serial initialization */ #ifdef USE_EARLYSERIALINIT up_earlyserialinit(); #endif - showprogress('D'); + showprogress('B'); /* For the case of the separate user-/kernel-space build, perform whatever * platform specific initialization of the user memory is required. @@ -143,13 +163,13 @@ void __start(void) #ifdef CONFIG_NUTTX_KERNEL sam_userspace(); - showprogress('E'); + showprogress('C'); #endif /* Initialize onboard resources */ sam_boardinitialize(); - showprogress('F'); + showprogress('D'); /* Then start NuttX */ diff --git a/nuttx/arch/arm/src/sam34/sam_timerisr.c b/nuttx/arch/arm/src/sam34/sam_timerisr.c index e1879d5cc..572b04626 100644 --- a/nuttx/arch/arm/src/sam34/sam_timerisr.c +++ b/nuttx/arch/arm/src/sam34/sam_timerisr.c @@ -55,6 +55,20 @@ /**************************************************************************** * Definitions ****************************************************************************/ +/* Select MCU-specific settings + * + * For the SAM3U, Systick is driven by the main clock. + * For the SAM4L, Systick is driven by the CPU clock which is just the main + * clock divided down. + */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_SYSTICK_CLOCK BOARD_MCK_FREQUENCY /* Frequency of the main clock */ +#elif defined(CONFIG_ARCH_CHIP_SAM4L) || defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_SYSTICK_CLOCK BOARD_CPU_FREQUENCY /* CPU frequency */ +#else +# error Unrecognized SAM architecture +#endif /* The desired timer interrupt frequency is provided by the definition * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of @@ -69,9 +83,9 @@ #undef CONFIG_SAM34_SYSTICK_HCLKd8 /* Power up default is MCK, not MCK/8 */ #if CONFIG_SAM34_SYSTICK_HCLKd8 -# define SYSTICK_RELOAD ((SAM_MCK_FREQUENCY / 8 / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((SAM_SYSTICK_CLOCK / 8 / CLK_TCK) - 1) #else -# define SYSTICK_RELOAD ((SAM_MCK_FREQUENCY / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((SAM_SYSTICK_CLOCK / CLK_TCK) - 1) #endif /* The size of the reload field is 24 bits. Verify that the reload value diff --git a/nuttx/arch/arm/src/sam34/sam_vectors.S b/nuttx/arch/arm/src/sam34/sam_vectors.S index 007367857..c6a11b31e 100644 --- a/nuttx/arch/arm/src/sam34/sam_vectors.S +++ b/nuttx/arch/arm/src/sam34/sam_vectors.S @@ -61,19 +61,23 @@ * 0x2000:bfff - End of SRAM and end of heap */ -#define IDLE_STACK (_ebss+CONFIG_IDLETHREAD_STACKSIZE) +#define IDLE_STACK (_ebss+CONFIG_IDLETHREAD_STACKSIZE-4) #define HEAP_BASE (_ebss+CONFIG_IDLETHREAD_STACKSIZE) /************************************************************************************************ * Global Symbols ************************************************************************************************/ - .globl __start - .syntax unified .thumb .file "sam_vectors.S" +/* Check if common ARMv7 interrupt vectoring is used (see arch/arm/src/armv7-m/up_vectors.S) */ + +#ifndef CONFIG_ARMV7M_CMNVECTOR + + .globl __start + /************************************************************************************************ * Macros ************************************************************************************************/ @@ -128,14 +132,16 @@ sam_vectors: #define VECTOR(l,i) .word l #undef UNUSED -#define UNUSED(i) .word stm32_reserved +#define UNUSED(i) .word sam_reserved #if defined(CONFIG_ARCH_CHIP_SAM3U) # include "chip/sam3u_vectors.h" #elif defined(CONFIG_ARCH_CHIP_SAM4L) # include "chip/sam4l_vectors.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# include "chip/sam4s_vectors.h" #else -# Unrecognized SAM architecture +# error Unrecognized SAM architecture #endif .size sam_vectors, .-sam_vectors @@ -169,8 +175,10 @@ handlers: # include "chip/sam3u_vectors.h" #elif defined(CONFIG_ARCH_CHIP_SAM4L) # include "chip/sam4l_vectors.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# include "chip/sam4s_vectors.h" #else -# Unrecognized SAM architecture +# error Unrecognized SAM architecture #endif /* Common IRQ handling logic. On entry here, the return stack is on either @@ -293,8 +301,8 @@ sam_common: #endif /* We are returning with a pending context switch. This case is different - * because in this case, the register save structure does not lie on the - * stack but, rather, are within a TCB structure. We'll have to copy some + * because in this case, the register save structure does not lie in the + * stack but, rather, within a TCB structure. We'll have to copy some * values to the stack. */ @@ -401,6 +409,7 @@ up_interruptstack: g_intstackbase: .size up_interruptstack, .-up_interruptstack #endif +#endif /* CONFIG_ARMV7M_CMNVECTOR */ /************************************************************************************************ * .rodata diff --git a/nuttx/arch/arm/src/stm32/stm32_otgfshost.c b/nuttx/arch/arm/src/stm32/stm32_otgfshost.c index 80a9392dc..4b9eeb6c2 100644 --- a/nuttx/arch/arm/src/stm32/stm32_otgfshost.c +++ b/nuttx/arch/arm/src/stm32/stm32_otgfshost.c @@ -1,7 +1,7 @@ /******************************************************************************* * arch/arm/src/stm32/stm32_otgfshost.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -2176,7 +2176,7 @@ static void stm32_gint_disconnected(FAR struct stm32_usbhost_s *priv) { /* Were we previously connected? */ - if (!priv->connected) + if (priv->connected) { /* Yes.. then we no longer connected */ diff --git a/nuttx/arch/arm/src/stm32/stm32_serial.c b/nuttx/arch/arm/src/stm32/stm32_serial.c index b172a224f..52a77e255 100644 --- a/nuttx/arch/arm/src/stm32/stm32_serial.c +++ b/nuttx/arch/arm/src/stm32/stm32_serial.c @@ -257,15 +257,23 @@ struct up_dev_s uint8_t parity; /* 0=none, 1=odd, 2=even */ uint8_t bits; /* Number of bits (7 or 8) */ bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL bool iflow; /* input flow control (RTS) enabled */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL bool oflow; /* output flow control (CTS) enabled */ +#endif uint32_t baud; /* Configured baud */ #else const uint8_t parity; /* 0=none, 1=odd, 2=even */ const uint8_t bits; /* Number of bits (7 or 8) */ const bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL const bool iflow; /* input flow control (RTS) enabled */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL const bool oflow; /* output flow control (CTS) enabled */ +#endif const uint32_t baud; /* Configured baud */ #endif @@ -274,8 +282,12 @@ struct up_dev_s const uint32_t usartbase; /* Base address of USART registers */ const uint32_t tx_gpio; /* U[S]ART TX GPIO pin configuration */ const uint32_t rx_gpio; /* U[S]ART RX GPIO pin configuration */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL const uint32_t rts_gpio; /* U[S]ART RTS GPIO pin configuration */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL const uint32_t cts_gpio; /* U[S]ART CTS GPIO pin configuration */ +#endif #ifdef SERIAL_HAVE_DMA const unsigned int rxdma_channel; /* DMA channel assigned */ @@ -496,17 +508,21 @@ static struct up_dev_s g_usart1priv = .parity = CONFIG_USART1_PARITY, .bits = CONFIG_USART1_BITS, .stopbits2 = CONFIG_USART1_2STOP, +#ifdef CONFIG_SERIAL_IFLOWCONTROL .iflow = false, +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL .oflow = false, +#endif .baud = CONFIG_USART1_BAUD, .apbclock = STM32_PCLK2_FREQUENCY, .usartbase = STM32_USART1_BASE, .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, -#ifdef GPIO_USART1_CTS +#if defined(CONFIG_SERIAL_OFLOWCONROL) && defined(CONFIG_USART1_OFLOWCONTROL) .cts_gpio = GPIO_USART1_CTS, #endif -#ifdef GPIO_USART1_RTS +#if defined(CONFIG_SERIAL_IFLOWCONROL) && defined(CONFIG_USART1_IFLOWCONTROL) .rts_gpio = GPIO_USART1_RTS, #endif #ifdef CONFIG_USART1_RXDMA @@ -558,17 +574,21 @@ static struct up_dev_s g_usart2priv = .parity = CONFIG_USART2_PARITY, .bits = CONFIG_USART2_BITS, .stopbits2 = CONFIG_USART2_2STOP, +#ifdef CONFIG_SERIAL_IFLOWCONTROL .iflow = false, +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL .oflow = false, +#endif .baud = CONFIG_USART2_BAUD, .apbclock = STM32_PCLK1_FREQUENCY, .usartbase = STM32_USART2_BASE, .tx_gpio = GPIO_USART2_TX, .rx_gpio = GPIO_USART2_RX, -#ifdef GPIO_USART2_CTS +#if defined(CONFIG_SERIAL_OFLOWCONROL) && defined(CONFIG_USART2_OFLOWCONTROL) .cts_gpio = GPIO_USART2_CTS, #endif -#ifdef GPIO_USART2_RTS +#if defined(CONFIG_SERIAL_IFLOWCONROL) && defined(CONFIG_USART2_IFLOWCONTROL) .rts_gpio = GPIO_USART2_RTS, #endif #ifdef CONFIG_USART2_RXDMA @@ -620,17 +640,21 @@ static struct up_dev_s g_usart3priv = .parity = CONFIG_USART3_PARITY, .bits = CONFIG_USART3_BITS, .stopbits2 = CONFIG_USART3_2STOP, +#ifdef CONFIG_SERIAL_IFLOWCONTROL .iflow = false, +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL .oflow = false, +#endif .baud = CONFIG_USART3_BAUD, .apbclock = STM32_PCLK1_FREQUENCY, .usartbase = STM32_USART3_BASE, .tx_gpio = GPIO_USART3_TX, .rx_gpio = GPIO_USART3_RX, -#ifdef GPIO_USART3_CTS +#if defined(CONFIG_SERIAL_OFLOWCONROL) && defined(CONFIG_USART3_OFLOWCONTROL) .cts_gpio = GPIO_USART3_CTS, #endif -#ifdef GPIO_USART3_RTS +#if defined(CONFIG_SERIAL_IFLOWCONROL) && defined(CONFIG_USART3_IFLOWCONTROL) .rts_gpio = GPIO_USART3_RTS, #endif #ifdef CONFIG_USART3_RXDMA @@ -682,15 +706,23 @@ static struct up_dev_s g_uart4priv = .parity = CONFIG_UART4_PARITY, .bits = CONFIG_UART4_BITS, .stopbits2 = CONFIG_UART4_2STOP, +#ifdef CONFIG_SERIAL_IFLOWCONTROL .iflow = false, +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL .oflow = false, +#endif .baud = CONFIG_UART4_BAUD, .apbclock = STM32_PCLK1_FREQUENCY, .usartbase = STM32_UART4_BASE, .tx_gpio = GPIO_UART4_TX, .rx_gpio = GPIO_UART4_RX, - .cts_gpio = 0, /* flow control not supported on this port */ - .rts_gpio = 0, /* flow control not supported on this port */ +#ifdef CONFIG_SERIAL_OFLOWCONROL + .cts_gpio = 0, +#endif +#ifdef CONFIG_SERIAL_IFLOWCONROL + .rts_gpio = 0, +#endif #ifdef CONFIG_UART4_RXDMA .rxdma_channel = DMAMAP_UART4_RX, .rxfifo = g_uart4rxfifo, @@ -740,15 +772,23 @@ static struct up_dev_s g_uart5priv = .parity = CONFIG_UART5_PARITY, .bits = CONFIG_UART5_BITS, .stopbits2 = CONFIG_UART5_2STOP, +#ifdef CONFIG_SERIAL_IFLOWCONTROL .iflow = false, +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL .oflow = false, +#endif .baud = CONFIG_UART5_BAUD, .apbclock = STM32_PCLK1_FREQUENCY, .usartbase = STM32_UART5_BASE, .tx_gpio = GPIO_UART5_TX, .rx_gpio = GPIO_UART5_RX, - .cts_gpio = 0, /* flow control not supported on this port */ - .rts_gpio = 0, /* flow control not supported on this port */ +#ifdef CONFIG_SERIAL_OFLOWCONROL + .cts_gpio = 0, +#endif +#ifdef CONFIG_SERIAL_IFLOWCONROL + .rts_gpio = 0, +#endif #ifdef CONFIG_UART5_RXDMA .rxdma_channel = DMAMAP_UART5_RX, .rxfifo = g_uart5rxfifo, @@ -798,17 +838,21 @@ static struct up_dev_s g_usart6priv = .parity = CONFIG_USART6_PARITY, .bits = CONFIG_USART6_BITS, .stopbits2 = CONFIG_USART6_2STOP, +#ifdef CONFIG_SERIAL_IFLOWCONTROL .iflow = false, +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL .oflow = false, +#endif .baud = CONFIG_USART6_BAUD, .apbclock = STM32_PCLK2_FREQUENCY, .usartbase = STM32_USART6_BASE, .tx_gpio = GPIO_USART6_TX, .rx_gpio = GPIO_USART6_RX, -#ifdef GPIO_USART6_CTS +#if defined(CONFIG_SERIAL_OFLOWCONROL) && defined(CONFIG_USART6_OFLOWCONTROL) .cts_gpio = GPIO_USART6_CTS, #endif -#ifdef GPIO_USART6_RTS +#if defined(CONFIG_SERIAL_IFLOWCONROL) && defined(CONFIG_USART6_IFLOWCONTROL) .rts_gpio = GPIO_USART6_RTS, #endif #ifdef CONFIG_USART6_RXDMA @@ -865,10 +909,10 @@ static struct up_dev_s g_uart7priv = .usartbase = STM32_UART7_BASE, .tx_gpio = GPIO_UART7_TX, .rx_gpio = GPIO_UART7_RX, -#ifdef GPIO_UART7_CTS +#if defined(CONFIG_SERIAL_OFLOWCONROL) && defined(CONFIG_USART7_OFLOWCONTROL) .cts_gpio = GPIO_UART7_CTS, #endif -#ifdef GPIO_UART7_RTS +#if defined(CONFIG_SERIAL_IFLOWCONROL) && defined(CONFIG_USART7_IFLOWCONTROL) .rts_gpio = GPIO_UART7_RTS, #endif #ifdef CONFIG_UART7_RXDMA @@ -925,10 +969,10 @@ static struct up_dev_s g_uart8priv = .usartbase = STM32_UART8_BASE, .tx_gpio = GPIO_UART8_TX, .rx_gpio = GPIO_UART8_RX, -#ifdef GPIO_UART8_CTS +#if defined(CONFIG_SERIAL_OFLOWCONROL) && defined(CONFIG_USART8_OFLOWCONTROL) .cts_gpio = GPIO_UART8_CTS, #endif -#ifdef GPIO_UART8_RTS +#if defined(CONFIG_SERIAL_IFLOWCONROL) && defined(CONFIG_USART8_IFLOWCONTROL) .rts_gpio = GPIO_UART8_RTS, #endif #ifdef CONFIG_UART8_RXDMA @@ -1109,13 +1153,14 @@ static int up_dma_nextrx(struct up_dev_s *priv) #ifndef CONFIG_SUPPRESS_UART_CONFIG static void up_set_format(struct uart_dev_s *dev) { -#ifdef CONFIG_STM32_STM32F30XX + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + uint32_t regval; +#ifdef CONFIG_STM32_STM32F30XX /* This first implementation is for U[S]ARTs that support oversampling * by 8 in additional to the standard oversampling by 16. */ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; uint32_t usartdiv8; uint32_t cr1; uint32_t brr; @@ -1171,12 +1216,10 @@ static void up_set_format(struct uart_dev_s *dev) * dividers. */ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; uint32_t usartdiv32; uint32_t mantissa; uint32_t fraction; uint32_t brr; - uint32_t regval; /* Configure the USART Baud Rate. The baud rate for the receiver and * transmitter (Rx and Tx) are both set to the same value as programmed @@ -1206,6 +1249,7 @@ static void up_set_format(struct uart_dev_s *dev) fraction = (usartdiv32 - (mantissa << 5) + 1) >> 1; brr |= fraction << USART_BRR_FRAC_SHIFT; up_serialout(priv, STM32_USART_BRR_OFFSET, brr); +#endif /* Configure parity mode */ @@ -1232,6 +1276,7 @@ static void up_set_format(struct uart_dev_s *dev) { regval |= USART_CR2_STOP2; } + up_serialout(priv, STM32_USART_CR2_OFFSET, regval); /* Configure hardware flow control */ @@ -1239,14 +1284,19 @@ static void up_set_format(struct uart_dev_s *dev) regval = up_serialin(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE|USART_CR3_RTSE); +#ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow && (priv->rts_gpio != 0)) - { + { regval |= USART_CR3_RTSE; } +#endif + +#ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->oflow && (priv->cts_gpio != 0)) - { + { regval |= USART_CR3_CTSE; } +#endif up_serialout(priv, STM32_USART_CR3_OFFSET, regval); @@ -1279,15 +1329,19 @@ static int up_setup(struct uart_dev_s *dev) stm32_configgpio(priv->tx_gpio); stm32_configgpio(priv->rx_gpio); +#ifdef CONFIG_SERIAL_OFLOWCONROL if (priv->cts_gpio != 0) { stm32_configgpio(priv->cts_gpio); } +#endif +#ifdef CONFIG_SERIAL_IFLOWCONROL if (priv->rts_gpio != 0) { stm32_configgpio(priv->rts_gpio); } +#endif #if HAVE_RS485 if (priv->rs485_dir_gpio != 0) @@ -1298,10 +1352,10 @@ static int up_setup(struct uart_dev_s *dev) #endif /* Configure CR2 */ - /* Clear CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ + /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ regval = up_serialin(priv, STM32_USART_CR2_OFFSET); - regval &= ~(USART_CR2_CLKEN|USART_CR2_CPOL| + regval &= ~(USART_CR2_STOP_MASK|USART_CR2_CLKEN|USART_CR2_CPOL| USART_CR2_CPHA|USART_CR2_LBCL|USART_CR2_LBDIE); /* Configure STOP bits */ @@ -1317,8 +1371,7 @@ static int up_setup(struct uart_dev_s *dev) /* Clear M, TE, REm and all interrupt enable bits */ regval = up_serialin(priv, STM32_USART_CR1_OFFSET); - regval &= ~(USART_CR1_M|USART_CR1_TE| - USART_CR1_RE|USART_CR1_ALLINTS); + regval &= ~(USART_CR1_M|USART_CR1_TE|USART_CR1_RE|USART_CR1_ALLINTS); /* Configure word length */ @@ -1347,8 +1400,6 @@ static int up_setup(struct uart_dev_s *dev) regval |= (USART_CR1_UE|USART_CR1_TE|USART_CR1_RE); up_serialout(priv, STM32_USART_CR1_OFFSET, regval); -#endif - /* Set up the cached interrupt enables value */ priv->ie = 0; @@ -1374,7 +1425,7 @@ static int up_dma_setup(struct uart_dev_s *dev) /* Do the basic UART setup first, unless we are the console */ if (!dev->isconsole) - { + { result = up_setup(dev); if (result != OK) { @@ -1706,7 +1757,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) up_serialout(priv, STM32_USART_CR3_OFFSET, cr); } - break; + break; #endif #ifdef CONFIG_SERIAL_TERMIOS @@ -1726,12 +1777,16 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * there is no way to report 9-bit mode, we always claim 8. */ - termiosp->c_cflag = + termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) | ((priv->parity == 1) ? PARODD : 0) | ((priv->stopbits2) ? CSTOPB : 0) | +#ifdef CONFIG_SERIAL_OFLOWCONTROL ((priv->oflow) ? CCTS_OFLOW : 0) | +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL ((priv->iflow) ? CRTS_IFLOW : 0) | +#endif CS8; /* TODO: CCTS_IFLOW, CCTS_OFLOW */ @@ -1750,26 +1805,35 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) /* Perform some sanity checks before accepting any changes */ - if (((termiosp->c_cflag & CSIZE) != CS8) || - ((termiosp->c_cflag & CCTS_OFLOW) && (priv->cts_gpio == 0)) || - ((termiosp->c_cflag & CRTS_IFLOW) && (priv->rts_gpio == 0))) - { + if (((termiosp->c_cflag & CSIZE) != CS8) +#ifdef CONFIG_SERIAL_IFLOWCONROL + || ((termiosp->c_cflag & CCTS_OFLOW) && (priv->cts_gpio == 0)) +#endif +#ifdef CONFIG_SERIAL_IFLOWCONROL + || ((termiosp->c_cflag & CRTS_IFLOW) && (priv->rts_gpio == 0)) +#endif + ) + { ret = -EINVAL; break; } if (termiosp->c_cflag & PARENB) - { + { priv->parity = (termiosp->c_cflag & PARODD) ? 1 : 2; } else - { + { priv->parity = 0; } priv->stopbits2 = (termiosp->c_cflag & CSTOPB) != 0; +#ifdef CONFIG_SERIAL_OFLOWCONTROL priv->oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0; +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL priv->iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0; +#endif /* Note that since there is no way to request 9-bit mode * and no way to support 5/6/7-bit modes, we ignore them |