1 files changed, 27 insertions, 28 deletions

diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-irq.c b/nuttx/arch/mips/src/pic32mx/pic32mx-irq.c
index fdaa232dc..ca860fb9a 100755
--- a/nuttx/arch/mips/src/pic32mx/pic32mx-irq.c
+++ b/nuttx/arch/mips/src/pic32mx/pic32mx-irq.c
@@ -125,9 +125,6 @@ void up_irqinitialize(void)
 
   current_regs = NULL;
 
-  /* Attach processor exceptions */
-#warning "Missing logic"
-
   /* Initialize logic to support a second level of interrupt decoding for
    * IOPORT pins.
    */
@@ -242,16 +239,18 @@ void up_enable_irq(int irq)
 }
 
 /****************************************************************************
- * Name: up_clrpend_irq
+ * Name: up_pending_irq
  *
  * Description:
- *   Clear any pending interrupt
+ *   Return true if the interrupt is pending and unmasked.
  *
  ****************************************************************************/
 
-void up_clrpend_irq(int irq)
+bool up_pending_irq(int irq)
 {
-  uint32_t regaddr;
+  uint32_t ifsaddr;
+  uint32_t iecaddr;
+  uint32_t regval;
   int bitno;
 
   /* Disable the interrupt by clearing the associated bit in the IEC and then
@@ -267,44 +266,47 @@ void up_clrpend_irq(int irq)
         {
           /* Use IFS0 */
 
-          regaddr = PIC32MX_INT_IFS0CLR;
+          ifsaddr = PIC32MX_INT_IFS0;
+          iecaddr = PIC32MX_INT_IEC0;
           bitno  -= PIC32MX_IRQSRC0_FIRST;
         }
       else if (irq <= PIC32MX_IRQSRC1_LAST)
         {
           /* Use IFS1 */
 
-          regaddr = PIC32MX_INT_IFS1CLR;
+          ifsaddr = PIC32MX_INT_IFS1;
+          iecaddr = PIC32MX_INT_IEC1;
           bitno  -= PIC32MX_IRQSRC1_FIRST;
         }
       else
         {
           /* Value out of range.. just ignore */
 
-          return;
+          return false;
         }
 
-      /* Disable then acknowledge interrupt */
+      /* Get the set of unmasked, pending interrupts.  Return true if the
+       * interrupt is pending and unmask.
+       */
 
-      putreg32((1 << bitno), regaddr);
+      regval = getreg32(ifsaddr) & getreg32(iecaddr);
+      return (regval & (1 << bitno)) != 0;
     }
+
+  return false;
 }
 
 /****************************************************************************
- * Name: up_maskack_irq
+ * Name: up_clrpend_irq
  *
  * Description:
- *   Mask the IRQ and acknowledge it.  This could be done by calling
- *   up_disable_irq followed by up_clrpend_irq, but since these function is
- *   called from interrupt handling logic it is probably worth the improved
- *   performance by doing doing both here.
+ *   Clear any pending interrupt
  *
  ****************************************************************************/
 
-void up_maskack_irq(int irq)
+void up_clrpend_irq(int irq)
 {
-  uint32_t iecaddr;
-  uint32_t ifsaddr;
+  uint32_t regaddr;
   int bitno;
 
   /* Disable the interrupt by clearing the associated bit in the IEC and then
@@ -318,18 +320,16 @@ void up_maskack_irq(int irq)
     {
       if (irq <= PIC32MX_IRQSRC0_LAST)
         {
-          /* Use IEC0 and IFS0*/
+          /* Use IFS0 */
 
-          iecaddr = PIC32MX_INT_IEC0CLR;
-          ifsaddr = PIC32MX_INT_IFS0CLR;
+          regaddr = PIC32MX_INT_IFS0CLR;
           bitno  -= PIC32MX_IRQSRC0_FIRST;
         }
       else if (irq <= PIC32MX_IRQSRC1_LAST)
         {
-          /* Use IEC1 and IFS1 */
+          /* Use IFS1 */
 
-          iecaddr = PIC32MX_INT_IEC1CLR;
-          ifsaddr = PIC32MX_INT_IFS1CLR;
+          regaddr = PIC32MX_INT_IFS1CLR;
           bitno  -= PIC32MX_IRQSRC1_FIRST;
         }
       else
@@ -341,8 +341,7 @@ void up_maskack_irq(int irq)
 
       /* Disable then acknowledge interrupt */
 
-      putreg32((1 << bitno), iecaddr);
-      putreg32((1 << bitno), ifsaddr);
+      putreg32((1 << bitno), regaddr);
     }
 }