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-rwxr-xr-xnuttx/arch/x86/src/i486/up_irq.c (renamed from nuttx/arch/x86/src/qemu/qemu_irq.c)159
-rwxr-xr-xnuttx/arch/x86/src/qemu/Make.defs6
-rwxr-xr-xnuttx/arch/x86/src/qemu/qemu_timerisr.c30
3 files changed, 141 insertions, 54 deletions
diff --git a/nuttx/arch/x86/src/qemu/qemu_irq.c b/nuttx/arch/x86/src/i486/up_irq.c
index b92db7882..33a9130d5 100755
--- a/nuttx/arch/x86/src/qemu/qemu_irq.c
+++ b/nuttx/arch/x86/src/i486/up_irq.c
@@ -1,6 +1,6 @@
/****************************************************************************
- * arch/x86/src/qemu/qemu_irq.c
- * arch/x86/src/chip/qemu_irq.c
+ * arch/x86/src/i486/up_irq.c
+ * arch/x86/src/chip/up_irq.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
@@ -113,27 +113,31 @@ static void up_remappic(void)
{
/* Mask interrupts from PIC */
- idt_outb(0xff, 0x21);
- idt_outb(0xff, 0xA1);
+ idt_outb(PIC1_IMR_ALL, PIC1_IMR);
+ idt_outb(PIC2_IMR_ALL, PIC2_IMR);
- /* Remap the irq table for primary */
+ /* If the PIC has been reset, it must be initialized with 2 to 4 Initialization
+ * Command Words (ICW) before it will accept and process Interrupt Requests. The
+ * following outlines the four possible Initialization Command Words.
+ */
- idt_outb(0x11, 0x20);
- idt_outb(0x20, 0x21);
- idt_outb(0x04, 0x21);
- idt_outb(0x01, 0x21);
-
- /* Remap irq for slave */
+ /* Remap the irq table for primary:
+ *
+ * ICW1 - We will be sending ICW4
+ * ICW2 - Address
+ * ICW3 */
- idt_outb(0x11, 0xA0);
- idt_outb(0x28, 0xA1);
- idt_outb(0x02, 0xA1);
- idt_outb(0x01, 0xA1);
+ idt_outb(PIC_ICW1_ICW4|PIC_ICW1_ICW1, PIC1_ICW1);
+ idt_outb(0x20, PIC1_ICW2);
+ idt_outb(PIC1_ICW3_IRQ2, PIC1_ICW3);
+ idt_outb(PIC_ICW4_808xMODE, PIC1_ICW4);
- /* Enable IRQ0 on the master with the mask */
+ /* Remap irq for slave */
- idt_outb( 0xff, 0xA1);
- idt_outb( 0xfe, 0x21);
+ idt_outb(PIC_ICW1_ICW4|PIC_ICW1_ICW1, PIC2_ICW1);
+ idt_outb(0x28, PIC2_ICW2);
+ idt_outb(PIC_ICW3_SID2, PIC2_ICW3);
+ idt_outb(PIC_ICW4_808xMODE, PIC2_ICW4);
}
/****************************************************************************
@@ -147,8 +151,8 @@ static void up_remappic(void)
static void up_idtentry(struct idt_entry_s *entry, uint32_t base,
uint16_t sel, uint8_t flags)
{
- entry->lobase = base & 0xFFFF;
- entry->hibase = (base >> 16) & 0xFFFF;
+ entry->lobase = base & 0xffff;
+ entry->hibase = (base >> 16) & 0xffff;
entry->sel = sel;
entry->zero = 0;
@@ -214,16 +218,16 @@ static inline void up_idtinit(void)
up_idtentry(&idt_entries[29], (uint32_t)vector_isr29, 0x08, 0x8e);
up_idtentry(&idt_entries[30], (uint32_t)vector_isr30, 0x08, 0x8e);
up_idtentry(&idt_entries[31], (uint32_t)vector_isr31, 0x08, 0x8e);
- up_idtentry(&idt_entries[32], (uint32_t)vector_irq0, 0x08, 0x8e);
- up_idtentry(&idt_entries[33], (uint32_t)vector_irq1, 0x08, 0x8e);
- up_idtentry(&idt_entries[34], (uint32_t)vector_irq2, 0x08, 0x8e);
- up_idtentry(&idt_entries[35], (uint32_t)vector_irq3, 0x08, 0x8e);
- up_idtentry(&idt_entries[36], (uint32_t)vector_irq4, 0x08, 0x8e);
- up_idtentry(&idt_entries[37], (uint32_t)vector_irq5, 0x08, 0x8e);
- up_idtentry(&idt_entries[38], (uint32_t)vector_irq6, 0x08, 0x8e);
- up_idtentry(&idt_entries[39], (uint32_t)vector_irq7, 0x08, 0x8e);
- up_idtentry(&idt_entries[40], (uint32_t)vector_irq8, 0x08, 0x8e);
- up_idtentry(&idt_entries[41], (uint32_t)vector_irq9, 0x08, 0x8e);
+ up_idtentry(&idt_entries[32], (uint32_t)vector_irq0, 0x08, 0x8e);
+ up_idtentry(&idt_entries[33], (uint32_t)vector_irq1, 0x08, 0x8e);
+ up_idtentry(&idt_entries[34], (uint32_t)vector_irq2, 0x08, 0x8e);
+ up_idtentry(&idt_entries[35], (uint32_t)vector_irq3, 0x08, 0x8e);
+ up_idtentry(&idt_entries[36], (uint32_t)vector_irq4, 0x08, 0x8e);
+ up_idtentry(&idt_entries[37], (uint32_t)vector_irq5, 0x08, 0x8e);
+ up_idtentry(&idt_entries[38], (uint32_t)vector_irq6, 0x08, 0x8e);
+ up_idtentry(&idt_entries[39], (uint32_t)vector_irq7, 0x08, 0x8e);
+ up_idtentry(&idt_entries[40], (uint32_t)vector_irq8, 0x08, 0x8e);
+ up_idtentry(&idt_entries[41], (uint32_t)vector_irq9, 0x08, 0x8e);
up_idtentry(&idt_entries[42], (uint32_t)vector_irq10, 0x08, 0x8e);
up_idtentry(&idt_entries[43], (uint32_t)vector_irq11, 0x08, 0x8e);
up_idtentry(&idt_entries[44], (uint32_t)vector_irq12, 0x08, 0x8e);
@@ -258,3 +262,98 @@ void up_irqinitialize(void)
irqrestore(X86_FLAGS_IF);
#endif
}
+
+/****************************************************************************
+ * Name: up_disable_irq
+ *
+ * Description:
+ * Disable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_disable_irq(int irq)
+{
+ unsigned int regaddr;
+ uint8_t regbit;
+
+ if ((unsigned)irq >= IRQ0)
+ {
+ /* Map the IRQ IMR regiser to a PIC and a bit number */
+
+ if ((unsigned)irq <= IRQ7)
+ {
+ regaddr = PIC1_IMR;
+ regbit = (1 << (irq - IRQ0));
+ }
+ else if ((unsigned)irq <= IRQ15)
+ {
+ regaddr = PIC2_IMR;
+ regbit = (1 << (irq - IRQ8));
+ }
+ else
+ {
+ return;
+ }
+
+ /* Disable the interrupt */
+
+ modifyreg8(regaddr, regbit, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: up_enable_irq
+ *
+ * Description:
+ * Enable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_enable_irq(int irq)
+{
+ unsigned int regaddr;
+ uint8_t regbit;
+
+ if ((unsigned)irq >= IRQ0)
+ {
+ /* Map the IRQ IMR regiser to a PIC and a bit number */
+
+ if ((unsigned)irq <= IRQ7)
+ {
+ regaddr = PIC1_IMR;
+ regbit = (1 << (irq - IRQ0));
+ }
+ else if ((unsigned)irq <= IRQ15)
+ {
+ regaddr = PIC2_IMR;
+ regbit = (1 << (irq - IRQ8));
+ }
+ else
+ {
+ return;
+ }
+
+ /* Enable the interrupt */
+
+ modifyreg8(regaddr, 0, regbit);
+ }
+}
+
+/****************************************************************************
+ * Name: up_prioritize_irq
+ *
+ * Description:
+ * Set the priority of an IRQ.
+ *
+ * Since this API is not supported on all architectures, it should be
+ * avoided in common implementations where possible.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_IRQPRIO
+int up_prioritize_irq(int irq, int priority)
+{
+#warning "Missing Logic"
+ return OK;
+}
+#endif
diff --git a/nuttx/arch/x86/src/qemu/Make.defs b/nuttx/arch/x86/src/qemu/Make.defs
index 4c3a83380..3177f3db4 100755
--- a/nuttx/arch/x86/src/qemu/Make.defs
+++ b/nuttx/arch/x86/src/qemu/Make.defs
@@ -42,7 +42,7 @@ HEAD_ASRC = qemu_head.S
CMN_ASRCS = i486_utils.S
CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
up_createstack.c up_mdelay.c up_udelay.c up_exit.c\
- up_initialize.c up_initialstate.c up_interruptcontext.c \
+ up_initialize.c up_initialstate.c up_interruptcontext.c up_irq.c \
up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c up_regdump.c \
up_releasepending.c up_releasestack.c up_reprioritizertr.c \
up_sigdeliver.c up_schedulesigaction.c up_unblocktask.c \
@@ -51,7 +51,7 @@ CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
# Required QEMU files
CHIP_ASRCS = qemu_saveusercontext.S qemu_fullcontextrestore.S qemu_vectors.S
-CHIP_CSRCS = qemu_handlers.c qemu_idle.c qemu_irq.c qemu_lowputc.c \
- qemu_lowsetup.c qemu_serial.c qemu_timerisr.c
+CHIP_CSRCS = qemu_handlers.c qemu_idle.c qemu_lowputc.c qemu_lowsetup.c \
+ qemu_serial.c qemu_timerisr.c
# Configuration-dependent QEMU files
diff --git a/nuttx/arch/x86/src/qemu/qemu_timerisr.c b/nuttx/arch/x86/src/qemu/qemu_timerisr.c
index ddc4a5e74..ca51816af 100755
--- a/nuttx/arch/x86/src/qemu/qemu_timerisr.c
+++ b/nuttx/arch/x86/src/qemu/qemu_timerisr.c
@@ -79,9 +79,6 @@
#define PIT_DIVISOR ((uint32_t)PIT_CLOCK/(uint32_t)CLK_TCK)
-#define PIT_MODE 0x43
-#define PIT_CH0 0x40
-
/****************************************************************************
* Private Types
****************************************************************************/
@@ -90,7 +87,7 @@
* Private Function Prototypes
****************************************************************************/
-static void pit_outb(uint8_t val, uint16_t addr) __attribute__((noinline));
+static void outb(uint8_t val, uint16_t addr) __attribute__((noinline));
static int up_timerisr(int irq, uint32_t *regs);
/****************************************************************************
@@ -98,19 +95,6 @@ static int up_timerisr(int irq, uint32_t *regs);
****************************************************************************/
/****************************************************************************
- * Name pit_outb
- *
- * Description:
- * A slightly slower version of outb
- *
- ****************************************************************************/
-
-static void pit_outb(uint8_t val, uint16_t addr)
-{
- outb(val, addr);
-}
-
-/****************************************************************************
* Function: up_timerisr
*
* Description:
@@ -151,12 +135,16 @@ void up_timerinit(void)
(void)irq_attach(IRQ0, (xcpt_t)up_timerisr);
- /* Send the command byte */
+ /* Send the command byte to configure counter 0 */
- pit_outb(0x36, PIT_MODE);
+ outb(PIT_OCW_MODE_SQUARE|PIT_OCW_RL_DATA|PIT_OCW_COUNTER_0, PIT_REG_COMMAND);
/* Set the PIT input frequency divisor */
- pit_outb((uint8_t)(divisor & 0xff), PIT_CH0);
- pit_outb((uint8_t)((divisor >> 8) & 0xff), PIT_CH0);
+ outb((uint8_t)(divisor & 0xff), PIT_REG_COUNTER0);
+ outb((uint8_t)((divisor >> 8) & 0xff), PIT_REG_COUNTER0);
+
+ /* And enable IRQ0 */
+
+ up_enable_irq(IRQ0);
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-30 17:18:46 +0000