diff options
Diffstat (limited to 'nuttx/arch')
| -rw-r--r-- | nuttx/arch/arm/src/stm32/Kconfig | 9 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/stm32/stm32f20xxx_rcc.c | 4 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c | 4 |
3 files changed, 17 insertions, 0 deletions
diff --git a/nuttx/arch/arm/src/stm32/Kconfig b/nuttx/arch/arm/src/stm32/Kconfig index 2807e1a47..99dde3209 100644 --- a/nuttx/arch/arm/src/stm32/Kconfig +++ b/nuttx/arch/arm/src/stm32/Kconfig @@ -689,6 +689,15 @@ endchoice endmenu +config STM32_FLASH_PREFETCH + bool "Enable FLASH Pre-fetch" + depends on STM32_STM32F20XX || STM32_STM32F40XX + default n + ---help--- + Enable FLASH prefetch and F2 and F4 parts (FLASH pre-fetch is always enabled + on F1 parts). Some early revisions of F4 parts do not support FLASH pre-fetch + properly and enabling this option may interfere with ADC accuracy. + choice prompt "JTAG Configuration" default STM32_JTAG_DISABLE diff --git a/nuttx/arch/arm/src/stm32/stm32f20xxx_rcc.c b/nuttx/arch/arm/src/stm32/stm32f20xxx_rcc.c index 335992524..ac72fb60b 100644 --- a/nuttx/arch/arm/src/stm32/stm32f20xxx_rcc.c +++ b/nuttx/arch/arm/src/stm32/stm32f20xxx_rcc.c @@ -631,7 +631,11 @@ static void stm32_stdclockconfig(void) /* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */ +#ifdef STM32_FLASH_PREFETCH + regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); +#else regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); +#endif putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ diff --git a/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c b/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c index 14ee1e754..c6c0b2382 100644 --- a/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c +++ b/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c @@ -633,7 +633,11 @@ static void stm32_stdclockconfig(void) /* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */ +#ifdef STM32_FLASH_PREFETCH regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); +#else + regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); +#endif putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ |