diff options
Diffstat (limited to 'nuttx/arch')
| -rw-r--r-- | nuttx/arch/arm/src/sam34/Kconfig | 13 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/sam34/Make.defs | 4 | ||||
| -rwxr-xr-x | nuttx/arch/arm/src/sam34/chip/sam_udp.h | 75 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/sam34/chip/sam_udphs.h | 18 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/sam34/sam_clockconfig.c | 21 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/sama5/Kconfig | 23 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/sama5/chip/sam_udphs.h | 122 |
7 files changed, 169 insertions, 107 deletions
diff --git a/nuttx/arch/arm/src/sam34/Kconfig b/nuttx/arch/arm/src/sam34/Kconfig index 31905ba7e..e77006200 100644 --- a/nuttx/arch/arm/src/sam34/Kconfig +++ b/nuttx/arch/arm/src/sam34/Kconfig @@ -570,7 +570,7 @@ config SAM34_UDPHS config SAM34_UOTGHS bool "USB OTG High Speed (UOTGHS)" default n - depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X + depends on ARCH_CHIP_SAM3A || ARCH_CHIP_SAM3X config SAM34_USBC bool "USB 2.0 Interface (USBC)" @@ -1129,6 +1129,17 @@ config SAM34_EMAC_ISETH0 endmenu # EMAC device driver options endif # SAM34_EMAC +if SAM34_UDP +menu "USB Full Speed Device Controller driver (DCD) options" + +config SAM34_UDP_REGDEBUG + bool "Enable low-level UPPHS register debug" + default n + depends on DEBUG + +endmenu # USB Full Speed Device Controller driver (DCD) options +endif # SAM34_UDP + if SAM34_WDT comment "AT91SAM3/4 Watchdog Configuration"| diff --git a/nuttx/arch/arm/src/sam34/Make.defs b/nuttx/arch/arm/src/sam34/Make.defs index 90aabdbe1..df6e30c42 100644 --- a/nuttx/arch/arm/src/sam34/Make.defs +++ b/nuttx/arch/arm/src/sam34/Make.defs @@ -108,6 +108,10 @@ ifeq ($(CONFIG_SAM34_EMAC),y) CHIP_CSRCS += sam_emac.c endif +ifeq ($(CONFIG_SAM34_UDP),y) +CHIP_CSRCS += sam_udp.c +endif + ifeq ($(CONFIG_SAM34_HSMCI),y) CHIP_CSRCS += sam_hsmci.c endif diff --git a/nuttx/arch/arm/src/sam34/chip/sam_udp.h b/nuttx/arch/arm/src/sam34/chip/sam_udp.h index 1cd3a46d8..f331213c0 100755 --- a/nuttx/arch/arm/src/sam34/chip/sam_udp.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_udp.h @@ -49,8 +49,32 @@ /**************************************************************************************** * Pre-processor Definitions ****************************************************************************************/ +/* General Definitions ******************************************************************/ +/* Capabilities and characteristics of endpoints + * + * EP EP BANKS EP SIZE EP TYPE + * --- --------- --------- --------- + * 0 1 64 Control/Bulk/Interrupt + * 1 2 64 Bulk/Iso/Interrupt + * 2 2 64 Bulk/Iso/Interrupt + * 3 1 64 Control/Bulk/Interrupt + * 4 2 512 Bulk/Iso/Interrupt + * 5 2 612 Bulk/Iso/Interrupt + * 6 2 64 Bulk/Iso/Interrupt + * 7 2 64 Bulk/Iso/Interrupt + */ + +#define SAM_UDP_NENDPOINTS 8 /* EP0-7 */ +#define SAM_UDP_MAXPACKETSIZE(ep) ((((unsigned)(ep) & 6) == 4) ? 512 : 64) +#define SAM_UDP_NBANKS(ep) (((unsigned)(ep) == 0 || (unsigned)(ep) == 3) ? 1 : 2) +#define SAM_UDP_CONTROL(ep) (((unsigned)(ep) == 0 || (unsigned)(ep) == 3)) +#define SAM_UDP_BULK(ep) (true) +#define SAM_UDP_ISOCHRONOUS(ep) (((unsigned)(ep) != 0 && (unsigned)(ep) != 3)) +#define SAM_UDP_INTERRUPT(ep) (true) -/* UDP register offsets ***************************************************************/ +/* UDP register offsets *****************************************************************/ + +/* Global Registers */ #define SAM_UDP_FRMNUM_OFFSET 0x0000 /* UDP Frame Number Register */ #define SAM_UDP_GLBSTAT_OFFSET 0x0004 /* UDP Global State Register */ @@ -62,10 +86,9 @@ #define SAM_UDP_ISR_OFFSET 0x001c /* UDP Interrupt Status Register */ #define SAM_UDP_ICR_OFFSET 0x0020 /* UDP Interrupt Clear Register */ /* 0x0024: Reserved */ -#define SAM_UDP_RSTEP_OFFSET 0x001c /* UDP Reset Endpoint Regis */ +#define SAM_UDP_RSTEP_OFFSET 0x001c /* UDP Reset Endpoint Register */ /* 0x002c: Reserved */ - -/* Endpoint 0-7 registers */ +/* Endpoint registers */ #define SAM_UDPEP_CSR_OFFSET(n) (0x0030+((n)<<2)) # define SAM_UDPEP_CSR0_OFFSET 0x0030 /* Endpoint Control and Status Register 0 */ @@ -89,7 +112,9 @@ #define SAM_UDP_TXVC_OFFSET 0x0074 /* Transceiver Control Register */ /* 0x0078-0x00fc: Reserved */ -/* UDP register addresses *************************************************************/ +/* UDP register addresses ***************************************************************/ + +/* Global Registers */ #define SAM_UDP_FRMNUM (SAM_UDP_BASE+SAM_UDP_FRMNUM_OFFSET) #define SAM_UDP_GLBSTAT (SAM_UDP_BASE+SAM_UDP_GLBSTAT_OFFSET) @@ -98,10 +123,10 @@ #define SAM_UDP_IDR (SAM_UDP_BASE+SAM_UDP_IDR_OFFSET) #define SAM_UDP_IMR (SAM_UDP_BASE+SAM_UDP_IMR_OFFSET) #define SAM_UDP_ISR (SAM_UDP_BASE+SAM_UDP_ISR_OFFSET) -#define SAM_UDP_ICR (SAM_UDP_BASE+ SAM_UDP_ICR_OFFSET) +#define SAM_UDP_ICR (SAM_UDP_BASE+SAM_UDP_ICR_OFFSET) #define SAM_UDP_RSTEP (SAM_UDP_BASE+SAM_UDP_RSTEP_OFFSET) -/* Endpoint 0-7 registers */ +/* Endpoint registers */ #define SAM_UDPEP_CSR(n) (SAM_UDP_BASE+SAM_UDPEP_CSR_OFFSET(n)) # define SAM_UDPEP_CSR0 (SAM_UDP_BASE+SAM_UDPEP_CSR0_OFFSET) @@ -124,7 +149,9 @@ #define SAM_UDP_TXVC (SAM_UDP_BASE+SAM_UDP_TXVC_OFFSET) -/* UDP register bit definitions *******************************************************/ +/* UDP register bit definitions *********************************************************/ + +/* Global Registers */ /* UDP Frame Number Register */ @@ -145,6 +172,7 @@ #define UDP_FADDR_SHIFT (0) /* Bits 0-6: Function Address Value */ #define UDP_FADDR_MASK (0x0000007f) +# define UDP_FADDR(n) ((uint32_t)(n)) #define UDP_FADDR_FEN (1 << 8) /* Bit 8: Function Enable */ /* UDP Interrupt Enable, UDP Interrupt Disable, UDP Interrupt Mask, UDP Interrupt @@ -152,22 +180,24 @@ */ #define UDP_INT_EP(n) (1 << (n)) -# define UDP_INT_EP0 (1 << 0) /* Bit 0: Enable Endpoint 0 Interrupt (Not ICR) */ -# define UDP_INT_EP1 (1 << 1) /* Bit 1: Enable Endpoint 1 Interrupt (Not ICR) */ -# define UDP_INT_EP2 (1 << 2) /* Bit 2: Enable Endpoint 2 Interrupt (Not ICR) */ -# define UDP_INT_EP3 (1 << 3) /* Bit 3: Enable Endpoint 3 Interrupt (Not ICR) */ -# define UDP_INT_EP4 (1 << 4) /* Bit 4: Enable Endpoint 4 Interrupt (Not ICR) */ -# define UDP_INT_EP5 (1 << 5) /* Bit 5: Enable Endpoint 5 Interrupt (Not ICR) */ -# define UDP_INT_EP6 (1 << 6) /* Bit 6: Enable Endpoint 6 Interrupt (Not ICR) */ -# define UDP_INT_EP7 (1 << 7) /* Bit 7: Enable Endpoint 7 Interrupt (Not ICR) */ -#define UDP_INT_RXSUSP (1 << 8) /* Bit 8: Enable UDP Suspend Interrupt */ -#define UDP_INT_RXRSM (1 << 9) /* Bit 9: Enable UDP Resume Interrupt */ +# define UDP_INT_EP0 (1 << 0) /* Bit 0: Endpoint 0 Interrupt (Not ICR) */ +# define UDP_INT_EP1 (1 << 1) /* Bit 1: Endpoint 1 Interrupt (Not ICR) */ +# define UDP_INT_EP2 (1 << 2) /* Bit 2: Endpoint 2 Interrupt (Not ICR) */ +# define UDP_INT_EP3 (1 << 3) /* Bit 3: Endpoint 3 Interrupt (Not ICR) */ +# define UDP_INT_EP4 (1 << 4) /* Bit 4: Endpoint 4 Interrupt (Not ICR) */ +# define UDP_INT_EP5 (1 << 5) /* Bit 5: Endpoint 5 Interrupt (Not ICR) */ +# define UDP_INT_EP6 (1 << 6) /* Bit 6: Endpoint 6 Interrupt (Not ICR) */ +# define UDP_INT_EP7 (1 << 7) /* Bit 7: Endpoint 7 Interrupt (Not ICR) */ +#define UDP_INT_RXSUSP (1 << 8) /* Bit 8: UDP Suspend Interrupt */ +#define UDP_INT_RXRSM (1 << 9) /* Bit 9: UDP Resume Interrupt */ #define UDP_INT_EXTRSM (1 << 10) /* Bit 10: */ -#define UDP_INT_SOF (1 << 11) /* Bit 11: Enable Start Of Frame Interrupt */ +#define UDP_INT_SOF (1 << 11) /* Bit 11: Start Of Frame Interrupt */ #define UDP_ISR_ENDBUSRES (1 << 12) /* Bit 12: End of BUS Reset Interrupt Status (ISR and ICR only) */ -#define UDP_INT_WAKEUP (1 << 13) /* Bit 13: Enable UDP bus Wake-up Interrupt */ +#define UDP_INT_WAKEUP (1 << 13) /* Bit 13: UDP bus Wake-up Interrupt */ -/* UDP Reset Endpoint Regis */ +#define UDP_INT_ALL (0x00003fff) + +/* UDP Reset Endpoint Register */ #define UDP_RSTEP(n) (1 << (n)) # define UDP_RSTEP0 (1 << 0) /* Bit 0: Reset Endpoint 0 */ @@ -179,7 +209,7 @@ # define UDP_RSTEP6 (1 << 6) /* Bit 6: Reset Endpoint 6 */ # define UDP_RSTEP7 (1 << 7) /* Bit 7: Reset Endpoint 7 */ -/* Endpoint 0-7 registers */ +/* Endpoint registers */ /* Endpoint Control and Status Registers */ #define UDPEP_CSR_TXCOMP (1 << 0) /* Bit 0: Generates an IN packet with data */ @@ -227,4 +257,3 @@ ****************************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_UDP_H */ - diff --git a/nuttx/arch/arm/src/sam34/chip/sam_udphs.h b/nuttx/arch/arm/src/sam34/chip/sam_udphs.h index de5a97019..e359c5555 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_udphs.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_udphs.h @@ -88,7 +88,7 @@ #define SAM_UDPHSDMA_NXTDSC_OFFSET 0x00 /* UDPHS DMA Next Descriptor Address Register */ #define SAM_UDPHSDMA_ADDRESS_OFFSET 0x04 /* UDPHS DMA Channel Address Register */ #define SAM_UDPHSDMA_CONTROL_OFFSET 0x08 /* UDPHS DMA Channel Control Register */ -#define SAM_UDPHSDMA_STATUS_OFFSET) 0x0c /* UDPHS DMA Channel Status Register */ +#define SAM_UDPHSDMA_STATUS_OFFSET 0x0c /* UDPHS DMA Channel Status Register */ /* UDPHS register addresses *************************************************************/ @@ -217,12 +217,12 @@ #define UDPHS_IPFEATURES_ISOEPT7 (1 << 23) /* Bit 23: EP7 High B/W Isoc Capability */ #define UDPHS_IPFEATURES_ISOEPT8 (1 << 24) /* Bit 24: EP8 High B/W Isoc Capability */ #define UDPHS_IPFEATURES_ISOEPT9 (1 << 25) /* Bit 25: EP9 High B/W Isoc Capability */ -#define UDPHS_IPFEATURES_ISOEPT0 (1 << 26) /* Bit 26: EP10 High B/W Isoc Capability */ -#define UDPHS_IPFEATURES_ISOEPT1 (1 << 27) /* Bit 27: EP11 High B/W Isoc Capability */ -#define UDPHS_IPFEATURES_ISOEPT2 (1 << 28) /* Bit 28: EP12 High B/W Isoc Capability */ -#define UDPHS_IPFEATURES_ISOEPT3 (1 << 29) /* Bit 29: EP13 High B/W Isoc Capability */ -#define UDPHS_IPFEATURES_ISOEPT4 (1 << 30) /* Bit 30: EP14 High B/W Isoc Capability */ -#define UDPHS_IPFEATURES_ISOEPT5 (1 << 31) /* Bit 31: EP15 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT10 (1 << 26) /* Bit 26: EP10 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT11 (1 << 27) /* Bit 27: EP11 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT12 (1 << 28) /* Bit 28: EP12 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT13 (1 << 29) /* Bit 29: EP13 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT14 (1 << 30) /* Bit 30: EP14 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT15 (1 << 31) /* Bit 31: EP15 High B/W Isoc Capability */ /* UDPHS Endpoint Configuration Register (0-6) */ @@ -231,7 +231,7 @@ # define UDPHSEP_CFG_SIZE_8b (0 << UDPHSEP_CFG_SIZE_SHIFT) /* 8 bytes */ # define UDPHSEP_CFG_SIZE_16b (1 << UDPHSEP_CFG_SIZE_SHIFT) /* 16 bytes */ # define UDPHSEP_CFG_SIZE_32b (2 << UDPHSEP_CFG_SIZE_SHIFT) /* 32 bytes */ -# define UDPHSEP_CFG_SIZE_16b (3 << UDPHSEP_CFG_SIZE_SHIFT) /* 64 bytes */ +# define UDPHSEP_CFG_SIZE_64b (3 << UDPHSEP_CFG_SIZE_SHIFT) /* 64 bytes */ # define UDPHSEP_CFG_SIZE_128b (4 << UDPHSEP_CFG_SIZE_SHIFT) /* 128 bytes */ # define UDPHSEP_CFG_SIZE_256b (5 << UDPHSEP_CFG_SIZE_SHIFT) /* 256 bytes */ # define UDPHSEP_CFG_SIZE_512b (6 << UDPHSEP_CFG_SIZE_SHIFT) /* 512 bytes */ @@ -330,7 +330,7 @@ #define UDPHSEP_STA_BUSYBANKSTA_MASK (3 << UDPHSEP_STA_BUSYBANKSTA_SHIFT) #define UDPHSEP_STA_BYTECOUNT_SHIFT (20) /* Bits 20-23: UDPHS Byte Count */ #define UDPHSEP_STA_BYTECOUNT_MASK (15 << UDPHSEP_STA_BYTECOUNT_SHIFT) -#define UDPHSEP_STA_SHRTPCKT (1 << 31) /* Bit 31: Short Packet +#define UDPHSEP_STA_SHRTPCKT (1 << 31) /* Bit 31: Short Packet */ /* UDPHS DMA Channel Control Register */ diff --git a/nuttx/arch/arm/src/sam34/sam_clockconfig.c b/nuttx/arch/arm/src/sam34/sam_clockconfig.c index fe114e74c..0d1e12edf 100644 --- a/nuttx/arch/arm/src/sam34/sam_clockconfig.c +++ b/nuttx/arch/arm/src/sam34/sam_clockconfig.c @@ -237,13 +237,32 @@ static inline void sam_pmcsetup(void) putreg32(BOARD_CKGR_PLLAR, SAM_PMC_CKGR_PLLAR); sam_pmcwait(PMC_INT_LOCKA); +#ifdef CONFIG_USBDEV /* Setup UTMI for USB and wait for LOCKU */ -#ifdef CONFIG_USBDEV +#ifdef SAM_PMC_CKGR_UCKR + /* This MCU has a USB PLL. Configure the UPLL and wait for it to lock. */ + regval = getreg32(SAM_PMC_CKGR_UCKR); regval |= BOARD_CKGR_UCKR; putreg32(regval, SAM_PMC_CKGR_UCKR); sam_pmcwait(PMC_INT_LOCKU); + +#else + /* This board does not have a UPLL. Use the output of PLLA or PLLA + * (depending on USBS) and setup the PLL divisor to generate the 48MHz + * USB clock. + */ + + regval = (BOARD_PMC_USBS | BOARD_PMC_USBDIV); + putreg32(regval, SAM_PMC_USB); + + /* Set the UDP bit in the SCER1 register to enable the USB clock output */ + + regval = getreg32(SAM_PMC_SCER); + regval |= PMC_UDP; + putreg32(regval, SAM_PMC_SCER); +#endif #endif /* Switch to the fast clock and wait for MCKRDY */ diff --git a/nuttx/arch/arm/src/sama5/Kconfig b/nuttx/arch/arm/src/sama5/Kconfig index 9a48ecadd..c6c1d1640 100644 --- a/nuttx/arch/arm/src/sama5/Kconfig +++ b/nuttx/arch/arm/src/sama5/Kconfig @@ -225,7 +225,6 @@ config SAMA5_UHPHS config SAMA5_UDPHS bool "USB Device High Speed (UDPHS)" default n - depends on SAMA5_HAVE_GMAC config SAMA5_GMAC bool "Gigabit Ethernet MAC (GMAC)" @@ -869,7 +868,7 @@ choice prompt "GMAC Speed" default SAMA5_GMAC_ETH100MBPS ---help--- - If autonegation is not used, then you must select the fixed speed + If autonegotiation is not used, then you must select the fixed speed of the PHY config SAMA5_GMAC_ETH10MBPS @@ -1512,9 +1511,9 @@ config SAMA5_SSC0_MCKDIV_SAMPLERATE depends on SAMA5_SSC0_RX_MCKDIV || SAMA5_SSC0_TX_MCKDIV ---help--- If the either the receiver or transmitter clock is provided by MCK/2 divided - down, then the samplerate must be provided. The bitrate will be the product + down, then the sample rate must be provided. The bit rate will be the product of the sample rate and the data width. The SSC driver will determine the best - divider to obtain that bitrate (up to 4095). If the bitrate can be realized + divider to obtain that bit rate (up to 4095). If the bit rate can be realized by dividing down the MCK/2, a compile time error will occur. config SAMA5_SSC0_LOOPBACK @@ -1524,7 +1523,7 @@ config SAMA5_SSC0_LOOPBACK ---help--- If both the receiver and transmitter are enabled, then the SSC can be configured in loopback mode. This setting selects SSC loopback - and will cause the LOOP bit to be set in the SSC_RFMR regsiter. In + and will cause the LOOP bit to be set in the SSC_RFMR register. In this case, RD is connected to TD, RF is connected to TF and RK is connected to TK. @@ -1646,9 +1645,9 @@ config SAMA5_SSC1_MCKDIV_SAMPLERATE depends on SAMA5_SSC1_RX_MCKDIV || SAMA5_SSC1_TX_MCKDIV ---help--- If the either the receiver or transmitter clock is provided by MCK/2 divided - down, then the samplerate must be provided. The bitrate will be the product + down, then the sample rate must be provided. The bit rate will be the product of the sample rate and the data width. The SSC driver will determine the best - divider to obtain that bitrate (up to 4095). If the bitrate can be realized + divider to obtain that bit rate (up to 4095). If the bit rate can be realized by dividing down the MCK/2, a compile time error will occur. config SAMA5_SSC1_LOOPBACK @@ -1658,7 +1657,7 @@ config SAMA5_SSC1_LOOPBACK ---help--- If both the receiver and transmitter are enabled, then the SSC can be configured in loopback mode. This setting selects SSC loopback - and will cause the LOOP bit to be set in the SSC_RFMR regsiter. In + and will cause the LOOP bit to be set in the SSC_RFMR register. In this case, RD is connected to TD, RF is connected to TF and RK is connected to TK. @@ -1767,7 +1766,7 @@ config SAMA5_UDPHS_NDTDS default 9 depends on UDPHS_SCATTERGATHER ---help--- - DMA tranfer descriptors are allocated in a pool at boot time. This + DMA transfer descriptors are allocated in a pool at boot time. This setting provides the number of DMA transfer descriptors to be allocated. @@ -1776,17 +1775,17 @@ config SAMA5_UDPHS_PREALLOCATE default y depends on UDPHS_SCATTERGATHER ---help--- - If this option is selected then DMA tranfer descriptors will be + If this option is selected then DMA transfer descriptors will be pre-allocated in .bss. Otherwise, the descriptors will be allocated at start-up time with kmalloc(). This might be important if a larger memory pool is available after startup. config SAMA5_UDPHS_REGDEBUG - bool "Enable low-level UPPHS register debug" + bool "Enable low-level UDPHS register debug" default n depends on DEBUG -endmenu # USB High Speed Host Device driver (DCD) options +endmenu # USB High Speed Device Controller driver (DCD) options endif # SAMA5_UDPHS if SAMA5_UHPHS diff --git a/nuttx/arch/arm/src/sama5/chip/sam_udphs.h b/nuttx/arch/arm/src/sama5/chip/sam_udphs.h index 3fae76900..5b5becbfa 100644 --- a/nuttx/arch/arm/src/sama5/chip/sam_udphs.h +++ b/nuttx/arch/arm/src/sama5/chip/sam_udphs.h @@ -82,23 +82,23 @@ /* 0x00e4-0x00e8 Reserved */ /* Endpoint Offsets */ -#define SAM_UPPHS_EP_OFFSET(ep) (0x0100+((unsigned int)(ep)<<5)) -#define SAM_UPPHS_EP0_OFFSET 0x0100 -#define SAM_UPPHS_EP1_OFFSET 0x0120 -#define SAM_UPPHS_EP2_OFFSET 0x0140 -#define SAM_UPPHS_EP3_OFFSET 0x0160 -#define SAM_UPPHS_EP4_OFFSET 0x0180 -#define SAM_UPPHS_EP5_OFFSET 0x01a0 -#define SAM_UPPHS_EP6_OFFSET 0x01c0 -#define SAM_UPPHS_EP7_OFFSET 0x01e0 -#define SAM_UPPHS_EP8_OFFSET 0x0200 -#define SAM_UPPHS_EP9_OFFSET 0x0220 -#define SAM_UPPHS_EP10_OFFSET 0x0240 -#define SAM_UPPHS_EP11_OFFSET 0x0260 -#define SAM_UPPHS_EP12_OFFSET 0x0280 -#define SAM_UPPHS_EP13_OFFSET 0x02a0 -#define SAM_UPPHS_EP14_OFFSET 0x02c0 -#define SAM_UPPHS_EP15_OFFSET 0x02e0 +#define SAM_UDPHS_EP_OFFSET(ep) (0x0100+((unsigned int)(ep)<<5)) +#define SAM_UDPHS_EP0_OFFSET 0x0100 +#define SAM_UDPHS_EP1_OFFSET 0x0120 +#define SAM_UDPHS_EP2_OFFSET 0x0140 +#define SAM_UDPHS_EP3_OFFSET 0x0160 +#define SAM_UDPHS_EP4_OFFSET 0x0180 +#define SAM_UDPHS_EP5_OFFSET 0x01a0 +#define SAM_UDPHS_EP6_OFFSET 0x01c0 +#define SAM_UDPHS_EP7_OFFSET 0x01e0 +#define SAM_UDPHS_EP8_OFFSET 0x0200 +#define SAM_UDPHS_EP9_OFFSET 0x0220 +#define SAM_UDPHS_EP10_OFFSET 0x0240 +#define SAM_UDPHS_EP11_OFFSET 0x0260 +#define SAM_UDPHS_EP12_OFFSET 0x0280 +#define SAM_UDPHS_EP13_OFFSET 0x02a0 +#define SAM_UDPHS_EP14_OFFSET 0x02c0 +#define SAM_UDPHS_EP15_OFFSET 0x02e0 /* Endpoint registers */ @@ -113,14 +113,14 @@ /* DMA Channel Offsets */ -#define SAM_UPPHS_CH_OFFSET(ch) (0x0300+((unsigned int)(ch)<<4)) -#define SAM_UPPHS_CH0_OFFSET 0x0300 -#define SAM_UPPHS_CH1_OFFSET 0x0310 -#define SAM_UPPHS_CH2_OFFSET 0x0320 -#define SAM_UPPHS_CH3_OFFSET 0x0330 -#define SAM_UPPHS_CH4_OFFSET 0x0340 -#define SAM_UPPHS_CH5_OFFSET 0x0350 -#define SAM_UPPHS_CH6_OFFSET 0x0360 +#define SAM_UDPHS_CH_OFFSET(ch) (0x0300+((unsigned int)(ch)<<4)) +#define SAM_UDPHS_CH0_OFFSET 0x0300 +#define SAM_UDPHS_CH1_OFFSET 0x0310 +#define SAM_UDPHS_CH2_OFFSET 0x0320 +#define SAM_UDPHS_CH3_OFFSET 0x0330 +#define SAM_UDPHS_CH4_OFFSET 0x0340 +#define SAM_UDPHS_CH5_OFFSET 0x0350 +#define SAM_UDPHS_CH6_OFFSET 0x0360 /* DMA Channel Registers */ @@ -143,51 +143,51 @@ /* Endpoint Base Addresses */ -#define SAM_UPPHS_EP_BASE(ep) (SAM_UDPHS_VBASE+SAM_UPPHS_EP_OFFSET(ep)) -#define SAM_UPPHS_EP0_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP0_OFFSET) -#define SAM_UPPHS_EP1_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP1_OFFSET) -#define SAM_UPPHS_EP2_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP2_OFFSET) -#define SAM_UPPHS_EP3_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP3_OFFSET) -#define SAM_UPPHS_EP4_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP4_OFFSET) -#define SAM_UPPHS_EP5_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP5_OFFSET) -#define SAM_UPPHS_EP6_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP6_OFFSET) -#define SAM_UPPHS_EP7_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP7_OFFSET) -#define SAM_UPPHS_EP8_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP8_OFFSET) -#define SAM_UPPHS_EP9_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP9_OFFSET) -#define SAM_UPPHS_EP10_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP10_OFFSET) -#define SAM_UPPHS_EP11_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP11_OFFSET) -#define SAM_UPPHS_EP12_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP12_OFFSET) -#define SAM_UPPHS_EP13_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP13_OFFSET) -#define SAM_UPPHS_EP14_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP14_OFFSET) -#define SAM_UPPHS_EP15_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP15_OFFSET) +#define SAM_UDPHS_EP_BASE(ep) (SAM_UDPHS_VBASE+SAM_UDPHS_EP_OFFSET(ep)) +#define SAM_UDPHS_EP0_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP0_OFFSET) +#define SAM_UDPHS_EP1_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP1_OFFSET) +#define SAM_UDPHS_EP2_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP2_OFFSET) +#define SAM_UDPHS_EP3_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP3_OFFSET) +#define SAM_UDPHS_EP4_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP4_OFFSET) +#define SAM_UDPHS_EP5_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP5_OFFSET) +#define SAM_UDPHS_EP6_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP6_OFFSET) +#define SAM_UDPHS_EP7_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP7_OFFSET) +#define SAM_UDPHS_EP8_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP8_OFFSET) +#define SAM_UDPHS_EP9_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP9_OFFSET) +#define SAM_UDPHS_EP10_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP10_OFFSET) +#define SAM_UDPHS_EP11_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP11_OFFSET) +#define SAM_UDPHS_EP12_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP12_OFFSET) +#define SAM_UDPHS_EP13_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP13_OFFSET) +#define SAM_UDPHS_EP14_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP14_OFFSET) +#define SAM_UDPHS_EP15_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP15_OFFSET) /* Endpoint registers */ -#define SAM_UDPHS_EPTCFG(ep) (SAM_UPPHS_EP_BASE(ep)+SAM_UDPHS_EPTCFG_OFFSET) -#define SAM_UDPHS_EPTCTLENB(ep) (SAM_UPPHS_EP_BASE(ep)+SAM_UDPHS_EPTCTLENB_OFFSET) -#define SAM_UDPHS_EPTCTLDIS(ep) (SAM_UPPHS_EP_BASE(ep)+SAM_UDPHS_EPTCTLDIS_OFFSET) -#define SAM_UDPHS_EPTCTL(ep) (SAM_UPPHS_EP_BASE(ep)+SAM_UDPHS_EPTCTL_OFFSET) -#define SAM_UDPHS_EPTSETSTA(ep) (SAM_UPPHS_EP_BASE(ep)+SAM_UDPHS_EPTSETSTA_OFFSET) -#define SAM_UDPHS_EPTCLRSTA(ep) (SAM_UPPHS_EP_BASE(ep)+SAM_UDPHS_EPTCLRSTA_OFFSET) -#define SAM_UDPHS_EPTSTA(ep) (SAM_UPPHS_EP_BASE(ep)+SAM_UDPHS_EPTSTA_OFFSET) +#define SAM_UDPHS_EPTCFG(ep) (SAM_UDPHS_EP_BASE(ep)+SAM_UDPHS_EPTCFG_OFFSET) +#define SAM_UDPHS_EPTCTLENB(ep) (SAM_UDPHS_EP_BASE(ep)+SAM_UDPHS_EPTCTLENB_OFFSET) +#define SAM_UDPHS_EPTCTLDIS(ep) (SAM_UDPHS_EP_BASE(ep)+SAM_UDPHS_EPTCTLDIS_OFFSET) +#define SAM_UDPHS_EPTCTL(ep) (SAM_UDPHS_EP_BASE(ep)+SAM_UDPHS_EPTCTL_OFFSET) +#define SAM_UDPHS_EPTSETSTA(ep) (SAM_UDPHS_EP_BASE(ep)+SAM_UDPHS_EPTSETSTA_OFFSET) +#define SAM_UDPHS_EPTCLRSTA(ep) (SAM_UDPHS_EP_BASE(ep)+SAM_UDPHS_EPTCLRSTA_OFFSET) +#define SAM_UDPHS_EPTSTA(ep) (SAM_UDPHS_EP_BASE(ep)+SAM_UDPHS_EPTSTA_OFFSET) /* DMA Channel Base Addresses */ -#define SAM_UPPHS_CH_BASE(ch) (SAM_UDPHS_VBASE+SAM_UPPHS_CH_OFFSET(ch)) -#define SAM_UPPHS_CH1_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_CH1_OFFSET) -#define SAM_UPPHS_CH2_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_CH2_OFFSET) -#define SAM_UPPHS_CH3_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_CH3_OFFSET) -#define SAM_UPPHS_CH4_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_CH4_OFFSET) -#define SAM_UPPHS_CH5_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_CH5_OFFSET) -#define SAM_UPPHS_CH6_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_CH6_OFFSET) -#define SAM_UPPHS_CH7_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_CH7_OFFSET) +#define SAM_UDPHS_CH_BASE(ch) (SAM_UDPHS_VBASE+SAM_UDPHS_CH_OFFSET(ch)) +#define SAM_UDPHS_CH1_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_CH1_OFFSET) +#define SAM_UDPHS_CH2_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_CH2_OFFSET) +#define SAM_UDPHS_CH3_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_CH3_OFFSET) +#define SAM_UDPHS_CH4_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_CH4_OFFSET) +#define SAM_UDPHS_CH5_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_CH5_OFFSET) +#define SAM_UDPHS_CH6_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_CH6_OFFSET) +#define SAM_UDPHS_CH7_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_CH7_OFFSET) /* DMA Channel Registers */ -#define SAM_UDPHS_DMANXTDSC(ch) (SAM_UPPHS_CH_BASE(ch)+SAM_UDPHS_DMANXTDSC_OFFSET) -#define SAM_UDPHS_DMAADDRESS(ch) (SAM_UPPHS_CH_BASE(ch)+SAM_UDPHS_DMAADDRESS_OFFSET) -#define SAM_UDPHS_DMACONTROL(ch) (SAM_UPPHS_CH_BASE(ch)+SAM_UDPHS_DMACONTROL_OFFSET) -#define SAM_UDPHS_DMASTATUS(ch) (SAM_UPPHS_CH_BASE(ch)+SAM_UDPHS_DMASTATUS_OFFSET) +#define SAM_UDPHS_DMANXTDSC(ch) (SAM_UDPHS_CH_BASE(ch)+SAM_UDPHS_DMANXTDSC_OFFSET) +#define SAM_UDPHS_DMAADDRESS(ch) (SAM_UDPHS_CH_BASE(ch)+SAM_UDPHS_DMAADDRESS_OFFSET) +#define SAM_UDPHS_DMACONTROL(ch) (SAM_UDPHS_CH_BASE(ch)+SAM_UDPHS_DMACONTROL_OFFSET) +#define SAM_UDPHS_DMASTATUS(ch) (SAM_UDPHS_CH_BASE(ch)+SAM_UDPHS_DMASTATUS_OFFSET) /* Register bit-field definitions ***********************************************************/ |