diff options
Diffstat (limited to 'nuttx/configs/stm3220g-eval/include/board.h')
| -rw-r--r-- | nuttx/configs/stm3220g-eval/include/board.h | 56 |
1 files changed, 29 insertions, 27 deletions
diff --git a/nuttx/configs/stm3220g-eval/include/board.h b/nuttx/configs/stm3220g-eval/include/board.h index 6aafaa4ca..0df5c0668 100644 --- a/nuttx/configs/stm3220g-eval/include/board.h +++ b/nuttx/configs/stm3220g-eval/include/board.h @@ -2,7 +2,7 @@ * configs/stm3220g-eval/include/board.h * include/arch/board/board.h * - * Copyright (C) 2012-12 Gregory Nutt. All rights reserved. + * Copyright (C) 2012 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -66,16 +66,16 @@ * * This is the "standard" configuration as set up by arch/arm/src/stm32f40xx_rcc.c: * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 168000000 Determined by PLL configuration - * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) + * SYSCLK(Hz) : 120000000 Determined by PLL configuration + * HCLK(Hz) : 120000000 (STM32_RCC_CFGR_HPRE) * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) * HSE Frequency(Hz) : 25000000 (STM32_BOARD_XTAL) * PLLM : 25 (STM32_PLLCFG_PLLM) - * PLLN : 336 (STM32_PLLCFG_PLLN) + * PLLN : 240 (STM32_PLLCFG_PLLN) * PLLP : 2 (STM32_PLLCFG_PLLP) - * PLLQ : 7 (STM32_PLLCFG_PPQ) + * PLLQ : 5 (STM32_PLLCFG_PPQ) * Main regulator output voltage : Scale1 mode Needed for high speed SYSCLK * Flash Latency(WS) : 5 * Prefetch Buffer : OFF @@ -102,34 +102,35 @@ * * PLL source is HSE * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (25,000,000 / 25) * 336 - * = 336,000,000 + * = (25,000,000 / 25) * 240 + * = 240,000,000 * SYSCLK = PLL_VCO / PLLP - * = 336,000,000 / 2 = 168,000,000 + * = 240,000,000 / 2 = 120,000,000 * USB OTG FS, SDIO and RNG Clock * = PLL_VCO / PLLQ + * = 240,000,000 / 5 = 48,000,000 * = 48,000,000 */ #define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(240) #define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PPQ RCC_PLLCFG_PLLQ(7) +#define STM32_PLLCFG_PPQ RCC_PLLCFG_PLLQ(5) -#define STM32_SYSCLK_FREQUENCY 168000000ul +#define STM32_SYSCLK_FREQUENCY 120000000ul -/* AHB clock (HCLK) is SYSCLK (168MHz) */ +/* AHB clock (HCLK) is SYSCLK (120MHz) */ #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */ -/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ +/* APB1 clock (PCLK1) is HCLK/4 (30MHz) */ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) -/* Timers driven from APB1 will be twice PCLK1 */ +/* Timers driven from APB1 will be twice PCLK1 (60Mhz)*/ #define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) @@ -141,12 +142,12 @@ #define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) -/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ +/* APB2 clock (PCLK2) is HCLK/2 (60MHz) */ #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) -/* Timers driven from APB2 will be twice PCLK2 */ +/* Timers driven from APB2 will be twice PCLK2 (120Mhz)*/ #define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) #define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) @@ -155,21 +156,21 @@ #define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. + * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 */ #define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY #define STM32_TIM27_FREQUENCY STM32_HCLK_FREQUENCY -/* SDIO dividers. Note that slower clocking is required when DMA is disabled +/* SDIO dividers. Note that slower clocking is required when DMA is disabled * in order to avoid RX overrun/TX underrun errors due to delayed responses * to service FIFOs in interrupt driven mode. These values have not been * tuned!!! * * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz */ - + #define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) /* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz @@ -177,9 +178,9 @@ */ #ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) #else -# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) #endif /* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz @@ -264,9 +265,10 @@ * - PC11 is MicroSDCard_D3 & RS232/IrDA_RX (JP22 open) * - PC10 is MicroSDCard_D2 & RSS232/IrDA_TX */ - -#define GPIO_USART3_RX GPIO_USART3_RX_2 -#define GPIO_USART3_TX GPIO_USART3_TX_2 +#ifdef CONFIG_STM32_USART3 +# define GPIO_USART3_RX GPIO_USART3_RX_2 +# define GPIO_USART3_TX GPIO_USART3_TX_2 +#endif /* Ethernet: * @@ -398,8 +400,8 @@ * * Mapping to STM32 GPIO pins: * - * PD0 = FSMC_D2 & CAN1_RX - * PD1 = FSMC_D3 & CAN1_TX + * PD0 = FSMC_D2 & CAN1_RX + * PD1 = FSMC_D3 & CAN1_TX * PB13 = ULPI_D6 & CAN2_TX * PB5 = ULPI_D7 & CAN2_RX */ @@ -416,7 +418,7 @@ * - PB6 is I2C1_SCL * - PB9 is I2C1_SDA */ - + #define GPIO_I2C1_SCL GPIO_I2C1_SCL_1 #define GPIO_I2C1_SDA GPIO_I2C1_SDA_2 |