diff options
Diffstat (limited to 'nuttx')
| -rw-r--r-- | nuttx/ChangeLog | 9 | ||||
| -rw-r--r-- | nuttx/Documentation/NuttX.html | 25 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/lpc17xx/chip/lpc178x_syscon.h | 42 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/lpc17xx/chip/lpc17_memorymap.h | 4 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconfig.h | 4 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconn.h | 4 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/lpc17xx/chip/lpc17_syscon.h | 4 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/lpc17xx/lpc176x_clockconfig.c | 221 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/lpc17xx/lpc178x_clockconfig.c | 233 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.c | 185 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/lpc17xx/lpc17_serial.c | 2 | ||||
| -rw-r--r-- | nuttx/configs/open1788/include/board.h | 6 | ||||
| -rw-r--r-- | nuttx/configs/open1788/nsh/Make.defs | 109 | ||||
| -rw-r--r-- | nuttx/configs/open1788/nsh/defconfig | 678 | ||||
| -rwxr-xr-x | nuttx/configs/open1788/nsh/setenv.sh | 73 | ||||
| -rw-r--r-- | nuttx/configs/open1788/src/lpc17_nsh.c | 101 | ||||
| -rw-r--r-- | nuttx/fs/fat/Kconfig | 1 |
17 files changed, 1469 insertions, 232 deletions
diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 5cb02ad69..548dffa1f 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -4233,4 +4233,11 @@ * arch/arm/src/stm32f20xxx_dma.c and stm32f40xxx_dma.c: Fix a typo in assigned base register addresses for each DMA channel. From Yan T. - + * Several build fixes from Mike Smithe were incorporated. These were + mostly compilation errors introduced into the system because of the + large number of recent changes with broad scope (2013-03-04). + * configs/zkit-arm-17969/src/up_can.c: Add CAN support to the + Zilogics Technologies ZKIT-ARM-1769 board (From Rashid Fatah, (2013-03-04)). + * arch/arm/src/lpc17/lpc17*_clockconfig.c: The WaveShare Open1788 + board now boots and passes the OS test. This is the work of + Rommel Marcelo (2013-03-04). diff --git a/nuttx/Documentation/NuttX.html b/nuttx/Documentation/NuttX.html index cd9cc489d..3d3782ab6 100644 --- a/nuttx/Documentation/NuttX.html +++ b/nuttx/Documentation/NuttX.html @@ -8,7 +8,7 @@ <tr align="center" bgcolor="#e4e4e4"> <td> <h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1> - <p>Last Updated: February 18, 2013</p> + <p>Last Updated: March 4, 2013</p> </td> </tr> </table> @@ -1679,7 +1679,7 @@ svn checkout -r5595 http://svn.code.sf.net/p/nuttx/code/trunk nuttx-code <li><a href="#arm920t">ARM920T</a> (1) </li> <li><a href="#arm926ejs">ARM926EJS</a> (3) </li> <li><a href="#armcortexm0">ARM Cortex-M0</a> (1)</li> - <li><a href="#armcortexm3">ARM Cortex-M3</a> (16)</li> + <li><a href="#armcortexm3">ARM Cortex-M3</a> (17)</li> <li><a href="#armcortexm4">ARM Cortex-M4</a> (6)</li> </ul> <li>Atmel AVR @@ -2530,6 +2530,27 @@ nsh> </td> </tr> <tr> + <td><br></td> + <td><hr></td> +</tr> +<tr> + <td><br></td> + <td> + <p> + <b>NXP LPC1788</b>. + The port of NuttX to the WaveShare Open1788 is a collaborative effort between Rommel Marcelo and myself + (with Rommel being the leading contributor and I claiming only a support role). + You can get more information at the Open1788 board from the WaveShare <a href="http://www.wvshare.com/product/Open1788-Standard.htm">website</a>. + </p> + <ul> + <b>STATUS:</b> + This is still a work in progess. + At present there is a working basic port with OS verification and Nuttshell (<a href="http://www.nuttx.org/Documentation/NuttShell.html">NSH</a>) configurations. + This is stablilizing nicely now and the next steps will involve getting solid LCD support on the WaveShare board. + </ul> + </td> +</tr> +<tr> <td valign="top"><img height="20" width="20" src="favicon.ico"></td> <td bgcolor="#5eaee1"> <a name="armcortexm4"><b>ARM Cortex-M4</b>.</a> diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_syscon.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_syscon.h index f52fca35c..80c5386af 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_syscon.h +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_syscon.h @@ -78,9 +78,9 @@ /* Clocking and power control -- Clock dividers */ -#define LPC17_SYSCON_EMCCLKCFG_OFFSET 0x0100 /* EMC Clock Configuration Register */ -#define LPC17_SYSCON_CCLKCFG_OFFSET 0x0104 /* CPU Clock Configuration Register */ -#define LPC17_SYSCON_USBCLKCFG_OFFSET 0x0108 /* USB Clock Configuration Register */ +#define LPC17_SYSCON_EMCCLKSEL_OFFSET 0x0100 /* EMC Clock Selection Register */ +#define LPC17_SYSCON_CCLKSEL_OFFSET 0x0104 /* CPU Clock Selection Register */ +#define LPC17_SYSCON_USBCLKSEL_OFFSET 0x0108 /* USB Clock Selection Register */ /* 0x400f c110 - 0x400f c114: CAN Wake and Sleep Registers */ @@ -160,9 +160,9 @@ /* Clocking and power control -- Clock dividers */ -#define LPC17_SYSCON_EMCCLKCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_EMCCLKCFG_OFFSET) -#define LPC17_SYSCON_CCLKCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_CCLKCFG_OFFSET) -#define LPC17_SYSCON_USBCLKCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_USBCLKCFG_OFFSET) +#define LPC17_SYSCON_EMCCLKSEL (LPC17_SYSCON_BASE+LPC17_SYSCON_EMCCLKSEL_OFFSET) +#define LPC17_SYSCON_CCLKSEL (LPC17_SYSCON_BASE+LPC17_SYSCON_CCLKSEL_OFFSET) +#define LPC17_SYSCON_USBCLKSEL (LPC17_SYSCON_BASE+LPC17_SYSCON_USBCLKSEL_OFFSET) /* 0x400f c110 - 0x400f c114: CAN Wake and Sleep Registers */ @@ -277,28 +277,28 @@ /* 0: EMC uses same clock as CPU */ /* 1: EMC uses half the rate of CPU */ /* Bits 1-31: Reserved */ -/* CPU Clock Configuration register */ +/* CPU Clock Selection register */ -#define SYSCON_CCLKCFG_CCLKDIV_SHIFT (0) /* 0-4: Divide value for CPU clock (CCLK) */ -#define SYSCON_CCLKCFG_CCLKDIV_MASK (0x1f << SYSCON_CCLKCFG_CCLKDIV_SHIFT) -# define SYSCON_CCLKCFG_CCLKDIV(n) ((n-1) << SYSCON_CCLKCFG_CCLKDIV_SHIFT) /* n = 2 - 31 */ +#define SYSCON_CCLKSEL_CCLKDIV_SHIFT (0) /* 0-4: Divide value for CPU clock (CCLK) */ +#define SYSCON_CCLKSEL_CCLKDIV_MASK (0x1f << SYSCON_CCLKSEL_CCLKDIV_SHIFT) +# define SYSCON_CCLKSEL_CCLKDIV(n) ((n-1) << SYSCON_CCLKSEL_CCLKDIV_SHIFT) /* n = 2 - 31 */ /* Bits 5-7: Reserved */ -#define SYSCON_CCLKCFG_CCLKSEL (1 << 8) /* Bit 8: Select input clock to CPU clock divider */ +#define SYSCON_CCLKSEL_CCLKSEL (1 << 8) /* Bit 8: Select input clock to CPU clock divider */ /* 0: Sysclk used as input to CCLKDIV */ /* 1: Main PLL used as input to CCLKDIV */ /* Bits 9-31: Reserved */ -/* USB Clock Configuration register */ +/* USB Clock Selection register */ -#define SYSCON_USBCLKCFG_USBDIV_SHIFT (0) /* Bits 0-4: PLL0/1 divide value USB clock */ -#define SYSCON_USBCLKCFG_USBDIV_MASK (0x1f << SYSCON_USBCLKCFG_USBDIV_SHIFT) -# define SYSCON_USBCLKCFG_USBDIV_DIV1 (1 << SYSCON_USBCLKCFG_USBDIV_SHIFT) /* PLL0/1 output must be 48MHz */ -# define SYSCON_USBCLKCFG_USBDIV_DIV2 (2 << SYSCON_USBCLKCFG_USBDIV_SHIFT) /* PLL0/1 output must be 96MHz */ -# define SYSCON_USBCLKCFG_USBDIV_DIV3 (3 << SYSCON_USBCLKCFG_USBDIV_SHIFT) /* PLL0/1 output must be 144MHz */ +#define SYSCON_USBCLKSEL_USBDIV_SHIFT (0) /* Bits 0-4: PLL0/1 divide value USB clock */ +#define SYSCON_USBCLKSEL_USBDIV_MASK (0x1f << SYSCON_USBCLKSEL_USBDIV_SHIFT) +# define SYSCON_USBCLKSEL_USBDIV_DIV1 (1 << SYSCON_USBCLKSEL_USBDIV_SHIFT) /* PLL0/1 output must be 48MHz */ +# define SYSCON_USBCLKSEL_USBDIV_DIV2 (2 << SYSCON_USBCLKSEL_USBDIV_SHIFT) /* PLL0/1 output must be 96MHz */ +# define SYSCON_USBCLKSEL_USBDIV_DIV3 (3 << SYSCON_USBCLKSEL_USBDIV_SHIFT) /* PLL0/1 output must be 144MHz */ /* Bits 5-7: Reserved */ -#define SYSCON_USBCLKCFG_USBSEL_SHIFT (8) /* Bits 8-9: Input clock to USBDIV */ -#define SYSCON_USBCLKCFG_USBSEL_MASK (3 << SYSCON_USBCLKCFG_USBSEL_SHIFT) -#define SYSCON_USBCLKCFG_USBSEL_PLL0 (1 << SYSCON_USBCLKCFG_USBSEL_SHIFT) /* 01: PLL0 is used as input clock to USBDIV */ -#define SYSCON_USBCLKCFG_USBSEL_PLL1 (2 << SYSCON_USBCLKCFG_USBSEL_SHIFT) /* 10: PLL1 is used as input clock to USBDIV */ +#define SYSCON_USBCLKSEL_USBSEL_SHIFT (8) /* Bits 8-9: Input clock to USBDIV */ +#define SYSCON_USBCLKSEL_USBSEL_MASK (3 << SYSCON_USBCLKSEL_USBSEL_SHIFT) +#define SYSCON_USBCLKSEL_USBSEL_PLL0 (1 << SYSCON_USBCLKSEL_USBSEL_SHIFT) /* 01: PLL0 is used as input clock to USBDIV */ +#define SYSCON_USBCLKSEL_USBSEL_PLL1 (2 << SYSCON_USBCLKSEL_USBSEL_SHIFT) /* 10: PLL1 is used as input clock to USBDIV */ /* 11: unused */ /* Bits 10-31: Reserved */ /* CAN0/1 Sleep Clear Register */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_memorymap.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_memorymap.h index ef720ae59..c51fe8e74 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_memorymap.h +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_memorymap.h @@ -42,6 +42,10 @@ #include <nuttx/config.h> +/* This file is only a thin shell that includes the correct memory map definitions + * for the selected LPC17xx family. + */ + #include <arch/lpc17xx/chip.h> #if defined(LPC176x) diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconfig.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconfig.h index e90b425a9..c98c90e6b 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconfig.h +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconfig.h @@ -42,6 +42,10 @@ #include <nuttx/config.h> +/* This file is only a thin shell that includes the correct pin configuration + * definitions for the selected LPC17xx family. + */ + #include <arch/lpc17xx/chip.h> #if defined(LPC176x) diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconn.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconn.h index 1ca4d163f..8b6829f9b 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconn.h +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconn.h @@ -42,6 +42,10 @@ #include <nuttx/config.h> +/* This file is only a thin shell that includes the correct pin configuration + * register definitions for the selected LPC17xx family. + */ + #include <arch/lpc17xx/chip.h> #if defined(LPC176x) diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_syscon.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_syscon.h index ebe39cb72..ebab3a1be 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_syscon.h +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_syscon.h @@ -42,6 +42,10 @@ #include <nuttx/config.h> +/* This file is only a thin shell that includes the correct system controller + * register definitions for the selected LPC17xx family. + */ + #include <arch/lpc17xx/chip.h> #if defined(LPC176x) diff --git a/nuttx/arch/arm/src/lpc17xx/lpc176x_clockconfig.c b/nuttx/arch/arm/src/lpc17xx/lpc176x_clockconfig.c new file mode 100644 index 000000000..4befd3759 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/lpc176x_clockconfig.c @@ -0,0 +1,221 @@ +/**************************************************************************** + * arch/arm/src/lpc17xx/lpc17_clockconfig.c + * arch/arm/src/chip/lpc17_clockconfig.c + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <debug.h> + +#include <nuttx/arch.h> +#include <arch/board/board.h> + +#include "up_arch.h" +#include "up_internal.h" +#include "lpc17_clockconfig.h" +#include "chip/lpc17_syscon.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef LPC176x +# error "The logic in this file applies only to the LPC176x family" +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/************************************************************************************ + * Name: lpc17_clockconfig + * + * Description: + * Called to initialize the LPC176x. This does whatever setup is needed to put the + * SoC in a usable state. This includes the initialization of clocking using the + * settings in board.h. + * + * The LPC176x and LPC178x system control block is *nearly* identical but we have + * found that the LPC178x is more sensitive to the ordering of certain operations. + * So, although the hardware seems very similar, the safer thing to do is to + * separate the LPC176x and LPC178x into separate files. + * + ************************************************************************************/ + +void lpc17_clockconfig(void) +{ + /* Enable the main oscillator (or not) and the frequency range of the main oscillator */ + + putreg32(BOARD_SCS_VALUE, LPC17_SYSCON_SCS); + + /* Wait for the main oscillator to be ready. */ + +#ifdef CONFIG_LPC17_MAINOSC + while ((getreg32(LPC17_SYSCON_SCS) & SYSCON_SCS_OSCSTAT) == 0); +#endif + + /* Setup up the divider value for the CPU clock. The output of the divider is CCLK. + * The input to the divider (PLLCLK) is equal to SYSCLK unless PLL0 is enabled. CCLK + * will be further divided to produce peripheral clocks, but that peripheral clock + * setup is performed in the peripheral device drivers. Here only CCLK is + * configured. + */ + + putreg32(BOARD_CCLKCFG_VALUE, LPC17_SYSCON_CCLKCFG); + + /* PLL0 is used to generate the CPU clock divider input (PLLCLK). */ + +#ifdef CONFIG_LPC17_PLL0 + /* Select the PLL0 source clock, multiplier, and pre-divider values. NOTE that + * a special "feed" sequence must be written to the PLL0FEED register in order + * for changes to the PLL0CFG register to take effect. + */ + + putreg32(BOARD_CLKSRCSEL_VALUE, LPC17_SYSCON_CLKSRCSEL); + putreg32(BOARD_PLL0CFG_VALUE, LPC17_SYSCON_PLL0CFG); + putreg32(0xaa, LPC17_SYSCON_PLL0FEED); + putreg32(0x55, LPC17_SYSCON_PLL0FEED); + + /* Enable the PLL. NOTE that a special "feed" sequence must be written to the + * PLL0FEED register in order for changes to the PLL0CON register to take effect. + */ + + putreg32(SYSCON_PLLCON_PLLE, LPC17_SYSCON_PLL0CON); + putreg32(0xaa, LPC17_SYSCON_PLL0FEED); + putreg32(0x55, LPC17_SYSCON_PLL0FEED); + + /* Wait for PLL0 to lock */ + + while ((getreg32(LPC17_SYSCON_PLL0STAT) & SYSCON_PLL0STAT_PLOCK) == 0); + + /* Enable and connect PLL0 */ + + putreg32(SYSCON_PLLCON_PLLE|SYSCON_PLLCON_PLLC, LPC17_SYSCON_PLL0CON); + putreg32(0xaa, LPC17_SYSCON_PLL0FEED); + putreg32(0x55, LPC17_SYSCON_PLL0FEED); + + /* Wait for PLL to report that it is connected and enabled */ + + while ((getreg32(LPC17_SYSCON_PLL0STAT) & (SYSCON_PLL0STAT_PLLE|SYSCON_PLL0STAT_PLLC)) + != (SYSCON_PLL0STAT_PLLE|SYSCON_PLL0STAT_PLLC)); + +#endif /* CONFIG_LPC17_PLL0 */ + + /* PLL1 receives its clock input from the main oscillator only and can be used to + * provide a fixed 48 MHz clock only to the USB subsystem (if that clock cannot be + * obtained from PLL0). + */ + +#ifdef CONFIG_LPC17_PLL1 + /* Select the PLL1 multiplier, and pre-divider values. NOTE that a special "feed" + * sequence must be written to the PLL1FEED register in order for changes to the + * PLL1CFG register to take effect. + */ + + putreg32(BOARD_PLL1CFG_VALUE, LPC17_SYSCON_PLL1CFG); + putreg32(0xaa, LPC17_SYSCON_PLL1FEED); + putreg32(0x55, LPC17_SYSCON_PLL1FEED); + + /* Enable the PLL. NOTE that a special "feed" sequence must be written to the + * PLL1FEED register in order for changes to the PLL1CON register to take effect. + */ + + putreg32(SYSCON_PLLCON_PLLE, LPC17_SYSCON_PLL1CON); + putreg32(0xaa, LPC17_SYSCON_PLL1FEED); + putreg32(0x55, LPC17_SYSCON_PLL1FEED); + + /* Wait for PLL1 to lock */ + + while ((getreg32(LPC17_SYSCON_PLL1STAT) & SYSCON_PLL1STAT_PLOCK) == 0); + + /* Enable and connect PLL1 */ + + putreg32(SYSCON_PLLCON_PLLE|SYSCON_PLLCON_PLLC, LPC17_SYSCON_PLL1CON); + putreg32(0xaa, LPC17_SYSCON_PLL1FEED); + putreg32(0x55, LPC17_SYSCON_PLL1FEED); + + /* Wait for PLL to report that it is connected and enabled */ + + while ((getreg32(LPC17_SYSCON_PLL1STAT) & (SYSCON_PLL1STAT_PLLE|SYSCON_PLL1STAT_PLLC)) + != (SYSCON_PLL1STAT_PLLE|SYSCON_PLL1STAT_PLLC)); + +#else /* CONFIG_LPC17_PLL1 */ + + /* Otherwise, setup up the USB clock divider to generate the USB clock from PLL0 */ + + putreg32(BOARD_USBCLKCFG_VALUE, LPC17_SYSCON_USBCLKCFG); + +#endif /* CONFIG_LPC17_PLL1 */ + + /* Disable all peripheral clocks. They must be configured by each device driver + * when the device driver is initialized. + */ + + putreg32(0, LPC17_SYSCON_PCLKSEL0); + putreg32(0, LPC17_SYSCON_PCLKSEL1); + + /* Disable power to all peripherals (execpt GPIO). Peripherals must be re-powered + * one at a time by each device driver when the driver is initialized. + */ + + putreg32(SYSCON_PCONP_PCGPIO, LPC17_SYSCON_PCONP); + + /* Disable CLKOUT */ + + putreg32(0, LPC17_SYSCON_CLKOUTCFG); + + /* Configure FLASH */ + +#ifdef CONFIG_LPC17_FLASH + putreg32(BOARD_FLASHCFG_VALUE, LPC17_SYSCON_FLASHCFG); +#endif +} + diff --git a/nuttx/arch/arm/src/lpc17xx/lpc178x_clockconfig.c b/nuttx/arch/arm/src/lpc17xx/lpc178x_clockconfig.c new file mode 100644 index 000000000..948c17d7f --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/lpc178x_clockconfig.c @@ -0,0 +1,233 @@ +/**************************************************************************** + * arch/arm/src/lpc17xx/lpc17_clockconfig.c + * arch/arm/src/chip/lpc17_clockconfig.c + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <debug.h> + +#include <nuttx/arch.h> +#include <arch/board/board.h> + +#include "up_arch.h" +#include "up_internal.h" +#include "lpc17_clockconfig.h" +#include "chip/lpc17_syscon.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef LPC178x +# error "The logic in this file applies only to the LPC178x family" +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/************************************************************************************ + * Name: lpc17_clockconfig + * + * Description: + * Called to initialize the LPC17xx. This does whatever setup is needed to put the + * SoC in a usable state. This includes the initialization of clocking using the + * settings in board.h. + * + * The LPC176x and LPC178x system control block is *nearly* identical but we have + * found that the LPC178x is more sensitive to the ordering of certain operations. + * So, although the hardware seems very similar, the safer thing to do is to + * separate the LPC176x and LPC178x into separate files. + * + ************************************************************************************/ + +void lpc17_clockconfig(void) +{ + /* TODO: + * + * (1) "Make sure that the PLL output is not already being used. The CCLKSEL, + * USBCLKSEL, and SPIFICLKSEL registers must not select the PLL being set up. + * Clock dividers included in these registers may also be set up at this time + * if writing to any of the noted registers." + * + * (2) "If the main PLL is being set up, and the main clock source is being changed + * (IRC versus main oscillator), change this first by writing the correct + * value to the CLKSRCSEL register." + * + * This is not an issue now because we only setup the clocks on power up, so the + * PLL cannot be the select source. However, this could be an issue at some point + * later when, for example, we may want to implement reduced power mode with other + * clocking. + */ + + /* Enable the main oscillator (or not) and the frequency range of the main oscillator */ + + putreg32(BOARD_SCS_VALUE, LPC17_SYSCON_SCS); + + /* Wait for the main oscillator to be ready. */ + +#ifdef CONFIG_LPC17_MAINOSC + while ((getreg32(LPC17_SYSCON_SCS) & SYSCON_SCS_OSCSTAT) == 0); +#endif + + /* PLL0 is used to generate the CPU clock divider input (PLLCLK). */ + +#ifdef CONFIG_LPC17_PLL0 + /* (3) "Write PLL new setup values to the PLLCFG register. Write a 1 to the + * PLLE bit in the PLLCON register. Perform a PLL feed sequence by writing + * first the value 0xAA, then the value 0x55 to the PLLFEED register" + * + * Select the PLL0 source clock, multiplier, and pre-divider values. NOTE that + * a special "feed" sequence must be written to the PLL0FEED register in order + * for changes to the PLL0CFG register to take effect. + */ + + putreg32(BOARD_CLKSRCSEL_VALUE, LPC17_SYSCON_CLKSRCSEL); + putreg32(BOARD_PLL0CFG_VALUE, LPC17_SYSCON_PLL0CFG); + putreg32(SYSCON_PLLCON_PLLE, LPC17_SYSCON_PLL0CON); + + /* Enable the PLL. NOTE that a special "feed" sequence must be written to the + * PLL0FEED register in order for changes to the PLL0CON register to take effect. + */ + + putreg32(0xaa, LPC17_SYSCON_PLL0FEED); + putreg32(0x55, LPC17_SYSCON_PLL0FEED); + + /* (4) "Set up the necessary clock dividers. These may include the CCLKSEL, + * PCLKSEL, EMCCLKSEL, USBCLKSEL, and the SPIFICLKSEL registers. + */ + + putreg32(BOARD_CCLKSEL_VALUE, LPC17_SYSCON_CCLKSEL); + putreg32(BOARD_PCLKDIV, LPC17_SYSCON_PCLKSEL); + +#ifdef CONFIG_LPC17_EMC + putreg32(BOARD_EMCCLKSEL_VALUE, LPC17_SYSCON_EMCCLKSEL); +#endif +#if defined(CONFIG_LPC17_USBDEV) || defined(CONFIG_LPC17_USBHOST) + putreg32(BOARD_USBCLKSEL_VALUE, LPC17_SYSCON_USBCLKSEL); +#endif +#ifdef CONFIG_LPC17_SPIFI + putreg32(BOARD_SPIFICLKSEL_VALUE, LPC17_SPIFICLKSEL_CCLKSEL); +#endif + + /* (5) "Wait for the PLL to lock. This may be accomplished by polling the + * PLLSTAT register and testing for PLOCK = 1, or by using the PLL lock + * interrupt.Wait for PLL0 to lock. + */ + + while ((getreg32(LPC17_SYSCON_PLL0STAT) & SYSCON_PLL0STAT_PLOCK) == 0); + + /* (6) "Connect the PLL by selecting its output in the appropriate places. This + * may include the CCLKSEL, USBCLKSEL, and SPIFICLKSEL registers. + */ + +#endif /* CONFIG_LPC17_PLL0 */ + + /* PLL1 receives its clock input from the main oscillator only and can be used to + * provide a fixed 48 MHz clock only to the USB subsystem (if that clock cannot be + * obtained from PLL0). + */ + +#ifdef CONFIG_LPC17_PLL1 + /* (3) "Write PLL new setup values to the PLLCFG register. Write a 1 to the + * PLLE bit in the PLLCON register. Perform a PLL feed sequence by writing + * first the value 0xAA, then the value 0x55 to the PLLFEED register" + * + * Select the PLL1 multiplier, and pre-divider values. NOTE that a special "feed" + * sequence must be written to the PLL1FEED register in order for changes to the + * PLL1CFG register to take effect. + */ + + putreg32(BOARD_PLL1CFG_VALUE, LPC17_SYSCON_PLL1CFG); + putreg32(SYSCON_PLLCON_PLLE, LPC17_SYSCON_PLL1CON); + + /* Enable the PLL. NOTE that a special "feed" sequence must be written to the + * PLL1FEED register in order for changes to the PLL1CON register to take effect. + */ + + putreg32(0xaa, LPC17_SYSCON_PLL1FEED); + putreg32(0x55, LPC17_SYSCON_PLL1FEED); + + /* (4) "Set up the necessary clock dividers. These may include the CCLKSEL, + * PCLKSEL, EMCCLKSEL, USBCLKSEL, and the SPIFICLKSEL registers. + */ + + /* (5) "Wait for the PLL to lock. This may be accomplished by polling the + * PLLSTAT register and testing for PLOCK = 1, or by using the PLL lock + * interrupt.Wait for PLL0 to lock. + */ + + while ((getreg32(LPC17_SYSCON_PLL1STAT) & SYSCON_PLL1STAT_PLOCK) == 0); + + /* (6) "Connect the PLL by selecting its output in the appropriate places. This + * may include the CCLKSEL, USBCLKSEL, and SPIFICLKSEL registers. + */ + +#endif /* CONFIG_LPC17_PLL1 */ + + /* Disable power to all peripherals (execpt GPIO). Peripherals must be re-powered + * one at a time by each device driver when the driver is initialized. + */ + + putreg32(SYSCON_PCONP_PCGPIO, LPC17_SYSCON_PCONP); + + /* Disable CLKOUT */ + + putreg32(0, LPC17_SYSCON_CLKOUTCFG); + + /* Configure FLASH */ + +#ifdef CONFIG_LPC17_FLASH + putreg32(BOARD_FLASHCFG_VALUE, LPC17_SYSCON_FLASHCFG); +#endif +} + diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.c b/nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.c index 9dc033d2d..97ef496f0 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.c @@ -40,16 +40,28 @@ #include <nuttx/config.h> -#include <stdint.h> -#include <debug.h> - -#include <nuttx/arch.h> -#include <arch/board/board.h> - -#include "up_arch.h" -#include "up_internal.h" -#include "lpc17_clockconfig.h" -#include "chip/lpc17_syscon.h" +/* This file is only a thin shell that includes the correct clock + * configuration logic for the selected LPC17xx family. The correct file + * cannot be selected by the make system because it needs the intelligence + * that only exists in chip.h that can associate an LPC17xx part number with + * an LPC17xx family. + * + * The LPC176x and LPC178x system control block is *nearly* identical but + * we have found that the LPC178x is more sensitive to the ordering of + * certain operations. So, although the hardware seems very similar, the + * safer thing to do is to separate the LPC176x and LPC178x into separate + * files. + */ + +#include <arch/lpc17xx/chip.h> + +#if defined(LPC176x) +# include "chip/lpc176x_clockconfig.c" +#elif defined(LPC178x) +# include "chip/lpc178x_clockconfig.c" +#else +# error "Unrecognized LPC17xx family" +#endif /**************************************************************************** * Pre-processor Definitions @@ -70,156 +82,3 @@ /**************************************************************************** * Public Functions ****************************************************************************/ - -/************************************************************************************ - * Name: lpc17_clockconfig - * - * Description: - * Called to initialize the LPC17xx. This does whatever setup is needed to put the - * SoC in a usable state. This includes the initialization of clocking using the - * settings in board.h. - * - ************************************************************************************/ - -void lpc17_clockconfig(void) -{ - /* Enable the main oscillator (or not) and the frequency range of the main oscillator */ - - putreg32(BOARD_SCS_VALUE, LPC17_SYSCON_SCS); - - /* Wait for the main oscillator to be ready. */ - -#ifdef CONFIG_LPC17_MAINOSC - while ((getreg32(LPC17_SYSCON_SCS) & SYSCON_SCS_OSCSTAT) == 0); -#endif - - /* Setup up the divider value for the CPU clock. The output of the divider is CCLK. - * The input to the divider (PLLCLK) is equal to SYSCLK unless PLL0 is enabled. CCLK - * will be further divided to produce peripheral clocks, but that peripheral clock - * setup is performed in the peripheral device drivers. Here only CCLK is - * configured. - */ - - putreg32(BOARD_CCLKCFG_VALUE, LPC17_SYSCON_CCLKCFG); - - /* PLL0 is used to generate the CPU clock divider input (PLLCLK). */ - -#ifdef CONFIG_LPC17_PLL0 - /* Select the PLL0 source clock, multiplier, and pre-divider values. NOTE that - * a special "feed" sequence must be written to the PLL0FEED register in order - * for changes to the PLL0CFG register to take effect. - */ - - putreg32(BOARD_CLKSRCSEL_VALUE, LPC17_SYSCON_CLKSRCSEL); - putreg32(BOARD_PLL0CFG_VALUE, LPC17_SYSCON_PLL0CFG); - putreg32(0xaa, LPC17_SYSCON_PLL0FEED); - putreg32(0x55, LPC17_SYSCON_PLL0FEED); - - /* Enable the PLL. NOTE that a special "feed" sequence must be written to the - * PLL0FEED register in order for changes to the PLL0CON register to take effect. - */ - - putreg32(SYSCON_PLLCON_PLLE, LPC17_SYSCON_PLL0CON); - putreg32(0xaa, LPC17_SYSCON_PLL0FEED); - putreg32(0x55, LPC17_SYSCON_PLL0FEED); - - /* Wait for PLL0 to lock */ - - while ((getreg32(LPC17_SYSCON_PLL0STAT) & SYSCON_PLL0STAT_PLOCK) == 0); - -# if defined(LPC176x) - /* Enable and connect PLL0 */ - - putreg32(SYSCON_PLLCON_PLLE|SYSCON_PLLCON_PLLC, LPC17_SYSCON_PLL0CON); - putreg32(0xaa, LPC17_SYSCON_PLL0FEED); - putreg32(0x55, LPC17_SYSCON_PLL0FEED); - - /* Wait for PLL to report that it is connected and enabled */ - - while ((getreg32(LPC17_SYSCON_PLL0STAT) & (SYSCON_PLL0STAT_PLLE|SYSCON_PLL0STAT_PLLC)) - != (SYSCON_PLL0STAT_PLLE|SYSCON_PLL0STAT_PLLC)); - -# endif /* LPC176x */ -#endif /* CONFIG_LPC17_PLL0 */ - - /* PLL1 receives its clock input from the main oscillator only and can be used to - * provide a fixed 48 MHz clock only to the USB subsystem (if that clock cannot be - * obtained from PLL0). - */ - -#ifdef CONFIG_LPC17_PLL1 - /* Select the PLL1 multiplier, and pre-divider values. NOTE that a special "feed" - * sequence must be written to the PLL1FEED register in order for changes to the - * PLL1CFG register to take effect. - */ - - putreg32(BOARD_PLL1CFG_VALUE, LPC17_SYSCON_PLL1CFG); - putreg32(0xaa, LPC17_SYSCON_PLL1FEED); - putreg32(0x55, LPC17_SYSCON_PLL1FEED); - - /* Enable the PLL. NOTE that a special "feed" sequence must be written to the - * PLL1FEED register in order for changes to the PLL1CON register to take effect. - */ - - putreg32(SYSCON_PLLCON_PLLE, LPC17_SYSCON_PLL1CON); - putreg32(0xaa, LPC17_SYSCON_PLL1FEED); - putreg32(0x55, LPC17_SYSCON_PLL1FEED); - - /* Wait for PLL1 to lock */ - - while ((getreg32(LPC17_SYSCON_PLL1STAT) & SYSCON_PLL1STAT_PLOCK) == 0); - -# if defined(LPC176x) - /* Enable and connect PLL1 */ - - putreg32(SYSCON_PLLCON_PLLE|SYSCON_PLLCON_PLLC, LPC17_SYSCON_PLL1CON); - putreg32(0xaa, LPC17_SYSCON_PLL1FEED); - putreg32(0x55, LPC17_SYSCON_PLL1FEED); - - /* Wait for PLL to report that it is connected and enabled */ - - while ((getreg32(LPC17_SYSCON_PLL1STAT) & (SYSCON_PLL1STAT_PLLE|SYSCON_PLL1STAT_PLLC)) - != (SYSCON_PLL1STAT_PLLE|SYSCON_PLL1STAT_PLLC)); - -# endif -#else /* CONFIG_LPC17_PLL1 */ - - /* Otherwise, setup up the USB clock divider to generate the USB clock from PLL0 */ - -#ifdef LPC176x - putreg32(BOARD_USBCLKCFG_VALUE, LPC17_SYSCON_USBCLKCFG); -#endif -#endif /* CONFIG_LPC17_PLL1 */ - - /* Disable all peripheral clocks. They must be configured by each device driver - * when the device driver is initialized. - */ - -#ifdef LPC176x - putreg32(0, LPC17_SYSCON_PCLKSEL0); - putreg32(0, LPC17_SYSCON_PCLKSEL1); -#endif - - /* Set the peripheral clock (PCLK) divider that is used by all APB peripherals. */ - -#ifdef LPC178x - putreg32(BOARD_PCLKDIV, LPC17_SYSCON_PCLKSEL); -#endif - - /* Disable power to all peripherals (execpt GPIO). Peripherals must be re-powered - * one at a time by each device driver when the driver is initialized. - */ - - putreg32(SYSCON_PCONP_PCGPIO, LPC17_SYSCON_PCONP); - - /* Disable CLKOUT */ - - putreg32(0, LPC17_SYSCON_CLKOUTCFG); - - /* Configure FLASH */ - -#ifdef CONFIG_LPC17_FLASH - putreg32(BOARD_FLASHCFG_VALUE, LPC17_SYSCON_FLASHCFG); -#endif -} - diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_serial.c b/nuttx/arch/arm/src/lpc17xx/lpc17_serial.c index 0159d7c75..713426b6e 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_serial.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_serial.c @@ -855,7 +855,7 @@ static inline uint32_t lpc17_uartdl(uint32_t baud, uint8_t divcode) #else static inline uint32_t lpc17_uartdl(uint32_t baud) { - return (uint32_t)BOARD_PCLK / (baud << 4); + return (uint32_t)BOARD_PCLK_FREQUENCY / (baud << 4); } #endif diff --git a/nuttx/configs/open1788/include/board.h b/nuttx/configs/open1788/include/board.h index b19c271e9..7a6fd0e07 100644 --- a/nuttx/configs/open1788/include/board.h +++ b/nuttx/configs/open1788/include/board.h @@ -86,8 +86,8 @@ * The input to the divider (PLLCLK) will be determined by the PLL output. */ -#define BOARD_CCLKCFG_DIVIDER 1 -#define BOARD_CCLKCFG_VALUE (BOARD_CCLKCFG_DIVIDER | SYSCON_CCLKCFG_CCLKSEL) +#define BOARD_CCLKSEL_DIVIDER 1 +#define BOARD_CCLKSEL_VALUE (BOARD_CCLKSEL_DIVIDER | SYSCON_CCLKSEL_CCLKSEL) /* PLL0. PLL0 is used to generate the CPU clock (PLLCLK). * @@ -125,7 +125,7 @@ * USBCLK = PLL1CLK = (SYSCLK * 4) = 48MHz */ -#define BOARD_USBCLKCFG_VALUE (SYSCON_USBCLKSEL_USBDIV_DIV1 | \ +#define BOARD_USBCLKSEL_VALUE (SYSCON_USBCLKSEL_USBDIV_DIV1 | \ SYSCON_USBCLKSEL_USBSEL_PLL1) #endif diff --git a/nuttx/configs/open1788/nsh/Make.defs b/nuttx/configs/open1788/nsh/Make.defs new file mode 100644 index 000000000..019f75024 --- /dev/null +++ b/nuttx/configs/open1788/nsh/Make.defs @@ -0,0 +1,109 @@ +############################################################################ +# configs/open1788k/nsh/Make.defs +# +# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt <gnutt@nuttx.org> +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mknulldeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script}" + MAXOPTIMIZATION = -O2 +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps.sh + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +else + ARCHOPTIMIZATION = $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow +ARCHWARNINGSXX = -Wall -Wshadow +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -g -pipe +HOSTLDFLAGS = + diff --git a/nuttx/configs/open1788/nsh/defconfig b/nuttx/configs/open1788/nsh/defconfig new file mode 100644 index 000000000..0d16b690e --- /dev/null +++ b/nuttx/configs/open1788/nsh/defconfig @@ -0,0 +1,678 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# +CONFIG_NUTTX_NEWCONFIG=y + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +# CONFIG_RAW_BINARY is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set + +# +# Debug Options +# +# CONFIG_DEBUG is not set +# CONFIG_DEBUG_SYMBOLS is not set + +# +# System Type +# +# CONFIG_ARCH_8051 is not set +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_IMX is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_LM is not set +CONFIG_ARCH_CHIP_LPC17XX=y +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +# CONFIG_ARCH_CHIP_SAM3U is not set +# CONFIG_ARCH_CHIP_STM32 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +CONFIG_ARCH_CORTEXM3=y +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="lpc17xx" +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_CMNVECTOR=y +# CONFIG_ARMV7M_CMNVECTOR is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARMV7M_MPU is not set + +# +# ARMV7M Configuration Options +# +CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set +CONFIG_ARMV7M_OABI_TOOLCHAIN=y + +# +# LPC17xx Configuration Options +# +# CONFIG_ARCH_CHIP_LPC1751 is not set +# CONFIG_ARCH_CHIP_LPC1752 is not set +# CONFIG_ARCH_CHIP_LPC1754 is not set +# CONFIG_ARCH_CHIP_LPC1756 is not set +# CONFIG_ARCH_CHIP_LPC1758 is not set +# CONFIG_ARCH_CHIP_LPC1759 is not set +# CONFIG_ARCH_CHIP_LPC1764 is not set +# CONFIG_ARCH_CHIP_LPC1765 is not set +# CONFIG_ARCH_CHIP_LPC1766 is not set +# CONFIG_ARCH_CHIP_LPC1767 is not set +# CONFIG_ARCH_CHIP_LPC1768 is not set +# CONFIG_ARCH_CHIP_LPC1769 is not set +# CONFIG_ARCH_CHIP_LPC1773 is not set +# CONFIG_ARCH_CHIP_LPC1774 is not set +# CONFIG_ARCH_CHIP_LPC1776 is not set +# CONFIG_ARCH_CHIP_LPC1777 is not set +# CONFIG_ARCH_CHIP_LPC1778 is not set +# CONFIG_ARCH_CHIP_LPC1785 is not set +# CONFIG_ARCH_CHIP_LPC1786 is not set +# CONFIG_ARCH_CHIP_LPC1787 is not set +CONFIG_ARCH_CHIP_LPC1788=y +CONFIG_ARCH_FAMILY_LPC178X=y + +# +# LPC17xx Peripheral Support +# +CONFIG_LPC17_MAINOSC=y +CONFIG_LPC17_PLL0=y +CONFIG_LPC17_PLL1=y +# CONFIG_LPC17_EMC is not set +# CONFIG_LPC17_ETHERNET is not set +# CONFIG_LPC17_USBHOST is not set +# CONFIG_LPC17_USBDEV is not set +CONFIG_LPC17_UART0=y +# CONFIG_LPC17_UART1 is not set +# CONFIG_LPC17_UART2 is not set +# CONFIG_LPC17_UART3 is not set +# CONFIG_LPC17_CAN1 is not set +# CONFIG_LPC17_CAN2 is not set +# CONFIG_LPC17_SPI is not set +# CONFIG_LPC17_SSP0 is not set +# CONFIG_LPC17_SSP1 is not set +# CONFIG_LPC17_I2C0 is not set +# CONFIG_LPC17_I2C1 is not set +# CONFIG_LPC17_I2C2 is not set +# CONFIG_LPC17_I2S is not set +# CONFIG_LPC17_TMR0 is not set +# CONFIG_LPC17_TMR1 is not set +# CONFIG_LPC17_TMR2 is not set +# CONFIG_LPC17_TMR3 is not set +# CONFIG_LPC17_RIT is not set +# CONFIG_LPC17_PWM is not set +# CONFIG_LPC17_MCPWM is not set +# CONFIG_LPC17_QEI is not set +# CONFIG_LPC17_RTC is not set +# CONFIG_LPC17_WDT is not set +# CONFIG_LPC17_ADC is not set +# CONFIG_LPC17_DAC is not set +# CONFIG_LPC17_GPDMA is not set +# CONFIG_LPC17_FLASH is not set + +# +# Serial driver options +# +# CONFIG_SERIAL_TERMIOS is not set +# CONFIG_UART0_FLOWCONTROL is not set + +# +# ADC driver options +# + +# +# CAN driver options +# +# CONFIG_GPIO_IRQ is not set + +# +# I2C driver options +# + +# +# Ethernet driver options +# + +# +# USB device driver options +# + +# +# USB host driver options +# + +# +# External Memory Configuration +# +CONFIG_ARCH_HAVE_EXTNAND=y +CONFIG_ARCH_HAVE_EXTNOR=y +CONFIG_ARCH_HAVE_EXTDRAM=y +CONFIG_ARCH_HAVE_EXTSRAM0=y +CONFIG_ARCH_EXTNAND=y +CONFIG_ARCH_EXTNANDSIZE=134217728 +CONFIG_ARCH_EXTNOR=y +CONFIG_ARCH_EXTNORSIZE=4194304 +CONFIG_ARCH_EXTDRAM=y +CONFIG_ARCH_EXTDRAMSIZE=67108864 +CONFIG_ARCH_EXTDRAMHEAP=y +CONFIG_ARCH_EXTSRAM0=y +CONFIG_ARCH_EXTSRAM0SIZE=131072 +CONFIG_ARCH_EXTSRAM0HEAP=y + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_IRQPRIO=y +# CONFIG_CUSTOM_STACK is not set +# CONFIG_ADDRENV is not set +CONFIG_ARCH_HAVE_VFORK=y +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=8079 +# CONFIG_ARCH_CALIBRATION is not set +CONFIG_DRAM_START=0x10000000 +CONFIG_DRAM_SIZE=65536 +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_OPEN1788=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="open1788" + +# +# Common Board Options +# +CONFIG_NSH_MMCSDMINOR=0 + +# +# Board-Specific Options +# + +# +# RTOS Features +# +# CONFIG_BOARD_INITIALIZE is not set +CONFIG_MSEC_PER_TICK=10 +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_INSTRUMENTATION is not set +CONFIG_TASK_NAME_SIZE=0 +# CONFIG_SCHED_HAVE_PARENT is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2013 +CONFIG_START_MONTH=3 +CONFIG_START_DAY=4 +CONFIG_DEV_CONSOLE=y +# CONFIG_MUTEX_TYPES is not set +# CONFIG_PRIORITY_INHERITANCE is not set +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +# CONFIG_SDCLONE_DISABLE is not set +# CONFIG_SCHED_WORKQUEUE is not set +CONFIG_SCHED_WAITPID=y +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_CLOCK is not set +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_ENVIRON is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + +# +# Sizes of configurable things (0 disables) +# +CONFIG_MAX_TASKS=16 +CONFIG_MAX_TASK_ARGS=4 +CONFIG_NPTHREAD_KEYS=4 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_PREALLOC_TIMERS=4 + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 + +# +# Device Drivers +# +# CONFIG_DISABLE_POLL is not set +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +CONFIG_LOOP=y +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_PWM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +CONFIG_BCH=y +# CONFIG_INPUT is not set +# CONFIG_LCD is not set +# CONFIG_MMCSD is not set +# CONFIG_MTD is not set +CONFIG_PIPES=y +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_16550_UART is not set +CONFIG_ARCH_HAVE_UART0=y +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +CONFIG_CONFIG_SERIAL_NPOLLWAITERS=2 +CONFIG_UART0_SERIAL_CONSOLE=y +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# UART0 Configuration +# +CONFIG_UART0_RXBUFSIZE=256 +CONFIG_UART0_TXBUFSIZE=256 +CONFIG_UART0_BAUD=115200 +CONFIG_UART0_BITS=8 +CONFIG_UART0_PARITY=0 +CONFIG_UART0_2STOP=0 +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_WIRELESS is not set + +# +# System Logging Device Options +# + +# +# System Logging +# +# CONFIG_RAMLOG is not set + +# +# Networking Support +# +# CONFIG_NET is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_RAMMAP is not set +CONFIG_FS_FAT=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FAT_MAXFNAME=32 +# CONFIG_FS_FATTIME is not set +# CONFIG_FAT_DMAMEMORY is not set +# CONFIG_FS_NXFFS is not set +CONFIG_FS_ROMFS=y + +# +# System Logging +# +# CONFIG_SYSLOG_ENABLE is not set +# CONFIG_SYSLOG is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=2 +# CONFIG_GRAN is not set + +# +# Binary Formats +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +# CONFIG_BUILTIN is not set +# CONFIG_PIC is not set +CONFIG_SYMTAB_ORDEREDBYNAME=y + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set + +# +# Non-standard Helper Functions +# +# CONFIG_LIB_KBDCODEC is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_COMPOSITE is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_LCDRW is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_MODBUS is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXCONSOLE is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXFLAT is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PASHELLO is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_POLL is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_QENCODER is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_ROMFS is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_THTTPD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_UIP is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBMSC is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# Network Utilities +# + +# +# Networking Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_DHCPC is not set +# CONFIG_NETUTILS_DHCPD is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_FTPD is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_RESOLV is not set +# CONFIG_NETUTILS_SMTP is not set +# CONFIG_NETUTILS_TELNETD is not set +# CONFIG_NETUTILS_TFTPC is not set +# CONFIG_NETUTILS_THTTPD is not set +# CONFIG_NETUTILS_UIPLIB is not set +# CONFIG_NETUTILS_WEBCLIENT is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKFATFS is not set +# CONFIG_NSH_DISABLE_MKFIFO is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MW is not set +# CONFIG_NSH_DISABLE_NSFMOUNT is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PING is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_CODECS_BUFSIZE=128 +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=80 +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_ROMFSETC is not set +CONFIG_NSH_CONSOLE=y + +# +# USB Trace Support +# +# CONFIG_NSH_CONDEV is not set +CONFIG_NSH_ARCHINIT=y + +# +# NxWidgets/NxWM +# + +# +# System NSH Add-Ons +# + +# +# Custom Free Memory Command +# +# CONFIG_SYSTEM_FREE is not set + +# +# I2C tool +# + +# +# FLASH Program Installation +# +# CONFIG_SYSTEM_INSTALL is not set + +# +# readline() +# +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y + +# +# Power Off +# +# CONFIG_SYSTEM_POWEROFF is not set + +# +# RAMTRON +# +# CONFIG_SYSTEM_RAMTRON is not set + +# +# SD Card +# +# CONFIG_SYSTEM_SDCARD is not set + +# +# Sysinfo +# +# CONFIG_SYSTEM_SYSINFO is not set + +# +# USB Monitor +# diff --git a/nuttx/configs/open1788/nsh/setenv.sh b/nuttx/configs/open1788/nsh/setenv.sh new file mode 100755 index 000000000..1a6cdd1a6 --- /dev/null +++ b/nuttx/configs/open1788/nsh/setenv.sh @@ -0,0 +1,73 @@ +#!/bin/bash +# configs/open1788/nsh/setenv.sh +# +# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt <gnutt@nuttx.org> +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" + +# These are the Cygwin paths to the locations where I installed the Atollic +# toolchain under windows. You will also have to edit this if you install +# the Atollic toolchain in any other location. /usr/bin is added before +# the Atollic bin path because there is are binaries named gcc.exe and g++.exe +# at those locations as well. +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin" +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" + +# The Olimex-lpc1766stk/tools directory +export LPCTOOL_DIR="${WD}/configs/open1788/tools" + +# Add the path to the toolchain and tools directory to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:${LPCTOOL_DIR}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/nuttx/configs/open1788/src/lpc17_nsh.c b/nuttx/configs/open1788/src/lpc17_nsh.c index 3e143df88..5406737d2 100644 --- a/nuttx/configs/open1788/src/lpc17_nsh.c +++ b/nuttx/configs/open1788/src/lpc17_nsh.c @@ -2,7 +2,7 @@ * config/open1788/src/lpc17_nsh.c * arch/arm/src/board/lpc17_nsh.c * - * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -58,60 +58,68 @@ /* Configuration ************************************************************/ -/* PORT and SLOT number probably depend on the board configuration */ +#define NSH_HAVE_MMCSD 1 +#define NSH_HAVE_USBHOST 1 +#define NSH_HAVE_USBHDEV 1 -#ifdef CONFIG_ARCH_BOARD_OPEN1788 -# define NSH_HAVEMMCSD 1 -# define NSH_HAVEUSBHOST 1 -# if !defined(CONFIG_NSH_MMCSDSPIPORTNO) || CONFIG_NSH_MMCSDSPIPORTNO != 1 -# error "The Open1788 MMC/SD is on SSP1" -# undef CONFIG_NSH_MMCSDSPIPORTNO -# define CONFIG_NSH_MMCSDSPIPORTNO 1 -# endif -# if !defined(CONFIG_NSH_MMCSDSLOTNO) || CONFIG_NSH_MMCSDSLOTNO != 0 -# error "The Open1788 MMC/SD is only one slot (0)" -# undef CONFIG_NSH_MMCSDSLOTNO -# define CONFIG_NSH_MMCSDSLOTNO 0 -# endif -# ifndef CONFIG_LPC17_SSP1 -# warning "CONFIG_LPC17_SSP1 is not enabled" -# undef NSH_HAVEMMCSD -# endif -#else -# error "Unrecognized board" -# undef NSH_HAVEMMCSD -# undef NSH_HAVEUSBHOST +/* MMC/SD support */ + +#if !defined(CONFIG_MMCSD) && !defined(CONFIG_MMCD_SPI) +# undef NSH_HAVE_MMCSD #endif /* Can't support MMC/SD features if mountpoints are disabled */ #if defined(CONFIG_DISABLE_MOUNTPOINT) -# undef NSH_HAVEMMCSD +# undef NSH_HAVE_MMCSD #endif -#ifndef CONFIG_NSH_MMCSDMINOR -# define CONFIG_NSH_MMCSDMINOR 0 +/* MMC/SD support requires that an SPI support is enabled and an SPI port is selected */ + +#ifdef NSH_HAVE_MMCSD +# if !defined(CONFIG_NSH_MMCSDSPIPORTNO) +# error "No SSP port number is provided for MMC/SD support" +# undef NSH_HAVE_MMCSD +# elif CONFIG_NSH_MMCSDSPIPORTNO == 0 && !defined(CONFIG_LPC17_SSP0) +# error "SSP port 0 is selected but SSP0 is not enabled" +# undef NSH_HAVE_MMCSD +# elif CONFIG_NSH_MMCSDSPIPORTNO == 1 && !defined(CONFIG_LPC17_SSP1) +# error "SSP port 1 is selected but SSP1 is not enabled" +# undef NSH_HAVE_MMCSD +# elif CONFIG_NSH_MMCSDSPIPORTNO == 2 && !defined(CONFIG_LPC17_SSP2) +# error "SSP port 2 is selected but SSP2 is not enabled" +# undef NSH_HAVE_MMCSD +# elif CONFIG_NSH_MMCSDSPIPORTNO > 2 +# error "SSP port number is out of range" +# undef NSH_HAVE_MMCSD +# endif #endif -/* USB Host */ - -#ifdef CONFIG_USBHOST -# ifndef CONFIG_LPC17_USBHOST -# error "CONFIG_LPC17_USBHOST is not selected" +#ifdef NSH_HAVE_MMCSD +# if !defined(CONFIG_NSH_MMCSDSLOTNO) +# warning "Assuming slot MMC/SD slot 0" +# define CONFIG_NSH_MMCSDSLOTNO 0 # endif #endif -#ifdef CONFIG_LPC17_USBHOST -# ifndef CONFIG_USBHOST -# warning "CONFIG_USBHOST is not selected" +#ifdef NSH_HAVE_MMCSD +# if !defined(CONFIG_NSH_MMCSDSLOTNO) +# warning "Assuming /dev/mmcsd0" +# define CONFIG_NSH_MMCSDMINOR 0 # endif #endif -#if !defined(CONFIG_USBHOST) || !defined(CONFIG_LPC17_USBHOST) -# undef NSH_HAVEUSBHOST +/* USB Host */ + +#ifndef CONFIG_USBHOST +# undef NSH_HAVE_USBHOST #endif -#ifdef NSH_HAVEUSBHOST +#ifndef CONFIG_LPC17_USBHOST +# undef NSH_HAVE_USBHOST +#endif + +#ifdef NSH_HAVE_USBHOST # ifndef CONFIG_USBHOST_DEFPRIO # define CONFIG_USBHOST_DEFPRIO 50 # endif @@ -120,6 +128,16 @@ # endif #endif +/* USB Device */ + +#ifndef CONFIG_USBDEV +# undef NSH_HAVE_USBDEV +#endif + +#ifndef CONFIG_LPC17_USBDEV +# undef NSH_HAVE_USBDEV +#endif + /* Debug ********************************************************************/ #ifdef CONFIG_CPP_HAVE_VARARGS @@ -140,7 +158,7 @@ * Private Data ****************************************************************************/ -#ifdef NSH_HAVEUSBHOST +#ifdef NSH_HAVE_USBHOST static struct usbhost_driver_s *g_drvr; #endif @@ -156,7 +174,7 @@ static struct usbhost_driver_s *g_drvr; * ****************************************************************************/ -#ifdef NSH_HAVEUSBHOST +#ifdef NSH_HAVE_USBHOST static int nsh_waiter(int argc, char *argv[]) { bool connected = false; @@ -197,7 +215,7 @@ static int nsh_waiter(int argc, char *argv[]) * ****************************************************************************/ -#ifdef NSH_HAVEMMCSD +#ifdef NSH_HAVE_MMCSD static int nsh_sdinitialize(void) { FAR struct spi_dev_s *ssp; @@ -257,7 +275,7 @@ errout: * ****************************************************************************/ -#ifdef NSH_HAVEUSBHOST +#ifdef NSH_HAVE_USBHOST static int nsh_usbhostinitialize(void) { int pid; @@ -325,5 +343,6 @@ int nsh_archinitialize(void) ret = nsh_usbhostinitialize(); } + return ret; } diff --git a/nuttx/fs/fat/Kconfig b/nuttx/fs/fat/Kconfig index 1de613ce4..22c67b05d 100644 --- a/nuttx/fs/fat/Kconfig +++ b/nuttx/fs/fat/Kconfig @@ -30,6 +30,7 @@ config FAT_LFN config FAT_MAXFNAME int "FAT maximum file name size" depends on FAT_LFN + default 32 ---help--- If CONFIG_FAT_LFN is defined, then the default, maximum long file name is 255 bytes. This can eat up a lot of memory (especially stack |