diff options
Diffstat (limited to 'nuttx')
| -rw-r--r-- | nuttx/arch/arm/src/lpc214x/lpc214x_decodeirq.c | 2 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/str71x/Make.defs | 57 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/str71x/str71x_apb.h | 65 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/str71x/str71x_decodeirq.c | 123 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/str71x/str71x_eic.h | 131 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/str71x/str71x_emi.h | 72 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/str71x/str71x_gpio.h | 27 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/str71x/str71x_head.S | 667 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/str71x/str71x_irq.c | 127 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/str71x/str71x_pcu.h | 112 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/str71x/str71x_rccu.h | 195 | ||||
| -rw-r--r-- | nuttx/configs/mcu123-lpc214x/src/up_spi.c | 10 | ||||
| -rw-r--r-- | nuttx/configs/olimex-strp711/ostest/defconfig | 33 | ||||
| -rw-r--r-- | nuttx/configs/olimex-strp711/ostest/ld.script | 4 |
14 files changed, 1322 insertions, 303 deletions
diff --git a/nuttx/arch/arm/src/lpc214x/lpc214x_decodeirq.c b/nuttx/arch/arm/src/lpc214x/lpc214x_decodeirq.c index bf7b4940e..a8bdf885b 100644 --- a/nuttx/arch/arm/src/lpc214x/lpc214x_decodeirq.c +++ b/nuttx/arch/arm/src/lpc214x/lpc214x_decodeirq.c @@ -65,7 +65,7 @@ * Private Data ********************************************************************************/ -/* This type arry maps 4 bits into the bit number of the lowest bit that it set */ +/* This array maps 4 bits into the bit number of the lowest bit that it set */ #ifndef CONFIG_SUPPRESS_INTERRUPTS static uint8 g_nibblemap[16] = { 0, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0 }; diff --git a/nuttx/arch/arm/src/str71x/Make.defs b/nuttx/arch/arm/src/str71x/Make.defs new file mode 100644 index 000000000..0b5fd99dd --- /dev/null +++ b/nuttx/arch/arm/src/str71x/Make.defs @@ -0,0 +1,57 @@ +############################################################################## +# arch/arm/src/str71x/Make.defs +# +# Copyright (C) 2008 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt <spudmonkey@racsa.co.cr> +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################## + +HEAD_ASRC = str71x_head.S + +CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_vectors.S +CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \ + up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c \ + up_exit.c up_idle.c up_initialize.c up_initialstate.c \ + up_interruptcontext.c up_prefetchabort.c up_releasepending.c \ + up_releasestack.c up_reprioritizertr.c up_syscall.c up_unblocktask.c \ + up_undefinedinsn.c up_usestack.c up_lowputs.c + +ifneq ($(CONFIG_DISABLE_SIGNALS),y) +CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c +endif + +CHIP_ASRCS = str71x_lowputc.S +CHIP_CSRCS = str71x_decodeirq.c str71x_irq.c str71x_timerisr.c \ + str71x_serial.c + +ifeq ($(CONFIG_USBDEV),y) +CHIP_CSRCS += str71x_usbdev.c +endif + diff --git a/nuttx/arch/arm/src/str71x/str71x_apb.h b/nuttx/arch/arm/src/str71x/str71x_apb.h index bb8448107..f5453dc2b 100644 --- a/nuttx/arch/arm/src/str71x/str71x_apb.h +++ b/nuttx/arch/arm/src/str71x/str71x_apb.h @@ -48,46 +48,51 @@ * Definitions
************************************************************************************/
-/* APB Registers ********************************************************************/
+/* APB register offsets *************************************************************/
-#define STR71X_APB1_CKDIS (STR71X_APB1_BASE + 0x0010) /* 32-bits wide */
-#define STR71X_APB1_SWRES (STR71X_APB1_BASE + 0x0014) /* 32-bits wide */
+#define STR71X_APB_CKDIS_OFFSET (0x0010) /* 32-bits wide */
+#define STR71X_APB_SWRES_OFFSET (0x0014) /* 32-bits wide */
-#define STR71X_APB2_CKDIS (STR71X_APB2_BASE + 0x0010) /* 32-bits wide */
-#define STR71X_APB2_SWRES (STR71X_APB2_BASE + 0x0014) /* 32-bits wide */
+/* APB register addresses ***********************************************************/
+
+#define STR71X_APB1_CKDIS (STR71X_APB1_BASE + STR71X_APB_CKDIS_OFFSET)
+#define STR71X_APB1_SWRES (STR71X_APB1_BASE + STR71X_APB_SWRES_OFFSET)
+
+#define STR71X_APB2_CKDIS (STR71X_APB2_BASE + STR71X_APB_CKDIS_OFFSET)
+#define STR71X_APB2_SWRES (STR71X_APB2_BASE + STR71X_APB_SWRES_OFFSET)
/* Register bit settings ***********************************************************/
/* APB1 periperals */
-#define STR71X_APB1_I2C0 (0x0001)
-#define STR71X_APB1_I2C1 (0x0002)
-#define STR71X_APB1_UART0 (0x0008)
-#define STR71X_APB1_UART1 (0x0010)
-#define STR71X_APB1_UART2 (0x0020)
-#define STR71X_APB1_UART3 (0x0040)
-#define STR71X_APB1_USB (0x0080)
-#define STR71X_APB1_CAN (0x0100)
-#define STR71X_APB1_BSPI0 (0x0200)
-#define STR71X_APB1_BSPI1 (0x0400)
-#define STR71X_APB1_HDLC (0x2000)
-#define STR71X_APB1_APB1ALL (0x27fb)
+#define STR71X_APB1_I2C0 (0x0001) /* Bit 0: I2C0 */
+#define STR71X_APB1_I2C1 (0x0002) /* Bit 1: I2C1 */
+#define STR71X_APB1_UART0 (0x0008) /* Bit 3: UART0 */
+#define STR71X_APB1_UART1 (0x0010) /* Bit 4: UART1 */
+#define STR71X_APB1_UART2 (0x0020) /* Bit 5: UART2 */
+#define STR71X_APB1_UART3 (0x0040) /* Bit 6: UART3 */
+#define STR71X_APB1_USB (0x0080) /* Bit 7: USB */
+#define STR71X_APB1_CAN (0x0100) /* Bit 8: CAN */
+#define STR71X_APB1_BSPI0 (0x0200) /* Bit 9: BSPI0 */
+#define STR71X_APB1_BSPI1 (0x0400) /* Bit 10: BSPI1 */
+#define STR71X_APB1_HDLC (0x2000) /* Bit 13: HDLC */
+#define STR71X_APB1_APB1ALL (0x27fb)
/* APB2 Peripherals */
-#define STR71X_APB2_XTI (0x0001)
-#define STR71X_APB2_GPIO0 (0x0004)
-#define STR71X_APB2_GPIO1 (0x0008)
-#define STR71X_APB2_GPIO2 (0x0010)
-#define STR71X_APB2_ADC12 (0x0040)
-#define STR71X_APB2_CKOUT (0x0080)
-#define STR71X_APB2_TIM0 (0x0100)
-#define STR71X_APB2_TIM1 (0x0200)
-#define STR71X_APB2_TIM2 (0x0400)
-#define STR71X_APB2_TIM3 (0x0800)
-#define STR71X_APB2_RTC (0x1000)
-#define STR71X_APB2_EIC (0x4000)
-#define STR71X_APB2_APB2ALL (0x5fdd)
+#define STR71X_APB2_XTI (0x0001) /* Bit 0: XTI */
+#define STR71X_APB2_GPIO0 (0x0004) /* Bit 2: IOPORT0 */
+#define STR71X_APB2_GPIO1 (0x0008) /* Bit 3: IOPORT1 */
+#define STR71X_APB2_GPIO2 (0x0010) /* Bit 4: IOPORT2 */
+#define STR71X_APB2_ADC12 (0x0040) /* Bit 6: ADC */
+#define STR71X_APB2_CKOUT (0x0080) /* Bit 7: CKOUT */
+#define STR71X_APB2_TIM0 (0x0100) /* Bit 8: TIMER0 */
+#define STR71X_APB2_TIM1 (0x0200) /* Bit 9: TIMER1 */
+#define STR71X_APB2_TIM2 (0x0400) /* Bit 10: TIMER2 */
+#define STR71X_APB2_TIM3 (0x0800) /* Bit 11: TIMER3 */
+#define STR71X_APB2_RTC (0x1000) /* Bit 12: RTC */
+#define STR71X_APB2_EIC (0x4000) /* Bit 14: EIC */
+#define STR71X_APB2_APB2ALL (0x5fdd)
/************************************************************************************
* Public Types
diff --git a/nuttx/arch/arm/src/str71x/str71x_decodeirq.c b/nuttx/arch/arm/src/str71x/str71x_decodeirq.c new file mode 100644 index 000000000..b4b3f37b1 --- /dev/null +++ b/nuttx/arch/arm/src/str71x/str71x_decodeirq.c @@ -0,0 +1,123 @@ +/******************************************************************************** + * arch/arm/src/str71x/str71x_decodeirq.c + * + * Copyright (C) 2008 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************/ + +/******************************************************************************** + * Included Files + ********************************************************************************/ + +#include <nuttx/config.h> +#include <sys/types.h> +#include <nuttx/irq.h> +#include <nuttx/arch.h> +#include <assert.h> +#include <debug.h> + +#include "up_arch.h" +#include "os_internal.h" +#include "up_internal.h" +#include "chip.h" + +/******************************************************************************** + * Definitions + ********************************************************************************/ + +/******************************************************************************** + * Private Types + ********************************************************************************/ + +/******************************************************************************** + * Public Data + ********************************************************************************/ + +/******************************************************************************** + * Private Data + ********************************************************************************/ + +/******************************************************************************** + * Private Functions + ********************************************************************************/ + +/******************************************************************************** + * Public Funstions + ********************************************************************************/ + +/******************************************************************************** + * up_decodeirq() + * + * Description: + * Read the IRQ number from the IVR register. During intialization, the IVR + * register was set to zero. Each SIR[n] register was programmed to contain + * the IRQ number. At IRQ processing time (when this function run), the IVR + * should contain the desired IRQ number. + * + ********************************************************************************/ + +void up_decodeirq(uint32 *regs) +{ +#ifdef CONFIG_SUPPRESS_INTERRUPTS + lib_lowprintf("Unexpected IRQ\n"); + current_regs = regs; + PANIC(OSERR_ERREXCEPTION); +#else + /* Read the IRQ number from the IVR register */ + + unsigned int irq = getreq32(STR71X_EIC_IVR_OFFSET); + + /* Verify that the resulting IRQ number is valid */ + + if (irq < NR_IRQS) + { + /* Current regs non-zero indicates that we are processing an interrupt; + * current_regs is also used to manage interrupt level context switches. + */ + + current_regs = regs; + + /* Deliver the IRQ */ + + irq_dispatch(irq, regs); + + /* Indicate that we are no long in an interrupt handler */ + + current_regs = NULL; + } +#if CONFIG_DEBUG + else + { + PANIC(OSERR_ERREXCEPTION); /* Normally never happens */ + } +#endif +#endif +} diff --git a/nuttx/arch/arm/src/str71x/str71x_eic.h b/nuttx/arch/arm/src/str71x/str71x_eic.h index 32b1fd91d..c777b5f13 100644 --- a/nuttx/arch/arm/src/str71x/str71x_eic.h +++ b/nuttx/arch/arm/src/str71x/str71x_eic.h @@ -48,50 +48,97 @@ * Definitions
************************************************************************************/
+/* Enhanced Interupt Controller (EIC) register offsets ******************************/
+
+#define STR71X_EIC_ICR_OFFSET (0x0000) /* 32-bits wide */
+#define STR71X_EIC_CICR_OFFSET (0x0004) /* 32-bits wide */
+#define STR71X_EIC_CIPR_OFFSET (0x0008) /* 32-bits wide */
+#define STR71X_EIC_IVR_OFFSET (0x0018) /* 32-bits wide */
+#define STR71X_EIC_FIR_OFFSET (0x001c) /* 32-bits wide */
+#define STR71X_EIC_IER_OFFSET (0x0020) /* 32-bits wide */
+#define STR71X_EIC_IPR_OFFSET (0x0040) /* 32-bits wide */
+
+#define STR71X_EIC_SIR_OFFSET (0x0060) /* 32 x 32-bits */
+#define STR71X_EIC_SIR0_OFFSET (0x0060) /* 32-bits wide */
+#define STR71X_EIC_SIR1_OFFSET (0x0064) /* 32-bits wide */
+#define STR71X_EIC_SIR2_OFFSET (0x0068) /* 32-bits wide */
+#define STR71X_EIC_SIR3_OFFSET (0x006c) /* 32-bits wide */
+#define STR71X_EIC_SIR4_OFFSET (0x0070) /* 32-bits wide */
+#define STR71X_EIC_SIR5_OFFSET (0x0074) /* 32-bits wide */
+#define STR71X_EIC_SIR6_OFFSET (0x0078) /* 32-bits wide */
+#define STR71X_EIC_SIR7_OFFSET (0x007c) /* 32-bits wide */
+#define STR71X_EIC_SIR8_OFFSET (0x0080) /* 32-bits wide */
+#define STR71X_EIC_SIR9_OFFSET (0x0084) /* 32-bits wide */
+#define STR71X_EIC_SIR10_OFFSET (0x0088) /* 32-bits wide */
+#define STR71X_EIC_SIR11_OFFSET (0x008c) /* 32-bits wide */
+#define STR71X_EIC_SIR12_OFFSET (0x0090) /* 32-bits wide */
+#define STR71X_EIC_SIR13_OFFSET (0x0094) /* 32-bits wide */
+#define STR71X_EIC_SIR14_OFFSET (0x0098) /* 32-bits wide */
+#define STR71X_EIC_SIR15_OFFSET (0x009c) /* 32-bits wide */
+#define STR71X_EIC_SIR16_OFFSET (0x00a0) /* 32-bits wide */
+#define STR71X_EIC_SIR17_OFFSET (0x00a4) /* 32-bits wide */
+#define STR71X_EIC_SIR18_OFFSET (0x00a8) /* 32-bits wide */
+#define STR71X_EIC_SIR19_OFFSET (0x00ac) /* 32-bits wide */
+#define STR71X_EIC_SIR20_OFFSET (0x00b0) /* 32-bits wide */
+#define STR71X_EIC_SIR21_OFFSET (0x00b4) /* 32-bits wide */
+#define STR71X_EIC_SIR22_OFFSET (0x00b8) /* 32-bits wide */
+#define STR71X_EIC_SIR23_OFFSET (0x00bc) /* 32-bits wide */
+#define STR71X_EIC_SIR24_OFFSET (0x00c0) /* 32-bits wide */
+#define STR71X_EIC_SIR25_OFFSET (0x00c4) /* 32-bits wide */
+#define STR71X_EIC_SIR26_OFFSET (0x00c8) /* 32-bits wide */
+#define STR71X_EIC_SIR27_OFFSET (0x00cc) /* 32-bits wide */
+#define STR71X_EIC_SIR28_OFFSET (0x00d0) /* 32-bits wide */
+#define STR71X_EIC_SIR29_OFFSET (0x00d4) /* 32-bits wide */
+#define STR71X_EIC_SIR30_OFFSET (0x00d8) /* 32-bits wide */
+#define STR71X_EIC_SIR31_OFFSET (0x00dc) /* 32-bits wide */
+
+#define STR71X_EIC_NCHANNELS (32)
+#define STR71X_EIC_SIR_BASE ((STR71X_EIC_BASE + STR71X_EIC_SIR_OFFSET)
+
/* Enhanced Interupt Controller (EIC) registers *************************************/
-#define STR71X_EIC_ICR (STR71X_EIC_BASE + 0x0000) /* 32-bits wide */
-#define STR71X_EIC_CICR (STR71X_EIC_BASE + 0x0004) /* 32-bits wide */
-#define STR71X_EIC_CIPR (STR71X_EIC_BASE + 0x0008) /* 32-bits wide */
-#define STR71X_EIC_IVR (STR71X_EIC_BASE + 0x0018) /* 32-bits wide */
-#define STR71X_EIC_FIR (STR71X_EIC_BASE + 0x001c) /* 32-bits wide */
-#define STR71X_EIC_IER0 (STR71X_EIC_BASE + 0x0020) /* 32-bits wide */
-#define STR71X_EIC_IPR0 (STR71X_EIC_BASE + 0x0040) /* 32-bits wide */
-
-#define STR71X_EIC_SIR(n) (STR71X_EIC_BASE + 0x0060 + ((n) << 2))
-
-#define STR71X_EIC_SIR0 (STR71X_EIC_BASE + 0x0060) /* 32-bits wide */
-#define STR71X_EIC_SIR1 (STR71X_EIC_BASE + 0x0064) /* 32-bits wide */
-#define STR71X_EIC_SIR2 (STR71X_EIC_BASE + 0x0068) /* 32-bits wide */
-#define STR71X_EIC_SIR3 (STR71X_EIC_BASE + 0x006c) /* 32-bits wide */
-#define STR71X_EIC_SIR4 (STR71X_EIC_BASE + 0x0070) /* 32-bits wide */
-#define STR71X_EIC_SIR5 (STR71X_EIC_BASE + 0x0074) /* 32-bits wide */
-#define STR71X_EIC_SIR6 (STR71X_EIC_BASE + 0x0078) /* 32-bits wide */
-#define STR71X_EIC_SIR7 (STR71X_EIC_BASE + 0x007c) /* 32-bits wide */
-#define STR71X_EIC_SIR8 (STR71X_EIC_BASE + 0x0080) /* 32-bits wide */
-#define STR71X_EIC_SIR9 (STR71X_EIC_BASE + 0x0084) /* 32-bits wide */
-#define STR71X_EIC_SIR10 (STR71X_EIC_BASE + 0x0088) /* 32-bits wide */
-#define STR71X_EIC_SIR11 (STR71X_EIC_BASE + 0x008c) /* 32-bits wide */
-#define STR71X_EIC_SIR12 (STR71X_EIC_BASE + 0x0090) /* 32-bits wide */
-#define STR71X_EIC_SIR13 (STR71X_EIC_BASE + 0x0094) /* 32-bits wide */
-#define STR71X_EIC_SIR14 (STR71X_EIC_BASE + 0x0098) /* 32-bits wide */
-#define STR71X_EIC_SIR15 (STR71X_EIC_BASE + 0x009c) /* 32-bits wide */
-#define STR71X_EIC_SIR16 (STR71X_EIC_BASE + 0x00a0) /* 32-bits wide */
-#define STR71X_EIC_SIR17 (STR71X_EIC_BASE + 0x00a4) /* 32-bits wide */
-#define STR71X_EIC_SIR18 (STR71X_EIC_BASE + 0x00a8) /* 32-bits wide */
-#define STR71X_EIC_SIR19 (STR71X_EIC_BASE + 0x00ac) /* 32-bits wide */
-#define STR71X_EIC_SIR20 (STR71X_EIC_BASE + 0x00b0) /* 32-bits wide */
-#define STR71X_EIC_SIR21 (STR71X_EIC_BASE + 0x00b4) /* 32-bits wide */
-#define STR71X_EIC_SIR22 (STR71X_EIC_BASE + 0x00b8) /* 32-bits wide */
-#define STR71X_EIC_SIR23 (STR71X_EIC_BASE + 0x00bc) /* 32-bits wide */
-#define STR71X_EIC_SIR24 (STR71X_EIC_BASE + 0x00c0) /* 32-bits wide */
-#define STR71X_EIC_SIR25 (STR71X_EIC_BASE + 0x00c4) /* 32-bits wide */
-#define STR71X_EIC_SIR26 (STR71X_EIC_BASE + 0x00c8) /* 32-bits wide */
-#define STR71X_EIC_SIR27 (STR71X_EIC_BASE + 0x00cc) /* 32-bits wide */
-#define STR71X_EIC_SIR28 (STR71X_EIC_BASE + 0x00d0) /* 32-bits wide */
-#define STR71X_EIC_SIR29 (STR71X_EIC_BASE + 0x00d4) /* 32-bits wide */
-#define STR71X_EIC_SIR30 (STR71X_EIC_BASE + 0x00d8) /* 32-bits wide */
-#define STR71X_EIC_SIR31 (STR71X_EIC_BASE + 0x00dc) /* 32-bits wide */
+#define STR71X_EIC_ICR (STR71X_EIC_BASE + STR71X_EIC_ICR_OFFSET)
+#define STR71X_EIC_CICR (STR71X_EIC_BASE + STR71X_EIC_CICR_OFFSET)
+#define STR71X_EIC_CIPR (STR71X_EIC_BASE + STR71X_EIC_CIPR_OFFSET)
+#define STR71X_EIC_IVR (STR71X_EIC_BASE + STR71X_EIC_IVR_OFFSET)
+#define STR71X_EIC_FIR (STR71X_EIC_BASE + STR71X_EIC_FIR_OFFSET)
+#define STR71X_EIC_IER (STR71X_EIC_BASE + STR71X_EIC_IER_OFFSET)
+#define STR71X_EIC_IPR (STR71X_EIC_BASE + STR71X_EIC_IPR_OFFSET)
+
+#define STR71X_EIC_SIR(n) (STR71X_EIC_SIR_BASE + ((n) << 2))
+
+#define STR71X_EIC_SIR0 (STR71X_EIC_BASE + STR71X_EIC_SIR0_OFFSET)
+#define STR71X_EIC_SIR1 (STR71X_EIC_BASE + STR71X_EIC_SIR1_OFFSET)
+#define STR71X_EIC_SIR2 (STR71X_EIC_BASE + STR71X_EIC_SIR2_OFFSET)
+#define STR71X_EIC_SIR3 (STR71X_EIC_BASE + STR71X_EIC_SIR3_OFFSET)
+#define STR71X_EIC_SIR4 (STR71X_EIC_BASE + STR71X_EIC_SIR4_OFFSET)
+#define STR71X_EIC_SIR5 (STR71X_EIC_BASE + STR71X_EIC_SIR5_OFFSET)
+#define STR71X_EIC_SIR6 (STR71X_EIC_BASE + STR71X_EIC_SIR6_OFFSET)
+#define STR71X_EIC_SIR7 (STR71X_EIC_BASE + STR71X_EIC_SIR7_OFFSET)
+#define STR71X_EIC_SIR8 (STR71X_EIC_BASE + STR71X_EIC_SIR8_OFFSET)
+#define STR71X_EIC_SIR9 (STR71X_EIC_BASE + STR71X_EIC_SIR9_OFFSET)
+#define STR71X_EIC_SIR10 (STR71X_EIC_BASE + STR71X_EIC_SIR10_OFFSET)
+#define STR71X_EIC_SIR11 (STR71X_EIC_BASE + STR71X_EIC_SIR11_OFFSET)
+#define STR71X_EIC_SIR12 (STR71X_EIC_BASE + STR71X_EIC_SIR12_OFFSET)
+#define STR71X_EIC_SIR13 (STR71X_EIC_BASE + STR71X_EIC_SIR13_OFFSET)
+#define STR71X_EIC_SIR14 (STR71X_EIC_BASE + STR71X_EIC_SIR14_OFFSET)
+#define STR71X_EIC_SIR15 (STR71X_EIC_BASE + STR71X_EIC_SIR15_OFFSET)
+#define STR71X_EIC_SIR16 (STR71X_EIC_BASE + STR71X_EIC_SIR16_OFFSET)
+#define STR71X_EIC_SIR17 (STR71X_EIC_BASE + STR71X_EIC_SIR17_OFFSET)
+#define STR71X_EIC_SIR18 (STR71X_EIC_BASE + STR71X_EIC_SIR18_OFFSET)
+#define STR71X_EIC_SIR19 (STR71X_EIC_BASE + STR71X_EIC_SIR19_OFFSET)
+#define STR71X_EIC_SIR20 (STR71X_EIC_BASE + STR71X_EIC_SIR20_OFFSET)
+#define STR71X_EIC_SIR21 (STR71X_EIC_BASE + STR71X_EIC_SIR21_OFFSET)
+#define STR71X_EIC_SIR22 (STR71X_EIC_BASE + STR71X_EIC_SIR22_OFFSET)
+#define STR71X_EIC_SIR23 (STR71X_EIC_BASE + STR71X_EIC_SIR23_OFFSET)
+#define STR71X_EIC_SIR24 (STR71X_EIC_BASE + STR71X_EIC_SIR24_OFFSET)
+#define STR71X_EIC_SIR25 (STR71X_EIC_BASE + STR71X_EIC_SIR25_OFFSET)
+#define STR71X_EIC_SIR26 (STR71X_EIC_BASE + STR71X_EIC_SIR26_OFFSET)
+#define STR71X_EIC_SIR27 (STR71X_EIC_BASE + STR71X_EIC_SIR27_OFFSET)
+#define STR71X_EIC_SIR28 (STR71X_EIC_BASE + STR71X_EIC_SIR28_OFFSET)
+#define STR71X_EIC_SIR29 (STR71X_EIC_BASE + STR71X_EIC_SIR29_OFFSET)
+#define STR71X_EIC_SIR30 (STR71X_EIC_BASE + STR71X_EIC_SIR30_OFFSET)
+#define STR71X_EIC_SIR31 (STR71X_EIC_BASE + STR71X_EIC_SIR31_OFFSET)
/* Register bit settings ************************************************************/
diff --git a/nuttx/arch/arm/src/str71x/str71x_emi.h b/nuttx/arch/arm/src/str71x/str71x_emi.h index 0bb0be5cc..27972c5b4 100644 --- a/nuttx/arch/arm/src/str71x/str71x_emi.h +++ b/nuttx/arch/arm/src/str71x/str71x_emi.h @@ -48,49 +48,45 @@ * Definitions
************************************************************************************/
-/* External Memory Interfac (EMI) registers *****************************************/
+/* External Memory Interfac (EMI) register offset ***********************************/
-#define STR71X_EMI_BCON0 (STR71X_EMI_BASE + 0x0000) /* 16-bits wide */
-#define STR71X_EMI_BCON1 (STR71X_EMI_BASE + 0x0004) /* 16-bits wide */
-#define STR71X_EMI_BCON2 (STR71X_EMI_BASE + 0x0008) /* 16-bits wide */
-#define STR71X_EMI_BCON3 (STR71X_EMI_BASE + 0x000c) /* 16-bits wide */
+#define STR71X_EMI_BCON0_OFFSET (0x0000) /* 16-bits wide */
+#define STR71X_EMI_BCON1_OFFSET (0x0004) /* 16-bits wide */
+#define STR71X_EMI_BCON2_OFFSET (0x0008) /* 16-bits wide */
+#define STR71X_EMI_BCON3_OFFSET (0x000c) /* 16-bits wide */
-/* Register bit settings ***********************************************************/
-
-/* EMI enable */
-
-#define STR71X_EMI_ENABLE (0x8000)
-
-/* Banks */
+/* External Memory Interfac (EMI) register addresses ********************************/
-#define STR71X_EMI_BANK0 (0x00)
-#define STR71X_EMI_BANK1 (0x01)
-#define STR71X_EMI_BANK2 (0x02)
-#define STR71X_EMI_BANK3 (0x03)
+#define STR71X_EMI_BCON0 (STR71X_EMI_BASE + STR71X_EMI_BCON0_OFFSET)
+#define STR71X_EMI_BCON1 (STR71X_EMI_BASE + STR71X_EMI_BCON1_OFFSET)
+#define STR71X_EMI_BCON2 (STR71X_EMI_BASE + STR71X_EMI_BCON2_OFFSET)
+#define STR71X_EMI_BCON3 (STR71X_EMI_BASE + STR71X_EMI_BCON3_OFFSET)
-/* EMI data bus length */
-
-#define STR71X_EMI_SIZE8 (0x0000)
-#define STR71X_EMI_SIZE16 (0x0001)
-
-/* Number of wait states */
+/* Register bit settings ***********************************************************/
-#define STR71X_EMI_0WaitState (0x00)
-#define STR71X_EMI_1WaitState (0x01)
-#define STR71X_EMI_2WaitStates (0x02)
-#define STR71X_EMI_3WaitStates (0x03)
-#define STR71X_EMI_4WaitStates (0x04)
-#define STR71X_EMI_5WaitStates (0x05)
-#define STR71X_EMI_6WaitStates (0x06)
-#define STR71X_EMI_7WaitStates (0x07)
-#define STR71X_EMI_8WaitStates (0x08)
-#define STR71X_EMI_9WaitStates (0x09)
-#define STR71X_EMI_10WaitStates (0x0a)
-#define STR71X_EMI_11WaitStates (0x0b)
-#define STR71X_EMI_12WaitStates (0x0c)
-#define STR71X_EMI_13WaitStates (0x0d)
-#define STR71X_EMI_14WaitStates (0x0e)
-#define STR71X_EMI_15WaitStates (0x0f)
+/* Bank-N configuration register (BCONn) bit definitions */
+
+#define STR71X_EMIBCON_BSIZEMASK (0x0003) /* Bits 0-1: Bank size */
+#define STR71X_EMIBCON_BSIZE8 (0x0000) /* 8-bit */
+#define STR71X_EMIBCON_BSIZE16 (0x0001) /* 16-bit */
+#define STR71X_EMIBCON_WSMASK (0x003c) /* Bits 2-5: Wait states */
+#define STR71X_EMIBCON_WS0 (0x0000) /* 0 waitstates */
+#define STR71X_EMIBCON_WS1 (0x0004) /* 1 waitstates */
+#define STR71X_EMIBCON_WS2 (0x0008) /* 2 waitstates */
+#define STR71X_EMIBCON_WS3 (0x000c) /* 3 waitstates */
+#define STR71X_EMIBCON_WS4 (0x0010) /* 4 waitstates */
+#define STR71X_EMIBCON_WS5 (0x0014) /* 5 waitstates */
+#define STR71X_EMIBCON_WS6 (0x0018) /* 6 waitstates */
+#define STR71X_EMIBCON_WS7 (0x001c) /* 7 waitstates */
+#define STR71X_EMIBCON_WS8 (0x0020) /* 8 waitstates */
+#define STR71X_EMIBCON_WS9 (0x0024) /* 9 waitstates */
+#define STR71X_EMIBCON_WS10 (0x0028) /* 10 waitstates */
+#define STR71X_EMIBCON_WS11 (0x002c) /* 11 waitstates */
+#define STR71X_EMIBCON_WS12 (0x0030) /* 12 waitstates */
+#define STR71X_EMIBCON_WS13 (0x0034) /* 13 waitstates */
+#define STR71X_EMIBCON_WS14 (0x0038) /* 14 waitstates */
+#define STR71X_EMIBCON_WS15 (0x003c) /* 15 waitstates */
+#define STR71X_EMIBCON_ENABLE (0x8000) /* Bit 15: Bank enable */
/************************************************************************************
* Public Types
diff --git a/nuttx/arch/arm/src/str71x/str71x_gpio.h b/nuttx/arch/arm/src/str71x/str71x_gpio.h index 78680a17d..99f2e6f35 100644 --- a/nuttx/arch/arm/src/str71x/str71x_gpio.h +++ b/nuttx/arch/arm/src/str71x/str71x_gpio.h @@ -48,26 +48,21 @@ * Definitions
************************************************************************************/
-/* GPIO registers *******************************************************************/
+/* GPIO register offsets ************************************************************/
-#define STR71X_GPIO_PC0 (STR71X_GPIO_BASE + 0x0000) /* 16-bits wide */
-#define STR71X_GPIO_PC1 (STR71X_GPIO_BASE + 0x0004) /* 16-bits wide */
-#define STR71X_GPIO_PC2 (STR71X_GPIO_BASE + 0x0008) /* 16-bits wide */
-#define STR71X_GPIO_PD (STR71X_GPIO_BASE + 0x000c) /* 16-bits wide */
+#define STR71X_GPIO_PC0_OFFSET (0x0000) /* 16-bits wide */
+#define STR71X_GPIO_PC1_OFFSET (0x0004) /* 16-bits wide */
+#define STR71X_GPIO_PC2_OFFSET (0x0008) /* 16-bits wide */
+#define STR71X_GPIO_PD_OFFSET (0x000c) /* 16-bits wide */
-/* Register bit settings ************************************************************/
+/* GPIO register addresses **********************************************************/
-#define STR71X_GPIO_HIAINTRI (0) /* High impedance analog input tristate */
-#define STR71X_GPIO_INTRITTL (1) /* Tristate ttl input */
-#define STR71X_GPIO_INTRICMOS (2) /* Tristate cmos input */
-#define STR71X_GPIO_IPUPDWP (3) /* Pull-up/pull-down weak push pull input */
-#define STR71X_GPIO_OUTOD (4) /* Open drain output */
-#define STR71X_GPIO_OUTPP (5) /* Push pull output */
-#define STR71X_GPIO_AFOD (6) /* Open drain output alternate function */
-#define STR71X_GPIO_AFPP (7) /* Push-pull output alternate function */
+#define STR71X_GPIO_PC0 (STR71X_GPIO_BASE + STR71X_GPIO_PC0_OFFSET)
+#define STR71X_GPIO_PC1 (STR71X_GPIO_BASE + STR71X_GPIO_PC1_OFFSET)
+#define STR71X_GPIO_PC2 (STR71X_GPIO_BASE + STR71X_GPIO_PC2_OFFSET)
+#define STR71X_GPIO_PD (STR71X_GPIO_BASE + STR71X_GPIO_PD_OFFSET)
-#define STR71X_GPIO_LSB (0x00)
-#define STR71X_GPIO_MSB (0x08)
+/* Register bit settings ************************************************************/
/************************************************************************************
* Public Types
diff --git a/nuttx/arch/arm/src/str71x/str71x_head.S b/nuttx/arch/arm/src/str71x/str71x_head.S new file mode 100644 index 000000000..6f2b2892e --- /dev/null +++ b/nuttx/arch/arm/src/str71x/str71x_head.S @@ -0,0 +1,667 @@ +/***************************************************************************** + * arch/arm/src/str71x/str71x_head.S + * + * Copyright (C) 2008 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +/***************************************************************************** + * Included Files + *****************************************************************************/ + +#include <nuttx/config.h> /* NuttX configuration settings */ +#include <arch/board/board.h> /* Board-specific settings */ +#include "arm.h" /* ARM-specific settings */ +#include "chip.h" /* Chip-specific settings */ +#include "up_internal.h" +#include "up_arch.h" + +/***************************************************************************** + * Definitions + *****************************************************************************/ + +/* This file holds the NuttX start logic that runs when the STR711 + * is reset. This logic must be located at address 0x0000:0000 in + * flash but may be linked to run at different locations based on + * the selected mode: + * + * default: Executes from 0x0000:0000. In non-default modes, the + * MEMAP register is set override the settings of the CPU configuration + * pins. + * + * CONFIG_EXTMEM_MODE: Code executes from external memory starting at + * address 0x6000:0000. + * + * CONFIG_RAM_MODE: Code executes from on-chip RAM at address + * 0x2000:0000. + * + * Starupt Code must be linked to run at the correct address + * corresponding to the selected mode. + */ + +#if defined(CONFIG_EXTMEM_MODE) +# if CONFIG_CODE_BASE != STR71X_EXTMEM_BASE +# error "CONFIG_CODE_BASE must be 0x60000000 in EXTMEM mode" +# endif +#elif defined(CONFIG_RAM_MODE) +# if CONFIG_CODE_BASE != STR71X_ONCHIP_RAM_BASE +# error "CONFIG_CODE_BASE must be 0x20000000 in EXTMEM mode" +# endif +#else +# if CONFIG_CODE_BASE != STR71X_FLASH_BASE +# error "CONFIG_CODE_BASE must be 0x00000000 in default mode" +# endif +#endif + +/***************************************************************************** + * Macros + *****************************************************************************/ + +/***************************************************************************** + * Name: showprogress + * + * Description: + * Print a character on the UART to show boot status. This macro will + * modify r0, r1, r2 and r14 + * + *****************************************************************************/ + + .macro showprogress, code +#ifdef CONFIG_DEBUG + mov r0, #\code + bl up_lowputc +#endif + .endm + +/***************************************************************************** + * Name: emiinit + * + * Description: + * Initialize external memory banks 0-3 as configured + * + *****************************************************************************/ + + .macro emiinit, base, value +#if defined(CONFIG_STR71X_BANK0) || defined(CONFIG_STR71X_BANK1) || \ + defined(CONFIG_STR71X_BANK2) || defined(CONFIG_STR71X_BANK3) + + /* In order to use the external memory, certain GPIO pins must be + * configured in the alternate function: + * + * GPIO ALT Description + * P2.0-3 CS.0-3 External memory chip select for banks 0,1,3,4 + * P2.4-7 A.20-23 External memory extended address bus (needed for + * address space > 1Mb) + */ + +#ifdef CONFIG_STR71X_BIGEXTMEM +# define EXTMEM_GPIO_BITSET 0x000000ff /* P2.0-7 */ +#else +# define EXTMEM_GPIO_BITSET 0x0000000f /* P2.0-3 */ +#endif + + ldr \base, =STR71X_GPIO_BASE ; Configure P2.0 to P2.3/7 in AF_PP mode + ldr \value, [\base, #STR71X_GPIO_PC0_OFFSET] + orr \value, \value, #EXTMEM_GPIO_BITSET + str \value, [\base, #STR71X_GPIO_PC0_OFFSET] + ldr \value, [\base, #STR71X_GPIO_PC1_OFFSET] + orr \value, \value, #EXTMEM_GPIO_BITSET + str \value, [\base, #STR71X_GPIO_PC1_OFFSET] + ldr \value, [\base, #STR71X_GPIO_PC2_OFFSET] + orr \value, \value, #EXTMEM_GPIO_BITSET + str \value, [\base, #STR71X_GPIO_PC2_OFFSET] + + /* Enable bank 0 */ + + ldr \base, =STR71X_EMI_BASE + +#ifdef CONFIG_STR71X_BANK0 + + /* Get the bank 0 size */ + +# if CONFIG_STR71X_BANK0_SIZE == 8 +# define EXTMEM_BANK0_SIZE STR71X_EMIBCON_BSIZE8 +# elif CONFIG_STR71X_BANK0_SIZE == 16 +# define EXTMEM_BANK0_SIZE STR71X_EMIBCON_BSIZE16 +# else +# error "CONFIG_STR71X_BANK0_SIZE invalid" +# endif + + /* Get the bank 0 waitstates */ + +# if !defined(CONFIG_STR71X_BANK0_WAITSTATES) || \ + CONFIG_STR71X_BANK0_WAITSTATES < 0 || CONFIG_STR71X_BANK0_WAITSTATES > 15 +# error "CONFIG_STR71X_BANK0_WAITSTATES invalid" +# else + /* Bits 2-5: wait states */ +# define EXTMEM_BANK0_WAITSTATES (CONFIG_STR71X_BANK0_WAITSTATES << 2) +# endif + + ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK0_WAITSTATES|EXTMEM_BANK0_SIZE) +#else + mov \value, #0 +#endif + str \value, [\base, #STR71X_EMI_BCON0_OFFSET] + + /* Enable bank 1 */ + +#ifdef CONFIG_STR71X_BANK1 + + /* Get the bank 1 size */ + +# if CONFIG_STR71X_BANK1_SIZE == 8 +# define EXTMEM_BANK1_SIZE STR71X_EMIBCON_BSIZE8 +# elif CONFIG_STR71X_BANK1_SIZE == 16 +# define EXTMEM_BANK1_SIZE STR71X_EMIBCON_BSIZE16 +# else +# error "CONFIG_STR71X_BANK1_SIZE invalid" +# endif + + /* Get the bank 1 waitstates */ + +# if !defined(CONFIG_STR71X_BANK1_WAITSTATES) || \ + CONFIG_STR71X_BANK1_WAITSTATES < 0 || CONFIG_STR71X_BANK1_WAITSTATES > 15 +# error "CONFIG_STR71X_BANK1_WAITSTATES invalid" +# else + /* Bits 2-5: wait states */ +# define EXTMEM_BANK1_WAITSTATES (CONFIG_STR71X_BANK1_WAITSTATES << 2) +# endif + + ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK1_WAITSTATES|EXTMEM_BANK1_SIZE) +#else + mov \value, #0 +#endif + str \value, [\base, #STR71X_EMI_BCON1_OFFSET] + + /* Enable bank 2 */ + +#ifdef CONFIG_STR71X_BANK2 + + /* Get the bank 2 size */ + +# if CONFIG_STR71X_BANK2_SIZE == 8 +# define EXTMEM_BANK2_SIZE STR71X_EMIBCON_BSIZE8 +# elif CONFIG_STR71X_BANK2_SIZE == 16 +# define EXTMEM_BANK2_SIZE STR71X_EMIBCON_BSIZE16 +# else +# error "CONFIG_STR71X_BANK2_SIZE invalid" +# endif + + /* Get the bank 2 waitstates */ + +# if !defined(CONFIG_STR71X_BANK2_WAITSTATES) || \ + CONFIG_STR71X_BANK2_WAITSTATES < 2 || CONFIG_STR71X_BANK2_WAITSTATES > 15 +# error "CONFIG_STR71X_BANK2_WAITSTATES invalid" +# else + /* Bits 2-5: wait states */ +# define EXTMEM_BANK2_WAITSTATES (CONFIG_STR71X_BANK2_WAITSTATES << 2) +# endif + + ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK2_WAITSTATES|EXTMEM_BANK2_SIZE) +#else + mov \value, #0 +#endif + str \value, [\base, #STR71X_EMI_BCON2_OFFSET] + + /* Enable bank 3 */ + +#ifdef CONFIG_STR71X_BANK3 + + /* Get the bank 3 size */ + +# if CONFIG_STR71X_BANK3_SIZE == 8 +# define EXTMEM_BANK3_SIZE STR71X_EMIBCON_BSIZE8 +# elif CONFIG_STR71X_BANK3_SIZE == 16 +# define EXTMEM_BANK3_SIZE STR71X_EMIBCON_BSIZE16 +# else +# error "CONFIG_STR71X_BANK3_SIZE invalid" +# endif + + /* Get the bank 3 waitstates */ + +# if !defined(CONFIG_STR71X_BANK3_WAITSTATES) || \ + CONFIG_STR71X_BANK3_WAITSTATES < 3 || CONFIG_STR71X_BANK3_WAITSTATES > 15 +# error "CONFIG_STR71X_BANK3_WAITSTATES invalid" +# else + /* Bits 2-5: wait states */ +# define EXTMEM_BANK3_WAITSTATES (CONFIG_STR71X_BANK3_WAITSTATES << 2) +# endif + + ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK3_WAITSTATES|EXTMEM_BANK3_SIZE) +#else + mov \value, #0 +#endif + str \value, [\base, #STR71X_EMI_BCON3_OFFSET] +#endif + .endm + +/***************************************************************************** + * Name: eicinit + * + * Description: + * The EIC is initialized for use with NuttX. This initialization does not + * take advantage of the high performance capabilities of the EIC. Instead, + * The EIC is only used to to provide NuttX IRQ numbers. Here is what is + * done: + * + * IRQs and FIQs are disabled + * IVR set to zero + * All channels are disabled + * Channels set to priority 0 + * All SIR[n] registers contain the NuttX IRQ number in the MS 16-bits + * + * At the time of IRQ processing, the IVR will contain the decoded IRQ + * number needed by NuttX. + * + *****************************************************************************/ + + .macro eicinit, eicbase, value, irqno, offset + /* Disable and clear all interrupts */ + + ldr \eicbase, =STR71X_EIC_BASE + + /* Disable FIQ and IRQ */ + + mov \value, #0 + str \value, [\eicbase, #STR71X_EIC_ICR_OFFSET] + + /* Disable all channel interrupts */ + + str \value, [\eicbase, #STR71X_EIC_IER_OFFSET] + + /* Clear all pending IRQs */ + + ldr \value, =0xffffffff + str \value, [\eicbase, #STR71X_EIC_IPR_OFFSET] + + /* Disable FIQ channels/clear pending FIQs */ + + mov \value, #0x0c + str \value, [\eicbase, #STR71X_EIC_FIR_OFFSET] + + /* Reset the current priority register */ + + mov \value, #0 + str \value, [\eicbase, #STR71X_EIC_CIPR_OFFSET] + + /* Zero IVR 31:16 */ + + str \value, [\eicbase, STR71X_EIC_IVR_OFFSET] + + /* Set up the loop to initialize each SIR register. Start + * with IRQ number 0 and SIR0 + */ + + mov \irqno, #0 + ldr \offset, =STR71X_EIC_SIR_OFFSET + + /* Then loop for each EIC channel */ +eicloop: + /* Shift the IRQ number to bits 16-31 and save the shifted IRQ + * number as SIR[irqno]. This will appear as bits 0:15 in the + * IVR during IRQ processing. + */ + + mov \value, \irqno, lsl #16 + str \value, [\eicbase, \offset] + + /* Increment the offset to the next SIR register and inrement + * the IRQ number. + */ + + add \offset, \offset, #4 + add \irqno, \irqno, #1 + + /* Continue to loop until all of the SIR registers have been + * intialized. + */ + + cmp \irqno, #STR71X_EIC_NCHANNELS + blt eicloop + .endm + +/***************************************************************************** + * Name: periphinit + * + * Description" + * Disable all perfipherals (except EIC) + * + *****************************************************************************/ + + .macro periphinit, value, base1, base2 +#ifndef CONFIG_STR71X_DISABLE_PERIPHINIT + /* Set up APB1 and APB2 addresses */ + + ldr \base1, =STR71X_APB1_BASE + ldr \base2, =STR71X_APB2_BASE + + /* Disable all APB1 peripherals */ + + ldr \value, =STR71X_APB1_APB1ALL + strh \value, [\base1, #STR71X_APB_CKDIS_OFFSET] + + /* Disable all(or most) APB1 peripherals */ +#if 1 /* See below */ + ldr \value, =(STR71X_APB2_APB2ALL & ~STR71X_APB2_EIC) +#else + ldr \value, =STR71X_APB2_APB2ALL +#endif + strh \value, [\base2, #STR71X_APB_CKDIS_OFFSET] + + /* Reset and enable peripherals */ +#if 0 + /* Hold all APB1 and APB2 peripherals under reset */ + + ldr \value, =STR71X_APB1_APB1ALL + strh \value, [\base1, #STR71X_APB_SWRES_OFFSET] + ldr \value, =STR71X_APB2_APB2ALL + strh \value, [\base2, #STR71X_APB_SWRES_OFFSET] + + /* Wait that the selected macrocells exit from reset */ + + mov \value, #10 +loop1: subs \value, \value, #1 + bne loop1 + + /* Release APB1 and APB2 peripherals from reset */ + + mov \value, #0 + strh \value, [\base1, #STR71X_APB_SWRES_OFFSET] + strh \value, [\base2, #STR71X_APB_SWRES_OFFSET] + + /* Enable clocking for all APB1 and APB2 peripherals */ + + strh \value, [\base1, #STR71X_APB_CKDIS_OFFSET] + strh \value, [\base2, #STR71X_APB_CKDIS_OFFSET]; + + /* Wait that the selected macrocells exit from reset */ + + mov \value, #10 +loop2: subs \value, \value, #1 + bne loop2 +#endif + + /* Allow EMI and USB */ + + ldr \base1, =STR71X_RCCU_BASE + ldr \value, =(STR71X_RCCUPER_EMI|STR71X_RCCUPER_USBKERNEL) + strh \value, [\base1, #STR71X_RCCU_PER_OFFSET] +#endif + .endm + +/***************************************************************************** + * Name: remap + * + * Description: + * Remap memory at address 0x0000000 to either FLASH. The system always + * boots at Bank0, sector 0 of FLASH. Part of the initial setup will be to + * map the memory appropriately for the execution configuration. Various + * options are possible, but only boot from FLASH is currently supported. + * + *****************************************************************************/ + + .macro remap, base, value + /* Read the PCU BOOTCR register */ + + ldr \base, =STR71X_PCU_BASE + ldrh \value, [\base, #STR71X_PCU_BOOTCR_OFFSET] + + /* Mask out the old boot mode bits and set the boot mode to FLASH */ + + bic \value, \value, #STR71X_PCUBOOTCR_BOOTMASK + orr \value, \value, #STR71X_PCUBOOTCR_BMFLASH + + /* Save the modified BOOTCR register */ + + strh \value, [\base, #STR71X_PCU_BOOTCR_OFFSET] + .endm + +/***************************************************************************** + * Text + *****************************************************************************/ + + .text + +/***************************************************************************** + * Name: _vector_table + * + * Description: + * Interrrupt vector table. This must be located at the beginning + * of the memory space (at CONFIG_CODE_BASE). The first entry in + * the vector table is the reset vector and this is the code that + * will execute whn the processor is reset. + * + *****************************************************************************/ + + .globl _vector_table + .type _vector_table, %function +_vector_table: + ldr pc, .Lresethandler /* 0x00: Reset */ + ldr pc, .Lundefinedhandler /* 0x04: Undefined instruction */ + ldr pc, .Lswihandler /* 0x08: Software interrupt */ + ldr pc, .Lprefetchaborthandler /* 0x0c: Prefetch abort */ + ldr pc, .Ldataaborthandler /* 0x10: Data abort */ + .long 0 /* 0x14: Reserved vector */ + ldr pc, .Lirqhandler /* 0x18: IRQ */ + ldr pc, .Lfiqhandler /* 0x1c: FIQ */ + + .globl __start + .globl up_vectorundefinsn + .globl up_vectorswi + .globl up_vectorprefetch + .globl up_vectordata + .globl up_vectorirq + .globl up_vectorfiq + +.Lresethandler: + .long __start +.Lundefinedhandler: + .long up_vectorundefinsn +.Lswihandler: + .long up_vectorswi +.Lprefetchaborthandler: + .long up_vectorprefetch +.Ldataaborthandler: + .long up_vectordata +.Lirqhandler: + .long up_vectorirq +.Lfiqhandler: + .long up_vectorfiq + .size _vector_table, . - _vector_table + +/***************************************************************************** + * Name: __start + * + * Description: + * Reset entry point. This is the first function to execute when + * the processor is reset. It initializes hardware and then gives + * control to NuttX. + * + *****************************************************************************/ + + .global __start + .type __start, #function + +__start: + /* On reset, an aliased copy of FLASH is mapped to address 0x00000000. + * Continue execution in the 'real' FLASH address space rather than + * the aliased copy + */ + + ldr pc, =__flashstart +__flashstart: + .rept 9 + nop /* Wait for OSC stabilization*/ + .endr + + /* Setup the initial processor mode */ + + mov r0, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT ) + msr cpsr, r0 + + /* Initialize the external memory interface (EMI) */ + + emiinit r0, r1 + + /* Initialize the enhanced interrupt controller (EIC) */ + + eicinit r0, r1, r2, r3 + + /* Disable all peripherals except EIC */ + + periphinit r0, r1, r2 + + /* Map memory appropriately for configuration */ + + remap r0, r1 + + /* Configure the uart so that we can get debug output as soon + * as possible. Modifies r0, r1, r2, and r14. + */ + + bl up_lowsetup + showprogress 'A' + + /* Setup system stack (and get the BSS range) */ + + adr r0, LC0 + ldmia r0, {r4, r5, sp} + + /* Clear system BSS section */ + + mov r0, #0 +1: cmp r4, r5 + strcc r0, [r4], #4 + bcc 1b + + showprogress 'B' + + /* Copy system .data sections to new home in RAM. */ + +#ifdef CONFIG_BOOT_FROM_FLASH + + adr r3, LC2 + ldmia r3, {r0, r1, r2} + +1: ldmia r0!, {r3 - r10} + stmia r1!, {r3 - r10} + cmp r1, r2 + blt 1b + +#endif + /* Perform early serial initialization */ + + mov fp, #0 +#ifdef CONFIG_USE_EARLYSERIALINIT + bl up_earlyserialinit +#endif + + showprogress 'C' + + /* Call C++ constructors */ + + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ +ctor_loop: + cmp r0, r1 + beq ctor_end + ldr r2, [r0], #4 + stmfd sp!, {r0-r1} + mov lr, pc + mov pc, r2 + ldmfd sp!, {r0-r1} + b ctor_loop +ctor_end: + + showprogress 'D' + showprogress '\n' + + /* Initialize onboard LEDs */ + +#ifdef CONFIG_ARCH_LEDS + bl up_ledinit +#endif + + /* Then jump to OS entry */ + + b os_start + + /* Call destructors -- never get here */ +#if 0 + ldr r0, =__dtors_start__ + ldr r1, =__dtors_end__ +dtor_loop: + cmp r0, r1 + beq dtor_end + ldr r2, [r0], #4 + stmfd sp!, {r0-r1} + mov lr, pc + mov pc, r2 + ldmfd sp!, {r0-r1} + b dtor_loop +dtor_end: +#endif + + /* Variables: + * _sbss is the start of the BSS region (see ld.script) + * _ebss is the end of the BSS regsion (see ld.script) + * The idle task stack starts at the end of BSS and is + * of size CONFIG_PROC_STACK_SIZE. The heap continues + * from there until the end of memory. See g_heapbase + * below. + */ + +LC0: .long _sbss + .long _ebss + .long _ebss+CONFIG_PROC_STACK_SIZE-4 + +#ifdef CONFIG_BOOT_FROM_FLASH +LC2: .long _eronly /* Where .data defaults are stored in FLASH */ + .long _sdata /* Where .data needs to reside in SDRAM */ + .long _edata +#endif + .size __start, .-__start + + /* This global variable is unsigned long g_heapbase and is + * exported from here only because of its coupling to LCO + * above. + */ + + .data + .align 4 + .globl g_heapbase + .type g_heapbase, object +g_heapbase: + .long _ebss+CONFIG_PROC_STACK_SIZE + .size g_heapbase, .-g_heapbase + + .end + diff --git a/nuttx/arch/arm/src/str71x/str71x_irq.c b/nuttx/arch/arm/src/str71x/str71x_irq.c new file mode 100644 index 000000000..601c1b60c --- /dev/null +++ b/nuttx/arch/arm/src/str71x/str71x_irq.c @@ -0,0 +1,127 @@ +/**************************************************************************** + * arch/arm/src/st71x/st71x_irq.c + * + * Copyright (C) 2008 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> +#include <sys/types.h> +#include <nuttx/irq.h> +#include "up_arch.h" +#include "os_internal.h" +#include "up_internal.h" + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +uint32 *current_regs; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Funtions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void) +{ + /* The bulk of IRQ initialization if performed in str71x_head.S, so we + * have very little to do here: + */ + + /* Currents_regs is non-NULL only while processing an interrupt */ + + current_regs = NULL; + + /* Enable interrupts */ + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + irqrestore(SVC_MODE | PSR_F_BIT); +#endif +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ +# warning "To be provided" +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ +# warning "To be provided" +} + +/**************************************************************************** + * Name: up_maskack_irq + * + * Description: + * Mask the IRQ and acknowledge it + * + ****************************************************************************/ + +void up_maskack_irq(int irq) +{ +# warning "To be provided" +} diff --git a/nuttx/arch/arm/src/str71x/str71x_pcu.h b/nuttx/arch/arm/src/str71x/str71x_pcu.h index 1ac7f39cf..8fdf5529d 100644 --- a/nuttx/arch/arm/src/str71x/str71x_pcu.h +++ b/nuttx/arch/arm/src/str71x/str71x_pcu.h @@ -48,55 +48,79 @@ * Definitions
************************************************************************************/
-/* Power Control Unit (PCU) registers ***********************************************/
+/* Power Control Unit (PCU) register offsets ****************************************/
-#define STR71X_PCU_MDIVR (STR71X_PCU_BASE + 0x0000) /* 16-bits wide */
-#define STR71X_PCU_PDIVR (STR71X_PCU_BASE + 0x0004) /* 16-bits wide */
-#define STR71X_PCU_RSTR (STR71X_PCU_BASE + 0x0008) /* 16-bits wide */
-#define STR71X_PCU_PLL2CR (STR71X_PCU_BASE + 0x000c) /* 16-bits wide */
-#define STR71X_PCU_BOOTCR (STR71X_PCU_BASE + 0x0010) /* 16-bits wide */
-#define STR71X_PCU_PWRCR (STR71X_PCU_BASE + 0x0014) /* 16-bits wide */
+#define STR71X_PCU_MDIVR_OFFSET (0x0000) /* 16-bits wide */
+#define STR71X_PCU_PDIVR_OFFSET (0x0004) /* 16-bits wide */
+#define STR71X_PCU_RSTR_OFFSET (0x0008) /* 16-bits wide */
+#define STR71X_PCU_PLL2CR_OFFSET (0x000c) /* 16-bits wide */
+#define STR71X_PCU_BOOTCR_OFFSET (0x0010) /* 16-bits wide */
+#define STR71X_PCU_PWRCR_OFFSET (0x0014) /* 16-bits wide */
-/* Register bit settings ************************************************************/
-
-/* PCU flags */
-
-#define STR71X_PCU_WREN (0x8000)
-#define STR71X_PCU_VROK (0x1000)
-
-/* PCU VR status */
-
-#define STR71X_PCU_STABLE (0)
-#define STR71X_PCU_UNSTABLE (1)
-
-/* PCU VR */
+/* Power Control Unit (PCU) register addresses **************************************/
-#define STR71X_PCU_MVR (0x0008)
-#define STR71X_PCU_LPR (0x0010)
+#define STR71X_PCU_MDIVR (STR71X_PCU_BASE + STR71X_PCU_MDIVR_OFFSET)
+#define STR71X_PCU_PDIVR (STR71X_PCU_BASE + STR71X_PCU_PDIVR_OFFSET)
+#define STR71X_PCU_RSTR (STR71X_PCU_BASE + STR71X_PCU_RSTR_OFFSET)
+#define STR71X_PCU_PLL2CR (STR71X_PCU_BASE + STR71X_PCU_PLL2CR_OFFSET)
+#define STR71X_PCU_BOOTCR (STR71X_PCU_BASE + STR71X_PCU_BOOTCR_OFFSET)
+#define STR71X_PCU_PWRCR (STR71X_PCU_BASE + STR71X_PCU_PWRCR_OFFSET)
-/* WFI Clocks */
-
-#define STR71X_PCU_WFICLOCK216 (0)
-#define STR71X_PCU_WFICkAF (1)
-
-/* LPWFI Clocks */
-
-#define STR71X_PCU_LPWFICLK216 (0)
-#define STR71X_PCU_LPWFICKAF (1)
-
-/* RCCU_CCR register bits definition */
-
-#define STR71X_PCUCCR_ENHALT (0x00000800) /* Bit 11: Enable Halt bit */
-#define STR71X_PCUCCR_LPOWFI (0x00000001) /* Bit 0: Low Power Mode in Wait For interrupt Mode */
-
-/* PCU_PWRCR register bits definition */
+/* Register bit settings ************************************************************/
-#define STR71X_PCUPWRCR_VRBYP (0x0008) /* Bit 3: Main Regulator Bypass bit */
-#define STR71X_PCUPWRCR_LPRWFI (0x0010) /* Bit 4: Low Power Regulator in Wait For interrupt Mode bit */
-#define STR71X_PCUPWRCR_LVDDIS (0x0100) /* Bit 8: Low Voltage Detector Disable bit */
-#define STR71X_PCUPWRCR_VROK (0x1000) /* Bit 12: Voltage Regulator OK flag */
-#define STR71X_PCUPWRCR_BUSY (0x4000) /* Bit 14: PCU register Backup logic Busy flag */
-#define STR71X_PCUPWRCR_WREN (0x8000) /* Bit 15: PCU register Write Enable Bit */
+/* PCU RSTR register bit definitions */
+
+#define STR71X_PCURSTR_EMIRESET (0x0004) /* Bit 2: EMI reset */
+
+/* PCU PLL2CR register bit definitions */
+
+#define STR71X_PCUPPL2CR_DXMASK (0x0007) /* Bits 0-2: PLL2 output clock divider */
+#define STR71X_PCUPPL2CR_DIV1 (0x0000) /* PLL2 / 1 */
+#define STR71X_PCUPPL2CR_DIV2 (0x0001) /* PLL2 / 2 */
+#define STR71X_PCUPPL2CR_DIV3 (0x0002) /* PLL2 / 3 */
+#define STR71X_PCUPPL2CR_DIV4 (0x0003) /* PLL2 / 4 */
+#define STR71X_PCUPPL2CR_DIV5 (0x0004) /* PLL2 / 5 */
+#define STR71X_PCUPPL2CR_DIV6 (0x0005) /* PLL2 / 6 */
+#define STR71X_PCUPPL2CR_DIV7 (0x0006) /* PLL2 / 7 */
+#define STR71X_PCUPPL2CR_OFF (0x0007) /* PLL2 OFF */
+#define STR71X_PCUPPL2CR_MXMASK (0x0030) /* Bits 4-5: PLL2 multiplier */
+#define STR71X_PCUPPL2CR_MUL20 (0x0000) /* CLK2 * 20 */
+#define STR71X_PCUPPL2CR_MUL12 (0x0010) /* CLK2 * 12 */
+#define STR71X_PCUPPL2CR_MUL28 (0x0020) /* CLK2 * 28 */
+#define STR71X_PCUPPL2CR_MUL16 (0x0030) /* CLK2 * 16 */
+#define STR71X_PCUPPL2CR_FRRRNG (0x0040) /* Bit 6: PLL2 frequency range selection */
+#define STR71X_PCUPPL2CR_PLLEN (0x0080) /* Bit 7: PLL2 enable */
+#define STR71X_PCUPPL2CR_USBEN (0x0100) /* Bit 8: Enable PLL clock to USB */
+#define STR71X_PCUPPL2CR_IRQMASK (0x0200) /* Bit 9: Enable interrupt request CPU on lock transition */
+#define STR71X_PCUPPL2CR_IRQPEND (0x0400) /* Bit 10: Interrtup request to CPU on lock transition pending */
+#define STR71X_PCUPPL2CR_LOCK (0x8000) /* Bit 15: PLL2 locked */
+
+/* PCU BOOTCR register bit definitions */
+
+#define STR71X_PCUBOOTCR_BOOTMASK (0x0003) /* Bits 0-1: Boot mode */
+#define STR71X_PCUBOOTCR_BMFLASH (0x0000) /* FLASH */
+#define STR71X_PCUBOOTCR_BMRAM (0x0002) /* RAM */
+#define STR71X_PCUBOOTCR_BMEXTMEM (0x0003) /* FLASH */
+#define STR71X_PCUBOOTCR_BSPIOEN (0x0004) /* Bit 2: Enable BSPI0 */
+#define STR71X_PCUBOOTCR_USBFILTEN (0x0008) /* Bit 3: Enable USB standby filtering */
+#define STR71X_PCUBOOTCR_LPOWDBGEN (0x0010) /* Bit 4: Enable reserved features for STOP mode */
+#define STR71X_PCUBOOTCR_ACDEN (0x0020) /* Bit 5: Enable ADC */
+#define STR71X_PCUBOOTCR_CANACTIVE (0x0040) /* Bit 6: CAN active */
+#define STR71X_PCUBOOTCR_HDLCACTIVE (0x0080) /* Bit 7: HDLC active */
+#define STR71X_PCUBOOTCR_PKG64 (0x0200) /* Bit 9: Die is hosted in 64-pin package */
+
+/* PCU PWRCR register bit definitions */
+
+#define STR71X_PCUPWRCR_VRBYP (0x0008) /* Bit 3: Main regulator bypass */
+#define STR71X_PCUPWRCR_LPRWFI (0x0010) /* Bit 4: Low power regulator in wait-for-interrupt mode */
+#define STR71X_PCUPWRCR_LPRBYP (0x0020) /* Bit 5: Low power regulator bypass */
+#define STR71X_PCUPWRCR_PWRDWN (0x0040) /* Bit 6: Activate standby mode */
+#define STR71X_PCUPWRCR_OSCBYP (0x0080) /* Bit 7: 32KHz oscillator bypass */
+#define STR71X_PCUPWRCR_LVDDIS (0x0100) /* Bit 8: Low voltage detector disable */
+#define STR71X_PCUPWRCR_LVDDIS (0x0200) /* Bit 9: FLASH low speed (low power) select */
+#define STR71X_PCUPWRCR_VROK (0x1000) /* Bit 12: Voltage regulator OK */
+#define STR71X_PCUPWRCR_BUSY (0x4000) /* Bit 14: PCU register backup logic busy */
+#define STR71X_PCUPWRCR_WREN (0x8000) /* Bit 15: PCU register write enable */
/************************************************************************************
* Public Types
diff --git a/nuttx/arch/arm/src/str71x/str71x_rccu.h b/nuttx/arch/arm/src/str71x/str71x_rccu.h index c7ff2a88d..9d6085ef1 100644 --- a/nuttx/arch/arm/src/str71x/str71x_rccu.h +++ b/nuttx/arch/arm/src/str71x/str71x_rccu.h @@ -48,136 +48,85 @@ * Definitions
************************************************************************************/
-/* Reset and Clock Control Unit (RCCU) registers ************************************/
+/* Reset and Clock Control Unit (RCCU) register offsets *****************************/
/* All registers are 32-bits wide, but with the top 16 bits "reserved" */
-#define STR71X_RCCU_CCR (STR71X_RCCU_BASE + 0x0000) /* 32-bits wide */
-#define STR71X_RCCU_CFR (STR71X_RCCU_BASE + 0x0008) /* 32-bits wide */
-#define STR71X_RCCU_PLL1CR (STR71X_RCCU_BASE + 0x0018) /* 32-bits wide */
-#define STR71X_RCCU_PER (STR71X_RCCU_BASE + 0x001c) /* 32-bits wide */
-#define STR71X_RCCU_SMR (STR71X_RCCU_BASE + 0x0020) /* 32-bits wide */
+#define STR71X_RCCU_CCR_OFFSET (0x0000) /* 32-bits wide */
+#define STR71X_RCCU_CFR_OFFSET (0x0008) /* 32-bits wide */
+#define STR71X_RCCU_PLL1CR_OFFSET (0x0018) /* 32-bits wide */
+#define STR71X_RCCU_PER_OFFSET (0x001c) /* 32-bits wide */
+#define STR71X_RCCU_SMR_OFFSET (0x0020) /* 32-bits wide */
-/* Register bit settings ************************************************************/
-/* RCCU Clock Div */
-
-#define STR71X_RCCU_DEFAULT (0x00)
-#define STR71X_RCCU_RCLK2 (0x01)
-#define STR71X_RCCU_RCLK4 (0x02)
-#define STR71X_RCCU_RCLK8 (0x03)
-
-/* RCCU RCLK Clocks */
-
-#define STR71X_RCCU_PLL1_OUTPUT (0)
-#define STR71X_RCCU_CLOCK216 (1)
-#define STR71X_RCCU_CLOCK2 (2)
-#define STR71X_RCCU_CK_AF (3)
-
-/* RCCU PLL1 Multipliers */
-
-#define STR71X_RCCU_PLL1_MUL12 (0x01)
-#define STR71X_RCCU_PLL1_MUL16 (0x03)
-#define STR71X_RCCU_PLL1_MUL20 (0x00)
-#define STR71X_RCCU_PLL1_MUL24 (0x02)
-
-/* RCCU PLL1 Multipliers */
-
-#define STR71X_RCCU_PLL2_MUL12 (0x01)
-#define STR71X_RCCU_PLL2_MUL16 (0x03)
-#define STR71X_RCCU_PLL2_MUL20 (0x00)
-#define STR71X_RCCU_PLL2_MUL28 (0x02)
-
-/* RCCU PLL Divisors */
-
-#define STR71X_RCCU_DIV1 (0x00)
-#define STR71X_RCCU_DIV2 (0x01)
-#define STR71X_RCCU_DIV3 (0x02)
-#define STR71X_RCCU_DIV4 (0x03)
-#define STR71X_RCCU_DIV5 (0x04)
-#define STR71X_RCCU_DIV6 (0x05)
-#define STR71X_RCCU_DIV7 (0x06)
-
-/* RCCU USB Clocks */
-
-#define STR71X_RCCU_PLL2_OUTPUT (0x01)
-#define STR71X_RCCU_USBCK (0x00)
-
-/* RCCU Clocks */
-
-#define STR71X_RCCU_CLK2 (0)
-#define STR71X_RCCU_RCLK (1)
-#define STR71X_RCCU_MCLK (2)
-#define STR71X_RCCU_PCLK2 (3)
-#define STR71X_RCCU_PCLK1 (4)
-
-/* RCCU Interrupts */
-
-#define STR71X_RCCU_INTPLL1LOCK (0x0080)
-#define STR71X_RCCU_INTCKAF (0x0100)
-#define STR71X_RCCU_INTCK216 (0x0200)
-#define STR71X_RCCU_INTSTOP (0x0400)
-
-/* RCCU Flags */
-
-#define STR71X_RCCU_PLL1LOCK (0x0002)
-#define STR71X_RCCU_CKAFST (0x0004)
-#define STR71X_RCCU_PLL1LOCKI (0x0800)
-#define STR71X_RCCU_CKAFI (0x1000)
-#define STR71X_RCCU_CK216I (0x2000)
-#define STR71X_RCCU_STOPI (0x4000
+/* Reset and Clock Control Unit (RCCU) register addresses ***************************/
-/* RCCU Reset Sources */
+#define STR71X_RCCU_CCR (STR71X_RCCU_BASE + STR71X_RCCU_CCR_OFFSET)
+#define STR71X_RCCU_CFR (STR71X_RCCU_BASE + STR71X_RCCU_CFR_OFFSET)
+#define STR71X_RCCU_PLL1CR (STR71X_RCCU_BASE + STR71X_RCCU_PLL1CR_OFFSET)
+#define STR71X_RCCU_PER (STR71X_RCCU_BASE + STR71X_RCCU_PER_OFFSET)
+#define STR71X_RCCU_SMR (STR71X_RCCU_BASE + STR71X_RCCU_SMR_OFFSET)
-#define STR71X_RCCU_RESETSOURCESMASK (0x000006e0)
-#define STR71X_RCCU_EXTERNALRESET (0x00000000)
-#define STR71X_RCCU_SOFTWARERESET (0x00000020)
-#define STR71X_RCCU_WDGRESET (0x00000040)
-#define STR71X_RCCU_RTCALARMRESET (0x00000080)
-#define STR71X_RCCU_LVDRESET (0x00000200)
-#define STR71X_RCCU_WKPRESET (0x00000400
-
-/* RCCU PLL1 free running modes */
-
-#define STR71X_RCCU_PLL1FRM125 (0)
-#define STR71X_RCCU_PLL1FRM250 (1)
-#define STR71X_RCCU_PLL1FRM500 (2)
-
-#define STR71X_RCCU_DIV2_MASK (0x00008000)
-#define STR71X_RCCU_DIV2_INDEX (0x0f)
-#define STR71X_RCCU_FACT_MASK (0x0003)
-
-#define STR71X_RCCU_FACT1_MASK (0x0003)
-
-#define STR71X_RCCU_FACT2_MASK (0x0300)
-#define STR71X_RCCU_FACT2_INDEX (0x08)
-
-#define STR71X_RCCU_MX_MASK (0x00000030)
-#define STR71X_RCCU_MX_INDEX (0x04)
-
-#define STR71X_RCCU_DX_MASK (0x00000007)
-
-#define STR71X_RCCU_FREFRANGE_MASK (0x00000040)
-
-#define STR71X_RCCU_FRQRNG_MASK (0x00000040)
-
-#define STR71X_RCCU_FREEN_MASK (0x00000080)
-
-#define STR71X_RCCU_PLLEN_MASK (0x00000080)
-
-#define STR71X_RCCU_CSU_CKSEL_MASK (0x00000001)
-
-#define STR71X_RCCU_CK2_16_MASK (0x00000008)
-
-#define STR71X_RCCU_CKAF_SEL_MASK (0x00000004)
-
-#define STR71X_RCCU_LOCK_MASK (0x00000002)
-
-#define STR71X_RCCU_USBEN_MASK (0x0100)
-#define STR71X_RCCU_USBEN_INDEX (0x08)
-
-/* RTC Oscillator Frequency value = 32 768 Hz */
+/* Register bit settings ************************************************************/
-#define STR71X_RCCU_RTC_OSC (32768)
+/* RCCU CCR register bit definitions */
+
+#define STR71X_RCCUCCR_LPOWFI (0x00000001) /* Bit 0: Low power mode in wait-for-interrupt mode */
+#define STR71X_RCCUCCR_WFICLKSEL (0x00000002) /* Bit 1: WFI clock select */
+#define STR71X_RCCUCCR_CKAFSEL (0x00000004) /* Bit 2: Alternate function clock select */
+#define STR71X_RCCUCCR_SRESEN (0x00000008) /* Bit 3: Software reset enable */
+#define STR71X_RCCUCCR_ENCLOCK (0x00000080) /* Bit 7: Lock interrupt enable */
+#define STR71X_RCCUCCR_ENCKAF (0x00000100) /* Bit 8: CKAF interrupt enable */
+#define STR71X_RCCUCCR_ENCK216 (0x00000200) /* Bit 9: CK2_16 interrupt enable */
+#define STR71X_RCCUCCR_ENSTOP (0x00000400) /* Bit 10: Stop interrupt enable */
+#define STR71X_RCCUCCR_ENHALT (0x00000800) /* Bit 11: Enable halt */
+
+/* RCCU CFR register bit definitions */
+
+#define STR71X_RCCUCFR_CSUCKSEL (0x00000001) /* Bit 0: CSU clock select */
+#define STR71X_RCCUCFR_LOCK (0x00000002) /* Bit 1: PLL locked-in */
+#define STR71X_RCCUCFR_CKAFST (0x00000004) /* Bit 2: CK_AF status */
+#define STR71X_RCCUCFR_CK216 (0x00000008) /* Bit 3: CLK2/16 selection */
+#define STR71X_RCCUCFR_CKSTOPEN (0x00000010) /* Bit 4: Clock stop enable */
+#define STR71X_RCCUCFR_SOFTRES (0x00000020) /* Bit 5: Software reset */
+#define STR71X_RCCUCFR_WDGRES (0x00000040) /* Bit 6: Watchdog reset */
+#define STR71X_RCCUCFR_RTCALARM (0x00000080) /* Bit 7: RTC alarm reset */
+#define STR71X_RCCUCFR_LVDRES (0x00000200) /* Bit 9: Voltage regulator low voltage detector reset */
+#define STR71X_RCCUCFR_WKPRES (0x00000400) /* Bit 10: External wakeup */
+#define STR71X_RCCUCFR_LOCKI (0x00000800) /* Bit 11: Lock interrupt pending */
+#define STR71X_RCCUCFR_CKAFI (0x00001000) /* Bit 12: CK_AF switching interrupt pending */
+#define STR71X_RCCUCFR_CK216I (0x00002000) /* Bit 13: CK2_16 switching interrupt pending */
+#define STR71X_RCCUCFR_STOPI (0x00004000) /* Bit 14: Stop interrupt pending */
+#define STR71X_RCCUCFR_DIV2 (0x00008000) /* Bit 15: OSCIN divided by 2 */
+
+/* RCCU PPL1CR register bit definitions */
+
+#define STR71X_RCCUPLL1CR_DXMASK (0x00000003) /* Bit 0-2: PLL1 clock divisor */
+#define STR71X_RCCUPLL1CR_DIV1 (0x00000000) /* PLLCK / 1 */
+#define STR71X_RCCUPLL1CR_DIV2 (0x00000001) /* PLLCK / 2 */
+#define STR71X_RCCUPLL1CR_DIV3 (0x00000002) /* PLLCK / 3 */
+#define STR71X_RCCUPLL1CR_DIV4 (0x00000003) /* PLLCK / 4 */
+#define STR71X_RCCUPLL1CR_DIV5 (0x00000004) /* PLLCK / 5 */
+#define STR71X_RCCUPLL1CR_DIV6 (0x00000005) /* PLLCK / 6 */
+#define STR71X_RCCUPLL1CR_DIV7 (0x00000006) /* PLLCK / 7 */
+#define STR71X_RCCUPLL1CR_CLK2 (0x00000007) /* FREEN==0: CLK2 */
+#define STR71X_RCCUPLL1CR_FREERM (0x00000007) /* FREEN==1: PLL1 in free running mode */
+#define STR71X_RCCUPLL1CR_MXMASK (0x00000030) /* Bit 4-5:
+#define STR71X_RCCUPLL1CR_MUL20 (0x00000000) /* CLK2 * 20 */
+#define STR71X_RCCUPLL1CR_MUL12 (0x00000010) /* CLK2 * 12 */
+#define STR71X_RCCUPLL1CR_MUL24 (0x00000020) /* CLK2 * 24 */
+#define STR71X_RCCUPLL1CR_MUL16 (0x00000030) /* CLK2 * 16 */
+#define STR71X_RCCUPLL1CR_FREFRANGE (0x00000040) /* Bit 6: Reference frequency range select */
+#define STR71X_RCCUPLL1CR_FREEN (0x00000080) /* Bit 7: PKL free running mode */
+
+/* RCCU PER register bit definitions */
+
+#define STR71X_RCCUPER_EMI (0x00000004) /* Bit 2: EMI */
+#define STR71X_RCCUPER_USBKERNEL (0x00000010) /* Bit 4: USB Kernel */
+
+/* RCCU SMR register bit definitions */
+
+#define STR71X_RCCUSMR_WFI (0x00000001) /* Bit 0: Wait for interrupt */
+#define STR71X_RCCUSMR_HALT (0x00000000) /* Bit 1: Halt */
/************************************************************************************
* Public Types
diff --git a/nuttx/configs/mcu123-lpc214x/src/up_spi.c b/nuttx/configs/mcu123-lpc214x/src/up_spi.c index 7a1789572..86ed79579 100644 --- a/nuttx/configs/mcu123-lpc214x/src/up_spi.c +++ b/nuttx/configs/mcu123-lpc214x/src/up_spi.c @@ -133,7 +133,7 @@ static struct spi_dev_s g_spidev = { &g_spiops }; * ****************************************************************************/ -void spi_select(FAR struct spi_dev_s *dev, boolean selected) +static void spi_select(FAR struct spi_dev_s *dev, boolean selected) { uint32 bit = 1 << 20; @@ -181,7 +181,7 @@ void spi_select(FAR struct spi_dev_s *dev, boolean selected) * ****************************************************************************/ -uint32 spi_setfrequency(FAR struct spi_dev_s *dev, uint32 frequency) +static uint32 spi_setfrequency(FAR struct spi_dev_s *dev, uint32 frequency) { uint32 divisor = LPC214X_PCLKFREQ / frequency; @@ -213,7 +213,7 @@ uint32 spi_setfrequency(FAR struct spi_dev_s *dev, uint32 frequency) * ****************************************************************************/ -ubyte spi_status(FAR struct spi_dev_s *dev) +static ubyte spi_status(FAR struct spi_dev_s *dev) { /* I don't think there is anyway to determine these things on the mcu123.com * board. @@ -236,7 +236,7 @@ ubyte spi_status(FAR struct spi_dev_s *dev) * ****************************************************************************/ -ubyte spi_sndbyte(FAR struct spi_dev_s *dev, ubyte ch) +static ubyte spi_sndbyte(FAR struct spi_dev_s *dev, ubyte ch) { /* Wait while the TX FIFO is full */ @@ -270,7 +270,7 @@ ubyte spi_sndbyte(FAR struct spi_dev_s *dev, ubyte ch) * ****************************************************************************/ -void spi_sndblock(FAR struct spi_dev_s *dev, FAR const ubyte *buffer, size_t buflen) +static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const ubyte *buffer, size_t buflen) { ubyte sr; diff --git a/nuttx/configs/olimex-strp711/ostest/defconfig b/nuttx/configs/olimex-strp711/ostest/defconfig index cbd2c7580..e662dc0f9 100644 --- a/nuttx/configs/olimex-strp711/ostest/defconfig +++ b/nuttx/configs/olimex-strp711/ostest/defconfig @@ -63,13 +63,42 @@ CONFIG_ARCH_BOARD=olimex-strp711 CONFIG_ARCH_BOARD_OLIMEX_STRP711=y CONFIG_BOARD_LOOPSPERMSEC=3270 CONFIG_ARCH_LEDS=y -CONFIG_DRAM_SIZE=0x00008000 -CONFIG_DRAM_START=0x40000000 +CONFIG_DRAM_SIZE=0x00010000 +CONFIG_DRAM_START=0x20000000 CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE) CONFIG_ARCH_INTERRUPTSTACK=0 CONFIG_ARCH_STACKDUMP=y # +# STR71x specific boot/build settings +# +# CONFIG_STR71X_BANK0, CONFIG_STR71X_BANK1, CONFIG_STR71X_BANK2, and CONFIG_STR71X_BANK3 +# Enable initialize of external memory banks 0-3. +# CONFIG_STR71X_BANK0_SIZE, CONFIG_STR71X_BANK1_SIZE, CONFIG_STR71X_BANK2_SIZE, and CONFIG_STR71X_BANK3_SIZE +# If a particular external memory bank is configured, then its width must be provided. +# 8 and 16 (bits) are the only valid options. +# CONFIG_STR71X_BANK0_WAITSTATES, CONFIG_STR71X_BANK1_WAITSTATES, CONFIG_STR71X_BANK2_WAITSTATES, and CONFIG_STR71X_BANK3_WAITSTATES +# If a particular external memory bank is configured, then the number of waistates +# for the bank must also be provided. Valid options are {0, .., 15} +# CONFIG_STR71X_BIGEXTMEM +# The default is to provide 20 bits of address for all external memory regions. If +# any memory region is larger than 1Mb, then this option should be selected. In this +# case, 24 bits of addressing will be used +CONFIG_STR71X_BANK0=n +CONFIG_STR71X_BANK0_SIZE=16 +CONFIG_STR71X_BANK0_WAITSTATES=0 +CONFIG_STR71X_BANK1=n +CONFIG_STR71X_BANK0_SIZE=16 +CONFIG_STR71X_BANK1_WAITSTATES=0 +CONFIG_STR71X_BANK2=n +CONFIG_STR71X_BANK0_SIZE=16 +CONFIG_STR71X_BANK3_WAITSTATES=0 +CONFIG_STR71X_BANK3=n +CONFIG_STR71X_BANK0_SIZE=16 +CONFIG_STR71X_BANK2_WAITSTATES=0 +CONFIG_STR71X_BIGEXTMEM=n + +# # STR71x specific device driver settings # # CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the diff --git a/nuttx/configs/olimex-strp711/ostest/ld.script b/nuttx/configs/olimex-strp711/ostest/ld.script index 1d8211ad0..c2a198791 100644 --- a/nuttx/configs/olimex-strp711/ostest/ld.script +++ b/nuttx/configs/olimex-strp711/ostest/ld.script @@ -38,12 +38,12 @@ ENTRY(_stext) SECTIONS { /* The str71x has 256Kb of non-volatile memory beginning at address - * 0x00000000 for program storage (Bank0, an addition 16Kb is avalable + * 0x40000000 for program storage (Bank0, an addition 16Kb is avalable * for data storage in Bank1). The OS entry point is via the reset vector * at address 0x00000000 where the FLASH is remapped at reset. */ - . = 0x00000000; + . = 0x40000000; .text : { _stext = ABSOLUTE(.); *(.text) |