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path: root/nuttx/arch/arm/src/sama5/sam_ehci.c
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* SAMA5 EHCI: Fix bits being clobbered in PORTSC on hand-off to OHCI. OHCI: F...Gregory Nutt2013-09-191-5/+8
* SAMA5 EHCI: Did not work with DEBUG off. Appears to be because of some D-Ca...Gregory Nutt2013-09-101-20/+40
* Extent the the USB host trace logic to include verbose debug outputGregory Nutt2013-09-091-23/+68
* Beginning of support for USB host side tracingGregory Nutt2013-09-091-45/+44
* Trivial updates assocaited with USB host mass storage and SAMA5 EHCIGregory Nutt2013-09-081-4/+28
* SAMA5: Add support EHCI/OHCI to sama5d3x-ek/demo (does not work yet); Fix so...Gregory Nutt2013-09-071-1/+1
* SAMA5 EHCI: Implemented (but did not test) interrupt endpoint logicGregory Nutt2013-08-281-94/+325
* SAMA5 EHCI: Correct and extend pool allocation logic; Fix data toggle valuesGregory Nutt2013-08-281-12/+49
* SAMA5 OHCI+EHCI: Using cp15_clean instead of cp15_coherent; EHCI: Need to set...Gregory Nutt2013-08-271-40/+113
* Fix all occurrences of "the the" in documentation and commentsGregory Nutt2013-08-271-4/+4
* SAMA4 EHCI: Correct some backward conditional compilation; fix some warningsGregory Nutt2013-08-261-4/+8
* Add a new method to the USB host driver interface: getdevinfo. This method ...Gregory Nutt2013-08-261-0/+61
* SAMA5 EHCI: Status phase is the opposite direction as the data phaseGregory Nutt2013-08-261-7/+26
* SAMA5 EHCI: Taking direction from wrong bit in SETUP request; need to flush ...Gregory Nutt2013-08-261-1/+13
* SAMA5 EHCI: Data toggle and status phase fixesGregory Nutt2013-08-251-3/+2
* EHCI reset bit was not being set correctlyGregory Nutt2013-08-251-1/+1
* SAMA5 OHCI: Fix backward conditional compilation. Clean-up OHCI/EHCI debug o...Gregory Nutt2013-08-251-8/+8
* SAMA5D3x-EK: Fix some backward conditional compilationGregory Nutt2013-08-241-1/+3
* SAMA5: EHCI now handles low- and full-speed connections by giving them to OHC...Gregory Nutt2013-08-241-27/+119
* SAMA5 EHCI: Added logic to detect port speed. Handling is insufficientGregory Nutt2013-08-241-2/+82
* SAMA5/ECHI: Debug register access, add logic to determine transfer size, fix...Gregory Nutt2013-08-231-32/+70
* SAMA5 EHCI: cosmetic changesGregory Nutt2013-08-231-14/+15
* SAMA5: Add support for sharing ports when both OHCI and EHCI are enabledGregory Nutt2013-08-231-10/+53
* SAMA5 EHCI: Fix some list traversal bugsGregory Nutt2013-08-221-41/+106
* SAMA5 EHCI: Initial debug changesGregory Nutt2013-08-221-21/+155
* SAMA5 EHCI: No complete for bulk and control endpointsGregory Nutt2013-08-221-99/+145
* SAMA5 EHCI: Add data transfer logic for asynchronous endpointsGregory Nutt2013-08-221-20/+488
* SAMA5 EHCI: Add IOC error handlingGregory Nutt2013-08-221-33/+104
* SAMA5 EHCI: transfer termination logic. IncompleteGregory Nutt2013-08-211-102/+464
* SAMA5 EHCI: Hardware initialization logicGregory Nutt2013-08-211-12/+202
* Move all SAMA5 EHCI interrupt handling to the worker threadGregory Nutt2013-08-211-23/+407
* SAMA5 EHCI: At list-oriented cache operationsGregory Nutt2013-08-201-2/+96
* Add SAMA5 EHCI list traversal logicGregory Nutt2013-08-201-15/+235
* Beginning of support for SAMA5 EHCI. Not much there yetGregory Nutt2013-08-201-0/+1626
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