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* SAMA5D4: Add missing mappings for the VDEC and L2CC memory regionsGregory Nutt2014-06-214-2/+23
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* Correct type of SAMA5 arm_decodefiq() return valueGregory Nutt2014-06-211-1/+1
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* Need to enable FIQ in initial task state; Improve H32/64 test in IRQ handlingGregory Nutt2014-06-218-106/+130
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* SAMA5: FIQs should be disabled along with IRQs on most exeptions in most ↵Gregory Nutt2014-06-201-22/+11
| | | | configuratinons. arm_decodefiq and arm_decodeirq are mutually exclusive and, hence, can use the same interrupt stack
* SAMA5D4: Add support for secure/FIQ interrupts; SAIC supports need to be be ↵Gregory Nutt2014-06-205-17/+127
| | | | enabled unconditionally
* SAMA5D4: Fix MATRIX32 base addressGregory Nutt2014-06-201-1/+1
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* SAMA5D4: Minor fixes to get working with SAMA5D3 againGregory Nutt2014-06-201-0/+2
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* SAMA5D4: Add partial support for secure interrupt controller (SAIC)Gregory Nutt2014-06-206-88/+300
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* SAMA5D4: USART peripheral clock appears to be MCK/2Gregory Nutt2014-06-202-6/+6
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* SAMA5D4-EK: Make sure that the H32MX divider is set; correct sense of bit ↵Gregory Nutt2014-06-202-3/+42
| | | | driver red LED
* SAMA5D4: Fix peripheral clocking macros: AIC and L2CC are continuously clockedGregory Nutt2014-06-193-26/+57
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* SAMA5D4: Initial bring-up fixesGregory Nutt2014-06-192-5/+16
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* Costmetic update to comments/README fileGregory Nutt2014-06-181-1/+1
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* Cosmetic cleanupGregory Nutt2014-06-181-13/+3
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* SAMA5D4: XDMAC driver now compiles error/warning free (still untested)Gregory Nutt2014-06-173-197/+156
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* SAMA5D4: More progress on XDMAC driver (still no complete); Also fixes some ↵Gregory Nutt2014-06-173-580/+583
| | | | critical errors in the SAMA5D3 DMA definitions
* SAMA5D4: Correct MATRIX register addressesGregory Nutt2014-06-141-127/+314
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* SAMA5D4: Implement SDRAM initializationGregory Nutt2014-06-141-1/+1
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* SAMA5D4: Fix some memory remapping issues; updates to comments and README filesGregory Nutt2014-06-143-55/+120
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* SAMA5: XDMAC update (still not complete)Gregory Nutt2014-06-133-101/+202
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* SAMA5D4: Initial XDMAC driver logic; initial check-in is little more the the ↵Gregory Nutt2014-06-126-59/+2845
| | | | DMAC driver with some name changes
* First check-in of Lazlo's PF_PACKET 'raw' socket implementationGregory Nutt2014-06-121-0/+9
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* STM32: Handle setting of USART CR1_M when 8 bits of data plus parityGregory Nutt2014-06-111-19/+27
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* Typo in last SAMA5D4 commitGregory Nutt2014-06-111-1/+1
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* SAMA5: Add support for Micrel KSZ8081 PHYGregory Nutt2014-06-113-16/+44
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* SAMA5D4: Add EMAC driverGregory Nutt2014-06-118-202/+3933
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* SAMA5D4: Still trying to reconcile Ethernet interfacesGregory Nutt2014-06-114-31/+99
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* SAMA5D3/4: More renaming. Change SAMA5D3 EMAC to EMACA and SAMA5D4 to ↵Gregory Nutt2014-06-109-91/+96
| | | | EMACB so that the configuration and build system can configure them. I might come up with something better later
* STM32: Expicitly include header file files. From Freddie ChopinGregory Nutt2014-06-109-0/+17
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* SAMA5D4: update MATRIX register definitions for the SAMA5D4Gregory Nutt2014-06-103-62/+404
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* SAMA5D4: Complete MPDDR header fileGregory Nutt2014-06-102-358/+570
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* SAMA5D4: Add MPDDRC file (incomplete)Gregory Nutt2014-06-101-0/+478
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* Move SAMA5D3 MPDDRC definitions to a separate header fileGregory Nutt2014-06-102-361/+415
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* SAMA5D4: Update LCDC header fileGregory Nutt2014-06-091-293/+386
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* Add logic to select between incompatible SAMA5D3 and SAMA5D4 EMAC header filesGregory Nutt2014-06-092-412/+466
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* SAMA5: Back out most of commit c37b5b7b97d0644743c04f2c3d9e2b7ef9f5d698. ↵Gregory Nutt2014-06-0911-303/+505
| | | | Things are going to have to be done differently
* SAMA5D4: Updated EMAC header fileGregory Nutt2014-06-091-4/+4
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* SAMA5D4: Add EMAC header fileGregory Nutt2014-06-093-9/+687
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* SAMA5D4: More header file changesGregory Nutt2014-06-093-23/+43
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* SAMA5D4: update ISI register definition header fileGregory Nutt2014-06-091-16/+11
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* SAMA5D4: Completes PMC modifications for the SAMA5D4Gregory Nutt2014-06-093-33/+90
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* SAMA5D4: Completes L2CC register definition header fileGregory Nutt2014-06-081-36/+259
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* SAMA5D4: Update HSMC register definitionsGregory Nutt2014-06-084-26/+32
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* SAMA5D4: Update PIO register definitionsGregory Nutt2014-06-081-12/+72
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* SAMA5D4: Update DBGU header fileGregory Nutt2014-06-081-9/+54
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* SAMA5D4: Update PWM header fileGregory Nutt2014-06-082-40/+143
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* SAMA5D4: Updated HSMCI header fileGregory Nutt2014-06-081-40/+53
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* SAMA5D4: Update ADC register definition header fileGregory Nutt2014-06-081-145/+226
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* SAMA5D4: Updated RTC header fileGregory Nutt2014-06-081-16/+145
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* SAMA5D4: Update register definitions; add support for TC2Gregory Nutt2014-06-084-11/+317
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