1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
|
/****************************************************************************
* arch/sh/src/sh1/sh1_serial.c
*
* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <unistd.h>
#include <semaphore.h>
#include <string.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/serial.h>
#include <arch/serial.h>
#include "chip.h"
#include "up_arch.h"
#include "up_internal.h"
#include "os_internal.h"
/****************************************************************************
* Definitions
****************************************************************************/
/* Some sanity checks *******************************************************/
/* Are there any SCIs? */
#if !defined(CONFIG_SH1_SCI0) && !defined(CONFIG_SH1_SCI1)
# ifdef CONFIG_USE_SERIALDRIVER
# error "Serial driver selected, but SCIs not enabled"
# undef CONFIG_USE_SERIALDRIVER
# endif
#endif
/* Is there a serial console? */
#if defined(CONFIG_SCI0_SERIAL_CONSOLE) && defined(CONFIG_SH1_SCI0)
# define HAVE_CONSOLE 1
# undef CONFIG_SCI1_SERIAL_CONSOLE
#elif defined(CONFIG_SCI1_SERIAL_CONSOLE) && defined(CONFIG_SH1_SCI1)
# define HAVE_CONSOLE 1
# undef CONFIG_SCI0_SERIAL_CONSOLE
#else
# if defined(CONFIG_SCI0_SERIAL_CONSOLE) || defined(CONFIG_SCI1_SERIAL_CONSOLE)
# error "Serial console selected, but corresponding SCI not enabled"
# endif
# undef HAVE_CONSOLE
# undef CONFIG_SCI0_SERIAL_CONSOLE
# undef CONFIG_SCI1_SERIAL_CONSOLE
#endif
#ifdef CONFIG_USE_SERIALDRIVER
/* Which SCI with be tty0/console and which tty1? */
/* CONFIG_SCI0_SERIAL_CONSOLE (implies CONFIG_SH1_SCI0 also defined) */
#if defined(CONFIG_SCI0_SERIAL_CONSOLE)
# define CONSOLE_DEV g_sci0port /* SCI0 is console */
# define TTYS0_DEV g_sci0port /* SCI0 is tty0 */
# ifdef CONFIG_SH1_SCI1
# define TTYS1_DEV g_sci1port /* SCI1 is tty1 */
# else
# undef TTYS1_DEV
# endif
/* CONFIG_SCI1_SERIAL_CONSOLE (implies CONFIG_SH1_SCI1 also defined) */
#elif defined(CONFIG_SCI1_SERIAL_CONSOLE)
# define CONSOLE_DEV g_sci1port /* SCI1 is console */
# define TTYS0_DEV g_sci1port /* SCI1 is tty0 */
# ifdef CONFIG_SH1_SCI0
# define TTYS1_DEV g_sci0port /* SCI0 is tty1 */
# else
# undef TTYS1_DEV /* No tty1 */
# endif
/* No console, at least one of CONFIG_SH1_SCI0 and CONFIG_SH1_SCI1 defined */
#elif defined(CONFIG_SH1_SCI0)
# undef CONSOLE_DEV /* No console */
# define TTYS0_DEV g_sci0port /* SCI0 is tty0 */
# ifdef CONFIG_SH1_SCI1
# define TTYS1_DEV g_sci1port /* SCI1 is tty1 */
# else
# undef TTYS1_DEV /* No tty1 */
# endif
/* Otherwise, there is no console and only CONFIG_SH1_SCI1 is defined */
#else
# undef CONSOLE_DEV /* No console */
# define TTYS0_DEV g_sci1port /* SCI1 is tty0 */
# undef TTYS1_DEV /* No tty1 */
#endif
/****************************************************************************
* Private Types
****************************************************************************/
struct up_dev_s
{
uint32_t scibase; /* Base address of SCI registers */
uint32_t baud; /* Configured baud */
volatile uint8_t scr; /* Saved SCR value */
volatile uint8_t ssr; /* Saved SR value (only used during interrupt processing) */
uint8_t irq; /* Base IRQ associated with this SCI */
uint8_t parity; /* 0=none, 1=odd, 2=even */
uint8_t bits; /* Number of bits (7 or 8) */
bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static int up_setup(struct uart_dev_s *dev);
static void up_shutdown(struct uart_dev_s *dev);
static int up_attach(struct uart_dev_s *dev);
static void up_detach(struct uart_dev_s *dev);
static int up_interrupt(int irq, void *context);
static int up_receive(struct uart_dev_s *dev, uint32_t *status);
static void up_rxint(struct uart_dev_s *dev, bool enable);
static bool up_rxavailable(struct uart_dev_s *dev);
static void up_send(struct uart_dev_s *dev, int ch);
static void up_txint(struct uart_dev_s *dev, bool enable);
static bool up_txready(struct uart_dev_s *dev);
/****************************************************************************
* Private Variables
****************************************************************************/
struct uart_ops_s g_sci_ops =
{
.setup = up_setup,
.shutdown = up_shutdown,
.attach = up_attach,
.detach = up_detach,
.receive = up_receive,
.rxint = up_rxint,
.rxavailable = up_rxavailable,
.send = up_send,
.txint = up_txint,
.txready = up_txready,
.txempty = up_txready,
};
/* I/O buffers */
#ifdef CONFIG_SH1_SCI0
static char g_sci0rxbuffer[CONFIG_SCI0_RXBUFSIZE];
static char g_sci0txbuffer[CONFIG_SCI0_TXBUFSIZE];
#endif
#ifdef CONFIG_SH1_SCI1
static char g_sci1rxbuffer[CONFIG_SCI1_RXBUFSIZE];
static char g_sci1txbuffer[CONFIG_SCI1_TXBUFSIZE];
#endif
/* This describes the state of the SH1 SCI0 port. */
#ifdef CONFIG_SH1_SCI0
static struct up_dev_s g_sci0priv =
{
.scibase = SH1_SCI0_BASE,
.baud = CONFIG_SCI0_BAUD,
.irq = SH1_SCI0_IRQBASE,
.parity = CONFIG_SCI0_PARITY,
.bits = CONFIG_SCI0_BITS,
.stopbits2 = CONFIG_SCI0_2STOP,
};
static uart_dev_t g_sci0port =
{
.recv =
{
.size = CONFIG_SCI0_RXBUFSIZE,
.buffer = g_sci0rxbuffer,
},
.xmit =
{
.size = CONFIG_SCI0_TXBUFSIZE,
.buffer = g_sci0txbuffer,
},
.ops = &g_sci_ops,
.priv = &g_sci0priv,
};
#endif
/* This describes the state of the SH1 SCI1 port. */
#ifdef CONFIG_SH1_SCI1
static struct up_dev_s g_sci1priv =
{
.scibase = SH1_SCI1_BASE,
.baud = CONFIG_SCI1_BAUD,
.irq = SH1_SCI1_IRQBASE,
.parity = CONFIG_SCI1_PARITY,
.bits = CONFIG_SCI1_BITS,
.stopbits2 = CONFIG_SCI1_2STOP,
};
static uart_dev_t g_sci1port =
{
.recv =
{
.size = CONFIG_SCI1_RXBUFSIZE,
.buffer = g_sci1rxbuffer,
},
.xmit =
{
.size = CONFIG_SCI1_TXBUFSIZE,
.buffer = g_sci1txbuffer,
},
.ops = &g_sci_ops,
.priv = &g_sci1priv,
};
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: up_serialin
****************************************************************************/
static inline uint8_t up_serialin(struct up_dev_s *priv, int offset)
{
return getreg8(priv->scibase + offset);
}
/****************************************************************************
* Name: up_serialout
****************************************************************************/
static inline void up_serialout(struct up_dev_s *priv, int offset, uint8_t value)
{
putreg8(value, priv->scibase + offset);
}
/****************************************************************************
* Name: up_disablesciint
****************************************************************************/
static inline void up_disablesciint(struct up_dev_s *priv, uint8_t *scr)
{
/* Return a copy of the current scr settings */
if (scr)
{
*scr = priv->scr;
}
/* The disable all interrupts */
priv->scr &= ~SH1_SCISCR_ALLINTS;
up_serialout(priv, SH1_SCI_SCR_OFFSET, priv->scr);
}
/****************************************************************************
* Name: up_restoresciint
****************************************************************************/
static inline void up_restoresciint(struct up_dev_s *priv, uint8_t scr)
{
/* Set the interrupt bits in the scr value */
priv->scr &= ~SH1_SCISCR_ALLINTS;
priv->scr |= (scr & SH1_SCISCR_ALLINTS);
up_serialout(priv, SH1_SCI_SCR_OFFSET, priv->scr);
}
/****************************************************************************
* Name: up_waittxready
****************************************************************************/
#ifdef HAVE_CONSOLE
static inline void up_waittxready(struct up_dev_s *priv)
{
int tmp;
/* Limit how long we will wait for the TDR empty condition */
for (tmp = 1000 ; tmp > 0 ; tmp--)
{
/* Check if the TDR is empty. The TDR becomes empty when: (1) the
* the chip is reset or enters standby mode, (2) the TE bit in the SCR
* is cleared, or (3) the current TDR contents are loaded in the TSR so
* that new data can be written in the TDR.
*/
if ((up_serialin(priv, SH1_SCI_SSR_OFFSET) & SH1_SCISSR_TDRE) != 0)
{
/* The TDR is empty... return */
break;
}
}
}
#endif
/****************************************************************************
* Name: up_setbrr
*
* Description:
* Calculate the correct value for the BRR given the configured frequency
* and the desired BAUD settings.
*
****************************************************************************/
static inline void up_setbrr(struct up_dev_s *priv, unsigned int baud)
{
/* The calculation of the BRR to achieve the desired BAUD is given by the
* following formula:
*
* brr = (f/(64*2**(2n-1)*b))-1
*
* Where:
*
* b = bit rate
* f = frequency (Hz)
* n = divider setting (0, 1, 2, 3)
*
* For n == 0 and with rounding this becomes:
*
* brr = ((((f+16)/32) +(b/2)) / b) - 1
*
* For example, if the processor is clocked at 10 MHz and 9600 is the
* desired BAUD:
*
* brr = ((10,000,016/32) + 4800) / 9600 -1
* = 32
*/
uint32_t brr = ((((SH1_CLOCK + 16) / 32) + (baud >> 1)) / baud) - 1;
up_serialout(priv, SH1_SCI_BRR_OFFSET, (uint16_t)brr);
}
/****************************************************************************
* Name: up_setup
*
* Description:
* Configure the SCI baud, bits, parity, fifos, etc. This
* method is called the first time that the serial port is
* opened.
*
****************************************************************************/
static int up_setup(struct uart_dev_s *dev)
{
#ifndef CONFIG_SUPPRESS_SCI_CONFIG
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
uint8_t smr;
/* Disable the transmitter and receiver */
priv->scr = up_serialin(priv, SH1_SCI_SCR_OFFSET);
priv->scr &= ~(SH1_SCISCR_TE | SH1_SCISCR_RE);
up_serialout(priv, SH1_SCI_SCR_OFFSET, priv->scr);
/* Set communication to be asynchronous with the configured number of data
* bits, parity, and stop bits. Use the internal clock (undivided)
*/
smr = 0;
if (priv->bits == 7)
{
smr |= SH1_SCISMR_CHR;
}
if (priv->parity == 1)
{
smr |= (SH1_SCISMR_PE|SH1_SCISMR_OE);
}
else if (priv->parity == 2)
{
smr |= SH1_SCISMR_PE;
}
if (priv->stopbits2)
{
smr |= SH1_SCISMR_STOP;
}
up_serialout(priv, SH1_SCI_SMR_OFFSET, smr);
/* Set the baud based on the configured console baud and configured
* system clock.
*/
up_setbrr(priv, priv->baud);
/* Select the internal clock source as input */
priv->scr &= ~SH1_SCISCR_CKEMASK;
up_serialout(priv, SH1_SCI_SCR_OFFSET, priv->scr);
/* Wait a bit for the clocking to settle */
up_udelay(100);
/* Then enable the transmitter and reciever */
priv->scr |= (SH1_SCISCR_TE | SH1_SCISCR_RE);
up_serialout(priv, SH1_SCI_SCR_OFFSET, priv->scr);
#endif
return OK;
}
/****************************************************************************
* Name: up_shutdown
*
* Description:
* Disable the SCI. This method is called when the serial port is closed
*
****************************************************************************/
static void up_shutdown(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
up_disablesciint(priv, NULL);
}
/****************************************************************************
* Name: up_attach
*
* Description:
* Configure the SCI to operation in interrupt driven mode. This method is
* called when the serial port is opened. Normally, this is just after the
* the setup() method is called, however, the serial console may operate in
* a non-interrupt driven mode during the boot phase.
*
* RX and TX interrupts are not enabled when by the attach method (unless the
* hardware supports multiple levels of interrupt enabling). The RX and TX
* interrupts are not enabled until the txint() and rxint() methods are called.
*
****************************************************************************/
static int up_attach(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
int ret;
/* Attach the RDR full IRQ (RXI) that is enabled by the RIE SCR bit */
ret = irq_attach(priv->irq + SH1_RXI_IRQ_OFFSET, up_interrupt);
if (ret == OK)
{
/* The RIE interrupt enable also enables the receive error interrupt (ERI) */
ret = irq_attach(priv->irq + SH1_ERI_IRQ_OFFSET, up_interrupt);
if (ret == OK)
{
/* Attach the TDR empty IRQ (TXI) enabled by the TIE SCR bit */
ret = irq_attach(priv->irq + SH1_TXI_IRQ_OFFSET, up_interrupt);
if (ret == OK)
{
/* All SCI0 interrupts share the same prioritization */
up_prioritize_irq(priv->irq, 7); /* Set SCI priority midway */
/* Return OK on success */
return OK;
}
/* Detach the ERI interrupt on failure */
(void)irq_detach(priv->irq + SH1_ERI_IRQ_OFFSET);
}
/* Detach the RXI interrupt on failure */
(void)irq_detach(priv->irq + SH1_RXI_IRQ_OFFSET);
}
return ret;
}
/****************************************************************************
* Name: up_detach
*
* Description:
* Detach SCI interrupts. This method is called when the serial port is
* closed normally just before the shutdown method is called. The exception is
* the serial console which is never shutdown.
*
****************************************************************************/
static void up_detach(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
/* Disable all SCI interrupts */
up_disablesciint(priv, NULL);
/* Detach the SCI interrupts */
(void)irq_detach(priv->irq + SH1_RXI_IRQ_OFFSET);
(void)irq_detach(priv->irq + SH1_ERI_IRQ_OFFSET);
(void)irq_detach(priv->irq + SH1_RXI_IRQ_OFFSET);
/* Set the interrupt priority to zero (masking all SCI interrupts). NOTE
* that all SCI0 interrupts share the same prioritization.
*/
up_prioritize_irq(priv->irq, 0);
}
/****************************************************************************
* Name: up_interrupt
*
* Description:
* This is the SCI interrupt handler. It will be invoked
* when an interrupt received on the 'irq' It should call
* uart_transmitchars or uart_receivechar to perform the
* appropriate data transfers. The interrupt handling logic\
* must be able to map the 'irq' number into the approprite
* up_dev_s structure in order to call these functions.
*
****************************************************************************/
static int up_interrupt(int irq, void *context)
{
struct uart_dev_s *dev = NULL;
struct up_dev_s *priv;
#ifdef CONFIG_SH1_SCI0
if ((irq >= g_sci0priv.irq) &&
(irq <= g_sci0priv.irq + SH1_SCI_NIRQS))
{
dev = &g_sci0port;
}
else
#endif
#ifdef CONFIG_SH1_SCI1
if ((irq >= g_sci1priv.irq) &&
(irq <= g_sci1priv.irq + SH1_SCI_NIRQS))
{
dev = &g_sci1port;
}
else
#endif
{
PANIC(OSERR_INTERNAL);
}
priv = (struct up_dev_s*)dev->priv;
/* Get the current SCI status */
priv->ssr = up_serialin(priv, SH1_SCI_SSR_OFFSET);
/* Handle receive-related events with RIE is enabled. RIE is enabled at
* times that driver is open EXCEPT when the driver is actively copying
* data from the circular buffer. In that case, the read events must
* pend until RIE is set
*/
if ((priv->scr & SH1_SCISCR_RIE) != 0)
{
/* Handle incoming, receive bytes (RDRF: Receive Data Register Full) */
if ((priv->ssr & SH1_SCISSR_RDRF) != 0)
{
/* Rx data register not empty ... process incoming bytes */
uart_recvchars(dev);
}
/* Clear all read related events (probably already done in up_receive)) */
priv->ssr &= ~(SH1_SCISSR_RDRF|SH1_SCISSR_ORER|SH1_SCISSR_FER|SH1_SCISSR_PER);
}
/* Handle outgoing, transmit bytes (TDRE: Transmit Data Register Empty)
* when TIE is enabled. TIE is only enabled when the driver is waiting with
* buffered data. Since TDRE is usually true,
*/
if ((priv->ssr & SH1_SCISSR_TDRE) != 0 && (priv->scr & SH1_SCISCR_TIE) != 0)
{
/* Tx data register empty ... process outgoing bytes */
uart_xmitchars(dev);
/* Clear the TDR empty flag (Possibly done in up_send, will have not
* effect if the TDR is still empty)
*/
priv->ssr &= ~SH1_SCISSR_TDRE;
}
/* Clear all (clear-able) status flags. Note that that SH-1 requires
* that you read the bit in the "1" then write "0" to the bit in order
* to clear it. Any bits in the SSR that transitioned from 0->1 after
* we read the SR will not be effected by the following:
*/
up_serialout(priv, SH1_SCI_SSR_OFFSET, priv->ssr);
return OK;
}
/****************************************************************************
* Name: up_receive
*
* Description:
* Called (usually) from the interrupt level to receive one
* character from the SCI. Error bits associated with the
* receipt are provided in the return 'status'.
*
****************************************************************************/
static int up_receive(struct uart_dev_s *dev, unsigned int *status)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
uint8_t rdr;
uint8_t ssr;
/* Read the character from the RDR port */
rdr = up_serialin(priv, SH1_SCI_RDR_OFFSET);
/* Clear all read related status in real ssr (so that when when rxavailable
* is called again, it will return false.
*/
ssr = up_serialin(priv, SH1_SCI_SSR_OFFSET);
ssr &= ~(SH1_SCISSR_RDRF|SH1_SCISSR_ORER|SH1_SCISSR_FER|SH1_SCISSR_PER);
up_serialout(priv, SH1_SCI_SSR_OFFSET, ssr);
/* For status, return the SSR at the time that the interrupt was received */
*status = (uint32_t)priv->ssr << 8 | rdr;
/* Return the received character */
return (int)rdr;
}
/****************************************************************************
* Name: up_rxint
*
* Description:
* Call to enable or disable RX interrupts
*
****************************************************************************/
static void up_rxint(struct uart_dev_s *dev, bool enable)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
irqstate_t flags;
/* Disable interrupts to prevent asynchronous accesses */
flags = irqsave();
/* Are we enabling or disabling? */
if (enable)
{
/* Enable the RDR full interrupt */
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
priv->scr |= SH1_SCISCR_RIE;
#endif
}
else
{
/* Disable the RDR full interrupt */
priv->scr &= ~SH1_SCISCR_RIE;
}
/* Write the modified SCR value to hardware */
up_serialout(priv, SH1_SCI_SCR_OFFSET, priv->scr);
irqrestore(flags);
}
/****************************************************************************
* Name: up_rxavailable
*
* Description:
* Return true if the RDR is not empty
*
****************************************************************************/
static bool up_rxavailable(struct uart_dev_s *dev)
{
/* Return true if the RDR full bit is set in the SSR */
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
return ((up_serialin(priv, SH1_SCI_SSR_OFFSET) & SH1_SCISSR_RDRF) != 0);
}
/****************************************************************************
* Name: up_send
*
* Description:
* This method will send one byte on the SCI
*
****************************************************************************/
static void up_send(struct uart_dev_s *dev, int ch)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
uint8_t ssr;
/* Write the data to the TDR */
up_serialout(priv, SH1_SCI_TDR_OFFSET, (uint8_t)ch);
/* Clear the TDRE bit in the SSR */
ssr = up_serialin(priv, SH1_SCI_SSR_OFFSET);
ssr &= ~SH1_SCISSR_TDRE;
up_serialout(priv, SH1_SCI_SSR_OFFSET, ssr);
}
/****************************************************************************
* Name: up_txint
*
* Description:
* Call to enable or disable TX interrupts
*
****************************************************************************/
static void up_txint(struct uart_dev_s *dev, bool enable)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
irqstate_t flags;
/* Disable interrupts to prevent asynchronous accesses */
flags = irqsave();
/* Are we enabling or disabling? */
if (enable)
{
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
/* Enable the TDR empty interrupt */
priv->scr |= SH1_SCISCR_TIE;
/* If the TDR is already empty, then don't wait for the interrupt */
#if 1
if (up_txready(dev))
{
/* Tx data register empty ... process outgoing bytes. Note:
* this could call up_txint to be called recursively. However,
* in this event, priv->scr should hold the correct value upon
* return from uuart_xmitchars().
*/
uart_xmitchars(dev);
}
#endif
#endif
}
else
{
/* Disable the TDR empty interrupt */
priv->scr &= ~SH1_SCISCR_TIE;
}
/* Write the modified SCR value to hardware */
up_serialout(priv, SH1_SCI_SCR_OFFSET, priv->scr);
irqrestore(flags);
}
/****************************************************************************
* Name: up_txready
*
* Description:
* Return true if the TDR is empty
*
****************************************************************************/
static bool up_txready(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
return (up_serialin(priv, SH1_SCI_SSR_OFFSET) & SH1_SCISSR_TDRE) != 0;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_earlyconsoleinit
*
* Description:
* Performs the low level SCI initialization early in
* debug so that the serial console will be available
* during bootup. This must be called before up_consoleinit.
*
****************************************************************************/
void up_earlyconsoleinit(void)
{
/* NOTE: All GPIO configuration for the SCIs was performed in
* up_lowsetup
*/
/* Disable all SCIs */
#ifdef TTYS0_DEV
up_disablesciint(TTYS0_DEV.priv, NULL);
#ifdef TTYS1_DEV
up_disablesciint(TTYS1_DEV.priv, NULL);
#endif
#endif
/* Configuration whichever one is the console */
#ifdef HAVE_CONSOLE
CONSOLE_DEV.isconsole = true;
up_setup(&CONSOLE_DEV);
#endif
}
/****************************************************************************
* Name: up_consoleinit
*
* Description:
* Register serial console and serial ports. This assumes
* that up_earlyconsoleinit was called previously.
*
****************************************************************************/
void up_consoleinit(void)
{
/* Register the console */
#ifdef HAVE_CONSOLE
(void)uart_register("/dev/console", &CONSOLE_DEV);
#endif
/* Register all SCIs */
#ifdef TTYS0_DEV
(void)uart_register("/dev/ttyS0", &TTYS0_DEV);
#ifdef TTYS1_DEV
(void)uart_register("/dev/ttyS1", &TTYS1_DEV);
#endif
#endif
}
/****************************************************************************
* Name: up_putc
*
* Description:
* Provide priority, low-level access to support OS debug writes
*
****************************************************************************/
int up_putc(int ch)
{
#ifdef HAVE_CONSOLE
struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv;
uint8_t scr;
up_disablesciint(priv, &scr);
/* Check for LF */
if (ch == '\n')
{
/* Add CR */
up_waittxready(priv);
up_serialout(priv, SH1_SCI_TDR_OFFSET, '\r');
}
up_waittxready(priv);
up_serialout(priv, SH1_SCI_TDR_OFFSET, (uint8_t)ch);
up_waittxready(priv);
up_restoresciint(priv, scr);
#endif
return ch;
}
#else /* CONFIG_USE_SERIALDRIVER */
/****************************************************************************
* Name: up_putc
*
* Description:
* Provide priority, low-level access to support OS debug writes
*
****************************************************************************/
int up_putc(int ch)
{
#ifdef HAVE_CONSOLE
/* Check for LF */
if (ch == '\n')
{
/* Add CR */
up_lowputc('\r');
}
up_lowputc(ch);
#endif
return ch;
}
#endif /* CONFIG_USE_SERIALDRIVER */
|