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/****************************************************************************
* drivers/net/enc28j60.h
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __DRIVERS_NET_ENC28J60_H
#define __DRIVERS_NET_ENC28J60_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* A total of seven instructions are implemented on the ENC28J60 */
#define ENC28J60_RCR (0x00) /* Read Control Register
* 000 | aaaaa | (Registe value returned)) */
#define ENC28J60_RBM (0x3a) /* Read Buffer Memory
* 001 | 11010 | (Read buffer data follows) */
#define ENC28J60_WCR (0x40) /* Write Control Register
* 010 | aaaaa | dddddddd */
#define ENC28J60_WBM (0x7a) /* Write Buffer Memory
* 011 | 11010 | (Write buffer data follows) */
#define ENC28J60_BFS (0x80) /* Bit Field Set
* 100 | aaaaa | dddddddd */
#define ENC28J60_BFC (0xa0) /* Bit Field Clear
* 101 | aaaaa | dddddddd */
#define ENC28J60_SRC (0xff) /* System Reset
* 111 | 11111 | (No data) */
/* Control registers are accessed with the RCR, RBM, WCR, BFS, and BFC commands.
* The following identifies all ENC28J60 control registers. The Control register
* memory is partitioned into four banks, selectable by the bank select bits,
* BSEL1:BSEL0, in the ECON1 register.
*
* The last five locations (0x1b to 0x1f) of all banks point to a common set of
* registers: EIE, EIR, ESTAT, ECON2 and ECON1. These are key registers used
* in controlling and monitoring the operation of the device. Their common
* mapping allows easy access without switching the bank.
*
* Control registers for the ENC28J60 are generically grouped as ETH, MAC and
* MII registers. Register names starting with E belong to the ETH group. Similarly,
* registers names starting with MA belong to the MAC group and registers prefixed
* with MI belong to the MII group.
*/
#define EIE (0x1b) /* Ethernet Interrupt Enable Register */
#define EIR (0x1c) /* Ethernet Interupt Request Register */
#define ESTAT (0x1d) /* Ethernet Status Register */
#define ECON2 (0x1e) /* Ethernet Control 2 Register */
#define ECON1 (0x1f) /* Ethernet Control 1 Register */
/* The remaining control registers are identified with a a 5 bit address and a
* bank selection. We pack the bank number and the control register address
* together to keep the design simpler.
*/
#define ENC28J60_ADDR_SHIFT (0) /* Bits 0-4: Register address */
#define ENC28J60_ADDR_MASK (0x1f << ENC28J60_ADDR_SHIFT)
#define ENC28J60_BANK_SHIFT (5) /* Bits 5-6: Bank number */
#define ENC28J60_BANK_MASK (3 << ENC28J60_BSEL_SHIFT)
# define ENC28J60_BANK0 (0 << ENC28J60_BSEL_SHIFT)
# define ENC28J60_BANK1 (1 << ENC28J60_BSEL_SHIFT)
# define ENC28J60_BANK2 (2 << ENC28J60_BSEL_SHIFT)
# define ENC28J60_BANK3 (3 << ENC28J60_BSEL_SHIFT)
#define REGADDR(a,b) ((b) << ENC28J60_BANK_SHIFT | (a))
#define GETADDR(a) ((a) & ENC28J60_ADDR_MASK)
#define GETBANK(a) (((a) >> ENC28J60_BANK_SHIFT) & 3)
/* Bank 0 Control Register Addresses */
#define ERDPTL REGADDR(0x00, 0) /* Read Pointer Low Byte (ERDPT<7:0> */
#define ERDPTH REGADDR(0x01, 0) /* Read Pointer High Byte (ERDPT<12:8>) */
#define EWRPTL REGADDR(0x02, 0) /* Write Pointer Low Byte (EWRPT<7:0>) */
#define EWRPTH REGADDR(0x03, 0) /* Write Pointer High Byte (EWRPT<12:8>) */
#define ETXSTL REGADDR(0x04, 0) /* TX Start Low Byte (ETXST<7:0>) */
#define ETXSTH REGADDR(0x05, 0) /* TX Start High Byte (ETXST<12:8>) */
#define ETXNDL REGADDR(0x06, 0) /* TX End Low Byte (ETXND<7:0>) */
#define ETXNDH REGADDR(0x07, 0) /* TX End High Byte (ETXND<12:8>) */
#define ERXSTL REGADDR(0x08, 0) /* RX Start Low Byte (ERXST<7:0>) */
#define ERXSTH REGADDR(0x09, 0) /* RX Start High Byte (ERXST<12:8>) */
#define ERXNDL REGADDR(0x0a, 0) /* RX End Low Byte (ERXND<7:0>) */
#define ERXNDH REGADDR(0x0b, 0) /* RX End High Byte (ERXND<12:8>) */
#define ERXRDPTL REGADDR(0x0c, 0) /* RX RD Pointer Low Byte (ERXRDPT<7:0>) */
#define ERXRDPTH REGADDR(0x0d, 0) /* RX RD Pointer High Byte (ERXRDPT<12:8>) */
#define ERXWRPTL REGADDR(0x0e, 0) /* RX WR Pointer Low Byte (ERXWRPT<7:0>) */
#define ERXWRPTH REGADDR(0x0f, 0) /* RX WR Pointer High Byte (ERXWRPT<12:8>) */
#define EDMASTL REGADDR(0x10, 0) /* DMA Start Low Byte (EDMAST<7:0>) */
#define EDMASTH REGADDR(0x11, 0) /* DMA Start High Byte (EDMAST<12:8>) */
#define EDMANDL REGADDR(0x12, 0) /* DMA End Low Byte (EDMAND<7:0>) */
#define EDMANDH REGADDR(0x13, 0) /* DMA End High Byte (EDMAND<12:8>) */
#define EDMADSTL REGADDR(0x14, 0) /* DMA Destination Low Byte (EDMADST<7:0>) */
#define EDMADSTH REGADDR(0x15, 0) /* DMA Destination High Byte (EDMADST<12:8>) */
#define EDMACSL REGADDR(0x16, 0) /* DMA Checksum Low Byte (EDMACS<7:0>) */
#define EDMACSH REGADDR(0x17, 0) /* DMA Checksum High Byte (EDMACS<15:8>) */
/* 0x18-0x1a: Reserved */
/* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */
/* Bank 1 Control Register Addresses */
#define EHT0 REGADDR(0x00, 1) /* Hash Table Byte 0 (EHT<7:0>) */
#define EHT1 REGADDR(0x01, 1) /* Hash Table Byte 1 (EHT<15:8>) */
#define EHT2 REGADDR(0x02, 1) /* Hash Table Byte 2 (EHT<23:16>) */
#define EHT3 REGADDR(0x03, 1) /* Hash Table Byte 3 (EHT<31:24>) */
#define EHT4 REGADDR(0x04, 1) /* Hash Table Byte 4 (EHT<39:32>) */
#define EHT5 REGADDR(0x05, 1) /* Hash Table Byte 5 (EHT<47:40>) */
#define EHT6 REGADDR(0x06, 1) /* Hash Table Byte 6 (EHT<55:48>) */
#define EHT7 REGADDR(0x07, 1) /* Hash Table Byte 7 (EHT<63:56>) */
#define EPMM0 REGADDR(0x08, 1) /* Pattern Match Mask Byte 0 (EPMM<7:0>) */
#define EPMM1 REGADDR(0x09, 1) /* Pattern Match Mask Byte 1 (EPMM<15:8>) */
#define EPMM2 REGADDR(0x0a, 1) /* Pattern Match Mask Byte 2 (EPMM<23:16>) */
#define EPMM3 REGADDR(0x0b, 1) /* Pattern Match Mask Byte 3 (EPMM<31:24>) */
#define EPMM4 REGADDR(0x0c, 1) /* Pattern Match Mask Byte 4 (EPMM<39:32>) */
#define EPMM5 REGADDR(0x0d, 1) /* Pattern Match Mask Byte 5 (EPMM<47:40>) */
#define EPMM6 REGADDR(0x0e, 1) /* Pattern Match Mask Byte 6 (EPMM<55:48>) */
#define EPMM7 REGADDR(0x0f, 1) /* Pattern Match Mask Byte 7 (EPMM<63:56>) */
#define EPMCSL REGADDR(0x10, 1) /* Pattern Match Checksum Low Byte (EPMCS<7:0>) */
#define EPMCSH REGADDR(0x11, 1) /* Pattern Match Checksum High Byte (EPMCS<15:0>) */
/* 0x12-0x13: Reserved */
#define EPMOL REGADDR(0x14, 1) /* Pattern Match Offset Low Byte (EPMO<7:0>) */
#define EPMOH REGADDR(0x15, 1) /* Pattern Match Offset High Byte (EPMO<12:8>) */
/* 0x16-0x17: Reserved */
#define ERXFCON REGADDR(0x18, 1) /* Receive Filter Configuration */
#define EPKTCNT REGADDR(0x19, 1) /* Ethernet Packet Count */
/* 0x1a: Reserved */
/* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */
/* Bank 2 Control Register Addresses */
#define MACON1 REGADDR(0x00, 2) /* MAC control 1 */
#define MACON2 REGADDR(0x01, 2) /* MAC control 2 */
#define MACON3 REGADDR(0x02, 2) /* MAC control 3 */
#define MACON4 REGADDR(0x03, 2) /* MAC control 4 */
#define MABBIPG REGADDR(0x04, 2) /* Back-to-Back Inter-Packet Gap (BBIPG<6:0>) */
/* 0x05: Reserved */
#define MAIPGL REGADDR(0x06, 2) /* Non-Back-to-Back Inter-Packet Gap Low Byte (MAIPGL<6:0>) */
#define MAIPGH REGADDR(0x07, 2) /* Non-Back-to-Back Inter-Packet Gap High Byte (MAIPGH<6:0>) */
#define MACLCON1 REGADDR(0x08, 2) /* MAC Collision Control 1 */
#define MACLCON2 REGADDR(0x09, 2) /* MAC Collision Control 2 */
#define MAMXFLL REGADDR(0x0a, 2) /* Maximum Frame Length Low Byte (MAMXFL<7:0>) */
#define MAMXFLH REGADDR(0x0b, 2) /* Maximum Frame Length High Byte (MAMXFL<15:8>) */
/* 0x0c-0x11: Reserved */
#define MICMD REGADDR(0x12, 2) /* MII Command Register */
/* 0x13: Reserved */
#define MIREGADR REGADDR(0x14, 2) /* MII Register Address */
/* 0x15: Reserved */
#define MIWRL REGADDR(0x16, 2) /* MII Write Data Low Byte (MIWR<7:0>) */
#define MIWRH REGADDR(0x17, 2) /* MII Write Data High Byte (MIWR<15:8>) */
#define MIRDL REGADDR(0x18, 2) /* MII Read Data Low Byte (MIRD<7:0>) */
#define MIRDH REGADDR(0x19, 2) /* MII Read Data High Byte(MIRD<15:8>) */
/* 0x1a: Reserved */
/* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */
/* Bank 3 Control Register Addresses */
#define MAADR5 REGADDR(0x00, 3) /* MAC Address Byte 5 (MAADR<15:8>) */
#define MAADR6 REGADDR(0x01, 3) /* MAC Address Byte 6 (MAADR<7:0>) */
#define MAADR3 REGADDR(0x02, 3) /* MAC Address Byte 3 (MAADR<31:24>), OUI Byte 3 */
#define MAADR4 REGADDR(0x03, 3) /* MAC Address Byte 4 (MAADR<23:16>) */
#define MAADR1 REGADDR(0x04, 3) /* MAC Address Byte 1 (MAADR<47:40>), OUI Byte 1 */
#define MAADR2 REGADDR(0x05, 3) /* MAC Address Byte 2 (MAADR<39:32>), OUI Byte */
#define EBSTSD REGADDR(0x06, 3) /* Built-in Self-Test Fill Seed (EBSTSD<7:0>) */
#define EBSTCON REGADDR(0x07, 3) /* Built-in Self-Test Control */
#define EBSTCSL REGADDR(0x08, 3) /* Built-in Self-Test Checksum Low Byte (EBSTCS<7:0>) */
#define EBSTCSH REGADDR(0x09, 3) /* Built-in Self-Test Checksum High Byte (EBSTCS<15:8>) */
#define MISTAT REGADDR(0x0a, 3) /* MII Status Register */
/* 0x0b-0x11: Reserved */
#define EREVID REGADDR(0x12, 3) /* Ethernet Revision ID */
/* 0x13-0x14: Reserved */
#define ECOCON REGADDR(0x15, 3) /* Clock Output Control */
/* 0x16: Reserved */
#define EFLOCON REGADDR(0x17, 3) /* Ethernet Flow Control */
#define EPAUSL REGADDR(0x18, 3) /* Pause Timer Value Low Byte (EPAUS<7:0>) */
#define EPAUSH REGADDR(0x19, 3) /* Pause Timer Value High Byte (EPAUS<15:8>) */
/* 0x1a: Reserved */
/* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */
/* Ethernet Interrupt Enable Register Bit Definitions */
#define EIE_RXERIE (1 << 0) /* Bit 0: Receive Error Interrupt Enable */
#define EIE_TXERIE (1 << 1) /* Bit 1: Transmit Error Interrupt Enable */
/* Bit 2: Reserved */
#define EIE_TXIE (1 << 3) /* Bit 3: Transmit Enable */
#define EIE_LINKIE (1 << 4) /* Bit 4: Link Status Change Interrupt Enable */
#define EIE_DMAIE (1 << 5) /* Bit 5: DMA Interrupt Enable */
#define EIE_PKTIE (1 << 6) /* Bit 6: Receive Packet Pending Interrupt Enable */
#define EIE_INTIE (1 << 7) /* Bit 7: Global INT Interrupt Enable */
/* Ethernet Interupt Request Register Bit Definitions */
#define EIR_RXERIF (1 << 0) /* Bit 0: Receive Error Interrupt */
#define EIR_TXERIF (1 << 1) /* Bit 1: Transmit Error Interrupt */
/* Bit 2: Reserved */
#define EIR_TXIF (1 << 3) /* Bit 3: Transmit Interrupt */
#define EIR_LINKIF (1 << 4) /* Bit 4: Link Change Interrupt */
#define EIR_DMAIF (1 << 5) /* Bit 5: DMA Interrupt */
#define EIR_PKTIF (1 << 6) /* Bit 6: Receive Packet Pending Interrupt */
/* Bit 7: Reserved */
/* Ethernet Status Register Bit Definitions */
#define ESTAT_CLKRDY (1 << 0) /* Bit 0: Clock Ready */
#define ESTAT_TXABRT (1 << 1) /* Bit 1: Transmit Abort Error */
#define ESTAT_RXBUSY (1 << 2) /* Bit 2: Receive Busy */
/* Bit 3: Reserved */
#define ESTAT_LATECOL (1 << 4) /* Bit 4: Late Collision Error */
/* Bit 5: Reserved */
#define ESTAT_BUFER (1 << 6) /* Bit 6: Ethernet Buffer Error Status */
#define ESTAT_INT (1 << 7) /* Bit 7: INT Interrupt */
/* Ethernet Control 1 Register Bit Definitions */
#define ECON1_BSEL_SHIFT (0) /* Bits 0-1: Bank select */
#define ECON1_BSEL_MASK (3 << ECON1_BSEL_SHIFT)
# define ECON1_BSEL_BANK0 (0 << 0) /* Bank 0 */
# define ECON1_BSEL_BANK1 (1 << 1) /* Bank 1 */
# define ECON1_BSEL_BANK2 (2 << 0) /* Bank 2 */
# define ECON1_BSEL_BANK3 (3 << 0) /* Bank 3 */
#define ECON1_RXEN (1 << 2) /* Bit 2: Receive Enable */
#define ECON1_TXRTS (1 << 3) /* Bit 3: Transmit Request to Send */
#define ECON1_CSUMEN (1 << 4) /* Bit 4: DMA Checksum Enable */
#define ECON1_DMAST (1 << 5) /* Bit 5: DMA Start and Busy Status */
#define ECON1_RXRST (1 << 6) /* Bit 6: Receive Logic Reset */
#define ECON1_TXRST (1 << 7) /* Bit 7: Transmit Logic Reset */
/* Ethernet Control 2 Register */
/* Bits 0-2: Reserved */
#define ECON2_VRPS (1 << 3) /* Bit 3: Voltage Regulator Power Save Enable */
/* Bit 4: Reserved */
#define ECON2_PWRSV (1 << 5) /* Bit 5: Power Save Enable */
#define ECON2_PKTDEC (1 << 6) /* Bit 6: Packet Decrement */
#define ECON2_AUTOINC (1 << 7) /* Bit 7: Automatic Buffer Pointer Increment Enable */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __DRIVERS_NET_ENC28J60_H */
|
