More trailing whilespace removal

24 files changed, 142 insertions, 143 deletions

diff --git a/nuttx/arch/arm/src/lpc43xx/Make.defs b/nuttx/arch/arm/src/lpc43xx/Make.defs
index e2d5ea0b1..366c051df 100644
--- a/nuttx/arch/arm/src/lpc43xx/Make.defs
+++ b/nuttx/arch/arm/src/lpc43xx/Make.defs
@@ -82,7 +82,7 @@ CMN_CSRCS += up_copyarmstate.c
 endif
 endif
 
-CHIP_ASRCS  = 
+CHIP_ASRCS  =
 CHIP_CSRCS  = lpc43_allocateheap.c lpc43_cgu.c lpc43_clrpend.c lpc43_gpio.c
 CHIP_CSRCS += lpc43_irq.c lpc43_pinconfig.c lpc43_rgu.c lpc43_serial.c
 CHIP_CSRCS += lpc43_start.c lpc43_timerisr.c lpc43_uart.c
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_aes.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_aes.h
index 74e53d616..e5f66d5f1 100644
--- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_aes.h
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_aes.h
@@ -58,9 +58,9 @@
 enum lpc43_aescmd_e
 {
   AES_API_CMD_ENCODE_ECB = 0,
-  AES_API_CMD_DECODE_ECB = 1, 
-  AES_API_CMD_ENCODE_CBC = 2, 
-  AES_API_CMD_DECODE_CBC = 3 
+  AES_API_CMD_DECODE_ECB = 1,
+  AES_API_CMD_ENCODE_CBC = 2,
+  AES_API_CMD_DECODE_CBC = 3
 };
 
 struct lpc43_aes_s
@@ -89,7 +89,7 @@ struct lpc43_aes_s
   void (*aes_LoadKeySW)(unsigned char *key);
 
   /* Loads 128-bit AES initialization vector (16 bytes) */
- 
+
   void (*aes_LoadIV_SW)(unsigned char *iv);
 
   /* Loads 128-bit AES IC specific initialization vector, which is used to decrypt
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_ethernet.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_ethernet.h
index e7d16fe26..275f896ad 100644
--- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_ethernet.h
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_ethernet.h
@@ -606,7 +606,7 @@
 
 /* Ethernet TX DMA Descriptor.  Descriptor size can be 4 DWORDS (16 bytes) or 8 DWORDS (32 bytes)
  * depending on the setting of the ATDS bit in the DMA Bus Mode register.
- */ 
+ */
 
 struct eth_txdesc_s
 {
@@ -629,7 +629,7 @@ struct eth_txdesc_s
 
 /* Ethernet RX DMA Descriptor.  Descriptor size can be 4 DWORDS (16 bytes) or 8 DWORDS (32 bytes)
  * depending on the setting of the ATDS bit in the DMA Bus Mode register.
- */ 
+ */
 
 struct eth_rxdesc_s
 {
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_evntrtr.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_evntrtr.h
index 644e6758e..1287dfd87 100644
--- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_evntrtr.h
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_evntrtr.h
@@ -90,7 +90,7 @@
 #define EVNTRTR_SOURCE_TIM6          14 /* Combined timer output 6 (SCT output 6 | TIMER1 Ch2) */
 #define EVNTRTR_SOURCE_QEI           15 /* QEI interrupt */
 #define EVNTRTR_SOURCE_TIM14         16 /* Combined timer output 14 (SCT output 14 | TIMER3 Ch2) */
-                                        /* 17-18: Reserved */              
+                                        /* 17-18: Reserved */
 #define EVNTRTR_SOURCE_RESET         19 /* Reset event */
 
 #define EVNTRTR_WAKEUP0              (1 << EVNTRTR_SOURCE_WAKEUP0)
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gpdma.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gpdma.h
index f885c1387..2139e0976 100644
--- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gpdma.h
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gpdma.h
@@ -252,7 +252,6 @@
 
 #define GPDMA_SOFTLBREQ(n)                (1 << (n)) /* Bits 0-15: Software last burst request flags for source n */
                                                      /* Bits 16-31: Reserved */
-                                                     
 /* DMA Software Last Single Request Register */
 
 #define GPDMA_SOFTLSREQ(n)                (1 << (n)) /* Bits 0-15: Software last single burst request flags for source n */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_mcpwm.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_mcpwm.h
index 6344c24c9..720b8affc 100644
--- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_mcpwm.h
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_mcpwm.h
@@ -257,7 +257,7 @@
 #define MCPWM_CAPCLR_CLR0            (1 << 0)  /* Bit 0:  Clear CAP0 register */
 #define MCPWM_CAPCLR_CLR1            (1 << 1)  /* Bit 1:  Clear CAP1 register */
 #define MCPWM_CAPCLR_CLR2            (1 << 2)  /* Bit 2:  Clear CAP2 register */
-                                               /* Bits 2-31: Reserved */ 
+                                               /* Bits 2-31: Reserved */
 
 /************************************************************************************
  * Public Types
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_otp.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_otp.h
index 67b5af319..45a777fd9 100644
--- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_otp.h
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_otp.h
@@ -59,7 +59,7 @@
 
 #define LPC43_OTP_MEM20_OFFSET   0x0034  /* General purpose OTP memory 2, word 0 */
 #define LPC43_OTP_MEM21_OFFSET   0x0038  /* General purpose OTP memory 2, word 1 */
-#define LPC43_OTP_MEM22_OFFSET   0x003c  /* General purpose OTP memory 2, word 2 */ 
+#define LPC43_OTP_MEM22_OFFSET   0x003c  /* General purpose OTP memory 2, word 2 */
 
 #define LPC43_OTP_AES00_OFFSET   0x0010  /* AES key 0, word 0 */
 #define LPC43_OTP_AES01_OFFSET   0x0014  /* AES key 0, word 1 */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_spifi.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_spifi.h
index a0bec7592..26cf82734 100644
--- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_spifi.h
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_spifi.h
@@ -88,7 +88,7 @@
 #define SPIFI_PROG_INST         2
 #define SPIFI_CHIP_ERASE        3
 
-/* Bit definitions in options operands (MODE3, RCVCLK, and FULLCLK 
+/* Bit definitions in options operands (MODE3, RCVCLK, and FULLCLK
  * have the same relationship as in the Control register)
  */
 
@@ -117,7 +117,7 @@
 
 /* SPI ROM driver table pointer */
 
-#define SPIFI_ROM_PTR LPC43_ROM_DRIVER_TABLE6 
+#define SPIFI_ROM_PTR LPC43_ROM_DRIVER_TABLE6
 #define pSPIFI *((struct spifi_driver_s **)SPIFI_ROM_PTR)
 
 /****************************************************************************
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_usb0.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_usb0.h
index 6d18dd41c..42ef4ba8d 100644
--- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_usb0.h
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_usb0.h
@@ -147,25 +147,25 @@
 
 /* Device side naming of common register offsets */
 
-#define LPC43_USBDEV_USBCMD                  LPC43_USBOTG_USBCMD       
-#define LPC43_USBDEV_USBSTS                  LPC43_USBOTG_USBSTS       
-#define LPC43_USBDEV_USBINTR                 LPC43_USBOTG_USBINTR       
-#define LPC43_USBDEV_FRINDEX                 LPC43_USBOTG_FRINDEX       
-#define LPC43_USBDEV_BURSTSIZE               LPC43_USBOTG_BURSTSIZE       
-#define LPC43_USBDEV_BINTERVAL               LPC43_USBOTG_BINTERVAL       
-#define LPC43_USBDEV_PORTSC1                 LPC43_USBOTG_USBMODE       
-#define LPC43_USBDEV_USBMODE                 LPC43_USBOTG_USBMODE       
+#define LPC43_USBDEV_USBCMD                  LPC43_USBOTG_USBCMD
+#define LPC43_USBDEV_USBSTS                  LPC43_USBOTG_USBSTS
+#define LPC43_USBDEV_USBINTR                 LPC43_USBOTG_USBINTR
+#define LPC43_USBDEV_FRINDEX                 LPC43_USBOTG_FRINDEX
+#define LPC43_USBDEV_BURSTSIZE               LPC43_USBOTG_BURSTSIZE
+#define LPC43_USBDEV_BINTERVAL               LPC43_USBOTG_BINTERVAL
+#define LPC43_USBDEV_PORTSC1                 LPC43_USBOTG_USBMODE
+#define LPC43_USBDEV_USBMODE                 LPC43_USBOTG_USBMODE
 
 /* Host side naming of common registers */
 
-#define LPC43_USBHOST_USBCMD                 LPC43_USBOTG_USBCMD       
-#define LPC43_USBHOST_USBSTS                 LPC43_USBOTG_USBSTS       
-#define LPC43_USBHOST_USBINTR                LPC43_USBOTG_USBINTR       
-#define LPC43_USBHOST_FRINDEX                LPC43_USBOTG_FRINDEX       
-#define LPC43_USBHOST_BURSTSIZE              LPC43_USBOTG_BURSTSIZE       
-#define LPC43_USBHOST_BINTERVAL              LPC43_USBOTG_BINTERVAL       
-#define LPC43_USBHOST_PORTSC1                LPC43_USBOTG_USBMODE       
-#define LPC43_USBHOST_USBMODE                LPC43_USBOTG_USBMODE       
+#define LPC43_USBHOST_USBCMD                 LPC43_USBOTG_USBCMD
+#define LPC43_USBHOST_USBSTS                 LPC43_USBOTG_USBSTS
+#define LPC43_USBHOST_USBINTR                LPC43_USBOTG_USBINTR
+#define LPC43_USBHOST_FRINDEX                LPC43_USBOTG_FRINDEX
+#define LPC43_USBHOST_BURSTSIZE              LPC43_USBOTG_BURSTSIZE
+#define LPC43_USBHOST_BINTERVAL              LPC43_USBOTG_BINTERVAL
+#define LPC43_USBHOST_PORTSC1                LPC43_USBOTG_USBMODE
+#define LPC43_USBHOST_USBMODE                LPC43_USBOTG_USBMODE
 
 /* Device endpoint registers */
 
@@ -381,13 +381,13 @@
 /* USB burst size register BURSTSIZE -- Device/Host Mode */
 
 #define USBHOST_BURSTSIZE_RXPBURST_SHIFT     (0)       /* Bits 0-7: RXPBURST Programmable RX burst length */
-#define USBHOST_BURSTSIZE_RXPBURST_MASK      (255 << USBHOST_BURSTSIZE_RXPBURST_SHIFT) 
+#define USBHOST_BURSTSIZE_RXPBURST_MASK      (255 << USBHOST_BURSTSIZE_RXPBURST_SHIFT)
 #define USBHOST_BURSTSIZE_TXPBURST_SHIFT     (8)       /* Bits 8-15: Programmable TX burst length */
 #define USBHOST_BURSTSIZE_TXPBURST_MASK      (255 << USBHOST_BURSTSIZE_TXPBURST_SHIFT)
                                                        /* Bits 16-31: Reserved */
 
 #define USBDEV_BURSTSIZE_RXPBURST_SHIFT      (0)       /* Bits 0-7: RXPBURST Programmable RX burst length */
-#define USBDEV_BURSTSIZE_RXPBURST_MASK       (255 << USBDEV_BURSTSIZE_RXPBURST_SHIFT) 
+#define USBDEV_BURSTSIZE_RXPBURST_MASK       (255 << USBDEV_BURSTSIZE_RXPBURST_SHIFT)
 #define USBDEV_BURSTSIZE_TXPBURST_SHIFT      (8)       /* Bits 8-15: Programmable TX burst length */
 #define USBDEV_BURSTSIZE_TXPBURST_MASK       (255 << USBDEV_BURSTSIZE_TXPBURST_SHIFT)
                                                        /* Bits 16-31: Reserved */
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_adc.c b/nuttx/arch/arm/src/lpc43xx/lpc43_adc.c
index d03abb162..71f1181e6 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_adc.c
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_adc.c
@@ -9,7 +9,7 @@
  *   Copyright (C) 2011 Li Zhuoyi. All rights reserved.
  *   Author: Li Zhuoyi <lzyy.cn@gmail.com>
  *   History: 0.1 2011-08-05 initial version
- * 
+ *
  * This file is a part of NuttX:
  *
  *   Copyright (C) 2010-2012 Gregory Nutt. All rights reserved.
@@ -181,7 +181,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
     lpc43_configgpio(GPIO_AD0p6);
   else if (priv->mask&0x80)
     lpc43_configgpio(GPIO_AD0p7);
-    
+
   irqrestore(flags);
 }
 
@@ -244,7 +244,7 @@ static int adc_interrupt(int irq, void *context)
   FAR struct up_dev_s *priv = (FAR struct up_dev_s *)g_adcdev.ad_priv;
   unsigned char ch;
   int32_t value;
-    
+
   regval = getreg32(LPC43_ADC_GDR);
   ch = (regval >> 24) & 0x07;
   priv->buf[ch] += regval & 0xfff0;
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_allocateheap.c b/nuttx/arch/arm/src/lpc43xx/lpc43_allocateheap.c
index d5d12aa54..0dd84e1ae 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_allocateheap.c
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_allocateheap.c
@@ -266,7 +266,7 @@ void up_addregion(void)
 {
 #if CONFIG_MM_REGIONS > 1
  /* Add the next SRAM region (which should exist) */
- 
+
  kmm_addregion((FAR void*)MM_REGION2_BASE, MM_REGION2_SIZE);
 
 #ifdef MM_REGION3_BASE
@@ -274,12 +274,12 @@ void up_addregion(void)
 
 #if CONFIG_MM_REGIONS > 2
  /* Add the third SRAM region (which may not exist) */
- 
+
  kmm_addregion((FAR void*)MM_REGION3_BASE, MM_REGION3_SIZE);
 
 #if CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE)
  /* Add the DMA region (which may not be available) */
- 
+
  kmm_addregion((FAR void*)MM_DMAHEAP_BASE, MM_DMAHEAP_SIZE);
 
 #endif /* CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE) */
@@ -288,7 +288,7 @@ void up_addregion(void)
 
 #if CONFIG_MM_REGIONS > 2 && defined(MM_DMAHEAP_BASE)
  /* Add the DMA region (which may not be available) */
- 
+
  kmm_addregion((FAR void*)MM_DMAHEAP_BASE, MM_DMAHEAP_SIZE);
 
 #endif /* CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE) */
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_cgu.c b/nuttx/arch/arm/src/lpc43xx/lpc43_cgu.c
index 61c4112ae..dcb446648 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_cgu.c
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_cgu.c
@@ -350,7 +350,7 @@ static inline void lpc43_pll1config(uint32_t ctrlvalue)
   regval &= ~(PLL1_CTRL_BYPASS    | PLL1_CTRL_FBSEL     | PLL1_CTRL_DIRECT |
               PLL1_CTRL_PSEL_MASK | PLL1_CTRL_NSEL_MASK |
               PLL1_CTRL_MSEL_MASK);
-  
+
   /* Set selected PLL1 controls:
    *
    *   - PLL1_CTRL_FBSEL:     Set in both integer and direct modes
@@ -380,7 +380,7 @@ static inline void lpc43_pll1enable(void)
   /* Take PLL1 out of power down mode.  The reset state of the PD bit
    * is one, i.e., powered down.
    */
-  
+
   regval  = getreg32(LPC43_PLL1_CTRL);
   regval &= ~PLL1_CTRL_PD;
   putreg32(regval, LPC43_PLL1_CTRL);
@@ -441,7 +441,7 @@ void lpc43_clockconfig(void)
   /* Enable PLL1 */
 
   lpc43_pll1enable();
- 
+
   /* Set up PLL1 output as the M4 clock */
 
   lpc43_m4clkselect(BASE_M4_CLKSEL_PLL1);
@@ -477,6 +477,6 @@ void lpc43_clockconfig(void)
 
   /* Go to the final, full-speed PLL1 configuration */
 
-  lpc43_pll1config(PLL_CONTROLS);  
+  lpc43_pll1config(PLL_CONTROLS);
 #endif
 }
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_dac.c b/nuttx/arch/arm/src/lpc43xx/lpc43_dac.c
index 5fcceaa1e..ba102c185 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_dac.c
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_dac.c
@@ -9,7 +9,7 @@
  *   Copyright (C) 2011 Li Zhuoyi. All rights reserved.
  *   Author: Li Zhuoyi <lzyy.cn@gmail.com>
  *   History: 0.1 2011-08-05 initial version
- * 
+ *
  * This file is a part of NuttX:
  *
  *   Copyright (C) 2010-2012 Gregory Nutt. All rights reserved.
@@ -121,7 +121,7 @@ static void dac_reset(FAR struct dac_dev_s *dev)
 {
   irqstate_t flags;
   uint32_t regval;
-    
+
   flags = irqsave();
 
   regval  = getreg32(LPC43_SYSCON_PCLKSEL0);
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_gpio.c b/nuttx/arch/arm/src/lpc43xx/lpc43_gpio.c
index 2b2c88f31..aaa18eccd 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_gpio.c
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_gpio.c
@@ -92,7 +92,7 @@ static inline void lpc43_configinput(uint16_t gpiocfg,
   regval  = getreg32(regaddr);
   regval &= ~GPIO_DIR(pin);
   putreg32(regval, regaddr);
-  
+
   /* To be able to read the signal on the GPIO input, the input
    * buffer must be enabled in the syscon block for the corresponding pin.
    * This should have been done when the pin was configured as a GPIO.
@@ -147,7 +147,7 @@ static inline void lpc43_configoutput(uint16_t gpiocfg,
  *
  * Description:
  *   Configure a GPIO based on bit-encoded description of the pin.  NOTE:
- *   The pin *must* have first been configured for GPIO usage with a 
+ *   The pin *must* have first been configured for GPIO usage with a
  *   corresponding call to lpc43_pin_config().
  *
  * Returned Value:
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_idle.c b/nuttx/arch/arm/src/lpc43xx/lpc43_idle.c
index e7be94e51..55631bc35 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_idle.c
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_idle.c
@@ -86,7 +86,7 @@ static void up_idlepm(void)
   enum pm_state_e newstate;
   irqstate_t flags;
   int ret;
-  
+
   /* Decide, which power saving level can be obtained */
 
   newstate = pm_checkstate();
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.c b/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.c
index fb5173339..77b979607 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.c
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.c
@@ -120,7 +120,7 @@ int lpc43_pin_config(uint32_t pinconf)
    {
      regval |= SCU_NDPIN_EHS; /* 0=slow; 1=fast */
    }
- 
+
   /* Only high drive pins suppose drive strength */
 
   switch (pinconf & PINCONF_DRIVE_MASK)
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.h b/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.h
index 293f838e9..fba0e1e49 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.h
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.h
@@ -183,7 +183,7 @@
  * ---- ---- ---- ---- ----
  * .... .... .... ...P PPPP
  */
- 
+
 #define PINCONF_PIN_SHIFT             (0)        /* Bits 0-4: Pin number */
 #define PINCONF_PIN_MASK              (31 << PINCONF_PIN_SHIFT)
 #  define PINCONF_PIN_0               (0 << PINCONF_PIN_SHIFT)
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_serial.c b/nuttx/arch/arm/src/lpc43xx/lpc43_serial.c
index a4d60dc15..df68c1301 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_serial.c
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_serial.c
@@ -617,7 +617,7 @@ static int up_setup(struct uart_dev_s *dev)
                (UART_FCR_RXTRIGGER_8|UART_FCR_TXRST|UART_FCR_RXRST|UART_FCR_FIFOEN));
 
   /* Enable Auto-RTS and Auto-CS Flow Control in the Modem Control Register */
-  
+
 #ifdef CONFIG_UART1_FLOWCONTROL
   if (priv->id == 1)
     {
@@ -896,7 +896,7 @@ static int up_interrupt(int irq, void *context)
  *       de-asserted (driven HIGH) once the last bit of data has been transmitted.
  *
  *     RS485/EIA-485 driver delay time -- Supported
- * 
+ *
  *       The driver delay time is the delay between the last stop bit leaving
  *       the TXFIFO and the de-assertion of the DIR pin. This delay time can be
  *       programmed in the 8-bit RS485DLY register. The delay time is in periods
@@ -931,21 +931,21 @@ static inline int up_set_rs485_mode(struct up_dev_s *priv,
   else
     {
       /* Set the RS-485/EIA-485 Control register:
-       * 
+       *
        *  NMMEN 0 = Normal Multidrop Mode (NMM) disabled
        *  RXDIS 0 = Receiver is not disabled
        *  AADEN 0 = Auto Address Detect (ADD) is disabled
        *  DCTRL 1 = Auto Direction Control is enabled
-       *  OINV  ? = Value control by user mode settings   
+       *  OINV  ? = Value control by user mode settings
        */
 
       regval = UART_RS485CTRL_DCTRL;
 
       /* Logic levels are controlled by the SER_RS485_RTS_ON_SEND and
-       * SER_RS485_RTS_AFTER_SEND bits in the mode flags. 
+       * SER_RS485_RTS_AFTER_SEND bits in the mode flags.
        * SER_RS485_RTS_AFTER_SEND is ignored.
        *
-       * By default, DIR will go logic low on send, but this can 
+       * By default, DIR will go logic low on send, but this can
        * be inverted.
        */
 
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_spi.c b/nuttx/arch/arm/src/lpc43xx/lpc43_spi.c
index 1058c85c9..6f51f1272 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_spi.c
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_spi.c
@@ -161,7 +161,7 @@ static const struct spi_ops_s g_spiops =
 static struct lpc43_spidev_s g_spidev =
 {
   .spidev            = { &g_spiops },
-}; 
+};
 
 /****************************************************************************
  * Public Data
@@ -269,7 +269,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
   divisor = (divisor + 1) & ~1;
 
   /* Save the new divisor value */
-  
+
   putreg32(divisor, LPC43_SPI_CCR);
 
   /* Calculate the new actual */
@@ -322,19 +322,19 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
         {
         case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
           break;
- 
+
         case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
           regval |= SPI_CR_CPHA;
           break;
- 
+
         case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
           regval |= SPI_CR_CPOL;
           break;
- 
+
         case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
           regval |= (SPI_CR_CPOL|SPI_CR_CPHA);
           break;
- 
+
         default:
           DEBUGASSERT(FALSE);
           return;
@@ -517,7 +517,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
 
      (void)getreg32(LPC43_SPI_SR);
 
-     /* Read the received data from the SPI Data Register */   
+     /* Read the received data from the SPI Data Register */
 
      *ptr++ = (uint8_t)getreg32(LPC43_SPI_DR);
      nwords--;
@@ -575,7 +575,7 @@ FAR struct spi_dev_s *lpc43_spiinitialize(int port)
   regval |= SYSCON_PCONP_PCSPI;
   putreg32(regval, LPC43_SYSCON_PCONP);
   irqrestore(flags);
-  
+
   /* Configure 8-bit SPI mode and master mode */
 
   putreg32(SPI_CR_BITS_8BITS|SPI_CR_BITENABLE|SPI_CR_MSTR, LPC43_SPI_CR);
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_spifi.c b/nuttx/arch/arm/src/lpc43xx/lpc43_spifi.c
index f7a7e41b7..fcaae5ea8 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_spifi.c
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_spifi.c
@@ -241,7 +241,7 @@
  * Compute this from the SPIFI clock period and the minimum high time of CS
  * from the serial flash data sheet:
  *
- *   csHigh = ceiling( min CS high / SPIFI clock period ) - 1 
+ *   csHigh = ceiling( min CS high / SPIFI clock period ) - 1
  *
  * where ceiling means round up to the next higher integer if the argument
  * isn’t an integer.
@@ -381,7 +381,7 @@ static void lpc43_blockerase(struct lpc43_dev_s *priv, off_t sector)
   priv->operands.dest   = SPIFI_BASE + (sector << SPIFI_BLKSHIFT);
   priv->operands.length = SPIFI_BLKSIZE;
 
-  fvdbg("SPIFI_ERASE: dest=%p length=%d\n", 
+  fvdbg("SPIFI_ERASE: dest=%p length=%d\n",
         priv->operands.dest, priv->operands.length);
 
   result = SPIFI_ERASE(priv, &priv->rom, &priv->operands);
@@ -456,7 +456,7 @@ static int lpc43_pagewrite(FAR struct lpc43_dev_s *priv, FAR uint8_t *dest,
   priv->operands.dest   = dest;
   priv->operands.length = nbytes;
 
-  fvdbg("SPIFI_PROGRAM: src=%p dest=%p length=%d\n", 
+  fvdbg("SPIFI_PROGRAM: src=%p dest=%p length=%d\n",
         src, priv->operands.dest, priv->operands.length);
 
   result = SPIFI_PROGRAM(priv, &priv->rom, src, &priv->operands);
@@ -543,7 +543,7 @@ static FAR uint8_t *lpc43_cacheread(struct lpc43_dev_s *priv, off_t sector)
   FAR const uint8_t *src;
   off_t blkno;
   int   index;
- 
+
   /* Convert from the 512 byte sector to the erase sector size of the device.  For
    * exmample, if the actual erase sector size if 4Kb (1 << 12), then we first
    * shift to the right by 3 to get the sector number in 4096 increments.
@@ -881,7 +881,7 @@ static int lpc43_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg)
             ret = lpc43_chiperase(priv);
         }
         break;
- 
+
       case MTDIOC_XIPBASE:
       default:
         ret = -ENOTTY; /* Bad command */
@@ -1156,7 +1156,7 @@ FAR struct mtd_dev_s *lpc43_spifi_initialize(void)
 
   priv->operands.protect = -1;              /* Save and restore protection */
   priv->operands.options = S_CALLER_ERASE;  /* This driver will do erasure */
-  
+
   /* Initialize the SPIFI.  Interrupts must be disabled here because shared
    * CGU registers will be modified.
    */
@@ -1230,7 +1230,7 @@ void pullMISO(int high)
 
   /* Control MISO pull-up/down state  Assume pull down by clearing:
    *
-   *  EPD = Enable pull-down connect (bit 
+   *  EPD = Enable pull-down connect (bit
    */
 
   pinconfig = PINCONF_SPIFI_MISO & ~(PINCONF_PULLUP | PINCONF_PULLDOWN);
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_ssp.c b/nuttx/arch/arm/src/lpc43xx/lpc43_ssp.c
index a7efe8471..5edc03c06 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_ssp.c
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_ssp.c
@@ -66,7 +66,7 @@
  ****************************************************************************/
 
 /* The following enable debug output from this file (needs CONFIG_DEBUG too).
- * 
+ *
  * CONFIG_SSP_DEBUG - Define to enable basic SSP debug
  * CONFIG_SSP_VERBOSE - Define to enable verbose SSP debug
  */
@@ -192,7 +192,7 @@ static struct lpc43_sspdev_s g_ssp0dev =
 #ifdef CONFIG_LPC43_SSP_INTERRUPTS
   .sspirq            = LPC43_IRQ_SSP0,
 #endif
-}; 
+};
 #endif /* CONFIG_LPC43_SSP0 */
 
 #ifdef CONFIG_LPC43_SSP1
@@ -226,7 +226,7 @@ static struct lpc43_sspdev_s g_ssp1dev =
 #ifdef CONFIG_LPC43_SSP_INTERRUPTS
   .sspirq            = LPC43_IRQ_SSP1,
 #endif
-}; 
+};
 #endif /* CONFIG_LPC43_SSP1 */
 
 /****************************************************************************
@@ -376,7 +376,7 @@ static uint32_t ssp_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
   divisor = (divisor + 1) & ~1;
 
   /* Save the new divisor value */
-  
+
   ssp_putreg(priv, LPC43_SSP_CPSR_OFFSET, divisor);
 
   /* Calculate the new actual */
@@ -429,19 +429,19 @@ static void ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
         {
         case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
           break;
- 
+
         case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
           regval |= SSP_CR0_CPHA;
           break;
- 
+
         case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
           regval |= SSP_CR0_CPOL;
           break;
- 
+
         case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
           regval |= (SSP_CR0_CPOL|SSP_CR0_CPHA);
           break;
- 
+
         default:
           sspdbg("Bad mode: %d\n", mode);
           DEBUGASSERT(FALSE);
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_uart.c b/nuttx/arch/arm/src/lpc43xx/lpc43_uart.c
index 4491830f9..f37387db5 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_uart.c
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_uart.c
@@ -58,7 +58,7 @@
 /**************************************************************************
  * Private Definitions
  **************************************************************************/
-     
+
 /* Select UART parameters for the selected console */
 
 #if defined(CONFIG_USART0_SERIAL_CONSOLE)
@@ -199,7 +199,7 @@ void up_lowputc(char ch)
  *      PCLK_UART1; in the PCLKSEL1 register, select PCLK_USART2 and PCLK_USART3.
  *   3. Baud rate: In the LCR register, set bit DLAB = 1. This enables access
  *      to registers DLL and DLM for setting the baud rate. Also, if needed,
- *      set the fractional baud rate in the fractional divider 
+ *      set the fractional baud rate in the fractional divider
  *   4. UART FIFO: Use bit FIFO enable (bit 0) in FCR register to
  *      enable FIFO.
  *   5. Pins: Select UART pins through the PINSEL registers and pin modes
@@ -496,7 +496,7 @@ void lpc43_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud)
   uint32_t errval;   /* Error value associated with the candidate */
 
  /* The U[S]ART buad is given by:
-  * 
+  *
   * Fbaud =  Fbase * mul / (mul + divadd) / (16 * dl)
   * dl    =  Fbase * mul / (mul + divadd) / Fbaud / 16
   *       =  Fbase * mul / ((mul + divadd) * Fbaud * 16)
@@ -507,7 +507,7 @@ void lpc43_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud)
   *  0 < mul < 16
   *  0 <= divadd < mul
   */
- 
+
   best   = UINT32_MAX;
   divadd = 0;
   mul    = 0;
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_usb0dev.c b/nuttx/arch/arm/src/lpc43xx/lpc43_usb0dev.c
index 379dbc435..c17f075b6 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_usb0dev.c
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_usb0dev.c
@@ -638,7 +638,7 @@ static bool lpc43_rqenqueue(FAR struct lpc43_ep_s *privep,
                               FAR struct lpc43_req_s *req)
 {
   bool is_empty = !privep->head;
-  
+
   req->flink = NULL;
   if (is_empty)
     {
@@ -692,7 +692,7 @@ static void lpc43_queuedtd(uint8_t epphy, struct lpc43_dtd_s *dtd)
   uint32_t bit = LPC43_ENDPTMASK(epphy);
 
   lpc43_setbits (bit, LPC43_USBDEV_ENDPTPRIME);
-    
+
   while (lpc43_getreg (LPC43_USBDEV_ENDPTPRIME) & bit)
     ;
 }
@@ -710,7 +710,7 @@ static inline void lpc43_ep0xfer(uint8_t epphy, uint8_t *buf, uint32_t nbytes)
   struct lpc43_dtd_s *dtd = &g_td[epphy];
 
   lpc43_writedtd(dtd, buf, nbytes);
-    
+
   lpc43_queuedtd(epphy, dtd);
 }
 
@@ -733,9 +733,9 @@ static void lpc43_readsetup(uint8_t epphy, struct usb_ctrlreq_s *ctrl)
     /* copy the request... */
     for (i = 0; i < 8; i++)
         ((uint8_t *) ctrl)[i] = ((uint8_t *) dqh->setup)[i];
-    
+
     } while (!(lpc43_getreg(LPC43_USBDEV_USBCMD) & USBDEV_USBCMD_SUTW));
-    
+
     /* Clear the trip wire */
     lpc43_clrbits(USBDEV_USBCMD_SUTW, LPC43_USBDEV_USBCMD);
 
@@ -756,7 +756,7 @@ static inline void lpc43_set_address(struct lpc43_usbdev_s *priv, uint16_t addre
   priv->paddr    = address;
   priv->paddrset = address != 0;
 
-  lpc43_chgbits(USBDEV_DEVICEADDR_MASK, priv->paddr << USBDEV_DEVICEADDR_SHIFT, 
+  lpc43_chgbits(USBDEV_DEVICEADDR_MASK, priv->paddr << USBDEV_DEVICEADDR_SHIFT,
                 LPC43_USBDEV_DEVICEADDR);
 }
 
@@ -807,7 +807,7 @@ static int lpc43_progressep(struct lpc43_ep_s *privep)
 
   if (privreq->req.len == 0)
     {
-    /* If the class driver is responding to a setup packet, then wait for the 
+    /* If the class driver is responding to a setup packet, then wait for the
      * host to illicit thr response */
 
     if (privep->epphy == LPC43_EP0_IN && privep->dev->ep0state == EP0STATE_SETUP_OUT)
@@ -819,7 +819,7 @@ static int lpc43_progressep(struct lpc43_ep_s *privep)
         else
         usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_EPOUTNULLPACKET), 0);
       }
-      
+
       lpc43_reqcomplete(privep, lpc43_rqdequeue(privep), OK);
       return OK;
     }
@@ -1016,10 +1016,10 @@ static void lpc43_ep0configure(struct lpc43_usbdev_s *priv)
   g_qh[LPC43_EP0_IN ].capability = (DQH_CAPABILITY_MAX_PACKET(CONFIG_USBDEV_EP0_MAXSIZE) |
                       DQH_CAPABILITY_IOS |
                       DQH_CAPABILITY_ZLT);
-  
+
   g_qh[LPC43_EP0_OUT].currdesc = DTD_NEXTDESC_INVALID;
   g_qh[LPC43_EP0_IN ].currdesc = DTD_NEXTDESC_INVALID;
-  
+
   /* Enable EP0 */
   lpc43_setbits (USBDEV_ENDPTCTRL0_RXE | USBDEV_ENDPTCTRL0_TXE, LPC43_USBDEV_ENDPTCTRL0);
 }
@@ -1067,7 +1067,7 @@ static void lpc43_usbreset(struct lpc43_usbdev_s *priv)
       privep->stalled = false;
     }
 
-  /* Tell the class driver that we are disconnected. The class 
+  /* Tell the class driver that we are disconnected. The class
    * driver should then accept any new configurations. */
 
   if (priv->driver)
@@ -1090,7 +1090,7 @@ static void lpc43_usbreset(struct lpc43_usbdev_s *priv)
   lpc43_ep0configure(priv);
 
   /* Enable Device interrupts */
-  lpc43_putreg(USB_FRAME_INT | USB_ERROR_INT | 
+  lpc43_putreg(USB_FRAME_INT | USB_ERROR_INT |
          USBDEV_USBINTR_NAKE | USBDEV_USBINTR_SLE | USBDEV_USBINTR_URE | USBDEV_USBINTR_PCE | USBDEV_USBINTR_UE,
          LPC43_USBDEV_USBINTR);
 }
@@ -1106,7 +1106,7 @@ static void lpc43_usbreset(struct lpc43_usbdev_s *priv)
 static inline void lpc43_ep0state(struct lpc43_usbdev_s *priv, uint16_t state)
 {
   priv->ep0state = state;
-  
+
   switch (state)
     {
     case EP0STATE_WAIT_NAK_IN:
@@ -1138,7 +1138,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv)
   uint16_t index;
   uint16_t len;
 
-  /* Terminate any pending requests - since all DTDs will have been retired 
+  /* Terminate any pending requests - since all DTDs will have been retired
    * because of the setup packet */
 
   lpc43_cancelrequests(&priv->eplist[LPC43_EP0_OUT], -EPROTO);
@@ -1180,7 +1180,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv)
            * index: zero interface endpoint
            * len:   2; data = status
            */
-  
+
           usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_GETSTATUS), 0);
           if (!priv->paddrset || len != 2 ||
               (ctrl.type & USB_REQ_DIR_IN) == 0 || value != 0)
@@ -1207,21 +1207,21 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv)
                         else
                           priv->ep0buf[0] = 0; /* Not stalled */
                         priv->ep0buf[1] = 0;
-  
+
                         lpc43_ep0xfer (LPC43_EP0_IN, priv->ep0buf, 2);
                         lpc43_ep0state (priv, EP0STATE_SHORTWRITE);
                       }
                     }
                   break;
-  
+
                 case USB_REQ_RECIPIENT_DEVICE:
                   {
                     if (index == 0)
                       {
                         usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_DEVGETSTATUS), 0);
-  
+
                         /* Features:  Remote Wakeup=YES; selfpowered=? */
-  
+
                         priv->ep0buf[0] = (priv->selfpowered << USB_FEATURE_SELFPOWERED) |
                               (1 << USB_FEATURE_REMOTEWAKEUP);
                         priv->ep0buf[1] = 0;
@@ -1236,7 +1236,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv)
                       }
                   }
                   break;
-  
+
                 case USB_REQ_RECIPIENT_INTERFACE:
                   {
                     usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_IFGETSTATUS), 0);
@@ -1247,7 +1247,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv)
                     lpc43_ep0state (priv, EP0STATE_SHORTWRITE);
                   }
                   break;
-  
+
                 default:
                   {
                     usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_BADGETSTATUS), 0);
@@ -1258,7 +1258,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv)
             }
         }
         break;
-  
+
       case USB_REQ_CLEARFEATURE:
         {
           /* type:  host-to-device; recipient = device, interface or endpoint
@@ -1266,7 +1266,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv)
            * index: zero interface endpoint;
            * len:   zero, data = none
            */
-  
+
           usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_CLEARFEATURE), 0);
           if ((ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
             {
@@ -1285,7 +1285,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv)
             }
         }
         break;
-  
+
       case USB_REQ_SETFEATURE:
         {
           /* type:  host-to-device; recipient = device, interface, endpoint
@@ -1293,7 +1293,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv)
            * index: zero interface endpoint;
            * len:   0; data = none
            */
-  
+
           usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_SETFEATURE), 0);
           if (((ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) &&
               value == USB_FEATURE_TESTMODE)
@@ -1317,7 +1317,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv)
             }
         }
         break;
-  
+
       case USB_REQ_SETADDRESS:
         {
           /* type:  host-to-device; recipient = device
@@ -1331,7 +1331,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv)
             {
               /* Save the address.  We cannot actually change to the next address until
                * the completion of the status phase. */
-  
+
               priv->paddr = ctrl.value[0];
               priv->paddrset = false;
               lpc43_ep0state (priv, EP0STATE_WAIT_NAK_IN);
@@ -1343,7 +1343,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv)
             }
         }
         break;
-  
+
       case USB_REQ_GETDESCRIPTOR:
         /* type:  device-to-host; recipient = device
          * value: descriptor type and index
@@ -1369,7 +1369,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv)
             }
         }
         break;
-  
+
       case USB_REQ_GETCONFIGURATION:
         /* type:  device-to-host; recipient = device
          * value: 0;
@@ -1390,7 +1390,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv)
             }
         }
         break;
-  
+
       case USB_REQ_SETCONFIGURATION:
         /* type:  host-to-device; recipient = device
          * value: configuration value
@@ -1411,7 +1411,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv)
             }
         }
         break;
-  
+
       case USB_REQ_GETINTERFACE:
         /* type:  device-to-host; recipient = interface
          * value: 0
@@ -1429,7 +1429,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv)
           lpc43_dispatchrequest(priv, &ctrl);
         }
         break;
-  
+
       case USB_REQ_SYNCHFRAME:
         /* type:  device-to-host; recipient = endpoint
          * value: 0
@@ -1440,7 +1440,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv)
           usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_SYNCHFRAME), 0);
         }
         break;
-  
+
       default:
         {
           usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_INVALIDCTRLREQ), 0);
@@ -1471,7 +1471,7 @@ static void lpc43_ep0complete(struct lpc43_usbdev_s *priv, uint8_t epphy)
   struct lpc43_ep_s *privep = &priv->eplist[epphy];
 
   usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_EP0COMPLETE), (uint16_t)priv->ep0state);
-  
+
   switch (priv->ep0state)
     {
     case EP0STATE_DATA_IN:
@@ -1485,15 +1485,15 @@ static void lpc43_ep0complete(struct lpc43_usbdev_s *priv, uint8_t epphy)
     case EP0STATE_DATA_OUT:
       if (lpc43_rqempty(privep))
     return;
-    
+
       if (lpc43_epcomplete (priv, epphy))
         lpc43_ep0state (priv, EP0STATE_WAIT_NAK_IN);
       break;
-    
+
     case EP0STATE_SHORTWRITE:
       lpc43_ep0state (priv, EP0STATE_WAIT_NAK_OUT);
       break;
-    
+
     case EP0STATE_WAIT_STATUS_IN:
       lpc43_ep0state (priv, EP0STATE_IDLE);
 
@@ -1592,9 +1592,9 @@ bool lpc43_epcomplete(struct lpc43_usbdev_s *priv, uint8_t epphy)
       usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_EPOUTQEMPTY), 0);
     return true;
   }
-    
+
   int xfrd = dtd->xfer_len - (dtd->config >> 16);
-    
+
   privreq->req.xfrd += xfrd;
 
   bool complete = true;
@@ -1621,7 +1621,7 @@ bool lpc43_epcomplete(struct lpc43_usbdev_s *priv, uint8_t epphy)
     {
       privreq = lpc43_rqdequeue (privep);
     }
-    
+
   if (!lpc43_rqempty(privep))
     {
       lpc43_progressep(privep);
@@ -1667,11 +1667,11 @@ static int lpc43_usbinterrupt(int irq, FAR void *context)
       usbtrace(TRACE_INTEXIT(LPC43_TRACEINTID_USB), 0);
       return OK;
     }
-  
+
   /* When the device controller enters a suspend state from an active state,
    * the SLI bit will be set to a one.
    */
- 
+
   if (!priv->suspended && (disr & USBDEV_USBSTS_SLI) != 0)
     {
       usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_SUSPENDED),0);
@@ -1718,30 +1718,30 @@ static int lpc43_usbinterrupt(int irq, FAR void *context)
       if (portsc1 & USBDEV_PRTSC1_FPR)
         {
           /* FIXME: this occurs because of a J-to-K transition detected
-           *         while the port is in SUSPEND state - presumambly this 
+           *         while the port is in SUSPEND state - presumambly this
            *         is where the host is resuming the device?
            *
            *  - but do we need to "ack" the interrupt
            */
         }
     }
-  
+
 #ifdef CONFIG_LPC43_USBDEV_FRAME_INTERRUPT
   if (disr & USBDEV_USBSTT_SRI)
     {
       usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_FRAME), 0);
-      
-      priv->sof = (int)lpc43_getreg(LPC43_USBDEV_FRINDEX_OFFSET); 
+
+      priv->sof = (int)lpc43_getreg(LPC43_USBDEV_FRINDEX_OFFSET);
     }
 #endif
 
   if (disr & USBDEV_USBSTS_UEI)
     {
       /* FIXME: these occur when a transfer results in an error condition
-       *        it is set alongside USBINT if the DTD also had its IOC 
+       *        it is set alongside USBINT if the DTD also had its IOC
        *        bit set. */
     }
-  
+
   if (disr & USBDEV_USBSTS_UI)
     {
       /* Handle completion interrupts */
@@ -1752,12 +1752,12 @@ static int lpc43_usbinterrupt(int irq, FAR void *context)
           /* Clear any NAK interrupt and completion interrupts */
           lpc43_putreg (mask, LPC43_USBDEV_ENDPTNAK);
           lpc43_putreg (mask, LPC43_USBDEV_ENDPTCOMPLETE);
-      
+
           if (mask & LPC43_ENDPTMASK(0))
             lpc43_ep0complete(priv, 0);
           if (mask & LPC43_ENDPTMASK(1))
             lpc43_ep0complete(priv, 1);
-      
+
           for (n = 1; n < LPC43_NLOGENDPOINTS; n++)
             {
               if (mask & LPC43_ENDPTMASK((n<<1)))
@@ -1772,9 +1772,9 @@ static int lpc43_usbinterrupt(int irq, FAR void *context)
       if (setupstat)
         {
           /* Clear the endpoint complete CTRL OUT and IN when a Setup is received */
-          lpc43_putreg(LPC43_ENDPTMASK(LPC43_EP0_IN) | LPC43_ENDPTMASK(LPC43_EP0_OUT), 
+          lpc43_putreg(LPC43_ENDPTMASK(LPC43_EP0_IN) | LPC43_ENDPTMASK(LPC43_EP0_OUT),
                        LPC43_USBDEV_ENDPTCOMPLETE);
-      
+
           if (setupstat & LPC43_ENDPTMASK(LPC43_EP0_OUT))
             {
               usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_EP0SETUP), setupstat);
@@ -1832,7 +1832,7 @@ static int lpc43_epconfigure(FAR struct usbdev_ep_s *ep,
   DEBUGASSERT(desc->addr == ep->eplog);
 
   /* Initialise EP capabilities */
-  
+
   uint16_t maxsize = GETUINT16(desc->mxpacketsize);
   if ((desc->attr & USB_EP_ATTR_XFERTYPE_MASK) == USB_EP_ATTR_XFER_ISOC)
     {
@@ -1886,7 +1886,7 @@ static int lpc43_epconfigure(FAR struct usbdev_ep_s *ep,
     lpc43_setbits (USBDEV_ENDPTCTRL_TXE, LPC43_USBDEV_ENDPTCTRL(privep->epphy));
   else
     lpc43_setbits (USBDEV_ENDPTCTRL_RXE, LPC43_USBDEV_ENDPTCTRL(privep->epphy));
-  
+
    return OK;
 }
 
@@ -2076,7 +2076,7 @@ static int lpc43_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r
     {
       ret = -EBUSY;
     }
-  else 
+  else
     {
       /* Add the new request to the request queue for the endpoint */
 
@@ -2121,7 +2121,7 @@ static int lpc43_epcancel(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r
   priv = privep->dev;
 
   flags = irqsave();
-  
+
   /* FIXME: if the request is the first, then we need to flush the EP
    *         otherwise just remove it from the list
    *
@@ -2379,7 +2379,7 @@ static int lpc43_wakeup(struct usbdev_s *dev)
  * Name: lpc43_selfpowered
  *
  * Description:
- *   Sets/clears the device selfpowered feature 
+ *   Sets/clears the device selfpowered feature
  *
  *******************************************************************************/
 
@@ -2449,7 +2449,7 @@ void up_usbinitialize(void)
   usbtrace(TRACE_DEVINIT, 0);
 
   /* Disable USB interrupts */
-  
+
   lpc43_putreg(0, LPC43_USBDEV_USBINTR);
 
   /* Initialize the device state structure */
@@ -2519,7 +2519,7 @@ void up_usbinitialize(void)
   /* Enable USB OTG PLL and wait for lock */
 
   lpc43_putreg (0, LPC43_SYSCREG_USB_ATXPLLPDREG);
-  
+
   uint32_t bank = EVNTRTR_BANK(EVENTRTR_USBATXPLLLOCK);
   uint32_t bit  = EVNTRTR_BIT(EVENTRTR_USBATXPLLLOCK);
 
@@ -2657,7 +2657,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver)
       up_enable_irq(LPC43_IRQ_USBOTG);
 
       /* FIXME: nothing seems to call DEV_CONNECT(), but we need to set
-       *        the RS bit to enable the controller.  It kind of makes sense 
+       *        the RS bit to enable the controller.  It kind of makes sense
        *        to do this after the class has bound to us...
        * GEN:   This bug is really in the class driver.  It should make the
        *        soft connect when it is ready to be enumerated.  I have added
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_userspace.c b/nuttx/arch/arm/src/lpc43xx/lpc43_userspace.c
index c5c62f716..7bc7f1c25 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_userspace.c
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_userspace.c
@@ -98,7 +98,7 @@ void lpc43_userspace(void)
   /* Initialize all of user-space .data */
 
   DEBUGASSERT(USERSPACE->us_datasource != 0 &&
-              USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && 
+              USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 &&
               USERSPACE->us_datastart <= USERSPACE->us_dataend);
 
   src  = (uint8_t*)USERSPACE->us_datasource;