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| author | Gregory Nutt <gnutt@nuttx.org> | 2014-04-13 16:22:22 -0600 |
|---|---|---|
| committer | Gregory Nutt <gnutt@nuttx.org> | 2014-04-13 16:22:22 -0600 |
| commit | 70b6bb22af51defd713adfd452309f32f0e523aa (patch) | |
| tree | b483c578cf6ae76888b89188bedb03f539ab4cd3 /nuttx/arch | |
| parent | 3cf6b4d6577c2f467dbb25dd0da8cdc6ad32a7b4 (diff) | |
| download | nuttx-70b6bb22af51defd713adfd452309f32f0e523aa.tar.gz nuttx-70b6bb22af51defd713adfd452309f32f0e523aa.tar.bz2 nuttx-70b6bb22af51defd713adfd452309f32f0e523aa.zip | |
More trailing whilespace removal
Diffstat (limited to 'nuttx/arch')
450 files changed, 1476 insertions, 1478 deletions
diff --git a/nuttx/arch/8051/include/irq.h b/nuttx/arch/8051/include/irq.h index ce6334dd0..da7513530 100644 --- a/nuttx/arch/8051/include/irq.h +++ b/nuttx/arch/8051/include/irq.h @@ -160,7 +160,7 @@ struct xcptcontext uint8_t nbytes; - /* This is the saved stack. Space is allocated for the + /* This is the saved stack. Space is allocated for the * entire 256 byte IRAM (minus register and bit usage at * the beginning). */ diff --git a/nuttx/arch/8051/include/limits.h b/nuttx/arch/8051/include/limits.h index fd8c086aa..5c8116e07 100644 --- a/nuttx/arch/8051/include/limits.h +++ b/nuttx/arch/8051/include/limits.h @@ -33,8 +33,8 @@ * ************************************************************/ -#ifndef __ARCH_8051_INCLUDE_LIMITS_H -#define __ARCH_8051_INCLUDE_LIMITS_H +#ifndef __ARCH_8051_INCLUDE_LIMITS_H +#define __ARCH_8051_INCLUDE_LIMITS_H /************************************************************ * Included Files diff --git a/nuttx/arch/8051/include/types.h b/nuttx/arch/8051/include/types.h index 4a528c7d0..a3865e978 100644 --- a/nuttx/arch/8051/include/types.h +++ b/nuttx/arch/8051/include/types.h @@ -37,8 +37,8 @@ * only indirectly through sys/types.h */ -#ifndef __ARCH_8051_INCLUDE_TYPES_H -#define __ARCH_8051_INCLUDE_TYPES_H +#ifndef __ARCH_8051_INCLUDE_TYPES_H +#define __ARCH_8051_INCLUDE_TYPES_H /************************************************************************ * Included Files diff --git a/nuttx/arch/8051/src/Makefile.sdccl b/nuttx/arch/8051/src/Makefile.sdccl index e90ef23e9..ee6fc69e3 100644 --- a/nuttx/arch/8051/src/Makefile.sdccl +++ b/nuttx/arch/8051/src/Makefile.sdccl @@ -200,7 +200,7 @@ up_mem.h: pass1.mem libarch$(LIBEXT): up_mem.h $(OBJS) $(call ARCHIVE, $@, $(OBJS)) -# This builds the libboard library in the board/ subdirectory +# This builds the libboard library in the board/ subdirectory board/libboard$(LIBEXT): $(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" libboard$(LIBEXT) EXTRADEFINES=$(EXTRADEFINES) diff --git a/nuttx/arch/8051/src/up_blocktask.c b/nuttx/arch/8051/src/up_blocktask.c index 018577477..1ae7a78a4 100644 --- a/nuttx/arch/8051/src/up_blocktask.c +++ b/nuttx/arch/8051/src/up_blocktask.c @@ -131,7 +131,7 @@ void up_block_task(FAR struct tcb_s *tcb, tstate_t task_state) up_saveirqcontext(&tcb->xcp); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -152,7 +152,7 @@ void up_block_task(FAR struct tcb_s *tcb, tstate_t task_state) else if (!up_savecontext(&rtcb->xcp)) { - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/8051/src/up_head.S b/nuttx/arch/8051/src/up_head.S index ee39cd54d..d4e2ba6e7 100644 --- a/nuttx/arch/8051/src/up_head.S +++ b/nuttx/arch/8051/src/up_head.S @@ -178,7 +178,7 @@ _up_timer0: push ie clr ea - /* Save the remaining registers with interrupts disabled + /* Save the remaining registers with interrupts disabled * * a, ie, and dptr go on the stack. */ @@ -232,7 +232,7 @@ _up_interrupt: push ie clr ea - /* Save the remaining registers with interrupts disabled + /* Save the remaining registers with interrupts disabled * * a, ie, and dptr go on the stack. */ diff --git a/nuttx/arch/8051/src/up_initialize.c b/nuttx/arch/8051/src/up_initialize.c index d812552a6..30c17053f 100644 --- a/nuttx/arch/8051/src/up_initialize.c +++ b/nuttx/arch/8051/src/up_initialize.c @@ -86,7 +86,7 @@ FAR struct xcptcontext *g_irqcontext; * to comput them. */ -const uint8_t g_ntobit[8] = +const uint8_t g_ntobit[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }; /************************************************************************ diff --git a/nuttx/arch/8051/src/up_irqtest.c b/nuttx/arch/8051/src/up_irqtest.c index 21b558c67..be8f6d00b 100644 --- a/nuttx/arch/8051/src/up_irqtest.c +++ b/nuttx/arch/8051/src/up_irqtest.c @@ -72,7 +72,7 @@ bool g_irqtest; volatile uint8_t g_irqtos; uint8_t g_irqregs[REGS_SIZE]; int g_nirqs; -FAR struct xcptcontext *g_irqcontext; +FAR struct xcptcontext *g_irqcontext; /************************************************************************ * Private Functions diff --git a/nuttx/arch/8051/src/up_putc.c b/nuttx/arch/8051/src/up_putc.c index 66979ce4a..bf2edb5e1 100644 --- a/nuttx/arch/8051/src/up_putc.c +++ b/nuttx/arch/8051/src/up_putc.c @@ -76,6 +76,6 @@ int up_putc(int ch) { _up_putc('\r'); } - return ch; + return ch; } diff --git a/nuttx/arch/8051/src/up_releasepending.c b/nuttx/arch/8051/src/up_releasepending.c index 0d87608cf..e26b4bcbb 100644 --- a/nuttx/arch/8051/src/up_releasepending.c +++ b/nuttx/arch/8051/src/up_releasepending.c @@ -98,7 +98,7 @@ void up_release_pending(void) up_saveirqcontext(&rtcb->xcp); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -114,13 +114,13 @@ void up_release_pending(void) /* Copy the exception context into the TCB of the task that * was currently active. if up_savecontext returns a non-zero - * value, then this is really the previously running task + * value, then this is really the previously running task * restarting! */ else if (!up_savecontext(&rtcb->xcp)) { - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/8051/src/up_reprioritizertr.c b/nuttx/arch/8051/src/up_reprioritizertr.c index 649db3a43..2807b1141 100644 --- a/nuttx/arch/8051/src/up_reprioritizertr.c +++ b/nuttx/arch/8051/src/up_reprioritizertr.c @@ -70,7 +70,7 @@ * * Description: * Called when the priority of a running or - * ready-to-run task changes and the reprioritization will + * ready-to-run task changes and the reprioritization will * cause a context switch. Two cases: * * 1) The priority of the currently running task drops and the next @@ -153,7 +153,7 @@ void up_reprioritize_rtr(FAR struct tcb_s *tcb, uint8_t priority) up_saveirqcontext(&tcb->xcp); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -174,7 +174,7 @@ void up_reprioritize_rtr(FAR struct tcb_s *tcb, uint8_t priority) else if (!up_savecontext(&rtcb->xcp)) { - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/8051/src/up_restorecontext.c b/nuttx/arch/8051/src/up_restorecontext.c index d1aaae182..6966866ee 100644 --- a/nuttx/arch/8051/src/up_restorecontext.c +++ b/nuttx/arch/8051/src/up_restorecontext.c @@ -276,7 +276,7 @@ void up_restorecontext(FAR struct xcptcontext *context) __naked /* Restore registers from the new stack */ pop dph - pop dpl + pop dpl /* Restore the interrupt state per the stored IE value */ diff --git a/nuttx/arch/8051/src/up_unblocktask.c b/nuttx/arch/8051/src/up_unblocktask.c index 621c8a783..d285ddbd2 100644 --- a/nuttx/arch/8051/src/up_unblocktask.c +++ b/nuttx/arch/8051/src/up_unblocktask.c @@ -112,7 +112,7 @@ void up_unblock_task(FAR struct tcb_s *tcb) /* The currently active task has changed! We need to do * a context switch to the new task. * - * Are we in an interrupt handler? + * Are we in an interrupt handler? */ if (g_irqtos) @@ -123,7 +123,7 @@ void up_unblock_task(FAR struct tcb_s *tcb) up_saveirqcontext(&rtcb->xcp); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -138,7 +138,7 @@ void up_unblock_task(FAR struct tcb_s *tcb) } /* We are not in an interrupt andler. Copy the user C context - * into the TCB of the task that was previously active. if + * into the TCB of the task that was previously active. if * up_savecontext returns a non-zero value, then this is really the * previously running task restarting! */ diff --git a/nuttx/arch/README.txt b/nuttx/arch/README.txt index d70db1179..e7ef76ddf 100644 --- a/nuttx/arch/README.txt +++ b/nuttx/arch/README.txt @@ -171,7 +171,7 @@ arch/arm - ARM-based micro-controllers is complete on the basic port (timer, serial console, SPI). arch/arm/include/lm and arch/arm/src/lm - These directories contain support for the Luminary LM3S/4F family. The + These directories contain support for the Luminary LM3S/4F family. The initial, release of this port was included in NuttX version 0.4.6. The current port includes timer, serial console, Ethernet, SSI, and microSD support. There are working configurations the NuttX OS test, to run the @@ -211,7 +211,7 @@ arch/arm - ARM-based micro-controllers STATUS: The basic AT91SAM3U port was released in NuttX version 5.1. The basic port includes boot-up logic, interrupt driven serial console, and system timer interrupts. That release passes the - NuttX OS test and is proven to have a valid OS implementation. A + NuttX OS test and is proven to have a valid OS implementation. A onfiguration to support the NuttShell is also included. arch/arm/include/stm32 and arch/arm/src/stm32 diff --git a/nuttx/arch/arm/include/a1x/a10_irq.h b/nuttx/arch/arm/include/a1x/a10_irq.h index 4cd291d20..29dbb5452 100644 --- a/nuttx/arch/arm/include/a1x/a10_irq.h +++ b/nuttx/arch/arm/include/a1x/a10_irq.h @@ -48,7 +48,7 @@ * Pre-Processor Definitions ****************************************************************************************/ -/* External interrupts numbers */ +/* External interrupts numbers */ #define A1X_IRQ_NMI 0 /* External Non-Mask Interrupt */ # define A1X_IRQ_POWER 0 /* Power module */ diff --git a/nuttx/arch/arm/include/armv7-a/irq.h b/nuttx/arch/arm/include/armv7-a/irq.h index 09880f450..2f90e7499 100755 --- a/nuttx/arch/arm/include/armv7-a/irq.h +++ b/nuttx/arch/arm/include/armv7-a/irq.h @@ -60,7 +60,7 @@ * (1) stmia rx, {r0-r14} * (2) then the PC and CPSR * - * This results in the following set of indices that can be used to access + * This results in the following set of indices that can be used to access * individual registers in the xcp.regs array: */ diff --git a/nuttx/arch/arm/include/armv7-m/irq_cmnvector.h b/nuttx/arch/arm/include/armv7-m/irq_cmnvector.h index bc67004ed..8a577d491 100644 --- a/nuttx/arch/arm/include/armv7-m/irq_cmnvector.h +++ b/nuttx/arch/arm/include/armv7-m/irq_cmnvector.h @@ -70,7 +70,7 @@ #ifdef CONFIG_ARCH_FPU /* If the MCU supports a floating point unit, then it will be necessary - * to save the state of the non-volatile registers before calling code + * to save the state of the non-volatile registers before calling code * that may save and overwrite them. */ diff --git a/nuttx/arch/arm/include/elf.h b/nuttx/arch/arm/include/elf.h index 21b2c1c2c..9928a85a7 100644 --- a/nuttx/arch/arm/include/elf.h +++ b/nuttx/arch/arm/include/elf.h @@ -64,7 +64,7 @@ #define EF_ARM_EABI_VER4 0x04000000 #define EF_ARM_EABI_VER5 0x05000000 -#define EF_ARM_BE8 0x00800000 +#define EF_ARM_BE8 0x00800000 /* Table 4-4, Processor specific section types */ diff --git a/nuttx/arch/arm/include/lpc2378/irq.h b/nuttx/arch/arm/include/lpc2378/irq.h index 807c99119..de580c68b 100644 --- a/nuttx/arch/arm/include/lpc2378/irq.h +++ b/nuttx/arch/arm/include/lpc2378/irq.h @@ -56,7 +56,7 @@ /**************************************************************************** * Definitions ****************************************************************************/ - + /* LPC2378 Interrupts */ #define WDT_IRQ 0 /* Watchdog */ diff --git a/nuttx/arch/arm/include/lpc43xx/irq.h b/nuttx/arch/arm/include/lpc43xx/irq.h index 37c1e9c29..88b83390f 100644 --- a/nuttx/arch/arm/include/lpc43xx/irq.h +++ b/nuttx/arch/arm/include/lpc43xx/irq.h @@ -51,7 +51,7 @@ /******************************************************************************************** * Pre-processor Definitions ********************************************************************************************/ - + /* IRQ numbers. The IRQ number corresponds vector number and hence map directly to bits in * the NVIC. This does, however, waste several words of memory in the IRQ to handle mapping * tables. diff --git a/nuttx/arch/arm/include/nuc1xx/nuc120_irq.h b/nuttx/arch/arm/include/nuc1xx/nuc120_irq.h index 5dcd1606c..8b04167f3 100644 --- a/nuttx/arch/arm/include/nuc1xx/nuc120_irq.h +++ b/nuttx/arch/arm/include/nuc1xx/nuc120_irq.h @@ -82,7 +82,7 @@ #define NUC_IRQ_ADC (45) /* ADC */ /* 46: Reserved */ #define NUC_IRQ_RTC (47) /* Real time clock */ - + #define NR_IRQS (48) /************************************************************************************ diff --git a/nuttx/arch/arm/include/sama5/chip.h b/nuttx/arch/arm/include/sama5/chip.h index 92a8ca2a4..709bf6c46 100644 --- a/nuttx/arch/arm/include/sama5/chip.h +++ b/nuttx/arch/arm/include/sama5/chip.h @@ -46,7 +46,7 @@ * Pre-processor Definitions ****************************************************************************************************/ /* SAMA5D3 Family - * + * * ATSAMA5D31 ATSAMA5D33 ATSAMA5D34 ATSAMA5D35 ATSAMA5D36 * ------------------------- ------------- ------------- ------------- ------------- ------------- * Pin Count 324 324 324 324 324 diff --git a/nuttx/arch/arm/src/a1x/a1x_pio.c b/nuttx/arch/arm/src/a1x/a1x_pio.c index cd1167b34..9817314df 100644 --- a/nuttx/arch/arm/src/a1x/a1x_pio.c +++ b/nuttx/arch/arm/src/a1x/a1x_pio.c @@ -113,7 +113,7 @@ static int a1x_pio_interrupt(int irq, void *context) int irq; /* Read the set of pending GPIO interrupts */ - + status = getreg32(A1X_PIO_INT_STA); mask = getreg32(A1X_PIO_INT_CTL); pending = status & mask; diff --git a/nuttx/arch/arm/src/a1x/a1x_timerisr.c b/nuttx/arch/arm/src/a1x/a1x_timerisr.c index 4e35af9d4..5487b7252 100644 --- a/nuttx/arch/arm/src/a1x/a1x_timerisr.c +++ b/nuttx/arch/arm/src/a1x/a1x_timerisr.c @@ -120,7 +120,7 @@ void up_timerinit(void) uint32_t regval; /* Set the timer reload interval value */ - + putreg32(TMR_INTERVAL, A1X_TMR0_INTV_VALUE); /* Configure timer 0: diff --git a/nuttx/arch/arm/src/arm/arm.h b/nuttx/arch/arm/src/arm/arm.h index 2ad31fc46..68036ef2e 100644 --- a/nuttx/arch/arm/src/arm/arm.h +++ b/nuttx/arch/arm/src/arm/arm.h @@ -332,7 +332,7 @@ static inline unsigned int get_cp15c3(void) * ARM926EJ-S operation: Invalidate set-associative * Data: Should be zero */ - + static inline void tlb_invalidate(void) { unsigned int sbz = 0; diff --git a/nuttx/arch/arm/src/arm/pg_macros.h b/nuttx/arch/arm/src/arm/pg_macros.h index e461ced41..622b14202 100644 --- a/nuttx/arch/arm/src/arm/pg_macros.h +++ b/nuttx/arch/arm/src/arm/pg_macros.h @@ -183,7 +183,7 @@ * larger than the size of the physical paged region. That is the * core of what the On-Demanding Paging feature provides. */ - + #define PG_L1_PAGED_PADDR (PGTABLE_BASE_PADDR + ((PG_PAGED_VBASE >> 20) << 2)) #define PG_L1_PAGED_VADDR (PGTABLE_BASE_VADDR + ((PG_PAGED_VBASE >> 20) << 2)) @@ -261,10 +261,10 @@ /* Case 2: Vectors are in low memory and the locked text region starts at * the beginning of SRAM (which will be aliased to address 0x00000000). * However, the beginning of SRAM may not be aligned to the beginning - * of the L2 page table (because the beginning of RAM is offset into + * of the L2 page table (because the beginning of RAM is offset into * the table. */ - + #elif defined(CONFIG_ARCH_LOWVECTORS) && !defined(CONFIG_PAGING_LOCKED_PBASE) # define PG_VECT_PBASE PG_LOCKED_PBASE # define PG_L2_VECT_OFFSET (((PG_LOCKED_VBASE & 0x000fffff) >> PAGESHIFT) << 2) @@ -327,7 +327,7 @@ * text region (the address at the beginning of * the page). * PG_POOL_MAXL2NDX - This is the maximum value+1 of such an index. - * + * * PG_POOL_PGPADDR(ndx) - Converts an page index into the corresponding * (physical) address of the backing page memory. * PG_POOL_PGVADDR(ndx) - Converts an page index into the corresponding @@ -340,7 +340,7 @@ * written. */ -#define PG_POOL_VA2L1OFFSET(va) (((va) >> 20) << 2) +#define PG_POOL_VA2L1OFFSET(va) (((va) >> 20) << 2) #define PG_POOL_VA2L1VADDR(va) (PGTABLE_BASE_VADDR + PG_POOL_VA2L1OFFSET(va)) #define PG_POOL_L12PPTABLE(L1) ((L1) & PG_L1_PADDRMASK) #define PG_POOL_L12VPTABLE(L1) (PG_POOL_L12PPTABLE(L1) - PGTABLE_BASE_PADDR + PGTABLE_BASE_VADDR) @@ -442,7 +442,7 @@ * follows: * * ldr r0, =PG_L1_PGTABLE_PADDR <-- Address in the L1 table - * ldr r1, =PG_L2_PGTABLE_PADDR <-- Physical address of L2 page table + * ldr r1, =PG_L2_PGTABLE_PADDR <-- Physical address of L2 page table * ldr r2, =PG_PGTABLE_NPAGES <-- Total number of pages * ldr r3, =PG_PGTABLE_NPAGE1 <-- Number of pages in the first PTE * ldr r4, =MMU_L1_PGTABFLAGS <-- L1 MMU flags diff --git a/nuttx/arch/arm/src/arm/up_allocpage.c b/nuttx/arch/arm/src/arm/up_allocpage.c index 8ec99b09c..da3c441f3 100644 --- a/nuttx/arch/arm/src/arm/up_allocpage.c +++ b/nuttx/arch/arm/src/arm/up_allocpage.c @@ -171,7 +171,7 @@ int up_allocpage(FAR struct tcb_s *tcb, FAR void **vpage) uintptr_t paddr; uint32_t *pte; unsigned int pgndx; - + /* Since interrupts are disabled, we don't need to anything special. */ DEBUGASSERT(tcb && vpage); @@ -199,7 +199,7 @@ int up_allocpage(FAR struct tcb_s *tcb, FAR void **vpage) if (g_pgwrap) { /* Yes.. Get a pointer to the L2 entry corresponding to the previous - * mapping -- then zero it! + * mapping -- then zero it! */ uintptr_t oldvaddr = PG_POOL_NDX2VA(g_ptemap[pgndx]); @@ -214,7 +214,7 @@ int up_allocpage(FAR struct tcb_s *tcb, FAR void **vpage) * case: The I-Cache uses a virtual address index and, hence, since the * NuttX address space is flat, the cached instruction value should be * correct even if the page mapping is no longer in place. - */ + */ } /* Then convert the index to a (physical) page address. */ @@ -231,7 +231,7 @@ int up_allocpage(FAR struct tcb_s *tcb, FAR void **vpage) *pte = (paddr | MMU_L2_ALLOCFLAGS); /* And save the new L1 index */ - + g_ptemap[pgndx] = PG_POOL_VA2L2NDX(vaddr); /* Finally, return the virtual address of allocated page */ diff --git a/nuttx/arch/arm/src/arm/up_blocktask.c b/nuttx/arch/arm/src/arm/up_blocktask.c index 04caa4481..d0e35e558 100644 --- a/nuttx/arch/arm/src/arm/up_blocktask.c +++ b/nuttx/arch/arm/src/arm/up_blocktask.c @@ -130,7 +130,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -148,7 +148,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state) else if (!up_saveusercontext(rtcb->xcp.regs)) { - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/arm/src/arm/up_cache.S b/nuttx/arch/arm/src/arm/up_cache.S index 74f337e95..e03099ce0 100644 --- a/nuttx/arch/arm/src/arm/up_cache.S +++ b/nuttx/arch/arm/src/arm/up_cache.S @@ -88,7 +88,7 @@ * Wait for interrupt SBZ MCR p15, 0, <Rd>, c7, c0, 4 */ -/* Esure coherency between the Icache and the Dcache in the region described +/* Esure coherency between the Icache and the Dcache in the region described * by r0=start and r1=end. Cleans the corresponding D-cache lines and invalidates * the corresponding I-Cache lines. */ diff --git a/nuttx/arch/arm/src/arm/up_dataabort.c b/nuttx/arch/arm/src/arm/up_dataabort.c index d5e652856..2b05abdeb 100644 --- a/nuttx/arch/arm/src/arm/up_dataabort.c +++ b/nuttx/arch/arm/src/arm/up_dataabort.c @@ -56,7 +56,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Output debug info if stack dump is selected -- even if +/* Output debug info if stack dump is selected -- even if * debug is not selected. */ @@ -139,7 +139,7 @@ void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr) * the exception occurred, this address was provided in the FAR register. * (It has not yet been saved in the register context save area). */ - + pgllvdbg("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND); if (far < PG_PAGED_VBASE || far >= PG_PAGED_VEND) { diff --git a/nuttx/arch/arm/src/arm/up_prefetchabort.c b/nuttx/arch/arm/src/arm/up_prefetchabort.c index c75a92a49..ae8af72bc 100644 --- a/nuttx/arch/arm/src/arm/up_prefetchabort.c +++ b/nuttx/arch/arm/src/arm/up_prefetchabort.c @@ -56,7 +56,7 @@ /* Debug ********************************************************************/ -/* Output debug info if stack dump is selected -- even if +/* Output debug info if stack dump is selected -- even if * debug is not selected. */ diff --git a/nuttx/arch/arm/src/arm/up_releasepending.c b/nuttx/arch/arm/src/arm/up_releasepending.c index 169262e95..215397706 100644 --- a/nuttx/arch/arm/src/arm/up_releasepending.c +++ b/nuttx/arch/arm/src/arm/up_releasepending.c @@ -97,7 +97,7 @@ void up_release_pending(void) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -111,13 +111,13 @@ void up_release_pending(void) /* Copy the exception context into the TCB of the task that * was currently active. if up_saveusercontext returns a non-zero - * value, then this is really the previously running task + * value, then this is really the previously running task * restarting! */ else if (!up_saveusercontext(rtcb->xcp.regs)) { - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/arm/src/arm/up_reprioritizertr.c b/nuttx/arch/arm/src/arm/up_reprioritizertr.c index 9d898ed7b..cd5955c24 100644 --- a/nuttx/arch/arm/src/arm/up_reprioritizertr.c +++ b/nuttx/arch/arm/src/arm/up_reprioritizertr.c @@ -69,7 +69,7 @@ * * Description: * Called when the priority of a running or - * ready-to-run task changes and the reprioritization will + * ready-to-run task changes and the reprioritization will * cause a context switch. Two cases: * * 1) The priority of the currently running task drops and the next @@ -152,7 +152,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -171,7 +171,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) else if (!up_saveusercontext(rtcb->xcp.regs)) { - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/arm/src/arm/up_syscall.c b/nuttx/arch/arm/src/arm/up_syscall.c index db3231646..35f7027dd 100644 --- a/nuttx/arch/arm/src/arm/up_syscall.c +++ b/nuttx/arch/arm/src/arm/up_syscall.c @@ -50,7 +50,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Output debug info if stack dump is selected -- even if +/* Output debug info if stack dump is selected -- even if * debug is not selected. */ diff --git a/nuttx/arch/arm/src/arm/up_unblocktask.c b/nuttx/arch/arm/src/arm/up_unblocktask.c index 2e373f38e..64536d959 100644 --- a/nuttx/arch/arm/src/arm/up_unblocktask.c +++ b/nuttx/arch/arm/src/arm/up_unblocktask.c @@ -109,7 +109,7 @@ void up_unblock_task(struct tcb_s *tcb) /* The currently active task has changed! We need to do * a context switch to the new task. * - * Are we in an interrupt handler? + * Are we in an interrupt handler? */ if (current_regs) @@ -120,7 +120,7 @@ void up_unblock_task(struct tcb_s *tcb) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -132,7 +132,7 @@ void up_unblock_task(struct tcb_s *tcb) } /* We are not in an interrupt handler. Copy the user C context - * into the TCB of the task that was previously active. if + * into the TCB of the task that was previously active. if * up_saveusercontext returns a non-zero value, then this is really the * previously running task restarting! */ diff --git a/nuttx/arch/arm/src/arm/up_undefinedinsn.c b/nuttx/arch/arm/src/arm/up_undefinedinsn.c index dd4f15e35..fa0da7352 100644 --- a/nuttx/arch/arm/src/arm/up_undefinedinsn.c +++ b/nuttx/arch/arm/src/arm/up_undefinedinsn.c @@ -48,7 +48,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Output debug info if stack dump is selected -- even if +/* Output debug info if stack dump is selected -- even if * debug is not selected. */ diff --git a/nuttx/arch/arm/src/arm/up_vectors.S b/nuttx/arch/arm/src/arm/up_vectors.S index 1dfdf623c..a167b1726 100644 --- a/nuttx/arch/arm/src/arm/up_vectors.S +++ b/nuttx/arch/arm/src/arm/up_vectors.S @@ -156,7 +156,7 @@ up_vectorirq: /************************************************************************************ * Function: up_vectorswi - * + * * Description: * SWI interrupt. We enter the SWI in SVC mode. * diff --git a/nuttx/arch/arm/src/arm/vfork.S b/nuttx/arch/arm/src/arm/vfork.S index 7c3c8b727..2f0edac82 100644 --- a/nuttx/arch/arm/src/arm/vfork.S +++ b/nuttx/arch/arm/src/arm/vfork.S @@ -64,7 +64,7 @@ * undefined if the process created by vfork() either modifies any data other than * a variable of type pid_t used to store the return value from vfork(), or returns * from the function in which vfork() was called, or calls any other function before - * successfully calling _exit() or one of the exec family of functions. + * successfully calling _exit() or one of the exec family of functions. * * This thin layer implements vfork by simply calling up_vfork() with the vfork() * context as an argument. The overall sequence is: @@ -93,7 +93,7 @@ * Upon successful completion, vfork() returns 0 to the child process and returns * the process ID of the child process to the parent process. Otherwise, -1 is * returned to the parent, no child process is created, and errno is set to - * indicate the error. + * indicate the error. * ************************************************************************************/ diff --git a/nuttx/arch/arm/src/armv6-m/nvic.h b/nuttx/arch/arm/src/armv6-m/nvic.h index d088d7827..945d5c433 100644 --- a/nuttx/arch/arm/src/armv6-m/nvic.h +++ b/nuttx/arch/arm/src/armv6-m/nvic.h @@ -368,7 +368,7 @@ #undef EXTERN #if defined(__cplusplus) #define EXTERN extern "C" -extern "C" +extern "C" { #else #define EXTERN extern diff --git a/nuttx/arch/arm/src/armv6-m/up_blocktask.c b/nuttx/arch/arm/src/armv6-m/up_blocktask.c index 57db2b4aa..c51308cfc 100644 --- a/nuttx/arch/arm/src/armv6-m/up_blocktask.c +++ b/nuttx/arch/arm/src/armv6-m/up_blocktask.c @@ -129,7 +129,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/arm/src/armv6-m/up_elf.c b/nuttx/arch/arm/src/armv6-m/up_elf.c index 367c93515..d24641005 100644 --- a/nuttx/arch/arm/src/armv6-m/up_elf.c +++ b/nuttx/arch/arm/src/armv6-m/up_elf.c @@ -296,7 +296,7 @@ int arch_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, S = (offset >> 24) & 1; J1 = S ^ (~(offset >> 23) & 1); J2 = S ^ (~(offset >> 22) & 1); - + upper_insn = ((upper_insn & 0xf800) | (S << 10) | ((offset >> 12) & 0x03ff)); *(uint16_t*)addr = (uint16_t)upper_insn; diff --git a/nuttx/arch/arm/src/armv6-m/up_initialstate.c b/nuttx/arch/arm/src/armv6-m/up_initialstate.c index 62c1d2780..6dc000d12 100644 --- a/nuttx/arch/arm/src/armv6-m/up_initialstate.c +++ b/nuttx/arch/arm/src/armv6-m/up_initialstate.c @@ -96,7 +96,7 @@ void up_initial_state(struct tcb_s *tcb) /* Save the task entry point (stripping off the thumb bit) */ xcp->regs[REG_PC] = (uint32_t)tcb->start & ~1; - + /* Specify thumb mode */ xcp->regs[REG_XPSR] = ARMV6M_XPSR_T; diff --git a/nuttx/arch/arm/src/armv6-m/up_releasepending.c b/nuttx/arch/arm/src/armv6-m/up_releasepending.c index 08c87ae47..5300f7598 100644 --- a/nuttx/arch/arm/src/armv6-m/up_releasepending.c +++ b/nuttx/arch/arm/src/armv6-m/up_releasepending.c @@ -96,7 +96,7 @@ void up_release_pending(void) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/arm/src/armv6-m/up_reprioritizertr.c b/nuttx/arch/arm/src/armv6-m/up_reprioritizertr.c index 07eeef14b..a90aa9835 100644 --- a/nuttx/arch/arm/src/armv6-m/up_reprioritizertr.c +++ b/nuttx/arch/arm/src/armv6-m/up_reprioritizertr.c @@ -69,7 +69,7 @@ * * Description: * Called when the priority of a running or - * ready-to-run task changes and the reprioritization will + * ready-to-run task changes and the reprioritization will * cause a context switch. Two cases: * * 1) The priority of the currently running task drops and the next @@ -153,7 +153,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/arm/src/armv6-m/up_systemreset.c b/nuttx/arch/arm/src/armv6-m/up_systemreset.c index a02a0abd2..b1c70b3e5 100644 --- a/nuttx/arch/arm/src/armv6-m/up_systemreset.c +++ b/nuttx/arch/arm/src/armv6-m/up_systemreset.c @@ -68,7 +68,7 @@ void up_systemreset(void) regval = ((0x5fa << SYSCON_AIRCR_VECTKEY_SHIFT) | SYSCON_AIRCR_SYSRESETREQ); putreg32(regval, ARMV6M_SYSCON_AIRCR); - /* Ensure completion of memory accesses */ + /* Ensure completion of memory accesses */ __asm volatile ("dsb"); diff --git a/nuttx/arch/arm/src/armv6-m/up_unblocktask.c b/nuttx/arch/arm/src/armv6-m/up_unblocktask.c index e4bfede97..0d51d21ca 100644 --- a/nuttx/arch/arm/src/armv6-m/up_unblocktask.c +++ b/nuttx/arch/arm/src/armv6-m/up_unblocktask.c @@ -108,7 +108,7 @@ void up_unblock_task(struct tcb_s *tcb) /* The currently active task has changed! We need to do * a context switch to the new task. * - * Are we in an interrupt handler? + * Are we in an interrupt handler? */ if (current_regs) @@ -119,7 +119,7 @@ void up_unblock_task(struct tcb_s *tcb) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/arm/src/armv6-m/up_vectors.c b/nuttx/arch/arm/src/armv6-m/up_vectors.c index bb98b0a79..c1d57f2fd 100644 --- a/nuttx/arch/arm/src/armv6-m/up_vectors.c +++ b/nuttx/arch/arm/src/armv6-m/up_vectors.c @@ -84,7 +84,7 @@ extern char _ebss; * Note that the [ ... ] desginated initialiser is a GCC extension. */ -unsigned _vectors[] __attribute__((section(".vectors"))) = +unsigned _vectors[] __attribute__((section(".vectors"))) = { /* Initial stack */ diff --git a/nuttx/arch/arm/src/armv6-m/vfork.S b/nuttx/arch/arm/src/armv6-m/vfork.S index 112d2d88d..5bee4c5e1 100644 --- a/nuttx/arch/arm/src/armv6-m/vfork.S +++ b/nuttx/arch/arm/src/armv6-m/vfork.S @@ -65,7 +65,7 @@ * undefined if the process created by vfork() either modifies any data other than * a variable of type pid_t used to store the return value from vfork(), or returns * from the function in which vfork() was called, or calls any other function before - * successfully calling _exit() or one of the exec family of functions. + * successfully calling _exit() or one of the exec family of functions. * * This thin layer implements vfork by simply calling up_vfork() with the vfork() * context as an argument. The overall sequence is: @@ -94,7 +94,7 @@ * Upon successful completion, vfork() returns 0 to the child process and returns * the process ID of the child process to the parent process. Otherwise, -1 is * returned to the parent, no child process is created, and errno is set to - * indicate the error. + * indicate the error. * ************************************************************************************/ diff --git a/nuttx/arch/arm/src/armv7-a/arm_allocpage.c b/nuttx/arch/arm/src/armv7-a/arm_allocpage.c index cb8710b47..baf2ca111 100644 --- a/nuttx/arch/arm/src/armv7-a/arm_allocpage.c +++ b/nuttx/arch/arm/src/armv7-a/arm_allocpage.c @@ -171,7 +171,7 @@ int arm_allocpage(FAR struct tcb_s *tcb, FAR void **vpage) uintptr_t paddr; uint32_t *pte; unsigned int pgndx; - + /* Since interrupts are disabled, we don't need to anything special. */ DEBUGASSERT(tcb && vpage); @@ -199,7 +199,7 @@ int arm_allocpage(FAR struct tcb_s *tcb, FAR void **vpage) if (g_pgwrap) { /* Yes.. Get a pointer to the L2 entry corresponding to the previous - * mapping -- then zero it! + * mapping -- then zero it! */ uintptr_t oldvaddr = PG_POOL_NDX2VA(g_ptemap[pgndx]); @@ -214,7 +214,7 @@ int arm_allocpage(FAR struct tcb_s *tcb, FAR void **vpage) * case: The I-Cache uses a virtual address index and, hence, since the * NuttX address space is flat, the cached instruction value should be * correct even if the page mapping is no longer in place. - */ + */ } /* Then convert the index to a (physical) page address. */ @@ -231,7 +231,7 @@ int arm_allocpage(FAR struct tcb_s *tcb, FAR void **vpage) *pte = (paddr | MMU_L2_ALLOCFLAGS); /* And save the new L1 index */ - + g_ptemap[pgndx] = PG_POOL_VA2L2NDX(vaddr); /* Finally, return the virtual address of allocated page */ diff --git a/nuttx/arch/arm/src/armv7-a/arm_blocktask.c b/nuttx/arch/arm/src/armv7-a/arm_blocktask.c index eac95984b..2cc52240e 100644 --- a/nuttx/arch/arm/src/armv7-a/arm_blocktask.c +++ b/nuttx/arch/arm/src/armv7-a/arm_blocktask.c @@ -130,7 +130,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -148,7 +148,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state) else if (!up_saveusercontext(rtcb->xcp.regs)) { - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/arm/src/armv7-a/arm_dataabort.c b/nuttx/arch/arm/src/armv7-a/arm_dataabort.c index 06ff0ba35..7a4d2bea1 100644 --- a/nuttx/arch/arm/src/armv7-a/arm_dataabort.c +++ b/nuttx/arch/arm/src/armv7-a/arm_dataabort.c @@ -56,7 +56,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Output debug info if stack dump is selected -- even if +/* Output debug info if stack dump is selected -- even if * debug is not selected. */ @@ -136,7 +136,7 @@ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr) * the exception occurred, this address was provided in the DFAR register. * (It has not yet been saved in the register context save area). */ - + pgllvdbg("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND); if (dfar < PG_PAGED_VBASE || dfar >= PG_PAGED_VEND) { diff --git a/nuttx/arch/arm/src/armv7-a/arm_prefetchabort.c b/nuttx/arch/arm/src/armv7-a/arm_prefetchabort.c index 89a6bf904..4a8e820ab 100644 --- a/nuttx/arch/arm/src/armv7-a/arm_prefetchabort.c +++ b/nuttx/arch/arm/src/armv7-a/arm_prefetchabort.c @@ -56,7 +56,7 @@ /* Debug ********************************************************************/ -/* Output debug info if stack dump is selected -- even if +/* Output debug info if stack dump is selected -- even if * debug is not selected. */ diff --git a/nuttx/arch/arm/src/armv7-a/arm_releasepending.c b/nuttx/arch/arm/src/armv7-a/arm_releasepending.c index 4dccc7e09..004ef51aa 100644 --- a/nuttx/arch/arm/src/armv7-a/arm_releasepending.c +++ b/nuttx/arch/arm/src/armv7-a/arm_releasepending.c @@ -97,7 +97,7 @@ void up_release_pending(void) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -111,13 +111,13 @@ void up_release_pending(void) /* Copy the exception context into the TCB of the task that * was currently active. if up_saveusercontext returns a non-zero - * value, then this is really the previously running task + * value, then this is really the previously running task * restarting! */ else if (!up_saveusercontext(rtcb->xcp.regs)) { - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/arm/src/armv7-a/arm_reprioritizertr.c b/nuttx/arch/arm/src/armv7-a/arm_reprioritizertr.c index 2055d395b..e14b5744b 100644 --- a/nuttx/arch/arm/src/armv7-a/arm_reprioritizertr.c +++ b/nuttx/arch/arm/src/armv7-a/arm_reprioritizertr.c @@ -69,7 +69,7 @@ * * Description: * Called when the priority of a running or - * ready-to-run task changes and the reprioritization will + * ready-to-run task changes and the reprioritization will * cause a context switch. Two cases: * * 1) The priority of the currently running task drops and the next @@ -152,7 +152,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -171,7 +171,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) else if (!up_saveusercontext(rtcb->xcp.regs)) { - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/arm/src/armv7-a/arm_syscall.c b/nuttx/arch/arm/src/armv7-a/arm_syscall.c index 656a3170c..2c9c951d8 100644 --- a/nuttx/arch/arm/src/armv7-a/arm_syscall.c +++ b/nuttx/arch/arm/src/armv7-a/arm_syscall.c @@ -50,7 +50,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Output debug info if stack dump is selected -- even if +/* Output debug info if stack dump is selected -- even if * debug is not selected. */ diff --git a/nuttx/arch/arm/src/armv7-a/arm_unblocktask.c b/nuttx/arch/arm/src/armv7-a/arm_unblocktask.c index 4906a4a8b..f08ceeca3 100644 --- a/nuttx/arch/arm/src/armv7-a/arm_unblocktask.c +++ b/nuttx/arch/arm/src/armv7-a/arm_unblocktask.c @@ -109,7 +109,7 @@ void up_unblock_task(struct tcb_s *tcb) /* The currently active task has changed! We need to do * a context switch to the new task. * - * Are we in an interrupt handler? + * Are we in an interrupt handler? */ if (current_regs) @@ -120,7 +120,7 @@ void up_unblock_task(struct tcb_s *tcb) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -132,7 +132,7 @@ void up_unblock_task(struct tcb_s *tcb) } /* We are not in an interrupt handler. Copy the user C context - * into the TCB of the task that was previously active. if + * into the TCB of the task that was previously active. if * up_saveusercontext returns a non-zero value, then this is really the * previously running task restarting! */ diff --git a/nuttx/arch/arm/src/armv7-a/arm_undefinedinsn.c b/nuttx/arch/arm/src/armv7-a/arm_undefinedinsn.c index af240cf56..5143f9bd5 100644 --- a/nuttx/arch/arm/src/armv7-a/arm_undefinedinsn.c +++ b/nuttx/arch/arm/src/armv7-a/arm_undefinedinsn.c @@ -48,7 +48,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Output debug info if stack dump is selected -- even if +/* Output debug info if stack dump is selected -- even if * debug is not selected. */ diff --git a/nuttx/arch/arm/src/armv7-a/arm_vfork.S b/nuttx/arch/arm/src/armv7-a/arm_vfork.S index d8fa0e14c..b7abc1c0f 100644 --- a/nuttx/arch/arm/src/armv7-a/arm_vfork.S +++ b/nuttx/arch/arm/src/armv7-a/arm_vfork.S @@ -66,7 +66,7 @@ * any data other than a variable of type pid_t used to store the return * value from vfork(), or returns from the function in which vfork() was * called, or calls any other function before successfully calling _exit() - * or one of the exec family of functions. + * or one of the exec family of functions. * * This thin layer implements vfork by simply calling up_vfork() with the * vfork() context as an argument. The overall sequence is: @@ -95,7 +95,7 @@ * Upon successful completion, vfork() returns 0 to the child process and * returns the process ID of the child process to the parent process. * Otherwise, -1 is returned to the parent, no child process is created, - * and errno is set to indicate the error. + * and errno is set to indicate the error. * ****************************************************************************/ diff --git a/nuttx/arch/arm/src/armv7-a/sctlr.h b/nuttx/arch/arm/src/armv7-a/sctlr.h index beb115b32..30b14bb31 100644 --- a/nuttx/arch/arm/src/armv7-a/sctlr.h +++ b/nuttx/arch/arm/src/armv7-a/sctlr.h @@ -256,7 +256,7 @@ nop .endm #endif /* __ASSEMBLY__ */ - + /************************************************************************************ * Inline Functions ************************************************************************************/ diff --git a/nuttx/arch/arm/src/armv7-m/exc_return.h b/nuttx/arch/arm/src/armv7-m/exc_return.h index 9490a3c8a..a84b8a7d4 100644 --- a/nuttx/arch/arm/src/armv7-m/exc_return.h +++ b/nuttx/arch/arm/src/armv7-m/exc_return.h @@ -50,10 +50,10 @@ * exception mechanism relies on this value to detect when the processor has * completed an exception handler. * - * Bits [31:28] of an EXC_RETURN value are always 1. When the processor loads a - * value matching this pattern to the PC it detects that the operation is a not - * a normal branch operation and instead, that the exception is complete. - * Therefore, it starts the exception return sequence. + * Bits [31:28] of an EXC_RETURN value are always 1. When the processor loads a + * value matching this pattern to the PC it detects that the operation is a not + * a normal branch operation and instead, that the exception is complete. + * Therefore, it starts the exception return sequence. * * Bits[4:0] of the EXC_RETURN value indicate the required return stack and eventual * processor mode. The remaining bits of the EXC_RETURN value should be set to 1. @@ -64,23 +64,23 @@ #define EXC_RETURN_BASE 0xffffffe1 /* EXC_RETURN_PROCESS_STACK: The exception saved (and will restore) the hardware - * context using the process stack pointer (if not set, the context was saved + * context using the process stack pointer (if not set, the context was saved * using the main stack pointer) */ - + #define EXC_RETURN_PROCESS_STACK (1 << 2) /* EXC_RETURN_THREAD_MODE: The exception will return to thread mode (if not set, * return stays in handler mode) */ - + #define EXC_RETURN_THREAD_MODE (1 << 3) -/* EXC_RETURN_STD_CONTEXT: The state saved on the stack does not include the +/* EXC_RETURN_STD_CONTEXT: The state saved on the stack does not include the * volatile FP registers and FPSCR. If this bit is clear, the state does include * these registers. */ - + #define EXC_RETURN_STD_CONTEXT (1 << 4) /* EXC_RETURN_HANDLER: Return to handler mode. Exception return gets state from diff --git a/nuttx/arch/arm/src/armv7-m/mpu.h b/nuttx/arch/arm/src/armv7-m/mpu.h index e6929cecf..f6b61816b 100644 --- a/nuttx/arch/arm/src/armv7-m/mpu.h +++ b/nuttx/arch/arm/src/armv7-m/mpu.h @@ -79,19 +79,19 @@ /* MPU Region Number Register Bit Definitions */ -#define MPU_RNR_MASK (0xff) +#define MPU_RNR_MASK (0xff) /* MPU Region Base Address Register Bit Definitions */ #define MPU_RBAR_REGION_SHIFT (0) /* Bits 0-3: MPU region */ #define MPU_RBAR_REGION_MASK (15 << MPU_RBAR_REGION_SHIFT) -#define MPU_RBAR_VALID (1 << 4) /* Bit 4: MPU Region Number valid */ +#define MPU_RBAR_VALID (1 << 4) /* Bit 4: MPU Region Number valid */ #define MPU_RBAR_ADDR_MASK 0xffffffe0 /* Bits N-31: Region base addrese */ /* MPU Region Attributes and Size Register Bit Definitions */ #define MPU_RASR_ENABLE (1 << 0) /* Bit 0: Region enable */ -#define MPU_RASR_SIZE_SHIFT (1) /* Bits 1-5: Size of the MPU protection region */ +#define MPU_RASR_SIZE_SHIFT (1) /* Bits 1-5: Size of the MPU protection region */ #define MPU_RASR_SIZE_MASK (31 << MPU_RASR_SIZE_SHIFT) # define MPU_RASR_SIZE_LOG2(n) ((n-1) << MPU_RASR_SIZE_SHIFT) #define MPU_RASR_SRD_SHIFT (8) /* Bits 8-15: Subregion disable */ diff --git a/nuttx/arch/arm/src/armv7-m/up_blocktask.c b/nuttx/arch/arm/src/armv7-m/up_blocktask.c index 8caf4a2b6..d7965d4c4 100644 --- a/nuttx/arch/arm/src/armv7-m/up_blocktask.c +++ b/nuttx/arch/arm/src/armv7-m/up_blocktask.c @@ -130,7 +130,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/arm/src/armv7-m/up_elf.c b/nuttx/arch/arm/src/armv7-m/up_elf.c index b838a6905..539873d45 100644 --- a/nuttx/arch/arm/src/armv7-m/up_elf.c +++ b/nuttx/arch/arm/src/armv7-m/up_elf.c @@ -296,7 +296,7 @@ int arch_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, S = (offset >> 24) & 1; J1 = S ^ (~(offset >> 23) & 1); J2 = S ^ (~(offset >> 22) & 1); - + upper_insn = ((upper_insn & 0xf800) | (S << 10) | ((offset >> 12) & 0x03ff)); *(uint16_t*)addr = (uint16_t)upper_insn; diff --git a/nuttx/arch/arm/src/armv7-m/up_fpu.S b/nuttx/arch/arm/src/armv7-m/up_fpu.S index f43367fa4..ea8a4995e 100644 --- a/nuttx/arch/arm/src/armv7-m/up_fpu.S +++ b/nuttx/arch/arm/src/armv7-m/up_fpu.S @@ -83,7 +83,7 @@ * * Returned Value: * None - * + * ************************************************************************************/ .thumb_func @@ -189,7 +189,7 @@ up_savefpu: * Returned Value: * This function does not return anything explicitly. However, it is called from * interrupt level assembly logic that assumes that r0 is preserved. - * + * ************************************************************************************/ .thumb_func diff --git a/nuttx/arch/arm/src/armv7-m/up_mpu.c b/nuttx/arch/arm/src/armv7-m/up_mpu.c index 5df3f4ec8..233e62147 100644 --- a/nuttx/arch/arm/src/armv7-m/up_mpu.c +++ b/nuttx/arch/arm/src/armv7-m/up_mpu.c @@ -67,7 +67,7 @@ * all subregions are available (0x00). */ -static const uint8_t g_ms_regionmask[9] = +static const uint8_t g_ms_regionmask[9] = { 0xff, 0xfe, 0xfc, 0xf8, 0xf0, 0xe0, 0xc0, 0x80, 0x00 }; @@ -77,7 +77,7 @@ static const uint8_t g_ms_regionmask[9] = * and 8 means all subregions must be disabled (0xff). */ -static const uint8_t g_ls_regionmask[9] = +static const uint8_t g_ls_regionmask[9] = { 0x00, 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f, 0x7f, 0xff }; diff --git a/nuttx/arch/arm/src/armv7-m/up_releasepending.c b/nuttx/arch/arm/src/armv7-m/up_releasepending.c index 21c79bfc7..0b3fc6247 100644 --- a/nuttx/arch/arm/src/armv7-m/up_releasepending.c +++ b/nuttx/arch/arm/src/armv7-m/up_releasepending.c @@ -96,7 +96,7 @@ void up_release_pending(void) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/arm/src/armv7-m/up_reprioritizertr.c b/nuttx/arch/arm/src/armv7-m/up_reprioritizertr.c index a0d54a688..c2cb07530 100644 --- a/nuttx/arch/arm/src/armv7-m/up_reprioritizertr.c +++ b/nuttx/arch/arm/src/armv7-m/up_reprioritizertr.c @@ -69,7 +69,7 @@ * * Description: * Called when the priority of a running or - * ready-to-run task changes and the reprioritization will + * ready-to-run task changes and the reprioritization will * cause a context switch. Two cases: * * 1) The priority of the currently running task drops and the next @@ -153,7 +153,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/arm/src/armv7-m/up_systemreset.c b/nuttx/arch/arm/src/armv7-m/up_systemreset.c index 0d7bd2736..ef6da0b9f 100644 --- a/nuttx/arch/arm/src/armv7-m/up_systemreset.c +++ b/nuttx/arch/arm/src/armv7-m/up_systemreset.c @@ -69,7 +69,7 @@ void up_systemreset(void) regval |= ((0x5fa << NVIC_AIRCR_VECTKEY_SHIFT) | NVIC_AIRCR_SYSRESETREQ); putreg32(regval, NVIC_AIRCR); - /* Ensure completion of memory accesses */ + /* Ensure completion of memory accesses */ __asm volatile ("dsb"); diff --git a/nuttx/arch/arm/src/armv7-m/up_unblocktask.c b/nuttx/arch/arm/src/armv7-m/up_unblocktask.c index 8c6551b8e..551e5b67b 100644 --- a/nuttx/arch/arm/src/armv7-m/up_unblocktask.c +++ b/nuttx/arch/arm/src/armv7-m/up_unblocktask.c @@ -109,7 +109,7 @@ void up_unblock_task(struct tcb_s *tcb) /* The currently active task has changed! We need to do * a context switch to the new task. * - * Are we in an interrupt handler? + * Are we in an interrupt handler? */ if (current_regs) @@ -120,7 +120,7 @@ void up_unblock_task(struct tcb_s *tcb) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/arm/src/armv7-m/up_vectors.c b/nuttx/arch/arm/src/armv7-m/up_vectors.c index b3f393f3b..dddccac31 100644 --- a/nuttx/arch/arm/src/armv7-m/up_vectors.c +++ b/nuttx/arch/arm/src/armv7-m/up_vectors.c @@ -79,7 +79,7 @@ extern char _ebss; * Note that the [ ... ] designated initialiser is a GCC extension. */ -unsigned _vectors[] __attribute__((section(".vectors"))) = +unsigned _vectors[] __attribute__((section(".vectors"))) = { /* Initial stack */ diff --git a/nuttx/arch/arm/src/armv7-m/vfork.S b/nuttx/arch/arm/src/armv7-m/vfork.S index f36ff23aa..c6a0f2401 100644 --- a/nuttx/arch/arm/src/armv7-m/vfork.S +++ b/nuttx/arch/arm/src/armv7-m/vfork.S @@ -66,7 +66,7 @@ * undefined if the process created by vfork() either modifies any data other than * a variable of type pid_t used to store the return value from vfork(), or returns * from the function in which vfork() was called, or calls any other function before - * successfully calling _exit() or one of the exec family of functions. + * successfully calling _exit() or one of the exec family of functions. * * This thin layer implements vfork by simply calling up_vfork() with the vfork() * context as an argument. The overall sequence is: @@ -95,7 +95,7 @@ * Upon successful completion, vfork() returns 0 to the child process and returns * the process ID of the child process to the parent process. Otherwise, -1 is * returned to the parent, no child process is created, and errno is set to - * indicate the error. + * indicate the error. * ************************************************************************************/ diff --git a/nuttx/arch/arm/src/c5471/c5471_ethernet.c b/nuttx/arch/arm/src/c5471/c5471_ethernet.c index 2799eb2ab..94b392153 100644 --- a/nuttx/arch/arm/src/c5471/c5471_ethernet.c +++ b/nuttx/arch/arm/src/c5471/c5471_ethernet.c @@ -413,7 +413,7 @@ static inline void c5471_dumpbuffer(const char *msg, const uint8_t *buffer, unsi /* CONFIG_DEBUG, CONFIG_DEBUG_VERBOSE, and CONFIG_DEBUG_NET have to be * defined or the following does nothing. */ - + nvdbgdumpbuffer(msg, buffer, nbytes); } #else @@ -723,7 +723,7 @@ static int c5471_phyinit (void) /* Next, request a chip reset */ - c5471_mdwrite(0, MD_PHY_CONTROL_REG, 0x8000); + c5471_mdwrite(0, MD_PHY_CONTROL_REG, 0x8000); while (c5471_mdread(0, MD_PHY_CONTROL_REG) & 0x8000) { /* wait for chip reset to complete */ @@ -743,15 +743,15 @@ static int c5471_phyinit (void) #ifdef CONFIG_C5471_AUTONEGOTIATION ndbg("Setting PHY Transceiver for Autonegotiation\n"); c5471_mdwrite(0, MD_PHY_CONTROL_REG, MODE_AUTONEG); -#endif +#endif #ifdef CONFIG_C5471_BASET100 ndbg("Setting PHY Transceiver for 100BaseT FullDuplex\n"); c5471_mdwrite(0, MD_PHY_CONTROL_REG, MODE_100MBIT_FULLDUP); -#endif +#endif #ifdef CONFIG_C5471_BASET10 ndbg("Setting PHY Transceiver for 10BaseT FullDuplex\n"); c5471_mdwrite(0, MD_PHY_CONTROL_REG, MODE_10MBIT_FULLDUP); -#endif +#endif status = c5471_mdread(0, MD_PHY_CTRL_STAT_REG); return status; @@ -1479,7 +1479,7 @@ static int c5471_interrupt(int irq, FAR void *context) c5471_txdone(c5471); } - /* Enable Ethernet interrupts (perhaps excluding the TX done interrupt if + /* Enable Ethernet interrupts (perhaps excluding the TX done interrupt if * there are no pending transmissions. */ @@ -1567,7 +1567,7 @@ static void c5471_polltimer(int argc, uint32_t arg, ...) * * Description: * NuttX Callback: Bring up the Ethernet interface when an IP address is - * provided + * provided * * Parameters: * dev - Reference to the NuttX driver state structure @@ -1680,7 +1680,7 @@ static int c5471_ifdown(struct uip_driver_s *dev) * Function: c5471_txavail * * Description: - * Driver callback invoked when new TX data is available. This is a + * Driver callback invoked when new TX data is available. This is a * stimulus perform an out-of-cycle poll and, thereby, reduce the TX * latency. * @@ -1732,7 +1732,7 @@ static int c5471_txavail(struct uip_driver_s *dev) * * Parameters: * dev - Reference to the NuttX driver state structure - * mac - The MAC address to be added + * mac - The MAC address to be added * * Returned Value: * None @@ -1762,7 +1762,7 @@ static int c5471_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac) * * Parameters: * dev - Reference to the NuttX driver state structure - * mac - The MAC address to be removed + * mac - The MAC address to be removed * * Returned Value: * None @@ -1973,7 +1973,7 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471) // putreg32(EIM_FILTER_LOGICAL|EIM_FILTER_UNICAST|EIM_FILTER_MULTICAST| // EIM_FILTER_BROADCAST, EIM_CPU_FILTER); putreg32(EIM_FILTER_UNICAST|EIM_FILTER_MULTICAST|EIM_FILTER_BROADCAST, EIM_CPU_FILTER); -#endif +#endif /* Disable all Ethernet interrupts */ @@ -1984,16 +1984,16 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471) #if 1 putreg32(EIM_CTRL_ENET0_EN|EIM_CTRL_RXENET0_EN|EIM_CTRL_TXENET0_EN| EIM_CTRL_RXCPU_EN|EIM_CTRL_TXCPU_EN, EIM_CTRL); -#else +#else putreg32(EIM_CTRL_ENET0_EN|EIM_CTRL_ENET0_FLW|EIM_CTRL_RXENET0_EN| EIM_CTRL_TXENET0_EN|EIM_CTRL_RXCPU_EN|EIM_CTRL_TXCPU_EN, EIM_CTRL); #endif -#if 1 +#if 1 putreg32(0x00000000, EIM_MFVHI); #else putreg32(0x0000ff00, EIM_MFVHI); -#endif +#endif putreg32(0x00000000, EIM_MFVLO); putreg32(0x00000000, EIM_MFMHI); @@ -2007,16 +2007,16 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471) putreg32(ENET_MODE_RJCT_SFE|ENET_MODE_MWIDTH|ENET_MODE_FULLDUPLEX, ENET0_MODE); #else putreg32(ENET_MODE_RJCT_SFE|ENET_MODE_MWIDTH|ENET_MODE_HALFDUPLEX, ENET0_MODE); -#endif +#endif putreg32(0x00000000, ENET0_BOFFSEED); putreg32(0x00000000, ENET0_FLWPAUSE); putreg32(0x00000000, ENET0_FLWCONTROL); putreg32(0x00000000, ENET0_VTYPE); -#if 0 +#if 0 putreg32(ENET_ADR_BROADCAST|ENET_ADR_PROMISCUOUS, ENET0_ADRMODE_EN); -#else +#else /* The CPU port is not PROMISCUOUS, it wants a no-promiscuous address * match yet the SWITCH receives packets from the PROMISCUOUS ENET0 * which routes all packets for filter matching at the CPU port which @@ -2026,7 +2026,7 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471) */ putreg32(ENET_ADR_PROMISCUOUS, ENET0_ADRMODE_EN); -#endif +#endif putreg32(0x00000000, ENET0_DRP); up_mdelay(500); @@ -2093,7 +2093,7 @@ static void c5471_macassign(struct c5471_driver_s *c5471) putreg32(getreg32(EIM_CPU_DALO), ENET0_LARLO); #else - /* ENET MAC assignment not needed for its PROMISCUOUS mode */ + /* ENET MAC assignment not needed for its PROMISCUOUS mode */ putreg32(0x00000000, ENET0_PARHI); putreg32(0x00000000, ENET0_PARLO); diff --git a/nuttx/arch/arm/src/c5471/c5471_serial.c b/nuttx/arch/arm/src/c5471/c5471_serial.c index 09018cb28..b993ee8bc 100644 --- a/nuttx/arch/arm/src/c5471/c5471_serial.c +++ b/nuttx/arch/arm/src/c5471/c5471_serial.c @@ -805,7 +805,7 @@ static bool up_txempty(struct uart_dev_s *dev) * Name: up_serialinit * * Description: - * Performs the low level UART initialization early in + * Performs the low level UART initialization early in * debug so that the serial console will be available * during bootup. This must be called before up_serialinit. * diff --git a/nuttx/arch/arm/src/c5471/c5471_vectors.S b/nuttx/arch/arm/src/c5471/c5471_vectors.S index ba4b5e3ee..511193f42 100644 --- a/nuttx/arch/arm/src/c5471/c5471_vectors.S +++ b/nuttx/arch/arm/src/c5471/c5471_vectors.S @@ -185,7 +185,7 @@ up_vectorirq: /************************************************************************************ * Function: up_vectorswi - * + * * Description: * SWI interrupt. We enter the SWI in SVC mode ************************************************************************************/ diff --git a/nuttx/arch/arm/src/common/up_internal.h b/nuttx/arch/arm/src/common/up_internal.h index 615af320e..2f0309b4f 100644 --- a/nuttx/arch/arm/src/common/up_internal.h +++ b/nuttx/arch/arm/src/common/up_internal.h @@ -248,7 +248,7 @@ extern uint32_t _ebss; /* End+1 of .bss */ * * will create a function named foo that will execute from RAM. */ - + #ifdef CONFIG_ARCH_RAMFUNCS # define __ramfunc__ __attribute__ ((section(".ramfunc"),long_call)) diff --git a/nuttx/arch/arm/src/common/up_signal_dispatch.c b/nuttx/arch/arm/src/common/up_signal_dispatch.c index 7755ca7e4..d46b77928 100644 --- a/nuttx/arch/arm/src/common/up_signal_dispatch.c +++ b/nuttx/arch/arm/src/common/up_signal_dispatch.c @@ -73,7 +73,7 @@ * * Normally the a user-mode signalling handling stub will also execute * before the ultimate signal handler is called. See - * arch/arm/src/armv[6\7]/up_signal_handler. This function is the + * arch/arm/src/armv[6\7]/up_signal_handler. This function is the * user-space, signal handler trampoline function. It is called from * up_signal_dispatch() in user-mode. * diff --git a/nuttx/arch/arm/src/common/up_stackframe.c b/nuttx/arch/arm/src/common/up_stackframe.c index 2a38f1db8..086d6cadc 100644 --- a/nuttx/arch/arm/src/common/up_stackframe.c +++ b/nuttx/arch/arm/src/common/up_stackframe.c @@ -127,7 +127,7 @@ FAR void *up_stack_frame(FAR struct tcb_s *tcb, size_t frame_size) /* Align the frame_size */ frame_size = STACK_ALIGN_UP(frame_size); - + /* Is there already a stack allocated? Is it big enough? */ if (!tcb->stack_alloc_ptr || tcb->adj_stack_size <= frame_size) diff --git a/nuttx/arch/arm/src/common/up_vfork.c b/nuttx/arch/arm/src/common/up_vfork.c index 4e9f76718..56b061b53 100644 --- a/nuttx/arch/arm/src/common/up_vfork.c +++ b/nuttx/arch/arm/src/common/up_vfork.c @@ -90,7 +90,7 @@ * any data other than a variable of type pid_t used to store the return * value from vfork(), or returns from the function in which vfork() was * called, or calls any other function before successfully calling _exit() - * or one of the exec family of functions. + * or one of the exec family of functions. * * The overall sequence is: * @@ -120,7 +120,7 @@ * Upon successful completion, vfork() returns 0 to the child process and * returns the process ID of the child process to the parent process. * Otherwise, -1 is returned to the parent, no child process is created, - * and errno is set to indicate the error. + * and errno is set to indicate the error. * ****************************************************************************/ @@ -180,7 +180,7 @@ pid_t up_vfork(const struct vfork_s *context) DEBUGASSERT((uint32_t)parent->adj_stack_ptr > context->sp); stackutil = (uint32_t)parent->adj_stack_ptr - context->sp; - svdbg("stacksize:%d stackutil:%d\n", stacksize, stackutil); + svdbg("stacksize:%d stackutil:%d\n", stacksize, stackutil); /* Make some feeble effort to perserve the stack contents. This is * feeble because the stack surely contains invalid pointers and other diff --git a/nuttx/arch/arm/src/dm320/dm320_boot.c b/nuttx/arch/arm/src/dm320/dm320_boot.c index e8041923a..f68f3ca36 100644 --- a/nuttx/arch/arm/src/dm320/dm320_boot.c +++ b/nuttx/arch/arm/src/dm320/dm320_boot.c @@ -74,21 +74,21 @@ extern uint32_t _vector_end; /* End+1 of vector block */ static const struct section_mapping_s section_mapping[] = { - { DM320_PERIPHERALS_PSECTION, DM320_PERIPHERALS_VSECTION, + { DM320_PERIPHERALS_PSECTION, DM320_PERIPHERALS_VSECTION, DM320_PERIPHERALS_MMUFLAGS, DM320_PERIPHERALS_NSECTIONS}, - { DM320_FLASH_PSECTION, DM320_FLASH_VSECTION, + { DM320_FLASH_PSECTION, DM320_FLASH_VSECTION, DM320_FLASH_MMUFLAGS, DM320_FLASH_NSECTIONS}, - { DM320_CFI_PSECTION, DM320_CFI_VSECTION, + { DM320_CFI_PSECTION, DM320_CFI_VSECTION, DM320_CFI_MMUFLAGS, DM320_CFI_NSECTIONS}, - { DM320_SSFDC_PSECTION, DM320_SSFDC_VSECTION, + { DM320_SSFDC_PSECTION, DM320_SSFDC_VSECTION, DM320_SSFDC_MMUFLAGS, DM320_SSFDC_NSECTIONS}, - { DM320_CE1_PSECTION, DM320_CE1_VSECTION, + { DM320_CE1_PSECTION, DM320_CE1_VSECTION, DM320_CE1_MMUFLAGS, DM320_CE1_NSECTIONS}, - { DM320_CE2_PSECTION, DM320_CE2_VSECTION, + { DM320_CE2_PSECTION, DM320_CE2_VSECTION, DM320_CE2_MMUFLAGS, DM320_CE2_NSECTIONS}, - { DM320_VLYNQ_PSECTION, DM320_VLYNQ_VSECTION, + { DM320_VLYNQ_PSECTION, DM320_VLYNQ_VSECTION, DM320_VLYNQ_MMUFLAGS, DM320_VLYNQ_NSECTIONS}, - { DM320_USBOTG_PSECTION, DM320_USBOTG_VSECTION, + { DM320_USBOTG_PSECTION, DM320_USBOTG_VSECTION, DM320_USBOTG_MMUFLAGS, DM320_USBOTG_NSECTIONS} }; #define NMAPPINGS (sizeof(section_mapping) / sizeof(struct section_mapping_s)) diff --git a/nuttx/arch/arm/src/dm320/dm320_memorymap.h b/nuttx/arch/arm/src/dm320/dm320_memorymap.h index edcf4312c..67923b150 100644 --- a/nuttx/arch/arm/src/dm320/dm320_memorymap.h +++ b/nuttx/arch/arm/src/dm320/dm320_memorymap.h @@ -67,7 +67,7 @@ * section address for most regions can be overriden if the same setting is * defined in the board.h file (These defaults correspond to the product Neuros * OSD memory configuration). - * + * * 2. The DM320 only has a single control line for external peripherals. To support * more than one peripheral, most hardware will use external memory decode logic, * so that physical memory regions is in the board-specific files. @@ -125,7 +125,7 @@ #define DM320_CFI_NSECTIONS 16 /* 16Mb 16 sections -- */ #define DM320_CFI_SIZE (16*1024*1024) #define DM320_SSFDC_NSECTIONS 16 /* 16Mb 16 sections -- */ -#define DM320_SSFDC_SIZE (16*1024*1024) +#define DM320_SSFDC_SIZE (16*1024*1024) #define DM320_CE1_NSECTIONS 16 /* 16Mb 16 sections -- */ #define DM320_CE1_SIZE (16*1024*1024) #define DM320_CE2_NSECTIONS 16 /* 16Mb 16 sections -- */ diff --git a/nuttx/arch/arm/src/dm320/dm320_serial.c b/nuttx/arch/arm/src/dm320/dm320_serial.c index abea36d57..daf711d69 100644 --- a/nuttx/arch/arm/src/dm320/dm320_serial.c +++ b/nuttx/arch/arm/src/dm320/dm320_serial.c @@ -502,7 +502,7 @@ static int up_interrupt(int irq, void *context) status = up_serialin(priv, UART_SR); status &= (UART_SR_RFTI | UART_SR_TFTI); - if (status == 0 || passes > 256) + if (status == 0 || passes > 256) { return OK; } @@ -719,7 +719,7 @@ static bool up_txempty(struct uart_dev_s *dev) * Name: up_serialinit * * Description: - * Performs the low level UART initialization early in + * Performs the low level UART initialization early in * debug so that the serial console will be available * during bootup. This must be called before up_serialinit. * diff --git a/nuttx/arch/arm/src/dm320/dm320_timerisr.c b/nuttx/arch/arm/src/dm320/dm320_timerisr.c index 59efa53d3..4914a8306 100644 --- a/nuttx/arch/arm/src/dm320/dm320_timerisr.c +++ b/nuttx/arch/arm/src/dm320/dm320_timerisr.c @@ -56,24 +56,24 @@ /* DM320 Timers * * Each of the general-purpose timers can run in one of two modes: one- - * shot mode and free-run mode. In one-shot mode, an interrupt only - * occurs once and then the timer must be explicitly reset to begin the - * timing operation again. In free-run mode, when the timer generates an - * interrupt, the timer counter is automatically reloaded to start the count - * operation again. Use the bit field MODE in TMMDx to configure the + * shot mode and free-run mode. In one-shot mode, an interrupt only + * occurs once and then the timer must be explicitly reset to begin the + * timing operation again. In free-run mode, when the timer generates an + * interrupt, the timer counter is automatically reloaded to start the count + * operation again. Use the bit field MODE in TMMDx to configure the * timer for one-shot more or free-run mode. The bit field MODE in TMMDx * also allows you to stop the timer. - * - * Either the ARM clock divided by 2 (CLK_ARM/2) or an external clock - * connected to the M27XI pin can be selected as the clock source of the + * + * Either the ARM clock divided by 2 (CLK_ARM/2) or an external clock + * connected to the M27XI pin can be selected as the clock source of the * timer. * - * The actual clock frequency used in the timer count operation is the input - * clock divided by: 1 plus the value set in the bit field PRSCL of the - * register TMPRSCLx (10 bits). The timer expires when it reaches the - * value set in the bit field DIV of the register TMDIVx (16 bits) plus 1. - * PRSCL+1 is the source clock frequency divide factor and DIV+1 is the - * timer count value. The frequency of a timer interrupt is given by the + * The actual clock frequency used in the timer count operation is the input + * clock divided by: 1 plus the value set in the bit field PRSCL of the + * register TMPRSCLx (10 bits). The timer expires when it reaches the + * value set in the bit field DIV of the register TMDIVx (16 bits) plus 1. + * PRSCL+1 is the source clock frequency divide factor and DIV+1 is the + * timer count value. The frequency of a timer interrupt is given by the * following equation: * * Interrupt Frequency = (Source Clock Frequency) / (PRSCL+1) / (DIV+1) diff --git a/nuttx/arch/arm/src/dm320/dm320_usbdev.c b/nuttx/arch/arm/src/dm320/dm320_usbdev.c index 97804b492..699a68edf 100644 --- a/nuttx/arch/arm/src/dm320/dm320_usbdev.c +++ b/nuttx/arch/arm/src/dm320/dm320_usbdev.c @@ -827,7 +827,7 @@ static int dm320_epread(uint8_t epphy, uint8_t *buf, uint16_t nbytes) bytesleft = nbytes; } } - else + else { bytesleft = dm320_getreg8(DM320_USB_RXCOUNT2); bytesleft = (bytesleft << 8) + dm320_getreg8(DM320_USB_RXCOUNT1); @@ -1562,7 +1562,7 @@ static int dm320_ctlrinterrupt(int irq, FAR void *context) { /* Now ignore these unknown interrupts */ - dm320_putreg8(USB_PERCSR0_CLRRXRDY | USB_PERCSR0_DATAEND, DM320_USB_PERCSR0); + dm320_putreg8(USB_PERCSR0_CLRRXRDY | USB_PERCSR0_DATAEND, DM320_USB_PERCSR0); usbtrace(TRACE_INTENTRY(DM320_TRACEINTID_UNKNOWN), csr0); } } @@ -1719,7 +1719,7 @@ static inline void dm320_epinitialize(struct dm320_usbdev_s *priv) /* Initialize endpoint 0 */ - dm320_putreg8(USB_EP0_SELECT, DM320_USB_INDEX); + dm320_putreg8(USB_EP0_SELECT, DM320_USB_INDEX); dm320_putreg8(USB_PERCSR0_CLRSETEND|USB_PERCSR0_CLRRXRDY, DM320_USB_PERCSR0); dm320_putreg8(USB_CSR2_FLFIFO, DM320_USB_CSR2); dm320_putreg8(USB_CSR2_FLFIFO, DM320_USB_CSR2); @@ -1837,7 +1837,7 @@ static void dm320_ctrlinitialize(FAR struct dm320_usbdev_s *priv) dm320_putreg8((DM320_EPBULKIN << 1), DM320_USB_INTRRX1E); dm320_putreg8((DM320_EPBULKOUT << 1) | USB_EP0, DM320_USB_INTRTX1E); dm320_putreg8(USB_INT_RESET|USB_INT_RESUME|USB_INT_SUSPEND|USB_INT_SESSRQ|USB_INT_SOF, - DM320_USB_INTRUSBE); + DM320_USB_INTRUSBE); /* Initialize endpoints ******************************************************/ @@ -2288,7 +2288,7 @@ static int dm320_wakeup(struct usbdev_s *dev) * Name: dm320_selfpowered * * Description: - * Sets/clears the device selfpowered feature + * Sets/clears the device selfpowered feature * *******************************************************************************/ @@ -2375,7 +2375,7 @@ void up_usbinitialize(void) /* Enable USB clock & GIO clock */ - dm320_putreg16(dm320_getreg16(DM320_CLKC_MOD2) | 0x0060, DM320_CLKC_MOD2); + dm320_putreg16(dm320_getreg16(DM320_CLKC_MOD2) | 0x0060, DM320_CLKC_MOD2); dm320_putreg16(dm320_getreg16(DM320_CLKC_DIV4) | (((4) - 1) << 8) | ((1) - 1), DM320_CLKC_DIV4); /* Initialize D+ pullup control GIO */ diff --git a/nuttx/arch/arm/src/imx/imx_aitc.h b/nuttx/arch/arm/src/imx/imx_aitc.h index 5b83c5f46..81da15ef8 100644 --- a/nuttx/arch/arm/src/imx/imx_aitc.h +++ b/nuttx/arch/arm/src/imx/imx_aitc.h @@ -39,7 +39,7 @@ /************************************************************************************ * Included Files ************************************************************************************/ - + /************************************************************************************ * Definitions ************************************************************************************/ diff --git a/nuttx/arch/arm/src/imx/imx_boot.c b/nuttx/arch/arm/src/imx/imx_boot.c index 2ab89b94e..e1dfb7846 100644 --- a/nuttx/arch/arm/src/imx/imx_boot.c +++ b/nuttx/arch/arm/src/imx/imx_boot.c @@ -78,19 +78,19 @@ extern uint32_t _vector_end; /* End+1 of vector block */ static const struct section_mapping_s section_mapping[] = { - { IMX_PERIPHERALS_PSECTION, IMX_PERIPHERALS_VSECTION, + { IMX_PERIPHERALS_PSECTION, IMX_PERIPHERALS_VSECTION, IMX_PERIPHERALS_MMUFLAGS, IMX_PERIPHERALS_NSECTIONS}, - { IMX_FLASH_PSECTION, IMX_FLASH_VSECTION, + { IMX_FLASH_PSECTION, IMX_FLASH_VSECTION, IMX_FLASH_MMUFLAGS, IMX_FLASH_NSECTIONS}, - { IMX_CS1_PSECTION, IMX_CS1_VSECTION, + { IMX_CS1_PSECTION, IMX_CS1_VSECTION, IMX_PERIPHERALS_MMUFLAGS, IMX_CS1_NSECTIONS}, - { IMX_CS2_PSECTION, IMX_CS2_VSECTION, + { IMX_CS2_PSECTION, IMX_CS2_VSECTION, IMX_PERIPHERALS_MMUFLAGS, IMX_CS2_NSECTIONS}, - { IMX_CS3_PSECTION, IMX_CS3_VSECTION, + { IMX_CS3_PSECTION, IMX_CS3_VSECTION, IMX_PERIPHERALS_MMUFLAGS, IMX_CS3_NSECTIONS}, - { IMX_CS4_PSECTION, IMX_CS4_VSECTION, + { IMX_CS4_PSECTION, IMX_CS4_VSECTION, IMX_PERIPHERALS_MMUFLAGS, IMX_CS4_NSECTIONS}, - { IMX_CS5_PSECTION, IMX_CS5_VSECTION, + { IMX_CS5_PSECTION, IMX_CS5_VSECTION, IMX_PERIPHERALS_MMUFLAGS, IMX_CS5_NSECTIONS}, }; diff --git a/nuttx/arch/arm/src/imx/imx_cspi.h b/nuttx/arch/arm/src/imx/imx_cspi.h index 0c8c0f9d9..14f95e7ed 100644 --- a/nuttx/arch/arm/src/imx/imx_cspi.h +++ b/nuttx/arch/arm/src/imx/imx_cspi.h @@ -182,7 +182,7 @@ extern "C" { * include/nuttx/spi/spi.h). All other methods (including up_spiinitialize()) are * provided by common logic. To use this common SPI logic on your board: * - * 1. Provide imx_spiselect() and imx_spistatus() functions in your board-specific + * 1. Provide imx_spiselect() and imx_spistatus() functions in your board-specific * logic. This function will perform chip selection and status operations using * GPIOs in the way your board is configured. * 2. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration, provide the diff --git a/nuttx/arch/arm/src/imx/imx_dma.h b/nuttx/arch/arm/src/imx/imx_dma.h index 2d5d553ce..13ad5ad70 100644 --- a/nuttx/arch/arm/src/imx/imx_dma.h +++ b/nuttx/arch/arm/src/imx/imx_dma.h @@ -39,7 +39,7 @@ /************************************************************************************ * Included Files ************************************************************************************/ - + /************************************************************************************ * Definitions ************************************************************************************/ diff --git a/nuttx/arch/arm/src/imx/imx_eim.h b/nuttx/arch/arm/src/imx/imx_eim.h index decd54e46..8a048259e 100644 --- a/nuttx/arch/arm/src/imx/imx_eim.h +++ b/nuttx/arch/arm/src/imx/imx_eim.h @@ -39,7 +39,7 @@ /************************************************************************************ * Included Files ************************************************************************************/ - + /************************************************************************************ * Definitions ************************************************************************************/ @@ -62,18 +62,18 @@ /* EIM Register Addresses ***********************************************************/ -#define IMX_EIM_CS0H (EIM_BASE_ADDR + EIM_CS0H_OFFSET) -#define IMX_EIM_CS0L (EIM_BASE_ADDR + EIM_CS0L_OFFSET) -#define IMX_EIM_CS1H (EIM_BASE_ADDR + EIM_CS1H_OFFSET) -#define IMX_EIM_CS1L (EIM_BASE_ADDR + EIM_CS1L_OFFSET) -#define IMX_EIM_CS2H (EIM_BASE_ADDR + EIM_CS2H_OFFSET) -#define IMX_EIM_CS2L (EIM_BASE_ADDR + EIM_CS2L_OFFSET) -#define IMX_EIM_CS3H (EIM_BASE_ADDR + EIM_CS3H_OFFSET) -#define IMX_EIM_CS3L (EIM_BASE_ADDR + EIM_CS3L_OFFSET) -#define IMX_EIM_CS4H (EIM_BASE_ADDR + EIM_CS4H_OFFSET) -#define IMX_EIM_CS4L (EIM_BASE_ADDR + EIM_CS4L_OFFSET) -#define IMX_EIM_CS5H (EIM_BASE_ADDR + EIM_CS5H_OFFSET) -#define IMX_EIM_CS5L (EIM_BASE_ADDR + EIM_CS5L_OFFSET) +#define IMX_EIM_CS0H (EIM_BASE_ADDR + EIM_CS0H_OFFSET) +#define IMX_EIM_CS0L (EIM_BASE_ADDR + EIM_CS0L_OFFSET) +#define IMX_EIM_CS1H (EIM_BASE_ADDR + EIM_CS1H_OFFSET) +#define IMX_EIM_CS1L (EIM_BASE_ADDR + EIM_CS1L_OFFSET) +#define IMX_EIM_CS2H (EIM_BASE_ADDR + EIM_CS2H_OFFSET) +#define IMX_EIM_CS2L (EIM_BASE_ADDR + EIM_CS2L_OFFSET) +#define IMX_EIM_CS3H (EIM_BASE_ADDR + EIM_CS3H_OFFSET) +#define IMX_EIM_CS3L (EIM_BASE_ADDR + EIM_CS3L_OFFSET) +#define IMX_EIM_CS4H (EIM_BASE_ADDR + EIM_CS4H_OFFSET) +#define IMX_EIM_CS4L (EIM_BASE_ADDR + EIM_CS4L_OFFSET) +#define IMX_EIM_CS5H (EIM_BASE_ADDR + EIM_CS5H_OFFSET) +#define IMX_EIM_CS5L (EIM_BASE_ADDR + EIM_CS5L_OFFSET) #define IMX_EIM_WEIM (EIM_BASE_ADDR + EIM_WEIM_OFFSET) /* EIM Register Bit Definitions *****************************************************/ diff --git a/nuttx/arch/arm/src/imx/imx_gpio.h b/nuttx/arch/arm/src/imx/imx_gpio.h index dcdf9c68e..415d16679 100644 --- a/nuttx/arch/arm/src/imx/imx_gpio.h +++ b/nuttx/arch/arm/src/imx/imx_gpio.h @@ -45,7 +45,7 @@ # include <stdint.h> #endif #include "up_arch.h" /* getreg32(), putreg32() */ - + /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ diff --git a/nuttx/arch/arm/src/imx/imx_i2c.h b/nuttx/arch/arm/src/imx/imx_i2c.h index 8b1c065e2..990199e1f 100644 --- a/nuttx/arch/arm/src/imx/imx_i2c.h +++ b/nuttx/arch/arm/src/imx/imx_i2c.h @@ -39,7 +39,7 @@ /************************************************************************************ * Included Files ************************************************************************************/ - + /************************************************************************************ * Definitions ************************************************************************************/ @@ -54,11 +54,11 @@ /* I2C Register Addresses ***********************************************************/ -#define IMX_I2C_IADR (IMX_I2C_VBASE + I2C_IADR_OFFSET) +#define IMX_I2C_IADR (IMX_I2C_VBASE + I2C_IADR_OFFSET) #define IMX_I2C_IFDR (IMX_I2C_VBASE + I2C_IFDR_OFFSET) #define IMX_I2C_I2CR (IMX_I2C_VBASE + I2C_I2CR_OFFSET) -#define IMX_I2C_I2SR (IMX_I2C_VBASE + I2C_I2SR_OFFSET) -#define IMX_I2C_I2DR (IMX_I2C_VBASE + I2C_I2DR_OFFSET) +#define IMX_I2C_I2SR (IMX_I2C_VBASE + I2C_I2SR_OFFSET) +#define IMX_I2C_I2DR (IMX_I2C_VBASE + I2C_I2DR_OFFSET) /* I2C Register Bit Definitions *****************************************************/ diff --git a/nuttx/arch/arm/src/imx/imx_lowputc.S b/nuttx/arch/arm/src/imx/imx_lowputc.S index b0c8163a3..2845dc3b9 100644 --- a/nuttx/arch/arm/src/imx/imx_lowputc.S +++ b/nuttx/arch/arm/src/imx/imx_lowputc.S @@ -93,7 +93,7 @@ up_lowputc: ldr r2, =IMX_UART2_VBASE /* r2=UART0 base */ #endif - /* Poll the TX fifo trigger level bit of the UART status register #2 . + /* Poll the TX fifo trigger level bit of the UART status register #2 . * When the bit is non-zero, the TX Buffer FIFO is empty. */ diff --git a/nuttx/arch/arm/src/imx/imx_memorymap.h b/nuttx/arch/arm/src/imx/imx_memorymap.h index 3a86ce943..9a063b368 100644 --- a/nuttx/arch/arm/src/imx/imx_memorymap.h +++ b/nuttx/arch/arm/src/imx/imx_memorymap.h @@ -85,7 +85,7 @@ * - All vector addresses are FLASH absolute addresses, * - DRAM cannot reside at address zero, * - Vectors at address zero (CR_V is not set), - * - The boot logic must configure SDRAM and, + * - The boot logic must configure SDRAM and, * - The .data section in RAM must be initialized. * * 2. We boot in FLASH but copy ourselves to DRAM from better performance. @@ -140,7 +140,7 @@ /* Peripheral Register Offsets ******************************************************/ #define IMX_AIPI1_OFFSET 0x00000000 /* -0x00000fff AIPI1 4Kb */ -#define IMX_WDOG_OFFSET 0x00001000 /* -0x00001fff WatchDog 4Kb */ +#define IMX_WDOG_OFFSET 0x00001000 /* -0x00001fff WatchDog 4Kb */ #define IMX_TIMER1_OFFSET 0x00002000 /* -0x00002fff Timer1 4Kb */ #define IMX_TIMER2_OFFSET 0x00003000 /* -0x00003fff Timer2 4Kb */ #define IMX_RTC_OFFSET 0x00004000 /* -0x00004fff RTC 4Kb */ diff --git a/nuttx/arch/arm/src/imx/imx_rtc.h b/nuttx/arch/arm/src/imx/imx_rtc.h index 249e7a40d..f07c00c91 100644 --- a/nuttx/arch/arm/src/imx/imx_rtc.h +++ b/nuttx/arch/arm/src/imx/imx_rtc.h @@ -39,7 +39,7 @@ /************************************************************************************ * Included Files ************************************************************************************/ - + /************************************************************************************ * Definitions ************************************************************************************/ diff --git a/nuttx/arch/arm/src/imx/imx_serial.c b/nuttx/arch/arm/src/imx/imx_serial.c index c866a53f9..d5423ff4a 100644 --- a/nuttx/arch/arm/src/imx/imx_serial.c +++ b/nuttx/arch/arm/src/imx/imx_serial.c @@ -514,7 +514,7 @@ static int up_setup(struct uart_dev_s *dev) if (priv->hwfc) { ucr2 |= UART_UCR2_IRTS; - + /* CTS controled by Rx FIFO */ ucr2 |= UART_UCR2_CTSC; @@ -533,7 +533,7 @@ static int up_setup(struct uart_dev_s *dev) up_serialout(priv, UART_UCR2, ucr2); - /* Set the baud. + /* Set the baud. * * baud * 16 / REFFREQ = NUM/DEN * UBIR = NUM-1; @@ -628,7 +628,7 @@ static int up_setup(struct uart_dev_s *dev) /* Set the TX trigger level to interrupt when the TxFIFO has 2 or fewer characters. * Set the RX trigger level to interrupt when the RxFIFO has 1 character. */ - + regval |= ((2 << UART_UFCR_TXTL_SHIFT) | (1 << UART_UFCR_RXTL_SHIFT)); up_serialout(priv, UART_UFCR, regval); @@ -803,7 +803,7 @@ static inline struct uart_dev_s *up_mapirq(int irq) break; } return dev; -} +} /**************************************************************************** * Name: up_interrupt (and front-ends) @@ -841,7 +841,7 @@ static int up_interrupt(int irq, void *context) usr1 = up_serialin(priv, UART_USR1); usr1 &= (UART_USR1_RRDY | UART_USR1_TRDY); - if (usr1 == 0 || passes > 256) + if (usr1 == 0 || passes > 256) { return OK; } @@ -971,7 +971,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) static bool up_rxavailable(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - + /* Return true is data is ready in the Rx FIFO */ return ((up_serialin(priv, UART_USR2) & UART_USR2_RDR) != 0); @@ -1062,7 +1062,7 @@ static bool up_txempty(struct uart_dev_s *dev) * Name: up_serialinit * * Description: - * Performs the low level UART initialization early in + * Performs the low level UART initialization early in * debug so that the serial console will be available * during bootup. This must be called before up_serialinit. * diff --git a/nuttx/arch/arm/src/imx/imx_spi.c b/nuttx/arch/arm/src/imx/imx_spi.c index 5b89ac18d..f51bfd734 100644 --- a/nuttx/arch/arm/src/imx/imx_spi.c +++ b/nuttx/arch/arm/src/imx/imx_spi.c @@ -140,7 +140,7 @@ struct imx_spidev_s ****************************************************************************/ /* SPI register access */ - + static inline uint32_t spi_getreg(struct imx_spidev_s *priv, unsigned int offset); static inline void spi_putreg(struct imx_spidev_s *priv, unsigned int offset, uint32_t value); @@ -1083,7 +1083,7 @@ FAR struct spi_dev_s *up_spiinitialize(int port) imxgpio_configinput(GPIOD, 31); imxgpio_ocrbin(GPIOD, 31); imxgpio_dirout(GPIOD, 31); -#else +#else imxgpio_configoutput(GPIOD, 10); #endif break; @@ -1101,7 +1101,7 @@ FAR struct spi_dev_s *up_spiinitialize(int port) /* Initialize control register: min frequency, ignore ready, master mode, mode=0, 8-bit */ - spi_putreg(priv, CSPI_CTRL_OFFSET, + spi_putreg(priv, CSPI_CTRL_OFFSET, CSPI_CTRL_DIV512 | /* Lowest frequency */ CSPI_CTRL_DRCTL_IGNRDY | /* Ignore ready */ CSPI_CTRL_MODE | /* Master mode */ diff --git a/nuttx/arch/arm/src/imx/imx_system.h b/nuttx/arch/arm/src/imx/imx_system.h index ad363f14a..c66a81699 100644 --- a/nuttx/arch/arm/src/imx/imx_system.h +++ b/nuttx/arch/arm/src/imx/imx_system.h @@ -39,7 +39,7 @@ /************************************************************************************ * Included Files ************************************************************************************/ - + /************************************************************************************ * Definitions ************************************************************************************/ @@ -170,13 +170,13 @@ /* SDRAMC Register Offsets **********************************************************/ -#define SDRAMC_SDCTL0_OFFSET 0x0000 -#define SDRAMC_SDCTL1_OFFSET 0x0004 +#define SDRAMC_SDCTL0_OFFSET 0x0000 +#define SDRAMC_SDCTL1_OFFSET 0x0004 /* SDRAMC Register Addresses ********************************************************/ -#define IMX_SDRAMC_SDCTL0 (IMX_SDRAMC_VBASE + SDRAMC_SDCTL0_OFFSET) -#define IMX_SDRAMC_SDCTL1 (IMX_SDRAMC_VBASE + SDRAMC_SDCTL1_OFFSET)) +#define IMX_SDRAMC_SDCTL0 (IMX_SDRAMC_VBASE + SDRAMC_SDCTL0_OFFSET) +#define IMX_SDRAMC_SDCTL1 (IMX_SDRAMC_VBASE + SDRAMC_SDCTL1_OFFSET)) /* SDRAMC Register Bit Definitions **************************************************/ diff --git a/nuttx/arch/arm/src/imx/imx_timer.h b/nuttx/arch/arm/src/imx/imx_timer.h index 9d91d3c0d..e83bb84a1 100644 --- a/nuttx/arch/arm/src/imx/imx_timer.h +++ b/nuttx/arch/arm/src/imx/imx_timer.h @@ -39,7 +39,7 @@ /************************************************************************************ * Included Files ************************************************************************************/ - + /************************************************************************************ * Definitions ************************************************************************************/ diff --git a/nuttx/arch/arm/src/imx/imx_timerisr.c b/nuttx/arch/arm/src/imx/imx_timerisr.c index 896dc86e5..b5ce77b39 100644 --- a/nuttx/arch/arm/src/imx/imx_timerisr.c +++ b/nuttx/arch/arm/src/imx/imx_timerisr.c @@ -135,7 +135,7 @@ void up_timerinit(void) /* The timer is driven by PERCLK1. Set prescaler for division by one * so that the clock is driven at PERCLK1. * - * putreg(0, IMX_TIMER1_TPRER); -- already the case + * putreg(0, IMX_TIMER1_TPRER); -- already the case * * Set the compare register so that the COMP interrupt is generated * with a period of MSEC_PER_TICK. The value IMX_PERCLK1_FREQ/1000 diff --git a/nuttx/arch/arm/src/imx/imx_uart.h b/nuttx/arch/arm/src/imx/imx_uart.h index 5646e83f7..17b0d7261 100644 --- a/nuttx/arch/arm/src/imx/imx_uart.h +++ b/nuttx/arch/arm/src/imx/imx_uart.h @@ -39,7 +39,7 @@ /************************************************************************************ * Included Files ************************************************************************************/ - + /************************************************************************************ * Definitions ************************************************************************************/ diff --git a/nuttx/arch/arm/src/imx/imx_usbd.h b/nuttx/arch/arm/src/imx/imx_usbd.h index 8c810cacf..eb0e2b7a3 100644 --- a/nuttx/arch/arm/src/imx/imx_usbd.h +++ b/nuttx/arch/arm/src/imx/imx_usbd.h @@ -39,7 +39,7 @@ /************************************************************************************ * Included Files ************************************************************************************/ - + /************************************************************************************ * Definitions ************************************************************************************/ diff --git a/nuttx/arch/arm/src/imx/imx_wdog.h b/nuttx/arch/arm/src/imx/imx_wdog.h index 4ee6438b3..2976ea4ef 100644 --- a/nuttx/arch/arm/src/imx/imx_wdog.h +++ b/nuttx/arch/arm/src/imx/imx_wdog.h @@ -39,7 +39,7 @@ /************************************************************************************ * Included Files ************************************************************************************/ - + /************************************************************************************ * Definitions ************************************************************************************/ diff --git a/nuttx/arch/arm/src/kinetis/kinetis_clockconfig.c b/nuttx/arch/arm/src/kinetis/kinetis_clockconfig.c index ad6e42884..c4012d8bc 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_clockconfig.c +++ b/nuttx/arch/arm/src/kinetis/kinetis_clockconfig.c @@ -62,7 +62,7 @@ /**************************************************************************** * Private Function Prototypes ****************************************************************************/ - + void __ramfunc__ kinesis_setdividers(uint32_t div1, uint32_t div2, uint32_t div3, uint32_t div4); @@ -205,8 +205,8 @@ void kinetis_pllconfig(void) * Flash clock = MCG / BOARD_OUTDIV4 */ - kinesis_setdividers(BOARD_OUTDIV1, BOARD_OUTDIV2, BOARD_OUTDIV3, BOARD_OUTDIV4); - + kinesis_setdividers(BOARD_OUTDIV1, BOARD_OUTDIV2, BOARD_OUTDIV3, BOARD_OUTDIV4); + /* Set the VCO divider, VDIV, is defined in the board.h file. VDIV * selects the amount to divide the VCO output of the PLL. The VDIV bits * establish the multiplication factor applied to the reference clock @@ -352,7 +352,7 @@ kinesis_setdividers(uint32_t div1, uint32_t div2, uint32_t div3, uint32_t div4) /* Save the current value of the Flash Access Protection Register */ regval = getreg32(KINETIS_FMC_PFAPR); - + /* Set M0PFD through M7PFD to 1 to disable prefetch */ putreg32(FMC_PFAPR_M7PFD | FMC_PFAPR_M6PFD | FMC_PFAPR_M5PFD | @@ -369,7 +369,7 @@ kinesis_setdividers(uint32_t div1, uint32_t div2, uint32_t div3, uint32_t div4) /* Wait for dividers to change */ for (i = 0 ; i < div4 ; i++); - + /* Re-store the saved value of FMC_PFAPR */ putreg32(regval, KINETIS_FMC_PFAPR); diff --git a/nuttx/arch/arm/src/kinetis/kinetis_clrpend.c b/nuttx/arch/arm/src/kinetis/kinetis_clrpend.c index 2837d867f..97ae5a610 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_clrpend.c +++ b/nuttx/arch/arm/src/kinetis/kinetis_clrpend.c @@ -71,7 +71,7 @@ * * Description: * Clear a pending interrupt at the NVIC. This does not seem to be required - * for most interrupts. Don't know why... + * for most interrupts. Don't know why... * * I keep it in a separate file so that it will not increase the footprint * on Kinetis platforms that do not need this function. diff --git a/nuttx/arch/arm/src/kinetis/kinetis_enet.h b/nuttx/arch/arm/src/kinetis/kinetis_enet.h index 0a5e78ea9..1843afcd0 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_enet.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_enet.h @@ -295,7 +295,7 @@ /* Receive Descriptor Ring Start Register */ /* Bits 0-2: Reserved */ #define ENET_RDSR_SHIFT (3) /* Bits 3-31: Start of the receive buffer descriptor queue */ -#define ENET_RDSR_MASK (0xfffffff8) +#define ENET_RDSR_MASK (0xfffffff8) /* Transmit Buffer Descriptor Ring Start Register */ /* Bits 0-2: Reserved */ @@ -476,9 +476,9 @@ #ifdef CONFIG_ENDIAN_BIG # define TXDESC_TSE (1 << 8) -# define TXDESC_OE (1 << 9) -# define TXDESC_LCE (1 << 10) -# define TXDESC_FE (1 << 11) +# define TXDESC_OE (1 << 9) +# define TXDESC_LCE (1 << 10) +# define TXDESC_FE (1 << 11) # define TXDESC_EE (1 << 12) # define TXDESC_UE (1 << 13) # define TXDESC_TXE (1 << 15) @@ -495,15 +495,15 @@ # define TXDESC_TS (1 << 5) # define TXDESC_INT (1 << 6) -# define TXDESC_TSE (1 << 16) -# define TXDESC_OE (1 << 17) -# define TXDESC_LCE (1 << 18) -# define TXDESC_FE (1 << 19) +# define TXDESC_TSE (1 << 16) +# define TXDESC_OE (1 << 17) +# define TXDESC_LCE (1 << 18) +# define TXDESC_FE (1 << 19) # define TXDESC_EE (1 << 20) # define TXDESC_UE (1 << 21) # define TXDESC_TXE (1 << 23) -# define TXDESC_BDU (1 << 7) +# define TXDESC_BDU (1 << 7) #endif /* Legacy (and Common) RX Buffer Descriptor Bit Definitions */ @@ -552,7 +552,7 @@ # define RXDESC_PE (1 << 26) # define RXDESC_ME (1 << 31) -# define RXDESC_BDU (1 << 31) +# define RXDESC_BDU (1 << 31) #else # define RXDESC_UC (1 << 0) # define RXDESC_CE (1 << 1) diff --git a/nuttx/arch/arm/src/kinetis/kinetis_k60pinmux.h b/nuttx/arch/arm/src/kinetis/kinetis_k60pinmux.h index 2c77dd4ba..199a02a0d 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_k60pinmux.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_k60pinmux.h @@ -47,7 +47,7 @@ /******************************************************************************************** * Pre-processor Definitions ********************************************************************************************/ -/* Reference: Paragraph 10.3.1, p 258, of FreeScale document K60P144M100SF2RM +/* Reference: Paragraph 10.3.1, p 258, of FreeScale document K60P144M100SF2RM * * In most cases, there are alternative configurations for various pins. Those alternative * pins are labeled with a suffix like _1, _2, etc. in order to distinguish them. Logic in diff --git a/nuttx/arch/arm/src/kinetis/kinetis_lowputc.c b/nuttx/arch/arm/src/kinetis/kinetis_lowputc.c index f52d3ba35..c3599618c 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_lowputc.c +++ b/nuttx/arch/arm/src/kinetis/kinetis_lowputc.c @@ -56,7 +56,7 @@ /************************************************************************** * Private Definitions **************************************************************************/ - + /* Select UART parameters for the selected console */ #if defined(CONFIG_UART0_SERIAL_CONSOLE) @@ -126,7 +126,7 @@ static uint8_t g_sizemap[8] = {1, 4, 8, 16, 32, 64, 128, 0}; /************************************************************************** * Private Functions **************************************************************************/ - + /************************************************************************** * Public Functions **************************************************************************/ @@ -347,7 +347,7 @@ void kinetis_uartconfigure(uintptr_t uart_base, uint32_t baud, { regval |= UART_C1_M; } - + /* The only other option is 8-bit operation */ else @@ -361,7 +361,7 @@ void kinetis_uartconfigure(uintptr_t uart_base, uint32_t baud, sbr = clock / (baud << 4); DEBUGASSERT(sbr < 0x2000); - + /* Save the new baud divisor, retaining other bits in the UARTx_BDH * register. */ @@ -373,7 +373,7 @@ void kinetis_uartconfigure(uintptr_t uart_base, uint32_t baud, regval = sbr & 0xff; putreg8(regval, uart_base+KINETIS_UART_BDL_OFFSET); - + /* Calculate a fractional divider to get closer to the requested baud. * The fractional divider, BRFA, is a 5 bit fractional value that is * logically added to the SBR: @@ -386,7 +386,7 @@ void kinetis_uartconfigure(uintptr_t uart_base, uint32_t baud, tmp = clock - (sbr * (baud << 4)); brfa = (tmp << 5) / (baud << 4); - + /* Set the BRFA field (retaining other bits in the UARTx_C4 register) */ regval = getreg8(uart_base+KINETIS_UART_C4_OFFSET) & UART_C4_BRFA_MASK; @@ -412,14 +412,14 @@ void kinetis_uartconfigure(uintptr_t uart_base, uint32_t baud, depth = (3 * depth) >> 2; } putreg8(depth , uart_base+KINETIS_UART_RWFIFO_OFFSET); - + depth = g_sizemap[(regval & UART_PFIFO_TXFIFOSIZE_MASK) >> UART_PFIFO_TXFIFOSIZE_SHIFT]; if (depth > 3) { depth = (depth >> 2); } putreg8(depth, uart_base+KINETIS_UART_TWFIFO_OFFSET); - + /* Enable RX and TX FIFOs */ putreg8(UART_PFIFO_RXFE | UART_PFIFO_TXFE, uart_base+KINETIS_UART_PFIFO_OFFSET); @@ -431,8 +431,8 @@ void kinetis_uartconfigure(uintptr_t uart_base, uint32_t baud, * (1 in this case) is less than or equal to 0. * RWFIFO[RXWATER] = 1: RDRF will be set when the number of queued bytes * (1 in this case) is greater than or equal to 1. - * - * Set the watermarks to one/zero and disable the FIFOs + * + * Set the watermarks to one/zero and disable the FIFOs */ putreg8(1, uart_base+KINETIS_UART_RWFIFO_OFFSET); diff --git a/nuttx/arch/arm/src/kinetis/kinetis_memorymap.h b/nuttx/arch/arm/src/kinetis/kinetis_memorymap.h index 7253717bd..ef1d22265 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_memorymap.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_memorymap.h @@ -185,7 +185,7 @@ # define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */ # define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */ -/* K60 Family +/* K60 Family * * The memory map for the following parts is defined in Freescale document * K60P144M100SF2RM diff --git a/nuttx/arch/arm/src/kinetis/kinetis_serial.c b/nuttx/arch/arm/src/kinetis/kinetis_serial.c index fc74f22ba..4cf414fd6 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_serial.c +++ b/nuttx/arch/arm/src/kinetis/kinetis_serial.c @@ -707,7 +707,7 @@ static int up_attach(struct uart_dev_s *dev) static void up_detach(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - + /* Disable interrupts */ up_restoreuartint(priv, 0); diff --git a/nuttx/arch/arm/src/kinetis/kinetis_timerisr.c b/nuttx/arch/arm/src/kinetis/kinetis_timerisr.c index 9f9f14ba6..8dd514a9c 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_timerisr.c +++ b/nuttx/arch/arm/src/kinetis/kinetis_timerisr.c @@ -126,7 +126,7 @@ void up_timerinit(void) regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT); putreg32(regval, NVIC_SYSH12_15_PRIORITY); - /* Note that is should not be neccesary to set the SYSTICK clock source: + /* Note that is should not be neccesary to set the SYSTICK clock source: * "The CLKSOURCE bit in SysTick Control and Status register is always set * to select the core clock." */ diff --git a/nuttx/arch/arm/src/kinetis/kinetis_userspace.c b/nuttx/arch/arm/src/kinetis/kinetis_userspace.c index 75b3c08fd..d0d57145d 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_userspace.c +++ b/nuttx/arch/arm/src/kinetis/kinetis_userspace.c @@ -98,7 +98,7 @@ void kinetis_userspace(void) /* Initialize all of user-space .data */ DEBUGASSERT(USERSPACE->us_datasource != 0 && - USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && + USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && USERSPACE->us_datastart <= USERSPACE->us_dataend); src = (uint8_t*)USERSPACE->us_datasource; diff --git a/nuttx/arch/arm/src/kl/chip/kl_tpm.h b/nuttx/arch/arm/src/kl/chip/kl_tpm.h index d9c8a9b70..7d185934b 100644 --- a/nuttx/arch/arm/src/kl/chip/kl_tpm.h +++ b/nuttx/arch/arm/src/kl/chip/kl_tpm.h @@ -176,7 +176,7 @@ #define TPM_CONF_CSOT (1 << 16) /* Bit 16: Counter Start On Trigger */ #define TPM_CONF_CSOO (1 << 17) /* Bit 17: Counter Stop On Overflow */ #define TPM_CONF_CROT (1 << 18) /* Bit 18: Counter Reload On Trigger */ - /* Bits 19-23: Reserved */ + /* Bits 19-23: Reserved */ #define TPM_CONF_TRGSEL_SHIFT 24 #define TPM_CONF_TRGSEL_MASK (15 << TPM_CONF_TRGSEL_SHIFT) # define TPM_CONF_TRGSEL_EXTRG_IN (0 << TPM_CONF_TRGSEL_SHIFT) /* External trigger pin input */ diff --git a/nuttx/arch/arm/src/kl/kl_config.h b/nuttx/arch/arm/src/kl/kl_config.h index 1a6d1f1e2..fd7cc592c 100644 --- a/nuttx/arch/arm/src/kl/kl_config.h +++ b/nuttx/arch/arm/src/kl/kl_config.h @@ -64,7 +64,7 @@ /* Are any UARTs enabled? */ #undef HAVE_UART_DEVICE -#if defined(CONFIG_KL_UART0) || defined(CONFIG_KL_UART1) || defined(CONFIG_KL_UART2) +#if defined(CONFIG_KL_UART0) || defined(CONFIG_KL_UART1) || defined(CONFIG_KL_UART2) # define HAVE_UART_DEVICE 1 #endif diff --git a/nuttx/arch/arm/src/kl/kl_gpio.c b/nuttx/arch/arm/src/kl/kl_gpio.c index 58de0eea1..78fba619a 100644 --- a/nuttx/arch/arm/src/kl/kl_gpio.c +++ b/nuttx/arch/arm/src/kl/kl_gpio.c @@ -145,7 +145,7 @@ int kl_configgpio(uint32_t cfgset) { regval |= PORT_PCR_ODE; } - + /* Check for high drive output */ if ((cfgset & _PIN_OUTPUT_DRIVE_MASK) == _PIN_OUTPUT_HIGHDRIVE) diff --git a/nuttx/arch/arm/src/kl/kl_gpio.h b/nuttx/arch/arm/src/kl/kl_gpio.h index e1db46d9a..d2d181b13 100644 --- a/nuttx/arch/arm/src/kl/kl_gpio.h +++ b/nuttx/arch/arm/src/kl/kl_gpio.h @@ -241,7 +241,7 @@ #define PIN_PASV_FILTER (1 << 18) /* Bit 18: Enable passive filter */ #define PIN_DIG_FILTER (1 << 17) /* Bit 17: Enable digital filter */ - + /* Three bits are used to define the port number: * * ---- ---- ---- ---- ---- -ppp ---- ---- diff --git a/nuttx/arch/arm/src/kl/kl_idle.c b/nuttx/arch/arm/src/kl/kl_idle.c index 6ec2ab46f..688a002bd 100644 --- a/nuttx/arch/arm/src/kl/kl_idle.c +++ b/nuttx/arch/arm/src/kl/kl_idle.c @@ -87,7 +87,7 @@ static void up_idlepm(void) enum pm_state_e newstate; irqstate_t flags; int ret; - + /* Decide, which power saving level can be obtained */ newstate = pm_checkstate(); diff --git a/nuttx/arch/arm/src/kl/kl_userspace.c b/nuttx/arch/arm/src/kl/kl_userspace.c index 00d0f5338..8949a90d2 100644 --- a/nuttx/arch/arm/src/kl/kl_userspace.c +++ b/nuttx/arch/arm/src/kl/kl_userspace.c @@ -97,7 +97,7 @@ void kl_userspace(void) /* Initialize all of user-space .data */ DEBUGASSERT(USERSPACE->us_datasource != 0 && - USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && + USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && USERSPACE->us_datastart <= USERSPACE->us_dataend); src = (uint8_t*)USERSPACE->us_datasource; diff --git a/nuttx/arch/arm/src/lpc17xx/Kconfig b/nuttx/arch/arm/src/lpc17xx/Kconfig index 20b4b37e6..d1e76062d 100644 --- a/nuttx/arch/arm/src/lpc17xx/Kconfig +++ b/nuttx/arch/arm/src/lpc17xx/Kconfig @@ -493,7 +493,7 @@ config ADC_CHANLIST config ADC_NCHANNELS int "ADC0 number of channels" depends on ADC_CHANLIST - default 0 + default 0 ---help--- If ADC_CHANLIST is enabled, then the platform specific code must do two things: (1) define ADC_NCHANNELS in the configuration @@ -606,7 +606,7 @@ config SDIO_DMA default y if LPC17_GPDMA depends on LPC17_GPDMA ---help--- - Support DMA data transfers. + Support DMA data transfers. Enable SD card DMA data transfers. This is a marginally optional. For most usages, SD accesses will cause data overruns if used without DMA. Requires LPC17_SDCARD and config LPC17_GPDMA. diff --git a/nuttx/arch/arm/src/lpc17xx/Make.defs b/nuttx/arch/arm/src/lpc17xx/Make.defs index be695a777..a7fa299df 100644 --- a/nuttx/arch/arm/src/lpc17xx/Make.defs +++ b/nuttx/arch/arm/src/lpc17xx/Make.defs @@ -36,7 +36,7 @@ # The start-up, "head", file ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y) -HEAD_ASRC = +HEAD_ASRC = else HEAD_ASRC = lpc17_vectors.S endif diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc176x_syscon.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc176x_syscon.h index fcf0fa3d4..bc3ae3c92 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip/lpc176x_syscon.h +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc176x_syscon.h @@ -60,12 +60,12 @@ /* Clocking and power control - Phase locked loops */ -#define LPC17_SYSCON_PLL0CON_OFFSET 0x0080 /* PLL0 Control Register */ +#define LPC17_SYSCON_PLL0CON_OFFSET 0x0080 /* PLL0 Control Register */ #define LPC17_SYSCON_PLL0CFG_OFFSET 0x0084 /* PLL0 Configuration Register */ #define LPC17_SYSCON_PLL0STAT_OFFSET 0x0088 /* PLL0 Status Register */ #define LPC17_SYSCON_PLL0FEED_OFFSET 0x008c /* PLL0 Feed Register */ -#define LPC17_SYSCON_PLL1CON_OFFSET 0x00a0 /* PLL1 Control Register */ +#define LPC17_SYSCON_PLL1CON_OFFSET 0x00a0 /* PLL1 Control Register */ #define LPC17_SYSCON_PLL1CFG_OFFSET 0x00a4 /* PLL1 Configuration Register */ #define LPC17_SYSCON_PLL1STAT_OFFSET 0x00a8 /* PLL1 Status Register */ #define LPC17_SYSCON_PLL1FEED_OFFSET 0x00ac /* PLL1 Feed Register */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_can.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_can.h index 84b019d61..74a210944 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_can.h +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_can.h @@ -377,7 +377,7 @@ /* Error Warning Limit */ -#define CAN_EWL_SHIFT (0) /* Bits 0-7: Error warning limit */ +#define CAN_EWL_SHIFT (0) /* Bits 0-7: Error warning limit */ #define CAN_EWL_MASK (0xff << CAN_EWL_SHIFT) /* Bits 8-31: Reserved */ /* Status Register */ @@ -482,7 +482,7 @@ #define CAN_TDA_DATA4_SHIFT (24) /* Bits 24-31: RTR=0 && DLC >= 4 */ #define CAN_TDA_DATA4_MASK (0x0ff << CAN_TDA_DATA4_SHIFT) -/* Transmit data bytes 5-8 (Tx Buffer 1), Transmit data bytes 5-8 (Tx Buffer 2), and +/* Transmit data bytes 5-8 (Tx Buffer 1), Transmit data bytes 5-8 (Tx Buffer 2), and * Transmit data bytes 5-8 (Tx Buffer 3) common bit field definitions. */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_lcd.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_lcd.h index d7b919cb6..ef334a1a6 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_lcd.h +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_lcd.h @@ -71,7 +71,7 @@ /* Cursor Image registers, n=0-255 */ -#define LPC17_LCD_CRSR_IMG_OFFSET(n) (0x0800 + ((n) << 2)) +#define LPC17_LCD_CRSR_IMG_OFFSET(n) (0x0800 + ((n) << 2)) #define LPC17_LCD_CRSR_CRTL_OFFSET (0x0c00) /* Cursor Control register */ #define LPC17_LCD_CRSR_CFG_OFFSET (0x0c04) /* Cursor Configuration register */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_mcpwm.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_mcpwm.h index 10abbd232..16a21a162 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_mcpwm.h +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_mcpwm.h @@ -263,7 +263,7 @@ #define MCPWM_CAPCLR_MCCLR0 (1 << 0) /* Bit 0: Clear MCCAP0 register */ #define MCPWM_CAPCLR_MCCLR1 (1 << 1) /* Bit 1: Clear MCCAP1 register */ #define MCPWM_CAPCLR_MCCLR2 (1 << 2) /* Bit 2: Clear MCCAP2 register */ - /* Bits 2-31: Reserved */ + /* Bits 2-31: Reserved */ /************************************************************************************ * Public Types diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_usb.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_usb.h index d1e6dd013..32b02455c 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_usb.h +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_usb.h @@ -49,7 +49,7 @@ /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ - + /* Register offsets *****************************************************************/ /* USB Host Controller (OHCI) *******************************************************/ /* See include/nuttx/usb/ohci.h */ @@ -326,7 +326,7 @@ /* USB Device Interrupt Status, USB Device Interrupt Enable, USB Device Interrupt * Clear, USB Device Interrupt Set, and USB Device Interrupt Priority */ - + #define USBDEV_INT_FRAME (1 << 0) /* Bit 0: frame interrupt (every 1 ms) */ #define USBDEV_INT_EPFAST (1 << 1) /* Bit 1: Fast endpoint interrupt */ #define USBDEV_INT_EPSLOW (1 << 2) /* Bit 2: Slow endpoints interrupt */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_adc.h b/nuttx/arch/arm/src/lpc17xx/lpc17_adc.h index a1bd9fe4d..d7736b979 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_adc.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_adc.h @@ -53,7 +53,7 @@ * the ADC0_MASK within the board-specific library. */ -#ifdef CONFIG_ADC_CHANLIST +#ifdef CONFIG_ADC_CHANLIST # if !defined(CONFIG_ADC_NCHANNELS) # error "CONFIG_ADC_CHANLIST must defined in this configuration" # elif CONFIG_ADC_NCHANNELS < 1 @@ -92,7 +92,7 @@ extern "C" * the ADC0_MASK within the board-specific library. */ -#ifdef CONFIG_ADC_CHANLIST +#ifdef CONFIG_ADC_CHANLIST EXTERN uint8_t g_adc_chanlist[CONFIG_ADC_NCHANNELS]; #endif diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_dac.c b/nuttx/arch/arm/src/lpc17xx/lpc17_dac.c index 4f3e5a512..87cc6a717 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_dac.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_dac.c @@ -4,7 +4,7 @@ * Copyright (C) 2011 Li Zhuoyi. All rights reserved. * Author: Li Zhuoyi <lzyy.cn@gmail.com> * History: 0.1 2011-08-05 initial version - * + * * This file is a part of NuttX: * * Copyright (C) 2010 Gregory Nutt. All rights reserved. @@ -117,7 +117,7 @@ static void dac_reset(FAR struct dac_dev_s *dev) { irqstate_t flags; uint32_t regval; - + flags = irqsave(); regval = getreg32(LPC17_SYSCON_PCLKSEL0); diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_gpiodbg.c b/nuttx/arch/arm/src/lpc17xx/lpc17_gpiodbg.c index d5ff51f61..7876da0ac 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_gpiodbg.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_gpiodbg.c @@ -163,7 +163,7 @@ int lpc17_dumpgpio(lpc17_pinset_t pinset, const char *msg) #if defined(LPC176x) lldbg(" PINSEL[%08x]: %08x PINMODE[%08x]: %08x ODMODE[%08x]: %08x\n", pinsel, pinsel ? getreg32(pinsel) : 0, - pinmode, pinmode ? getreg32(pinmode) : 0, + pinmode, pinmode ? getreg32(pinmode) : 0, g_odmode[port], getreg32(g_odmode[port])); #elif defined(LPC178x) lldbg(" IOCON[%08x]: %08x\n", iocon, getreg32(iocon)); diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_gpioint.c b/nuttx/arch/arm/src/lpc17xx/lpc17_gpioint.c index 1d6b4b1d6..7cb51ed07 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_gpioint.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_gpioint.c @@ -396,7 +396,7 @@ static void lpc17_gpiodemux(uint32_t intbase, uint32_t intmask, * * Description: * Handle the GPIO interrupt. For the LPC176x family, that interrupt could - * also that also indicates that an EINT3 interrupt has occurred. NOTE: + * also that also indicates that an EINT3 interrupt has occurred. NOTE: * This logic would have to be extended if EINT3 is actually used for * External Interrupt 3 on an LPC176x platform. * diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_ohciram.h b/nuttx/arch/arm/src/lpc17xx/lpc17_ohciram.h index c508ddf6a..5e039dad7 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_ohciram.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_ohciram.h @@ -141,11 +141,11 @@ #define LPC17_TD_SIZE 32 /* Configurable number of user transfer descriptors (TDs). */ - + #ifndef CONFIG_USBHOST_NTDS # define CONFIG_USBHOST_NTDS 3 #endif - + #if CONFIG_USBHOST_NTDS < 2 # error "Insufficent TDs" #endif diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_sdcard.h b/nuttx/arch/arm/src/lpc17xx/lpc17_sdcard.h index 66eb68b9b..12c2fba9d 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_sdcard.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_sdcard.h @@ -88,7 +88,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno); * * Input Parameters: * dev - An instance of the SDIO driver device state structure. - * cardinslot - true is a card has been detected in the slot; false if a + * cardinslot - true is a card has been detected in the slot; false if a * card has been removed from the slot. Only transitions * (inserted->removed or removed->inserted should be reported) * diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_serial.c b/nuttx/arch/arm/src/lpc17xx/lpc17_serial.c index 57a775a6a..7c0f0e04a 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_serial.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_serial.c @@ -611,7 +611,7 @@ static inline uint32_t lpc17_uartcclkdiv(uint32_t baud) { return SYSCON_PCLKSEL_CCLK; } - + /* Check divisor == 2. This works if: * * 2 * CCLK / BAUD / 16 < 0xffff, or @@ -636,7 +636,7 @@ static inline uint32_t lpc17_uartcclkdiv(uint32_t baud) * And * * 4 * CCLK / BAUD / 16 >= MinDL, or - * BAUD <= CCLK / 4 / MinDL + * BAUD <= CCLK / 4 / MinDL */ else if (baud < (LPC17_CCLK / 4 / UART_MINDL )) @@ -652,7 +652,7 @@ static inline uint32_t lpc17_uartcclkdiv(uint32_t baud) * And * * 8 * CCLK / BAUD / 16 >= MinDL, or - * BAUD <= CCLK / 2 / MinDL + * BAUD <= CCLK / 2 / MinDL */ else /* if (baud < (LPC17_CCLK / 2 / UART_MINDL )) */ @@ -942,7 +942,7 @@ static int up_setup(struct uart_dev_s *dev) (UART_FCR_RXTRIGGER_8|UART_FCR_TXRST|UART_FCR_RXRST|UART_FCR_FIFOEN)); /* Enable Auto-RTS and Auto-CS Flow Control in the Modem Control Register */ - + #if defined(CONFIG_UART1_IFLOWCONTROL) || defined(CONFIG_UART1_OFLOWCONTROL) if (priv->uartbase == LPC17_UART1_BASE) { diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c b/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c index 08599e68e..aae65f651 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c @@ -73,7 +73,7 @@ /* Debug ********************************************************************/ /* The following enable debug output from this file: - * + * * CONFIG_DEBUG - Define to enable general debug features * CONFIG_DEBUG_SPI - Define to enable basic SSP debug (needs CONFIG_DEBUG) * CONFIG_DEBUG_VERBOSE - Define to enable verbose SSP debug @@ -212,7 +212,7 @@ static struct lpc17_sspdev_s g_ssp0dev = #ifdef CONFIG_LPC17_SSP_INTERRUPTS .sspirq = LPC17_IRQ_SSP0, #endif -}; +}; #endif /* CONFIG_LPC17_SSP0 */ #ifdef CONFIG_LPC17_SSP1 @@ -246,7 +246,7 @@ static struct lpc17_sspdev_s g_ssp1dev = #ifdef CONFIG_LPC17_SSP_INTERRUPTS .sspirq = LPC17_IRQ_SSP1, #endif -}; +}; #endif /* CONFIG_LPC17_SSP1 */ #ifdef CONFIG_LPC17_SSP2 @@ -280,7 +280,7 @@ static struct lpc17_sspdev_s g_ssp2dev = #ifdef CONFIG_LPC17_SSP_INTERRUPTS .sspirq = LPC17_IRQ_SSP2, #endif -}; +}; #endif /* CONFIG_LPC17_SSP2 */ /**************************************************************************** @@ -462,7 +462,7 @@ static uint32_t ssp_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) cpsdvsr = (cpsdvsr + 1) & ~1; /* Save the new CPSDVSR and SCR values */ - + ssp_putreg(priv, LPC17_SSP_CPSR_OFFSET, cpsdvsr); regval = ssp_getreg(priv, LPC17_SSP_CR0_OFFSET); @@ -520,19 +520,19 @@ static void ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) { case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */ break; - + case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */ regval |= SSP_CR0_CPHA; break; - + case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */ regval |= SSP_CR0_CPOL; break; - + case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ regval |= (SSP_CR0_CPOL|SSP_CR0_CPHA); break; - + default: sspdbg("Bad mode: %d\n", mode); DEBUGASSERT(FALSE); diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_start.c b/nuttx/arch/arm/src/lpc17xx/lpc17_start.c index 7f8756f4c..80f136f11 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_start.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_start.c @@ -122,7 +122,7 @@ static inline void lpc17_fpuconfig(void) * with the volatile FP registers stacked above the basic context. */ - regval = getcontrol(); + regval = getcontrol(); regval |= (1 << 2); setcontrol(regval); @@ -152,7 +152,7 @@ static inline void lpc17_fpuconfig(void) * with the volatile FP registers stacked in the saved context. */ - regval = getcontrol(); + regval = getcontrol(); regval &= ~(1 << 2); setcontrol(regval); diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_usbdev.c b/nuttx/arch/arm/src/lpc17xx/lpc17_usbdev.c index 938d0c8a7..7dbb2170b 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_usbdev.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_usbdev.c @@ -1490,7 +1490,7 @@ static void lpc17_usbreset(struct lpc17_usbdev_s *priv) lpc17_putreg(USB_SLOW_INT|USB_DEVSTATUS_INT|USB_FAST_INT|USB_FRAME_INT|USB_ERROR_INT, LPC17_USBDEV_INTEN); - /* Tell the class driver that we are disconnected. The class + /* Tell the class driver that we are disconnected. The class * driver should then accept any new configurations. */ @@ -3130,7 +3130,7 @@ static int lpc17_wakeup(struct usbdev_s *dev) * Name: lpc17_selfpowered * * Description: - * Sets/clears the device selfpowered feature + * Sets/clears the device selfpowered feature * *******************************************************************************/ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_usbhost.c b/nuttx/arch/arm/src/lpc17xx/lpc17_usbhost.c index 1e1681ee5..c9e1a3a7a 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_usbhost.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_usbhost.c @@ -271,13 +271,13 @@ static void lpc17_setinttab(uint32_t value, unsigned int interval, unsigned int #endif static inline int lpc17_addinted(struct lpc17_usbhost_s *priv, - FAR const struct usbhost_epdesc_s *epdesc, + FAR const struct usbhost_epdesc_s *epdesc, struct lpc17_ed_s *ed); static inline int lpc17_reminted(struct lpc17_usbhost_s *priv, struct lpc17_ed_s *ed); static inline int lpc17_addisoced(struct lpc17_usbhost_s *priv, - FAR const struct usbhost_epdesc_s *epdesc, + FAR const struct usbhost_epdesc_s *epdesc, struct lpc17_ed_s *ed); static inline int lpc17_remisoced(struct lpc17_usbhost_s *priv, struct lpc17_ed_s *ed); @@ -724,7 +724,7 @@ static void lpc17_freeio(uint8_t *buffer) * Helper function to add an ED to the bulk list. * *******************************************************************************/ - + static inline int lpc17_addbulked(struct lpc17_usbhost_s *priv, struct lpc17_ed_s *ed) { @@ -757,7 +757,7 @@ static inline int lpc17_addbulked(struct lpc17_usbhost_s *priv, * Helper function remove an ED from the bulk list. * *******************************************************************************/ - + static inline int lpc17_rembulked(struct lpc17_usbhost_s *priv, struct lpc17_ed_s *ed) { @@ -891,9 +891,9 @@ static void lpc17_setinttab(uint32_t value, unsigned int interval, unsigned int * 2. Some devices may get polled at a much higher rate than they request. * *******************************************************************************/ - + static inline int lpc17_addinted(struct lpc17_usbhost_s *priv, - FAR const struct usbhost_epdesc_s *epdesc, + FAR const struct usbhost_epdesc_s *epdesc, struct lpc17_ed_s *ed) { #ifndef CONFIG_USBHOST_INT_DISABLE @@ -1000,7 +1000,7 @@ static inline int lpc17_addinted(struct lpc17_usbhost_s *priv, * 2. Some devices may get polled at a much higher rate than they request. * *******************************************************************************/ - + static inline int lpc17_reminted(struct lpc17_usbhost_s *priv, struct lpc17_ed_s *ed) { @@ -1088,7 +1088,7 @@ static inline int lpc17_reminted(struct lpc17_usbhost_s *priv, uvdbg("min interval: %d offset: %d\n", interval, offset); /* Save the new minimum interval */ - + if ((ed->hw.ctrl && ED_CONTROL_D_MASK) == ED_CONTROL_D_IN) { priv->ininterval = interval; @@ -1127,9 +1127,9 @@ static inline int lpc17_reminted(struct lpc17_usbhost_s *priv, * Helper functions to add an ED to the periodic table. * *******************************************************************************/ - + static inline int lpc17_addisoced(struct lpc17_usbhost_s *priv, - FAR const struct usbhost_epdesc_s *epdesc, + FAR const struct usbhost_epdesc_s *epdesc, struct lpc17_ed_s *ed) { #ifndef CONFIG_USBHOST_ISOC_DISABLE @@ -1146,7 +1146,7 @@ static inline int lpc17_addisoced(struct lpc17_usbhost_s *priv, * Helper functions to remove an ED from the periodic table. * *******************************************************************************/ - + static inline int lpc17_remisoced(struct lpc17_usbhost_s *priv, struct lpc17_ed_s *ed) { @@ -1302,7 +1302,7 @@ static int lpc17_ctrltd(struct lpc17_usbhost_s *priv, uint32_t dirpid, { ret = OK; } - else + else { uvdbg("Bad TD completion status: %d\n", EDCTRL->tdstatus); ret = EDCTRL->tdstatus == TD_CC_STALL ? -EPERM : -EIO; @@ -1397,7 +1397,7 @@ static int lpc17_usbinterrupt(int irq, FAR void *context) } /* Check if we are now disconnected */ - + else if (priv->connected) { /* Yes.. disconnect the device */ @@ -1446,7 +1446,7 @@ static int lpc17_usbinterrupt(int irq, FAR void *context) } /* Writeback Done Head interrupt */ - + if ((pending & OHCI_INT_WDH) != 0) { struct lpc17_gtd_s *td; @@ -1617,7 +1617,7 @@ static int lpc17_enumerate(FAR struct usbhost_connection_s *conn, int rphndx) udbg("Not connected\n"); return -ENODEV; } - + /* USB 2.0 spec says at least 50ms delay before port reset */ (void)usleep(100*1000); @@ -1681,7 +1681,7 @@ static int lpc17_ep0configure(FAR struct usbhost_driver_s *drvr, uint8_t funcadd /* Set the EP0 ED control word */ - EDCTRL->hw.ctrl = (uint32_t)funcaddr << ED_CONTROL_FA_SHIFT | + EDCTRL->hw.ctrl = (uint32_t)funcaddr << ED_CONTROL_FA_SHIFT | (uint32_t)maxpacketsize << ED_CONTROL_MPS_SHIFT; if (priv->lowspeed) @@ -1780,9 +1780,9 @@ static int lpc17_epalloc(FAR struct usbhost_driver_s *drvr, g_edfree = ((struct lpc17_list_s*)ed)->flink; /* Configure the endpoint descriptor. */ - + memset((void*)ed, 0, sizeof(struct lpc17_ed_s)); - ed->hw.ctrl = (uint32_t)(epdesc->funcaddr) << ED_CONTROL_FA_SHIFT | + ed->hw.ctrl = (uint32_t)(epdesc->funcaddr) << ED_CONTROL_FA_SHIFT | (uint32_t)(epdesc->addr) << ED_CONTROL_EN_SHIFT | (uint32_t)(epdesc->mxpacketsize) << ED_CONTROL_MPS_SHIFT; @@ -2259,7 +2259,7 @@ static int lpc17_ctrlout(FAR struct usbhost_driver_s *drvr, * - Never called from an interrupt handler. * *******************************************************************************/ - + static int lpc17_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep, FAR uint8_t *buffer, size_t buflen) { @@ -2277,10 +2277,10 @@ static int lpc17_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep, in = (ed->hw.ctrl & ED_CONTROL_D_MASK) == ED_CONTROL_D_IN; uvdbg("EP%d %s toggle:%d maxpacket:%d buflen:%d\n", - (ed->hw.ctrl & ED_CONTROL_EN_MASK) >> ED_CONTROL_EN_SHIFT, + (ed->hw.ctrl & ED_CONTROL_EN_MASK) >> ED_CONTROL_EN_SHIFT, in ? "IN" : "OUT", (ed->hw.headp & ED_HEADP_C) != 0 ? 1 : 0, - (ed->hw.ctrl & ED_CONTROL_MPS_MASK) >> ED_CONTROL_MPS_SHIFT, + (ed->hw.ctrl & ED_CONTROL_MPS_MASK) >> ED_CONTROL_MPS_SHIFT, buflen); /* We must have exclusive access to the endpoint, the TD pool, the I/O buffer @@ -2360,7 +2360,7 @@ static int lpc17_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep, /* BulkListFilled. This bit is used to indicate whether there are any * TDs on the Bulk list. */ - + regval = lpc17_getreg(LPC17_USBHOST_CMDST); regval |= OHCI_CMDST_BLF; lpc17_putreg(regval, LPC17_USBHOST_CMDST); @@ -2375,7 +2375,7 @@ static int lpc17_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep, { ret = OK; } - else + else { uvdbg("Bad TD completion status: %d\n", ed->tdstatus); ret = -EIO; @@ -2443,7 +2443,7 @@ static void lpc17_disconnect(FAR struct usbhost_driver_s *drvr) priv->class = NULL; } - + /******************************************************************************* * Initialization *******************************************************************************/ @@ -2687,11 +2687,11 @@ FAR struct usbhost_connection_s *lpc17_usbhost_initialize(int controller) /* Software reset */ lpc17_putreg(OHCI_CMDST_HCR, LPC17_USBHOST_CMDST); - + /* Write Fm interval (FI), largest data packet counter (FSMPS), and * periodic start. */ - + lpc17_putreg(DEFAULT_FMINTERVAL, LPC17_USBHOST_FMINT); lpc17_putreg(DEFAULT_PERSTART, LPC17_USBHOST_PERSTART); diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_userspace.c b/nuttx/arch/arm/src/lpc17xx/lpc17_userspace.c index a9bddfc8c..8a2d23dde 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_userspace.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_userspace.c @@ -98,7 +98,7 @@ void lpc17_userspace(void) /* Initialize all of user-space .data */ DEBUGASSERT(USERSPACE->us_datasource != 0 && - USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && + USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && USERSPACE->us_datastart <= USERSPACE->us_dataend); src = (uint8_t*)USERSPACE->us_datasource; diff --git a/nuttx/arch/arm/src/lpc214x/README.txt b/nuttx/arch/arm/src/lpc214x/README.txt index 9cfc99593..752060c05 100644 --- a/nuttx/arch/arm/src/lpc214x/README.txt +++ b/nuttx/arch/arm/src/lpc214x/README.txt @@ -9,7 +9,7 @@ microcontroller with embedded high-speed flash memory ranging from 32 kB to 512 kB. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 pct -with minimal performance penalty. +with minimal performance penalty. Due to their tiny size and low power consumption, LPC2141/42/44/46/48 are ideal for applications where miniaturization is a key requirement, such as access @@ -20,42 +20,42 @@ protocol converters, soft modems, voice recognition and low end imaging, providi both large buffer size and high processing power. Various 32-bit timers, single or dual 10-bit ADC(s), 10-bit DAC, PWM channels and 45 fast GPIO lines with up to nine edge or level sensitive external interrupt pins make these microcontrollers -suitable for industrial control and medical systems. +suitable for industrial control and medical systems. Features ^^^^^^^^ -o 16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package. +o 16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package. o 8 kB to 40 kB of on-chip static RAM and 32 kB to 512 kB of on-chip flash memory. - 128-bit wide interface/accelerator enables high-speed 60 MHz operation. + 128-bit wide interface/accelerator enables high-speed 60 MHz operation. o In-System Programming/In-Application Programming (ISP/IAP) via on-chip boot loader software. Single flash sector or full chip erase in 400 ms and programming - of 256 B in 1 ms. + of 256 B in 1 ms. o EmbeddedICE RT and Embedded Trace interfaces offer real-time debugging with the - on-chip RealMonitor software and high-speed tracing of instruction execution. + on-chip RealMonitor software and high-speed tracing of instruction execution. o USB 2.0 Full-speed compliant device controller with 2 kB of endpoint RAM. In addition, - the LPC2146/48 provides 8 kB of on-chip RAM accessible to USB by DMA. + the LPC2146/48 provides 8 kB of on-chip RAM accessible to USB by DMA. o One or two (LPC2141/42 vs. LPC2144/46/48) 10-bit ADCs provide a total of 6/14 analog - inputs, with conversion times as low as 2.44 us per channel. -o Single 10-bit DAC provides variable analog output (LPC2142/44/46/48 only). + inputs, with conversion times as low as 2.44 us per channel. +o Single 10-bit DAC provides variable analog output (LPC2142/44/46/48 only). o Two 32-bit timers/external event counters (with four capture and four compare - channels each), PWM unit (six outputs) and watchdog. -o Low power Real-Time Clock (RTC) with independent power and 32 kHz clock input. + channels each), PWM unit (six outputs) and watchdog. +o Low power Real-Time Clock (RTC) with independent power and 32 kHz clock input. o Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus (400 - kbit/s), SPI and SSP with buffering and variable data length capabilities. -o Vectored Interrupt Controller (VIC) with configurable priorities and vector addresses. -o Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package. -o Up to 21 external interrupt pins available. + kbit/s), SPI and SSP with buffering and variable data length capabilities. +o Vectored Interrupt Controller (VIC) with configurable priorities and vector addresses. +o Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package. +o Up to 21 external interrupt pins available. o 60 MHz maximum CPU clock available from programmable on-chip PLL with settling - time of 100 us. -o On-chip integrated oscillator operates with an external crystal from 1 MHz to 25 MHz. -o Power saving modes include Idle and Power-down. + time of 100 us. +o On-chip integrated oscillator operates with an external crystal from 1 MHz to 25 MHz. +o Power saving modes include Idle and Power-down. o Individual enable/disable of peripheral functions as well as peripheral clock scaling - for additional power optimization. -o Processor wake-up from Power-down mode via external interrupt or BOD. -o Single power supply chip with POR and BOD circuits: + for additional power optimization. +o Processor wake-up from Power-down mode via external interrupt or BOD. +o Single power supply chip with POR and BOD circuits: o CPU operating voltage range of 3.0 V to 3.6 V (3.3 V +- 10 pct) with 5 V tolerant - I/O pads. + I/O pads. + - diff --git a/nuttx/arch/arm/src/lpc214x/chip.h b/nuttx/arch/arm/src/lpc214x/chip.h index d469aae8b..725cd520e 100644 --- a/nuttx/arch/arm/src/lpc214x/chip.h +++ b/nuttx/arch/arm/src/lpc214x/chip.h @@ -90,7 +90,7 @@ #define LPC214X_PLL_BASE 0xe01fc080 /* Phase Locked Loop (PLL) base address */ #define LPC214X_PCON_BASE 0xe01fc0c0 /* Power Control (PCON) base address */ #define LPC214X_APBDIV 0xe01fc100 /* APBDIV Address */ -#define LPC214X_EXT_BASE 0xe01fc140 /* External Interrupt base address */ +#define LPC214X_EXT_BASE 0xe01fc140 /* External Interrupt base address */ /* AHB Register block base addresses */ diff --git a/nuttx/arch/arm/src/lpc214x/lpc214x_head.S b/nuttx/arch/arm/src/lpc214x/lpc214x_head.S index 25986def8..a29b78eb5 100644 --- a/nuttx/arch/arm/src/lpc214x/lpc214x_head.S +++ b/nuttx/arch/arm/src/lpc214x/lpc214x_head.S @@ -90,7 +90,7 @@ * * Bit 0:4 MSEL: PLL Multiplier "M" Value * CCLK = M * Fosc - * Bit 5:6 PSEL: PLL Divider "P" Value + * Bit 5:6 PSEL: PLL Divider "P" Value * Fcco = CCLK * 2 * P * 156MHz <= Fcco <= 320MHz */ @@ -403,9 +403,9 @@ #ifdef CONFIG_MAM_SETUP ldr \base, =LPC214X_MAM_BASE mov \val, #CONFIG_MAMTIM_VALUE - str \val, [\base, #LPC214x_MAM_TIM_OFFSET] + str \val, [\base, #LPC214x_MAM_TIM_OFFSET] mov \val, #CONFIG_MAMCR_VALUE - str \val, [\base, #LPC214X_MAM_CR_OFFSET] + str \val, [\base, #LPC214X_MAM_CR_OFFSET] #endif .endm diff --git a/nuttx/arch/arm/src/lpc214x/lpc214x_lowputc.S b/nuttx/arch/arm/src/lpc214x/lpc214x_lowputc.S index b53e7aa78..d863c9e2f 100644 --- a/nuttx/arch/arm/src/lpc214x/lpc214x_lowputc.S +++ b/nuttx/arch/arm/src/lpc214x/lpc214x_lowputc.S @@ -199,7 +199,7 @@ up_lowsetup: /* Configure the FIFOs */ - mov r1, #LPC214X_FCR_VALUE + mov r1, #LPC214X_FCR_VALUE strb r1, [r0, #LPC214X_UART_FCR_OFFSET] /* And return */ diff --git a/nuttx/arch/arm/src/lpc214x/lpc214x_serial.c b/nuttx/arch/arm/src/lpc214x/lpc214x_serial.c index 7b3192b31..5df5264fe 100644 --- a/nuttx/arch/arm/src/lpc214x/lpc214x_serial.c +++ b/nuttx/arch/arm/src/lpc214x/lpc214x_serial.c @@ -742,7 +742,7 @@ static bool up_txempty(struct uart_dev_s *dev) * Name: up_serialinit * * Description: - * Performs the low level UART initialization early in + * Performs the low level UART initialization early in * debug so that the serial console will be available * during bootup. This must be called before up_serialinit. * diff --git a/nuttx/arch/arm/src/lpc214x/lpc214x_usbdev.c b/nuttx/arch/arm/src/lpc214x/lpc214x_usbdev.c index da55c67db..fcc6d90c6 100644 --- a/nuttx/arch/arm/src/lpc214x/lpc214x_usbdev.c +++ b/nuttx/arch/arm/src/lpc214x/lpc214x_usbdev.c @@ -3094,7 +3094,7 @@ static int lpc214x_wakeup(struct usbdev_s *dev) * Name: lpc214x_selfpowered * * Description: - * Sets/clears the device selfpowered feature + * Sets/clears the device selfpowered feature * *******************************************************************************/ diff --git a/nuttx/arch/arm/src/lpc2378/chip.h b/nuttx/arch/arm/src/lpc2378/chip.h index 6113f21e8..e39ceed72 100644 --- a/nuttx/arch/arm/src/lpc2378/chip.h +++ b/nuttx/arch/arm/src/lpc2378/chip.h @@ -44,7 +44,7 @@ /**************************************************************************************************** * Included Files ****************************************************************************************************/ - + #include <sys/types.h> /**************************************************************************************************** @@ -57,7 +57,7 @@ #define LPC23XX_FIO_BASE 0x3fffc000 #define LPC23XX_ONCHIP_RAM_BASE 0x40000000 #define LPC23XX_USBDMA_RAM_BASE 0x7fd00000 -#define LPC23XX_ETHERNET_RAM_BASE 0x7fe00000 +#define LPC23XX_ETHERNET_RAM_BASE 0x7fe00000 #define LPC23XX_BOOT_BLOCK 0x7fffd000 #define LPC23XX_EXTMEM_BASE 0x80000000 #define LPC23XX_APB_BASE 0xe0000000 @@ -101,7 +101,7 @@ #define LPC23XX_EMAC_BASE 0xFFE00000 /* Ethernet MAC base address */ #define LPC23XX_USB_BASE 0xFFE0C200 /* USB base address */ #define LPC23XX_SCB_BASE 0xE01FC000 /* System Control Block (SBC) base address */ -#define LPC23XX_EXT_BASE 0xe01fc140 /* External Interrupt base address */ +#define LPC23XX_EXT_BASE 0xe01fc140 /* External Interrupt base address */ /* AHB Register block base addresses */ @@ -513,7 +513,7 @@ #define USB_SYS_ERR_INT_SET_OFFSET 0xC0 /* System Control Block(SCB) modules include Memory Accelerator Module, -Phase Locked Loop, VPB divider, Power Control, External Interrupt, +Phase Locked Loop, VPB divider, Power Control, External Interrupt, Reset, and Code Security/Debugging */ #define SCB_BASE_ADDR 0xE01FC000 @@ -556,7 +556,7 @@ Reset, and Code Security/Debugging */ //~ /* External Memory Controller (EMC) definitions */ -/* MPMC(EMC) registers, note: all the external memory controller(EMC) registers +/* MPMC(EMC) registers, note: all the external memory controller(EMC) registers are for LPC24xx only. */ #define STATIC_MEM0_BASE 0x80000000 #define STATIC_MEM1_BASE 0x81000000 diff --git a/nuttx/arch/arm/src/lpc2378/lpc23xx_lowputc.S b/nuttx/arch/arm/src/lpc2378/lpc23xx_lowputc.S index cc332a961..45dae1338 100755 --- a/nuttx/arch/arm/src/lpc2378/lpc23xx_lowputc.S +++ b/nuttx/arch/arm/src/lpc2378/lpc23xx_lowputc.S @@ -81,7 +81,7 @@ # define UARTx2STOP CONFIG_UART1_2STOP #elif defined(CONFIG_UART2_SERIAL_CONSOLE) # define UARTxBASE UART2_BASE_ADDR -# define PINSELECT LPC23XX_PINSEL0 +# define PINSELECT LPC23XX_PINSEL0 # define UARTxPCLKSEL 0xE01FC1AC # define PCLKSEL_MASK U2_PCLKSEL_MASK # define UARTxPINSEL UART2_PINSEL @@ -249,7 +249,7 @@ up_lowsetup: /* Configure the FIFOs */ - mov r1, #FCR_VALUE + mov r1, #FCR_VALUE strb r1, [r0, #UART_FCR_OFFSET] mov r1, #LCR_VALUE diff --git a/nuttx/arch/arm/src/lpc2378/lpc23xx_serial.c b/nuttx/arch/arm/src/lpc2378/lpc23xx_serial.c index a7fce9739..dcd630eee 100644 --- a/nuttx/arch/arm/src/lpc2378/lpc23xx_serial.c +++ b/nuttx/arch/arm/src/lpc2378/lpc23xx_serial.c @@ -348,7 +348,7 @@ static inline void up_configbaud(struct up_dev_s *priv) for (tmulval = 1; tmulval <= 15 && err > 0; tmulval++) { - /* Try every valid pre-scale div, tdivaddval (or until a perfect match is + /* Try every valid pre-scale div, tdivaddval (or until a perfect match is * found). */ @@ -481,7 +481,7 @@ static int up_setup(struct uart_dev_s *dev) (FCR_FIFO_TRIG8 | FCR_TX_FIFO_RESET | FCR_RX_FIFO_RESET | FCR_FIFO_ENABLE)); - /* The NuttX serial driver waits for the first THRE interrrupt before sending + /* The NuttX serial driver waits for the first THRE interrrupt before sending * serial data... However, it appears that the LPC2378 hardware too does not * generate that interrupt until a transition from not-empty to empty. So, * the current kludge here is to send one NULL at startup to kick things off. diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_allocateheap.c b/nuttx/arch/arm/src/lpc31xx/lpc31_allocateheap.c index 47136fdb8..6606f5a80 100644 --- a/nuttx/arch/arm/src/lpc31xx/lpc31_allocateheap.c +++ b/nuttx/arch/arm/src/lpc31xx/lpc31_allocateheap.c @@ -129,15 +129,15 @@ #ifdef CONFIG_PAGING # ifdef PGTABLE_IN_HIGHSRAM -# define LPC31_HEAP_VEND (PG_LOCKED_VBASE + PG_TOTAL_VSIZE - PGTABLE_SIZE) +# define LPC31_HEAP_VEND (PG_LOCKED_VBASE + PG_TOTAL_VSIZE - PGTABLE_SIZE) # else -# define LPC31_HEAP_VEND (PG_LOCKED_VBASE + PG_TOTAL_VSIZE) +# define LPC31_HEAP_VEND (PG_LOCKED_VBASE + PG_TOTAL_VSIZE) # endif #else # ifdef PGTABLE_IN_HIGHSRAM -# define LPC31_HEAP_VEND (LPC31_INTSRAM_VSECTION + LPC31_ISRAM_SIZE - PGTABLE_SIZE) +# define LPC31_HEAP_VEND (LPC31_INTSRAM_VSECTION + LPC31_ISRAM_SIZE - PGTABLE_SIZE) # else -# define LPC31_HEAP_VEND (LPC31_INTSRAM_VSECTION + LPC31_ISRAM_SIZE) +# define LPC31_HEAP_VEND (LPC31_INTSRAM_VSECTION + LPC31_ISRAM_SIZE) # endif #endif diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_boot.c b/nuttx/arch/arm/src/lpc31xx/lpc31_boot.c index 24beb87fa..3e8b1949d 100644 --- a/nuttx/arch/arm/src/lpc31xx/lpc31_boot.c +++ b/nuttx/arch/arm/src/lpc31xx/lpc31_boot.c @@ -90,40 +90,40 @@ extern uint32_t _vector_end; /* End+1 of vector block */ #ifndef CONFIG_ARCH_ROMPGTABLE static const struct section_mapping_s section_mapping[] = { - { LPC31_SHADOWSPACE_PSECTION, LPC31_SHADOWSPACE_VSECTION, + { LPC31_SHADOWSPACE_PSECTION, LPC31_SHADOWSPACE_VSECTION, LPC31_SHADOWSPACE_MMUFLAGS, LPC31_SHADOWSPACE_NSECTIONS}, #ifndef CONFIG_PAGING /* SRAM is already fully mapped */ - { LPC31_INTSRAM_PSECTION, LPC31_INTSRAM_VSECTION, + { LPC31_INTSRAM_PSECTION, LPC31_INTSRAM_VSECTION, LPC31_INTSRAM_MMUFLAGS, LPC31_INTSRAM_NSECTIONS}, #endif #ifdef CONFIG_ARCH_ROMPGTABLE - { LPC31_INTSROM0_PSECTION, LPC31_INTSROM0_VSECTION, + { LPC31_INTSROM0_PSECTION, LPC31_INTSROM0_VSECTION, LPC31_INTSROM_MMUFLAGS, LPC31_INTSROM0_NSECTIONS}, #endif - { LPC31_APB01_PSECTION, LPC31_APB01_VSECTION, + { LPC31_APB01_PSECTION, LPC31_APB01_VSECTION, LPC31_APB01_MMUFLAGS, LPC31_APB01_NSECTIONS}, - { LPC31_APB2_PSECTION, LPC31_APB2_VSECTION, + { LPC31_APB2_PSECTION, LPC31_APB2_VSECTION, LPC31_APB2_MMUFLAGS, LPC31_APB2_NSECTIONS}, - { LPC31_APB3_PSECTION, LPC31_APB3_VSECTION, + { LPC31_APB3_PSECTION, LPC31_APB3_VSECTION, LPC31_APB3_MMUFLAGS, LPC31_APB3_NSECTIONS}, - { LPC31_APB4MPMC_PSECTION, LPC31_APB4MPMC_VSECTION, + { LPC31_APB4MPMC_PSECTION, LPC31_APB4MPMC_VSECTION, LPC31_APB4MPMC_MMUFLAGS, LPC31_APB4MPMC_NSECTIONS}, - { LPC31_MCI_PSECTION, LPC31_MCI_VSECTION, + { LPC31_MCI_PSECTION, LPC31_MCI_VSECTION, LPC31_MCI_MMUFLAGS, LPC31_MCI_NSECTIONS}, - { LPC31_USBOTG_PSECTION, LPC31_USBOTG_VSECTION, + { LPC31_USBOTG_PSECTION, LPC31_USBOTG_VSECTION, LPC31_USBOTG_MMUFLAGS, LPC31_USBOTG_NSECTIONS}, #if defined(CONFIG_LPC31_EXTSRAM0) && CONFIG_LPC31_EXTSRAM0SIZE > 0 - { LPC31_EXTSRAM_PSECTION, LPC31_EXTSRAM_VSECTION, + { LPC31_EXTSRAM_PSECTION, LPC31_EXTSRAM_VSECTION, LPC31_EXTSDRAM_MMUFLAGS, LPC31_EXTSRAM_NSECTIONS}, #endif #if defined(CONFIG_LPC31_EXTDRAM) && CONFIG_LPC31_EXTDRAMSIZE > 0 - { LPC31_EXTSDRAM0_PSECTION, LPC31_EXTSDRAM0_VSECTION, + { LPC31_EXTSDRAM0_PSECTION, LPC31_EXTSDRAM0_VSECTION, LPC31_EXTSDRAM_MMUFLAGS, LPC31_EXTSDRAM0_NSECTIONS}, #endif - { LPC31_INTC_PSECTION, LPC31_INTC_VSECTION, + { LPC31_INTC_PSECTION, LPC31_INTC_VSECTION, LPC31_INTC_MMUFLAGS, LPC31_INTC_NSECTIONS}, #ifdef CONFIG_LPC31_EXTNAND - { LPC31_NAND_PSECTION, LPC31_NAND_VSECTION + { LPC31_NAND_PSECTION, LPC31_NAND_VSECTION LPC31_NAND_MMUFLAGS, LPC31_NAND_NSECTIONS}, #endif }; @@ -218,7 +218,7 @@ static void up_vectorpermissions(uint32_t mmuflags) pte = *ptr; if (pte == 0) { - pte = PG_VECT_PBASE; + pte = PG_VECT_PBASE; } else { @@ -372,10 +372,10 @@ void up_boot(void) lpc31_hp1pllconfig(); lpc31_hp0pllconfig(); - + /* Initialize clocking to settings provided by board-specific logic */ - lpc31_clkinit(&g_boardclks); + lpc31_clkinit(&g_boardclks); /* Map first 4KB of ARM space to ISRAM area */ diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_cgu.h b/nuttx/arch/arm/src/lpc31xx/lpc31_cgu.h index 0d1d7b7fb..15c16e8a8 100644 --- a/nuttx/arch/arm/src/lpc31xx/lpc31_cgu.h +++ b/nuttx/arch/arm/src/lpc31xx/lpc31_cgu.h @@ -1121,7 +1121,7 @@ #define CGU_FREQIN_I2SRXWS1 4 /* I2SRX_WS1 */ #define CGU_FREQIN_HPPLL0 5 /* HPPLL0 (Audio/I2S PLL) */ #define CGU_FREQIN_HPPLL1 6 /* HPPLL1 (System PLL) */ -#define CGU_NFREQIN 7 +#define CGU_NFREQIN 7 /* CGU clock switchbox register bit definitions *************************************************/ @@ -1569,7 +1569,7 @@ Nandflash Controller */ /* HP0 Bandwith Selection register HP0_INSELR, address 0x13004d10, * HP1 bandwith Selection register HP1_INSELR, address 0x13004d48 */ - + #define CGU_HPINSELR_SHIFT (0) /* Bits 0-3: Pins to select the bandwidth */ #define CGU_HPINSELR_MASK (15 << CGU_HPINSELR_SHIFT) diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_cgudrvr.h b/nuttx/arch/arm/src/lpc31xx/lpc31_cgudrvr.h index 8aae207ed..19078cf3f 100644 --- a/nuttx/arch/arm/src/lpc31xx/lpc31_cgudrvr.h +++ b/nuttx/arch/arm/src/lpc31xx/lpc31_cgudrvr.h @@ -229,7 +229,7 @@ enum lpc31_clockid_e CLKID_DMACLKGATED, /* 9 DMA_CLK_GATED */ CLKID_NANDFLASHS0CLK, /* 10 NANDFLASH_S0_CLK */ CLKID_NANDFLASHECCCLK, /* 11 NANDFLASH_ECC_CLK */ - CLKID_NANDFLASHAESCLK, /* 12 NANDFLASH_AES_CLK (Reserved on LPC313x) */ + CLKID_NANDFLASHAESCLK, /* 12 NANDFLASH_AES_CLK (Reserved on LPC313x) */ CLKID_NANDFLASHNANDCLK, /* 13 NANDFLASH_NAND_CLK */ CLKID_NANDFLASHPCLK, /* 14 NANDFLASH_PCLK */ CLKID_CLOCKOUT, /* 15 CLOCK_OUT */ @@ -307,7 +307,7 @@ enum lpc31_clockid_e /* Domain 6: UART_BASE */ CLKID_UARTUCLK, /* 72 UART_U_CLK */ - + /* Domain 7: CLK1024FS_BASE */ CLKID_I2SEDGEDETECTCLK, /* 73 I2S_EDGE_DETECT_CLK */ @@ -383,11 +383,11 @@ enum lpc31_resetid_e RESETID_I2SRXIF0RST, /* 33 I2SRX_IF_0 */ RESETID_I2SRXFF1RST, /* 34 I2SRX_FIFO_1 */ RESETID_I2SRXIF1RST, /* 35 I2SRX_IF_1 */ - RESETID_RESERVED40, /* 36 Reserved */ - RESETID_RESERVED41, /* 37 Reserved */ - RESETID_RESERVED42, /* 38 Reserved */ - RESETID_RESERVED43, /* 39 Reserved */ - RESETID_RESERVED44, /* 40 Reserved */ + RESETID_RESERVED40, /* 36 Reserved */ + RESETID_RESERVED41, /* 37 Reserved */ + RESETID_RESERVED42, /* 38 Reserved */ + RESETID_RESERVED43, /* 39 Reserved */ + RESETID_RESERVED44, /* 40 Reserved */ RESETID_LCDRST, /* 41 LCD Interface */ RESETID_SPIRSTAPB, /* 42 apb_clk domain of SPI */ RESETID_SPIRSTIP, /* 43 ip_clk domain of SPI */ diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_clkexten.c b/nuttx/arch/arm/src/lpc31xx/lpc31_clkexten.c index 4ed0e5f73..770bfb6a8 100644 --- a/nuttx/arch/arm/src/lpc31xx/lpc31_clkexten.c +++ b/nuttx/arch/arm/src/lpc31xx/lpc31_clkexten.c @@ -64,7 +64,7 @@ /**************************************************************************** * Public Functions ****************************************************************************/ - + /**************************************************************************** * Name: lpc31_enableexten * @@ -77,7 +77,7 @@ void lpc31_enableexten(enum lpc31_clockid_e clkid) { uint32_t regaddr; uint32_t regval; - + switch (clkid) { case CLKID_DMACLKGATED: /* 9 DMA_CLK_GATED */ @@ -120,7 +120,7 @@ void lpc31_disableexten(enum lpc31_clockid_e clkid) { uint32_t regaddr; uint32_t regval; - + switch (clkid) { case CLKID_DMACLKGATED: /* 9 DMA_CLK_GATED */ diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_clkinit.c b/nuttx/arch/arm/src/lpc31xx/lpc31_clkinit.c index b0e032281..0f2c1141f 100644 --- a/nuttx/arch/arm/src/lpc31xx/lpc31_clkinit.c +++ b/nuttx/arch/arm/src/lpc31xx/lpc31_clkinit.c @@ -107,7 +107,7 @@ static void lpc31_domaininit(struct lpc31_domainconfig_s* dmn) } /* Configure the fractional dividers in this domain */ - + for (fdndx = 0; fdndx < dmn->nfdiv; fdndx++, sub++) { /* Set fractional divider confiruation but don't enable it yet */ @@ -125,7 +125,7 @@ static void lpc31_domaininit(struct lpc31_domainconfig_s* dmn) for (clkndx = 0; clkndx <= dmn->nclks; clkndx++) { /* Does this clock have an ESR register? */ - + esrndx = lpc31_esrndx((enum lpc31_clockid_e)(clkndx + dmn->clk1)); if (esrndx != ESRNDX_INVALID) { diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_defclk.c b/nuttx/arch/arm/src/lpc31xx/lpc31_defclk.c index 1f0ec194b..4670253f4 100644 --- a/nuttx/arch/arm/src/lpc31xx/lpc31_defclk.c +++ b/nuttx/arch/arm/src/lpc31xx/lpc31_defclk.c @@ -85,7 +85,7 @@ bool lpc31_defclk(enum lpc31_clockid_e clkid) /* Check if this clock should be enabled. This is determined by * 3 bitsets provided by board-specific logic in board/board.h. */ - + if ((int)clkid < 32) { enable = ((BOARD_CLKS_0_31 & (1 << (int)clkid)) != 0); diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_ehci.c b/nuttx/arch/arm/src/lpc31xx/lpc31_ehci.c index e41485b4d..46a4b4951 100755 --- a/nuttx/arch/arm/src/lpc31xx/lpc31_ehci.c +++ b/nuttx/arch/arm/src/lpc31xx/lpc31_ehci.c @@ -4320,7 +4320,7 @@ FAR struct usbhost_connection_s *lpc31_ehci_initialize(int controller) /* Enable USB OTG PLL and wait for lock */ putreg32(0, LPC31_SYSCREG_USB_ATXPLLPDREG); - + uint32_t bank = EVNTRTR_BANK(EVENTRTR_USBATXPLLLOCK); uint32_t bit = EVNTRTR_BIT(EVENTRTR_USBATXPLLLOCK); diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_esrndx.c b/nuttx/arch/arm/src/lpc31xx/lpc31_esrndx.c index e29fe937d..a868dc57a 100644 --- a/nuttx/arch/arm/src/lpc31xx/lpc31_esrndx.c +++ b/nuttx/arch/arm/src/lpc31xx/lpc31_esrndx.c @@ -89,7 +89,7 @@ int lpc31_esrndx(enum lpc31_clockid_e clkid) /* There ar 89 Enable Select Registers (ESR). Indexing for these * registers is identical to indexing to other registers (like PCR), - * except that there are no ESR registers for + * except that there are no ESR registers for * * * CLKID_I2SRXBCK0 Clock ID 87: I2SRX_BCK0 diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_fdivinit.c b/nuttx/arch/arm/src/lpc31xx/lpc31_fdivinit.c index f8ecb00f3..488a802f9 100644 --- a/nuttx/arch/arm/src/lpc31xx/lpc31_fdivinit.c +++ b/nuttx/arch/arm/src/lpc31xx/lpc31_fdivinit.c @@ -110,7 +110,7 @@ lpc31_bitwidth(unsigned int value, unsigned int fdwid) /* Is this bit set? If so, then the width of the value is 0 to bit, * or bit+1. */ - + if ((value & (1 << bit)) != 0) { width = bit + 1; @@ -148,7 +148,7 @@ uint32_t lpc31_fdivinit(int fdcndx, * consumption, the lpc313x user manual recommends that madd and msub * be shifted right to have as many trailing zero's as possible. */ - + madd = fdiv->m - fdiv->n; msub = -fdiv->n; @@ -170,7 +170,7 @@ uint32_t lpc31_fdivinit(int fdcndx, } /* Find maximum bit width of madd & msub. Here we calculate the width of the OR - * of the two values. The width of the OR will be the width of the wider value + * of the two values. The width of the OR will be the width of the wider value */ fdshift = fdwid - lpc31_bitwidth((unsigned int)madd | (unsigned int)fdiv->n, fdwid); @@ -181,7 +181,7 @@ uint32_t lpc31_fdivinit(int fdcndx, madd = (madd << fdshift) & fdmask; msub = (msub << fdshift) & fdmask; regval = (madd << maddshift) | (msub << msubshift); - + /* Check if 50% duty cycle is needed for this divider */ if (fdiv->stretch) diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_internal.h b/nuttx/arch/arm/src/lpc31xx/lpc31_internal.h index 6b784cd6d..4730fd439 100644 --- a/nuttx/arch/arm/src/lpc31xx/lpc31_internal.h +++ b/nuttx/arch/arm/src/lpc31xx/lpc31_internal.h @@ -193,7 +193,7 @@ void lpc31_clockconfig(void); * 4. Add a calls to up_spiinitialize() in your low level application * initialization logic * 5. The handle returned by up_spiinitialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * @@ -318,7 +318,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno); * * Input Parameters: * dev - An instance of the SDIO driver device state structure. - * cardinslot - true is a card has been detected in the slot; false if a + * cardinslot - true is a card has been detected in the slot; false if a * card has been removed from the slot. Only transitions * (inserted->removed or removed->inserted should be reported) * diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_irq.c b/nuttx/arch/arm/src/lpc31xx/lpc31_irq.c index 4418ebc08..ec1f7bbdb 100644 --- a/nuttx/arch/arm/src/lpc31xx/lpc31_irq.c +++ b/nuttx/arch/arm/src/lpc31xx/lpc31_irq.c @@ -102,7 +102,7 @@ void up_irqinitialize(void) putreg32(0, LPC31_INTC_PRIORITYMASK0); /* Proc interrupt request 0: IRQ */ putreg32(0, LPC31_INTC_PRIORITYMASK1); /* Proc interrupt request 1: FIQ */ - + /* Disable all interrupts. Start from index 1 since 0 is unused.*/ for (irq = 0; irq < NR_IRQS; irq++) diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_lowputc.c b/nuttx/arch/arm/src/lpc31xx/lpc31_lowputc.c index 12e368db7..e031ef10d 100644 --- a/nuttx/arch/arm/src/lpc31xx/lpc31_lowputc.c +++ b/nuttx/arch/arm/src/lpc31xx/lpc31_lowputc.c @@ -113,7 +113,7 @@ static inline void up_waittxready(void) for (tmp = 1000 ; tmp > 0 ; tmp--) { /* Check if the tranmitter holding register (THR) is empty */ - + if ((getreg32(LPC31_UART_LSR) & UART_LSR_THRE) != 0) { /* The THR is empty, return */ @@ -169,7 +169,7 @@ static inline void up_configbaud(void) */ /* Get UART block clock divided by 16 */ - + qtrclk = lpc31_clkfreq(CLKID_UARTUCLK, DOMAINID_UART) >> 4; /* Try every valid multiplier, tmulval (or until a perfect diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_pllconfig.c b/nuttx/arch/arm/src/lpc31xx/lpc31_pllconfig.c index fc6d4dc3b..427606b02 100644 --- a/nuttx/arch/arm/src/lpc31xx/lpc31_pllconfig.c +++ b/nuttx/arch/arm/src/lpc31xx/lpc31_pllconfig.c @@ -143,7 +143,7 @@ lpc31_restoredomains(const struct lpc31_pllconfig_s * const cfg, /**************************************************************************** * Public Functions ****************************************************************************/ - + /**************************************************************************** * Name: lpc31_pllconfig * @@ -171,13 +171,13 @@ void lpc31_pllconfig(const struct lpc31_pllconfig_s * const cfg) */ putreg32(CGU_HPMODE_PD, pllbase + LPC31_CGU_HPMODE_OFFSET); - + /* Select PLL input frequency source */ putreg32(cfg->finsel, pllbase + LPC31_CGU_HPFINSEL_OFFSET); /* Set M divider */ - + putreg32(cfg->mdec & CGU_HPMDEC_MASK, pllbase + LPC31_CGU_HPMDEC_OFFSET); /* Set N divider */ @@ -195,7 +195,7 @@ void lpc31_pllconfig(const struct lpc31_pllconfig_s * const cfg) putreg32(cfg->selp, pllbase + LPC31_CGU_HPSELP_OFFSET); /* Power up pll */ - + putreg32((cfg->mode & ~CGU_HPMODE_PD) | CGU_HPMODE_CLKEN, pllbase + LPC31_CGU_HPMODE_OFFSET); /* Save the estimated freq in driver data for future clk calcs */ @@ -221,7 +221,7 @@ void lpc31_pllconfig(const struct lpc31_pllconfig_s * const cfg) void lpc31_hp0pllconfig(void) { - struct lpc31_pllconfig_s cfg = + struct lpc31_pllconfig_s cfg = { .hppll = CGU_HP0PLL, .finsel = BOARD_HPLL0_FINSEL, @@ -248,7 +248,7 @@ void lpc31_hp0pllconfig(void) void lpc31_hp1pllconfig(void) { - struct lpc31_pllconfig_s cfg = + struct lpc31_pllconfig_s cfg = { .hppll = CGU_HP1PLL, .finsel = BOARD_HPLL1_FINSEL, diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_serial.c b/nuttx/arch/arm/src/lpc31xx/lpc31_serial.c index b79295488..46e91aba4 100644 --- a/nuttx/arch/arm/src/lpc31xx/lpc31_serial.c +++ b/nuttx/arch/arm/src/lpc31xx/lpc31_serial.c @@ -238,7 +238,7 @@ static inline void up_configbaud(void) */ /* Get UART block clock divided by 16 */ - + qtrclk = lpc31_clkfreq(CLKID_UARTUCLK, DOMAINID_UART) >> 4; /* Try every valid multiplier, tmulval (or until a perfect diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_setfdiv.c b/nuttx/arch/arm/src/lpc31xx/lpc31_setfdiv.c index 196118b18..c532dcf97 100644 --- a/nuttx/arch/arm/src/lpc31xx/lpc31_setfdiv.c +++ b/nuttx/arch/arm/src/lpc31xx/lpc31_setfdiv.c @@ -84,7 +84,7 @@ void lpc31_setfdiv(enum lpc31_domainid_e dmnid, unsigned int basefreq; int fdcndx; int bcrndx; - + /* Get the frequency divider associated with this clock */ fdcndx = lpc31_fdcndx(clkid, dmnid); @@ -97,7 +97,7 @@ void lpc31_setfdiv(enum lpc31_domainid_e dmnid, regaddr = LPC31_CGU_SSR((int)dmnid); basefreq = (getreg32(regaddr) & CGU_SSR_FS_MASK) >> CGU_SSR_FS_SHIFT; - + /* Switch domain to FFAST input */ lpc31_selectfreqin(dmnid, CGU_FS_FFAST); diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_spi.c b/nuttx/arch/arm/src/lpc31xx/lpc31_spi.c index 19e3e3592..ee9034c54 100644 --- a/nuttx/arch/arm/src/lpc31xx/lpc31_spi.c +++ b/nuttx/arch/arm/src/lpc31xx/lpc31_spi.c @@ -91,7 +91,7 @@ struct lpc31_spidev_s uint32_t actual; /* Actual clock frequency */ uint8_t nbits; /* Width of work in bits (8 or 16) */ uint8_t mode; /* Mode 0,1,2,3 */ - + uint32_t slv1; uint32_t slv2; }; @@ -156,7 +156,7 @@ static const struct spi_ops_s g_spiops = .registercallback = 0, }; -static struct lpc31_spidev_s g_spidev = +static struct lpc31_spidev_s g_spidev = { .spidev = { &g_spiops }, }; @@ -299,7 +299,7 @@ static inline void spi_drive_cs(FAR struct lpc31_spidev_s *priv, uint8_t slave, } spi_putreg(IOCONFIG_SPI_CSOUT0, LPC31_IOCONFIG_SPI_MODE1SET); break; - + case 1: if (val == 0) { @@ -350,7 +350,7 @@ static inline void spi_select_slave(FAR struct lpc31_spidev_s *priv, uint8_t sla spi_putreg(priv->slv2, LPC31_SPI_SLV0_2); spi_putreg(SPI_SLVENABLE1_ENABLED, LPC31_SPI_SLVENABLE); break; - + case 1: spi_putreg(priv->slv1, LPC31_SPI_SLV1_1); spi_putreg(priv->slv2, LPC31_SPI_SLV1_2); @@ -483,7 +483,7 @@ static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool sel { struct lpc31_spidev_s *priv = (struct lpc31_spidev_s *) dev; uint8_t slave = 0; - + /* FIXME: map the devid to the SPI slave - this should really * be in board specific code..... */ switch (devid) @@ -503,19 +503,19 @@ static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool sel default: return; } - + /* - * Since we don't use sequential multi-slave mode, but rather - * perform the transfer piecemeal by consecutive calls to - * SPI_SEND, then we must manually assert the chip select - * across the whole transfer + * Since we don't use sequential multi-slave mode, but rather + * perform the transfer piecemeal by consecutive calls to + * SPI_SEND, then we must manually assert the chip select + * across the whole transfer */ if (selected) { spi_drive_cs(priv, slave, 0); spi_select_slave(priv, slave); - + /* Enable SPI as master and notify of slave enables change */ spi_putreg((1 << SPI_CONFIG_INTERSLVDELAY_SHIFT) | SPI_CONFIG_UPDENABLE | SPI_CONFIG_SPIENABLE, LPC31_SPI_CONFIG); @@ -523,11 +523,11 @@ static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool sel else { spi_drive_cs(priv, slave, 1); - + /* Disable all slaves */ spi_putreg(0, LPC31_SPI_SLVENABLE); - + /* Disable SPI as master */ spi_putreg(SPI_CONFIG_UPDENABLE, LPC31_SPI_CONFIG); @@ -553,18 +553,18 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) { FAR struct lpc31_spidev_s *priv = (FAR struct lpc31_spidev_s *)dev; uint32_t spi_clk, div, div1, div2; - + if (priv->frequency != frequency) { /* The SPI clock is derived from the (main system oscillator / 2), * so compute the best divider from that clock */ - + spi_clk = lpc31_clkfreq(CLKID_SPICLK, DOMAINID_SPI); - + /* Find closest divider to get at or under the target frequency */ - + div = (spi_clk + frequency / 2) / frequency; - + if (div > SPI_MAX_DIVIDER) { div = SPI_MAX_DIVIDER; @@ -573,7 +573,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) { div = SPI_MIN_DIVIDER; } - + div2 = (((div-1) / 512) + 2) * 2; div1 = ((((div + div2 / 2) / div2) - 1)); @@ -619,22 +619,22 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) setbits = 0; clrbits = SPI_SLV_2_SPO|SPI_SLV_2_SPH; break; - + case SPIDEV_MODE1: /* SPO=0; SPH=1 */ setbits = SPI_SLV_2_SPH; clrbits = SPI_SLV_2_SPO; break; - + case SPIDEV_MODE2: /* SPO=1; SPH=0 */ setbits = SPI_SLV_2_SPO; clrbits = SPI_SLV_2_SPH; break; - + case SPIDEV_MODE3: /* SPO=1; SPH=1 */ setbits = SPI_SLV_2_SPO|SPI_SLV_2_SPH; clrbits = 0; break; - + default: return; } @@ -689,7 +689,7 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits) static uint8_t spi_status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) { - /* FIXME: is there anyway to determine this + /* FIXME: is there anyway to determine this * it should probably be board dependant anyway */ return SPI_STATUS_PRESENT; @@ -789,7 +789,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, *dest++ = word; } } - } + } } else { diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_spi.h b/nuttx/arch/arm/src/lpc31xx/lpc31_spi.h index 6d63fe65d..a83734b3f 100644 --- a/nuttx/arch/arm/src/lpc31xx/lpc31_spi.h +++ b/nuttx/arch/arm/src/lpc31xx/lpc31_spi.h @@ -230,13 +230,13 @@ * Interrupt clear status register INTCLRSTATUS, address 0x15002fe8, * Interrupt set status register INTSETSTATUS, address 0x15002fec */ - + #define SPI_INT_SMS (1 << 4) /* Bit 4: Sequential multi-slave mode ready interrupt bit */ #define SPI_INT_TX (1 << 3) /* Bit 3: Transmit threshold level interrupt bit */ #define SPI_INT_RX (1 << 2) /* Bit 3: Receive threshold level interrupt bit */ #define SPI_INT_TO (1 << 1) /* Bit 1: Receive timeout interrupt bit */ #define SPI_INT_OV (1 << 0) /* Bit 0: Receive overrtun interrrupt bit */ - + /************************************************************************************************ * Public Types ************************************************************************************************/ diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_syscreg.h b/nuttx/arch/arm/src/lpc31xx/lpc31_syscreg.h index c14c7267c..72b08c9d9 100644 --- a/nuttx/arch/arm/src/lpc31xx/lpc31_syscreg.h +++ b/nuttx/arch/arm/src/lpc31xx/lpc31_syscreg.h @@ -375,7 +375,7 @@ #define SYSCREG_EBI_TIMEOUT_SHIFT (0) /* Bits 0-9: Time MPMC, NAND or unused channel */ #define SYSCREG_EBI_TIMEOUT_MASK (0x3ff << SYSCREG_EBI_TIMEOUT_SHIFT) - + /* RINGOSCCFG address 0x13002814 */ #define SYSCREG_RINGOSCCFG_OSC1EN (1 << 1) /* Bit 1: Enable ring oscillator 1 */ diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_usbdev.c b/nuttx/arch/arm/src/lpc31xx/lpc31_usbdev.c index bdfca4654..ba1e0c240 100644 --- a/nuttx/arch/arm/src/lpc31xx/lpc31_usbdev.c +++ b/nuttx/arch/arm/src/lpc31xx/lpc31_usbdev.c @@ -635,7 +635,7 @@ static bool lpc31_rqenqueue(FAR struct lpc31_ep_s *privep, FAR struct lpc31_req_s *req) { bool is_empty = !privep->head; - + req->flink = NULL; if (is_empty) { @@ -689,7 +689,7 @@ static void lpc31_queuedtd(uint8_t epphy, struct lpc31_dtd_s *dtd) uint32_t bit = LPC31_ENDPTMASK(epphy); lpc31_setbits (bit, LPC31_USBDEV_ENDPTPRIME); - + while (lpc31_getreg (LPC31_USBDEV_ENDPTPRIME) & bit) ; } @@ -707,7 +707,7 @@ static inline void lpc31_ep0xfer(uint8_t epphy, uint8_t *buf, uint32_t nbytes) struct lpc31_dtd_s *dtd = &g_td[epphy]; lpc31_writedtd(dtd, buf, nbytes); - + lpc31_queuedtd(epphy, dtd); } @@ -730,9 +730,9 @@ static void lpc31_readsetup(uint8_t epphy, struct usb_ctrlreq_s *ctrl) /* copy the request... */ for (i = 0; i < 8; i++) ((uint8_t *) ctrl)[i] = ((uint8_t *) dqh->setup)[i]; - + } while (!(lpc31_getreg(LPC31_USBDEV_USBCMD) & USBDEV_USBCMD_SUTW)); - + /* Clear the trip wire */ lpc31_clrbits(USBDEV_USBCMD_SUTW, LPC31_USBDEV_USBCMD); @@ -753,7 +753,7 @@ static inline void lpc31_set_address(struct lpc31_usbdev_s *priv, uint16_t addre priv->paddr = address; priv->paddrset = address != 0; - lpc31_chgbits(USBDEV_DEVICEADDR_MASK, priv->paddr << USBDEV_DEVICEADDR_SHIFT, + lpc31_chgbits(USBDEV_DEVICEADDR_MASK, priv->paddr << USBDEV_DEVICEADDR_SHIFT, LPC31_USBDEV_DEVICEADDR); } @@ -804,7 +804,7 @@ static int lpc31_progressep(struct lpc31_ep_s *privep) if (privreq->req.len == 0) { - /* If the class driver is responding to a setup packet, then wait for the + /* If the class driver is responding to a setup packet, then wait for the * host to illicit thr response */ if (privep->epphy == LPC31_EP0_IN && privep->dev->ep0state == EP0STATE_SETUP_OUT) @@ -816,7 +816,7 @@ static int lpc31_progressep(struct lpc31_ep_s *privep) else usbtrace(TRACE_DEVERROR(LPC31_TRACEERR_EPOUTNULLPACKET), 0); } - + lpc31_reqcomplete(privep, lpc31_rqdequeue(privep), OK); return OK; } @@ -1013,10 +1013,10 @@ static void lpc31_ep0configure(struct lpc31_usbdev_s *priv) g_qh[LPC31_EP0_IN ].capability = (DQH_CAPABILITY_MAX_PACKET(CONFIG_LPC31_USBDEV_EP0_MAXSIZE) | DQH_CAPABILITY_IOS | DQH_CAPABILITY_ZLT); - + g_qh[LPC31_EP0_OUT].currdesc = DTD_NEXTDESC_INVALID; g_qh[LPC31_EP0_IN ].currdesc = DTD_NEXTDESC_INVALID; - + /* Enable EP0 */ lpc31_setbits (USBDEV_ENDPTCTRL0_RXE | USBDEV_ENDPTCTRL0_TXE, LPC31_USBDEV_ENDPTCTRL0); } @@ -1064,7 +1064,7 @@ static void lpc31_usbreset(struct lpc31_usbdev_s *priv) privep->stalled = false; } - /* Tell the class driver that we are disconnected. The class + /* Tell the class driver that we are disconnected. The class * driver should then accept any new configurations. */ if (priv->driver) @@ -1089,7 +1089,7 @@ static void lpc31_usbreset(struct lpc31_usbdev_s *priv) lpc31_ep0configure(priv); /* Enable Device interrupts */ - lpc31_putreg(USB_FRAME_INT | USB_ERROR_INT | + lpc31_putreg(USB_FRAME_INT | USB_ERROR_INT | USBDEV_USBINTR_NAKE | USBDEV_USBINTR_SLE | USBDEV_USBINTR_URE | USBDEV_USBINTR_PCE | USBDEV_USBINTR_UE, LPC31_USBDEV_USBINTR); } @@ -1105,7 +1105,7 @@ static void lpc31_usbreset(struct lpc31_usbdev_s *priv) static inline void lpc31_ep0state(struct lpc31_usbdev_s *priv, uint16_t state) { priv->ep0state = state; - + switch (state) { case EP0STATE_WAIT_NAK_IN: @@ -1137,7 +1137,7 @@ static inline void lpc31_ep0setup(struct lpc31_usbdev_s *priv) uint16_t index; uint16_t len; - /* Terminate any pending requests - since all DTDs will have been retired + /* Terminate any pending requests - since all DTDs will have been retired * because of the setup packet */ lpc31_cancelrequests(&priv->eplist[LPC31_EP0_OUT], -EPROTO); @@ -1179,7 +1179,7 @@ static inline void lpc31_ep0setup(struct lpc31_usbdev_s *priv) * index: zero interface endpoint * len: 2; data = status */ - + usbtrace(TRACE_INTDECODE(LPC31_TRACEINTID_GETSTATUS), 0); if (!priv->paddrset || len != 2 || (ctrl.type & USB_REQ_DIR_IN) == 0 || value != 0) @@ -1206,21 +1206,21 @@ static inline void lpc31_ep0setup(struct lpc31_usbdev_s *priv) else priv->ep0buf[0] = 0; /* Not stalled */ priv->ep0buf[1] = 0; - + lpc31_ep0xfer (LPC31_EP0_IN, priv->ep0buf, 2); lpc31_ep0state (priv, EP0STATE_SHORTWRITE); } } break; - + case USB_REQ_RECIPIENT_DEVICE: { if (index == 0) { usbtrace(TRACE_INTDECODE(LPC31_TRACEINTID_DEVGETSTATUS), 0); - + /* Features: Remote Wakeup=YES; selfpowered=? */ - + priv->ep0buf[0] = (priv->selfpowered << USB_FEATURE_SELFPOWERED) | (1 << USB_FEATURE_REMOTEWAKEUP); priv->ep0buf[1] = 0; @@ -1235,7 +1235,7 @@ static inline void lpc31_ep0setup(struct lpc31_usbdev_s *priv) } } break; - + case USB_REQ_RECIPIENT_INTERFACE: { usbtrace(TRACE_INTDECODE(LPC31_TRACEINTID_IFGETSTATUS), 0); @@ -1246,7 +1246,7 @@ static inline void lpc31_ep0setup(struct lpc31_usbdev_s *priv) lpc31_ep0state (priv, EP0STATE_SHORTWRITE); } break; - + default: { usbtrace(TRACE_DEVERROR(LPC31_TRACEERR_BADGETSTATUS), 0); @@ -1257,7 +1257,7 @@ static inline void lpc31_ep0setup(struct lpc31_usbdev_s *priv) } } break; - + case USB_REQ_CLEARFEATURE: { /* type: host-to-device; recipient = device, interface or endpoint @@ -1265,7 +1265,7 @@ static inline void lpc31_ep0setup(struct lpc31_usbdev_s *priv) * index: zero interface endpoint; * len: zero, data = none */ - + usbtrace(TRACE_INTDECODE(LPC31_TRACEINTID_CLEARFEATURE), 0); if ((ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT) { @@ -1284,7 +1284,7 @@ static inline void lpc31_ep0setup(struct lpc31_usbdev_s *priv) } } break; - + case USB_REQ_SETFEATURE: { /* type: host-to-device; recipient = device, interface, endpoint @@ -1292,7 +1292,7 @@ static inline void lpc31_ep0setup(struct lpc31_usbdev_s *priv) * index: zero interface endpoint; * len: 0; data = none */ - + usbtrace(TRACE_INTDECODE(LPC31_TRACEINTID_SETFEATURE), 0); if (((ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) && value == USB_FEATURE_TESTMODE) @@ -1316,7 +1316,7 @@ static inline void lpc31_ep0setup(struct lpc31_usbdev_s *priv) } } break; - + case USB_REQ_SETADDRESS: { /* type: host-to-device; recipient = device @@ -1330,7 +1330,7 @@ static inline void lpc31_ep0setup(struct lpc31_usbdev_s *priv) { /* Save the address. We cannot actually change to the next address until * the completion of the status phase. */ - + priv->paddr = ctrl.value[0]; priv->paddrset = false; lpc31_ep0state (priv, EP0STATE_WAIT_NAK_IN); @@ -1342,7 +1342,7 @@ static inline void lpc31_ep0setup(struct lpc31_usbdev_s *priv) } } break; - + case USB_REQ_GETDESCRIPTOR: /* type: device-to-host; recipient = device * value: descriptor type and index @@ -1368,7 +1368,7 @@ static inline void lpc31_ep0setup(struct lpc31_usbdev_s *priv) } } break; - + case USB_REQ_GETCONFIGURATION: /* type: device-to-host; recipient = device * value: 0; @@ -1389,7 +1389,7 @@ static inline void lpc31_ep0setup(struct lpc31_usbdev_s *priv) } } break; - + case USB_REQ_SETCONFIGURATION: /* type: host-to-device; recipient = device * value: configuration value @@ -1410,7 +1410,7 @@ static inline void lpc31_ep0setup(struct lpc31_usbdev_s *priv) } } break; - + case USB_REQ_GETINTERFACE: /* type: device-to-host; recipient = interface * value: 0 @@ -1428,7 +1428,7 @@ static inline void lpc31_ep0setup(struct lpc31_usbdev_s *priv) lpc31_dispatchrequest(priv, &ctrl); } break; - + case USB_REQ_SYNCHFRAME: /* type: device-to-host; recipient = endpoint * value: 0 @@ -1439,7 +1439,7 @@ static inline void lpc31_ep0setup(struct lpc31_usbdev_s *priv) usbtrace(TRACE_INTDECODE(LPC31_TRACEINTID_SYNCHFRAME), 0); } break; - + default: { usbtrace(TRACE_DEVERROR(LPC31_TRACEERR_INVALIDCTRLREQ), 0); @@ -1470,7 +1470,7 @@ static void lpc31_ep0complete(struct lpc31_usbdev_s *priv, uint8_t epphy) struct lpc31_ep_s *privep = &priv->eplist[epphy]; usbtrace(TRACE_INTDECODE(LPC31_TRACEINTID_EP0COMPLETE), (uint16_t)priv->ep0state); - + switch (priv->ep0state) { case EP0STATE_DATA_IN: @@ -1484,15 +1484,15 @@ static void lpc31_ep0complete(struct lpc31_usbdev_s *priv, uint8_t epphy) case EP0STATE_DATA_OUT: if (lpc31_rqempty(privep)) return; - + if (lpc31_epcomplete (priv, epphy)) lpc31_ep0state (priv, EP0STATE_WAIT_NAK_IN); break; - + case EP0STATE_SHORTWRITE: lpc31_ep0state (priv, EP0STATE_WAIT_NAK_OUT); break; - + case EP0STATE_WAIT_STATUS_IN: lpc31_ep0state (priv, EP0STATE_IDLE); @@ -1591,9 +1591,9 @@ bool lpc31_epcomplete(struct lpc31_usbdev_s *priv, uint8_t epphy) usbtrace(TRACE_INTDECODE(LPC31_TRACEINTID_EPOUTQEMPTY), 0); return true; } - + int xfrd = dtd->xfer_len - (dtd->config >> 16); - + privreq->req.xfrd += xfrd; bool complete = true; @@ -1620,7 +1620,7 @@ bool lpc31_epcomplete(struct lpc31_usbdev_s *priv, uint8_t epphy) { privreq = lpc31_rqdequeue (privep); } - + if (!lpc31_rqempty(privep)) { lpc31_progressep(privep); @@ -1671,7 +1671,7 @@ static int lpc31_usbinterrupt(int irq, FAR void *context) /* When the device controller enters a suspend state from an active state, * the SLI bit will be set to a one. */ - + if (!priv->suspended && (disr & USBDEV_USBSTS_SLI) != 0) { usbtrace(TRACE_INTDECODE(LPC31_TRACEINTID_SUSPENDED),0); @@ -1718,30 +1718,30 @@ static int lpc31_usbinterrupt(int irq, FAR void *context) if (portsc1 & USBDEV_PRTSC1_FPR) { /* FIXME: this occurs because of a J-to-K transition detected - * while the port is in SUSPEND state - presumambly this + * while the port is in SUSPEND state - presumambly this * is where the host is resuming the device? * * - but do we need to "ack" the interrupt */ } } - + #ifdef CONFIG_LPC31_USBDEV_FRAME_INTERRUPT if (disr & USBDEV_USBSTT_SRI) { usbtrace(TRACE_INTDECODE(LPC31_TRACEINTID_FRAME), 0); - - priv->sof = (int)lpc31_getreg(LPC31_USBDEV_FRINDEX_OFFSET); + + priv->sof = (int)lpc31_getreg(LPC31_USBDEV_FRINDEX_OFFSET); } #endif if (disr & USBDEV_USBSTS_UEI) { /* FIXME: these occur when a transfer results in an error condition - * it is set alongside USBINT if the DTD also had its IOC + * it is set alongside USBINT if the DTD also had its IOC * bit set. */ } - + if (disr & USBDEV_USBSTS_UI) { /* Handle completion interrupts */ @@ -1752,12 +1752,12 @@ static int lpc31_usbinterrupt(int irq, FAR void *context) /* Clear any NAK interrupt and completion interrupts */ lpc31_putreg (mask, LPC31_USBDEV_ENDPTNAK); lpc31_putreg (mask, LPC31_USBDEV_ENDPTCOMPLETE); - + if (mask & LPC31_ENDPTMASK(0)) lpc31_ep0complete(priv, 0); if (mask & LPC31_ENDPTMASK(1)) lpc31_ep0complete(priv, 1); - + for (n = 1; n < LPC31_NLOGENDPOINTS; n++) { if (mask & LPC31_ENDPTMASK((n<<1))) @@ -1772,9 +1772,9 @@ static int lpc31_usbinterrupt(int irq, FAR void *context) if (setupstat) { /* Clear the endpoint complete CTRL OUT and IN when a Setup is received */ - lpc31_putreg(LPC31_ENDPTMASK(LPC31_EP0_IN) | LPC31_ENDPTMASK(LPC31_EP0_OUT), + lpc31_putreg(LPC31_ENDPTMASK(LPC31_EP0_IN) | LPC31_ENDPTMASK(LPC31_EP0_OUT), LPC31_USBDEV_ENDPTCOMPLETE); - + if (setupstat & LPC31_ENDPTMASK(LPC31_EP0_OUT)) { usbtrace(TRACE_INTDECODE(LPC31_TRACEINTID_EP0SETUP), setupstat); @@ -1832,7 +1832,7 @@ static int lpc31_epconfigure(FAR struct usbdev_ep_s *ep, DEBUGASSERT(desc->addr == ep->eplog); /* Initialise EP capabilities */ - + uint16_t maxsize = GETUINT16(desc->mxpacketsize); if ((desc->attr & USB_EP_ATTR_XFERTYPE_MASK) == USB_EP_ATTR_XFER_ISOC) { @@ -1886,7 +1886,7 @@ static int lpc31_epconfigure(FAR struct usbdev_ep_s *ep, lpc31_setbits (USBDEV_ENDPTCTRL_TXE, LPC31_USBDEV_ENDPTCTRL(privep->epphy)); else lpc31_setbits (USBDEV_ENDPTCTRL_RXE, LPC31_USBDEV_ENDPTCTRL(privep->epphy)); - + return OK; } @@ -2076,7 +2076,7 @@ static int lpc31_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r { ret = -EBUSY; } - else + else { /* Add the new request to the request queue for the endpoint */ @@ -2121,7 +2121,7 @@ static int lpc31_epcancel(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r priv = privep->dev; flags = irqsave(); - + /* FIXME: if the request is the first, then we need to flush the EP * otherwise just remove it from the list * @@ -2379,7 +2379,7 @@ static int lpc31_wakeup(struct usbdev_s *dev) * Name: lpc31_selfpowered * * Description: - * Sets/clears the device selfpowered feature + * Sets/clears the device selfpowered feature * *******************************************************************************/ @@ -2449,7 +2449,7 @@ void up_usbinitialize(void) usbtrace(TRACE_DEVINIT, 0); /* Disable USB interrupts */ - + lpc31_putreg(0, LPC31_USBDEV_USBINTR); /* Initialize the device state structure */ @@ -2519,7 +2519,7 @@ void up_usbinitialize(void) /* Enable USB OTG PLL and wait for lock */ lpc31_putreg (0, LPC31_SYSCREG_USB_ATXPLLPDREG); - + uint32_t bank = EVNTRTR_BANK(EVENTRTR_USBATXPLLLOCK); uint32_t bit = EVNTRTR_BIT(EVENTRTR_USBATXPLLLOCK); @@ -2655,7 +2655,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) up_enable_irq(LPC31_IRQ_USBOTG); /* FIXME: nothing seems to call DEV_CONNECT(), but we need to set - * the RS bit to enable the controller. It kind of makes sense + * the RS bit to enable the controller. It kind of makes sense * to do this after the class has bound to us... * GEN: This bug is really in the class driver. It should make the * soft connect when it is ready to be enumerated. I have added diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_usbotg.h b/nuttx/arch/arm/src/lpc31xx/lpc31_usbotg.h index 28a7fe7ee..c8e7c25fb 100644 --- a/nuttx/arch/arm/src/lpc31xx/lpc31_usbotg.h +++ b/nuttx/arch/arm/src/lpc31xx/lpc31_usbotg.h @@ -381,12 +381,12 @@ #define USBDEV_BURSTSIZE_TXPBURST_SHIFT (8) /* Bits 8-15: Programmable TX burst length */ #define USBDEV_BURSTSIZE_TXPBURST_MASK (255 << USBDEV_BURSTSIZE_TXPBURST_SHIFT) #define USBDEV_BURSTSIZE_RXPBURST_SHIFT (0) /* Bits 0-7: RXPBURST Programmable RX burst length */ -#define USBDEV_BURSTSIZE_RXPBURST_MASK (255 << USBDEV_BURSTSIZE_RXPBURST_SHIFT) +#define USBDEV_BURSTSIZE_RXPBURST_MASK (255 << USBDEV_BURSTSIZE_RXPBURST_SHIFT) #define USBHOST_BURSTSIZE_TXPBURST_SHIFT (8) /* Bits 8-15: Programmable TX burst length */ #define USBHOST_BURSTSIZE_TXPBURST_MASK (255 << USBHOST_BURSTSIZE_TXPBURST_SHIFT) #define USBHOST_BURSTSIZE_RXPBURST_SHIFT (0) /* Bits 0-7: RXPBURST Programmable RX burst length */ -#define USBHOST_BURSTSIZE_RXPBURST_MASK (255 << USBHOST_BURSTSIZE_RXPBURST_SHIFT) +#define USBHOST_BURSTSIZE_RXPBURST_MASK (255 << USBHOST_BURSTSIZE_RXPBURST_SHIFT) /* USB Transfer buffer Fill Tuning register TXFIFOFILLTUNING (address 0x19000164) -- Host Mode */ diff --git a/nuttx/arch/arm/src/lpc43xx/Make.defs b/nuttx/arch/arm/src/lpc43xx/Make.defs index e2d5ea0b1..366c051df 100644 --- a/nuttx/arch/arm/src/lpc43xx/Make.defs +++ b/nuttx/arch/arm/src/lpc43xx/Make.defs @@ -82,7 +82,7 @@ CMN_CSRCS += up_copyarmstate.c endif endif -CHIP_ASRCS = +CHIP_ASRCS = CHIP_CSRCS = lpc43_allocateheap.c lpc43_cgu.c lpc43_clrpend.c lpc43_gpio.c CHIP_CSRCS += lpc43_irq.c lpc43_pinconfig.c lpc43_rgu.c lpc43_serial.c CHIP_CSRCS += lpc43_start.c lpc43_timerisr.c lpc43_uart.c diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_aes.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_aes.h index 74e53d616..e5f66d5f1 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_aes.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_aes.h @@ -58,9 +58,9 @@ enum lpc43_aescmd_e { AES_API_CMD_ENCODE_ECB = 0, - AES_API_CMD_DECODE_ECB = 1, - AES_API_CMD_ENCODE_CBC = 2, - AES_API_CMD_DECODE_CBC = 3 + AES_API_CMD_DECODE_ECB = 1, + AES_API_CMD_ENCODE_CBC = 2, + AES_API_CMD_DECODE_CBC = 3 }; struct lpc43_aes_s @@ -89,7 +89,7 @@ struct lpc43_aes_s void (*aes_LoadKeySW)(unsigned char *key); /* Loads 128-bit AES initialization vector (16 bytes) */ - + void (*aes_LoadIV_SW)(unsigned char *iv); /* Loads 128-bit AES IC specific initialization vector, which is used to decrypt diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_ethernet.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_ethernet.h index e7d16fe26..275f896ad 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_ethernet.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_ethernet.h @@ -606,7 +606,7 @@ /* Ethernet TX DMA Descriptor. Descriptor size can be 4 DWORDS (16 bytes) or 8 DWORDS (32 bytes) * depending on the setting of the ATDS bit in the DMA Bus Mode register. - */ + */ struct eth_txdesc_s { @@ -629,7 +629,7 @@ struct eth_txdesc_s /* Ethernet RX DMA Descriptor. Descriptor size can be 4 DWORDS (16 bytes) or 8 DWORDS (32 bytes) * depending on the setting of the ATDS bit in the DMA Bus Mode register. - */ + */ struct eth_rxdesc_s { diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_evntrtr.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_evntrtr.h index 644e6758e..1287dfd87 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_evntrtr.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_evntrtr.h @@ -90,7 +90,7 @@ #define EVNTRTR_SOURCE_TIM6 14 /* Combined timer output 6 (SCT output 6 | TIMER1 Ch2) */ #define EVNTRTR_SOURCE_QEI 15 /* QEI interrupt */ #define EVNTRTR_SOURCE_TIM14 16 /* Combined timer output 14 (SCT output 14 | TIMER3 Ch2) */ - /* 17-18: Reserved */ + /* 17-18: Reserved */ #define EVNTRTR_SOURCE_RESET 19 /* Reset event */ #define EVNTRTR_WAKEUP0 (1 << EVNTRTR_SOURCE_WAKEUP0) diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gpdma.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gpdma.h index f885c1387..2139e0976 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gpdma.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gpdma.h @@ -252,7 +252,6 @@ #define GPDMA_SOFTLBREQ(n) (1 << (n)) /* Bits 0-15: Software last burst request flags for source n */ /* Bits 16-31: Reserved */ - /* DMA Software Last Single Request Register */ #define GPDMA_SOFTLSREQ(n) (1 << (n)) /* Bits 0-15: Software last single burst request flags for source n */ diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_mcpwm.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_mcpwm.h index 6344c24c9..720b8affc 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_mcpwm.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_mcpwm.h @@ -257,7 +257,7 @@ #define MCPWM_CAPCLR_CLR0 (1 << 0) /* Bit 0: Clear CAP0 register */ #define MCPWM_CAPCLR_CLR1 (1 << 1) /* Bit 1: Clear CAP1 register */ #define MCPWM_CAPCLR_CLR2 (1 << 2) /* Bit 2: Clear CAP2 register */ - /* Bits 2-31: Reserved */ + /* Bits 2-31: Reserved */ /************************************************************************************ * Public Types diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_otp.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_otp.h index 67b5af319..45a777fd9 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_otp.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_otp.h @@ -59,7 +59,7 @@ #define LPC43_OTP_MEM20_OFFSET 0x0034 /* General purpose OTP memory 2, word 0 */ #define LPC43_OTP_MEM21_OFFSET 0x0038 /* General purpose OTP memory 2, word 1 */ -#define LPC43_OTP_MEM22_OFFSET 0x003c /* General purpose OTP memory 2, word 2 */ +#define LPC43_OTP_MEM22_OFFSET 0x003c /* General purpose OTP memory 2, word 2 */ #define LPC43_OTP_AES00_OFFSET 0x0010 /* AES key 0, word 0 */ #define LPC43_OTP_AES01_OFFSET 0x0014 /* AES key 0, word 1 */ diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_spifi.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_spifi.h index a0bec7592..26cf82734 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_spifi.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_spifi.h @@ -88,7 +88,7 @@ #define SPIFI_PROG_INST 2 #define SPIFI_CHIP_ERASE 3 -/* Bit definitions in options operands (MODE3, RCVCLK, and FULLCLK +/* Bit definitions in options operands (MODE3, RCVCLK, and FULLCLK * have the same relationship as in the Control register) */ @@ -117,7 +117,7 @@ /* SPI ROM driver table pointer */ -#define SPIFI_ROM_PTR LPC43_ROM_DRIVER_TABLE6 +#define SPIFI_ROM_PTR LPC43_ROM_DRIVER_TABLE6 #define pSPIFI *((struct spifi_driver_s **)SPIFI_ROM_PTR) /**************************************************************************** diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_usb0.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_usb0.h index 6d18dd41c..42ef4ba8d 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_usb0.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_usb0.h @@ -147,25 +147,25 @@ /* Device side naming of common register offsets */ -#define LPC43_USBDEV_USBCMD LPC43_USBOTG_USBCMD -#define LPC43_USBDEV_USBSTS LPC43_USBOTG_USBSTS -#define LPC43_USBDEV_USBINTR LPC43_USBOTG_USBINTR -#define LPC43_USBDEV_FRINDEX LPC43_USBOTG_FRINDEX -#define LPC43_USBDEV_BURSTSIZE LPC43_USBOTG_BURSTSIZE -#define LPC43_USBDEV_BINTERVAL LPC43_USBOTG_BINTERVAL -#define LPC43_USBDEV_PORTSC1 LPC43_USBOTG_USBMODE -#define LPC43_USBDEV_USBMODE LPC43_USBOTG_USBMODE +#define LPC43_USBDEV_USBCMD LPC43_USBOTG_USBCMD +#define LPC43_USBDEV_USBSTS LPC43_USBOTG_USBSTS +#define LPC43_USBDEV_USBINTR LPC43_USBOTG_USBINTR +#define LPC43_USBDEV_FRINDEX LPC43_USBOTG_FRINDEX +#define LPC43_USBDEV_BURSTSIZE LPC43_USBOTG_BURSTSIZE +#define LPC43_USBDEV_BINTERVAL LPC43_USBOTG_BINTERVAL +#define LPC43_USBDEV_PORTSC1 LPC43_USBOTG_USBMODE +#define LPC43_USBDEV_USBMODE LPC43_USBOTG_USBMODE /* Host side naming of common registers */ -#define LPC43_USBHOST_USBCMD LPC43_USBOTG_USBCMD -#define LPC43_USBHOST_USBSTS LPC43_USBOTG_USBSTS -#define LPC43_USBHOST_USBINTR LPC43_USBOTG_USBINTR -#define LPC43_USBHOST_FRINDEX LPC43_USBOTG_FRINDEX -#define LPC43_USBHOST_BURSTSIZE LPC43_USBOTG_BURSTSIZE -#define LPC43_USBHOST_BINTERVAL LPC43_USBOTG_BINTERVAL -#define LPC43_USBHOST_PORTSC1 LPC43_USBOTG_USBMODE -#define LPC43_USBHOST_USBMODE LPC43_USBOTG_USBMODE +#define LPC43_USBHOST_USBCMD LPC43_USBOTG_USBCMD +#define LPC43_USBHOST_USBSTS LPC43_USBOTG_USBSTS +#define LPC43_USBHOST_USBINTR LPC43_USBOTG_USBINTR +#define LPC43_USBHOST_FRINDEX LPC43_USBOTG_FRINDEX +#define LPC43_USBHOST_BURSTSIZE LPC43_USBOTG_BURSTSIZE +#define LPC43_USBHOST_BINTERVAL LPC43_USBOTG_BINTERVAL +#define LPC43_USBHOST_PORTSC1 LPC43_USBOTG_USBMODE +#define LPC43_USBHOST_USBMODE LPC43_USBOTG_USBMODE /* Device endpoint registers */ @@ -381,13 +381,13 @@ /* USB burst size register BURSTSIZE -- Device/Host Mode */ #define USBHOST_BURSTSIZE_RXPBURST_SHIFT (0) /* Bits 0-7: RXPBURST Programmable RX burst length */ -#define USBHOST_BURSTSIZE_RXPBURST_MASK (255 << USBHOST_BURSTSIZE_RXPBURST_SHIFT) +#define USBHOST_BURSTSIZE_RXPBURST_MASK (255 << USBHOST_BURSTSIZE_RXPBURST_SHIFT) #define USBHOST_BURSTSIZE_TXPBURST_SHIFT (8) /* Bits 8-15: Programmable TX burst length */ #define USBHOST_BURSTSIZE_TXPBURST_MASK (255 << USBHOST_BURSTSIZE_TXPBURST_SHIFT) /* Bits 16-31: Reserved */ #define USBDEV_BURSTSIZE_RXPBURST_SHIFT (0) /* Bits 0-7: RXPBURST Programmable RX burst length */ -#define USBDEV_BURSTSIZE_RXPBURST_MASK (255 << USBDEV_BURSTSIZE_RXPBURST_SHIFT) +#define USBDEV_BURSTSIZE_RXPBURST_MASK (255 << USBDEV_BURSTSIZE_RXPBURST_SHIFT) #define USBDEV_BURSTSIZE_TXPBURST_SHIFT (8) /* Bits 8-15: Programmable TX burst length */ #define USBDEV_BURSTSIZE_TXPBURST_MASK (255 << USBDEV_BURSTSIZE_TXPBURST_SHIFT) /* Bits 16-31: Reserved */ diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_adc.c b/nuttx/arch/arm/src/lpc43xx/lpc43_adc.c index d03abb162..71f1181e6 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_adc.c +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_adc.c @@ -9,7 +9,7 @@ * Copyright (C) 2011 Li Zhuoyi. All rights reserved. * Author: Li Zhuoyi <lzyy.cn@gmail.com> * History: 0.1 2011-08-05 initial version - * + * * This file is a part of NuttX: * * Copyright (C) 2010-2012 Gregory Nutt. All rights reserved. @@ -181,7 +181,7 @@ static void adc_reset(FAR struct adc_dev_s *dev) lpc43_configgpio(GPIO_AD0p6); else if (priv->mask&0x80) lpc43_configgpio(GPIO_AD0p7); - + irqrestore(flags); } @@ -244,7 +244,7 @@ static int adc_interrupt(int irq, void *context) FAR struct up_dev_s *priv = (FAR struct up_dev_s *)g_adcdev.ad_priv; unsigned char ch; int32_t value; - + regval = getreg32(LPC43_ADC_GDR); ch = (regval >> 24) & 0x07; priv->buf[ch] += regval & 0xfff0; diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_allocateheap.c b/nuttx/arch/arm/src/lpc43xx/lpc43_allocateheap.c index d5d12aa54..0dd84e1ae 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_allocateheap.c +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_allocateheap.c @@ -266,7 +266,7 @@ void up_addregion(void) { #if CONFIG_MM_REGIONS > 1 /* Add the next SRAM region (which should exist) */ - + kmm_addregion((FAR void*)MM_REGION2_BASE, MM_REGION2_SIZE); #ifdef MM_REGION3_BASE @@ -274,12 +274,12 @@ void up_addregion(void) #if CONFIG_MM_REGIONS > 2 /* Add the third SRAM region (which may not exist) */ - + kmm_addregion((FAR void*)MM_REGION3_BASE, MM_REGION3_SIZE); #if CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE) /* Add the DMA region (which may not be available) */ - + kmm_addregion((FAR void*)MM_DMAHEAP_BASE, MM_DMAHEAP_SIZE); #endif /* CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE) */ @@ -288,7 +288,7 @@ void up_addregion(void) #if CONFIG_MM_REGIONS > 2 && defined(MM_DMAHEAP_BASE) /* Add the DMA region (which may not be available) */ - + kmm_addregion((FAR void*)MM_DMAHEAP_BASE, MM_DMAHEAP_SIZE); #endif /* CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE) */ diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_cgu.c b/nuttx/arch/arm/src/lpc43xx/lpc43_cgu.c index 61c4112ae..dcb446648 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_cgu.c +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_cgu.c @@ -350,7 +350,7 @@ static inline void lpc43_pll1config(uint32_t ctrlvalue) regval &= ~(PLL1_CTRL_BYPASS | PLL1_CTRL_FBSEL | PLL1_CTRL_DIRECT | PLL1_CTRL_PSEL_MASK | PLL1_CTRL_NSEL_MASK | PLL1_CTRL_MSEL_MASK); - + /* Set selected PLL1 controls: * * - PLL1_CTRL_FBSEL: Set in both integer and direct modes @@ -380,7 +380,7 @@ static inline void lpc43_pll1enable(void) /* Take PLL1 out of power down mode. The reset state of the PD bit * is one, i.e., powered down. */ - + regval = getreg32(LPC43_PLL1_CTRL); regval &= ~PLL1_CTRL_PD; putreg32(regval, LPC43_PLL1_CTRL); @@ -441,7 +441,7 @@ void lpc43_clockconfig(void) /* Enable PLL1 */ lpc43_pll1enable(); - + /* Set up PLL1 output as the M4 clock */ lpc43_m4clkselect(BASE_M4_CLKSEL_PLL1); @@ -477,6 +477,6 @@ void lpc43_clockconfig(void) /* Go to the final, full-speed PLL1 configuration */ - lpc43_pll1config(PLL_CONTROLS); + lpc43_pll1config(PLL_CONTROLS); #endif } diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_dac.c b/nuttx/arch/arm/src/lpc43xx/lpc43_dac.c index 5fcceaa1e..ba102c185 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_dac.c +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_dac.c @@ -9,7 +9,7 @@ * Copyright (C) 2011 Li Zhuoyi. All rights reserved. * Author: Li Zhuoyi <lzyy.cn@gmail.com> * History: 0.1 2011-08-05 initial version - * + * * This file is a part of NuttX: * * Copyright (C) 2010-2012 Gregory Nutt. All rights reserved. @@ -121,7 +121,7 @@ static void dac_reset(FAR struct dac_dev_s *dev) { irqstate_t flags; uint32_t regval; - + flags = irqsave(); regval = getreg32(LPC43_SYSCON_PCLKSEL0); diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_gpio.c b/nuttx/arch/arm/src/lpc43xx/lpc43_gpio.c index 2b2c88f31..aaa18eccd 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_gpio.c +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_gpio.c @@ -92,7 +92,7 @@ static inline void lpc43_configinput(uint16_t gpiocfg, regval = getreg32(regaddr); regval &= ~GPIO_DIR(pin); putreg32(regval, regaddr); - + /* To be able to read the signal on the GPIO input, the input * buffer must be enabled in the syscon block for the corresponding pin. * This should have been done when the pin was configured as a GPIO. @@ -147,7 +147,7 @@ static inline void lpc43_configoutput(uint16_t gpiocfg, * * Description: * Configure a GPIO based on bit-encoded description of the pin. NOTE: - * The pin *must* have first been configured for GPIO usage with a + * The pin *must* have first been configured for GPIO usage with a * corresponding call to lpc43_pin_config(). * * Returned Value: diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_idle.c b/nuttx/arch/arm/src/lpc43xx/lpc43_idle.c index e7be94e51..55631bc35 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_idle.c +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_idle.c @@ -86,7 +86,7 @@ static void up_idlepm(void) enum pm_state_e newstate; irqstate_t flags; int ret; - + /* Decide, which power saving level can be obtained */ newstate = pm_checkstate(); diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.c b/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.c index fb5173339..77b979607 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.c +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.c @@ -120,7 +120,7 @@ int lpc43_pin_config(uint32_t pinconf) { regval |= SCU_NDPIN_EHS; /* 0=slow; 1=fast */ } - + /* Only high drive pins suppose drive strength */ switch (pinconf & PINCONF_DRIVE_MASK) diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.h b/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.h index 293f838e9..fba0e1e49 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.h +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.h @@ -183,7 +183,7 @@ * ---- ---- ---- ---- ---- * .... .... .... ...P PPPP */ - + #define PINCONF_PIN_SHIFT (0) /* Bits 0-4: Pin number */ #define PINCONF_PIN_MASK (31 << PINCONF_PIN_SHIFT) # define PINCONF_PIN_0 (0 << PINCONF_PIN_SHIFT) diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_serial.c b/nuttx/arch/arm/src/lpc43xx/lpc43_serial.c index a4d60dc15..df68c1301 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_serial.c +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_serial.c @@ -617,7 +617,7 @@ static int up_setup(struct uart_dev_s *dev) (UART_FCR_RXTRIGGER_8|UART_FCR_TXRST|UART_FCR_RXRST|UART_FCR_FIFOEN)); /* Enable Auto-RTS and Auto-CS Flow Control in the Modem Control Register */ - + #ifdef CONFIG_UART1_FLOWCONTROL if (priv->id == 1) { @@ -896,7 +896,7 @@ static int up_interrupt(int irq, void *context) * de-asserted (driven HIGH) once the last bit of data has been transmitted. * * RS485/EIA-485 driver delay time -- Supported - * + * * The driver delay time is the delay between the last stop bit leaving * the TXFIFO and the de-assertion of the DIR pin. This delay time can be * programmed in the 8-bit RS485DLY register. The delay time is in periods @@ -931,21 +931,21 @@ static inline int up_set_rs485_mode(struct up_dev_s *priv, else { /* Set the RS-485/EIA-485 Control register: - * + * * NMMEN 0 = Normal Multidrop Mode (NMM) disabled * RXDIS 0 = Receiver is not disabled * AADEN 0 = Auto Address Detect (ADD) is disabled * DCTRL 1 = Auto Direction Control is enabled - * OINV ? = Value control by user mode settings + * OINV ? = Value control by user mode settings */ regval = UART_RS485CTRL_DCTRL; /* Logic levels are controlled by the SER_RS485_RTS_ON_SEND and - * SER_RS485_RTS_AFTER_SEND bits in the mode flags. + * SER_RS485_RTS_AFTER_SEND bits in the mode flags. * SER_RS485_RTS_AFTER_SEND is ignored. * - * By default, DIR will go logic low on send, but this can + * By default, DIR will go logic low on send, but this can * be inverted. */ diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_spi.c b/nuttx/arch/arm/src/lpc43xx/lpc43_spi.c index 1058c85c9..6f51f1272 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_spi.c +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_spi.c @@ -161,7 +161,7 @@ static const struct spi_ops_s g_spiops = static struct lpc43_spidev_s g_spidev = { .spidev = { &g_spiops }, -}; +}; /**************************************************************************** * Public Data @@ -269,7 +269,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) divisor = (divisor + 1) & ~1; /* Save the new divisor value */ - + putreg32(divisor, LPC43_SPI_CCR); /* Calculate the new actual */ @@ -322,19 +322,19 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) { case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */ break; - + case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */ regval |= SPI_CR_CPHA; break; - + case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */ regval |= SPI_CR_CPOL; break; - + case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ regval |= (SPI_CR_CPOL|SPI_CR_CPHA); break; - + default: DEBUGASSERT(FALSE); return; @@ -517,7 +517,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw (void)getreg32(LPC43_SPI_SR); - /* Read the received data from the SPI Data Register */ + /* Read the received data from the SPI Data Register */ *ptr++ = (uint8_t)getreg32(LPC43_SPI_DR); nwords--; @@ -575,7 +575,7 @@ FAR struct spi_dev_s *lpc43_spiinitialize(int port) regval |= SYSCON_PCONP_PCSPI; putreg32(regval, LPC43_SYSCON_PCONP); irqrestore(flags); - + /* Configure 8-bit SPI mode and master mode */ putreg32(SPI_CR_BITS_8BITS|SPI_CR_BITENABLE|SPI_CR_MSTR, LPC43_SPI_CR); diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_spifi.c b/nuttx/arch/arm/src/lpc43xx/lpc43_spifi.c index f7a7e41b7..fcaae5ea8 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_spifi.c +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_spifi.c @@ -241,7 +241,7 @@ * Compute this from the SPIFI clock period and the minimum high time of CS * from the serial flash data sheet: * - * csHigh = ceiling( min CS high / SPIFI clock period ) - 1 + * csHigh = ceiling( min CS high / SPIFI clock period ) - 1 * * where ceiling means round up to the next higher integer if the argument * isn’t an integer. @@ -381,7 +381,7 @@ static void lpc43_blockerase(struct lpc43_dev_s *priv, off_t sector) priv->operands.dest = SPIFI_BASE + (sector << SPIFI_BLKSHIFT); priv->operands.length = SPIFI_BLKSIZE; - fvdbg("SPIFI_ERASE: dest=%p length=%d\n", + fvdbg("SPIFI_ERASE: dest=%p length=%d\n", priv->operands.dest, priv->operands.length); result = SPIFI_ERASE(priv, &priv->rom, &priv->operands); @@ -456,7 +456,7 @@ static int lpc43_pagewrite(FAR struct lpc43_dev_s *priv, FAR uint8_t *dest, priv->operands.dest = dest; priv->operands.length = nbytes; - fvdbg("SPIFI_PROGRAM: src=%p dest=%p length=%d\n", + fvdbg("SPIFI_PROGRAM: src=%p dest=%p length=%d\n", src, priv->operands.dest, priv->operands.length); result = SPIFI_PROGRAM(priv, &priv->rom, src, &priv->operands); @@ -543,7 +543,7 @@ static FAR uint8_t *lpc43_cacheread(struct lpc43_dev_s *priv, off_t sector) FAR const uint8_t *src; off_t blkno; int index; - + /* Convert from the 512 byte sector to the erase sector size of the device. For * exmample, if the actual erase sector size if 4Kb (1 << 12), then we first * shift to the right by 3 to get the sector number in 4096 increments. @@ -881,7 +881,7 @@ static int lpc43_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg) ret = lpc43_chiperase(priv); } break; - + case MTDIOC_XIPBASE: default: ret = -ENOTTY; /* Bad command */ @@ -1156,7 +1156,7 @@ FAR struct mtd_dev_s *lpc43_spifi_initialize(void) priv->operands.protect = -1; /* Save and restore protection */ priv->operands.options = S_CALLER_ERASE; /* This driver will do erasure */ - + /* Initialize the SPIFI. Interrupts must be disabled here because shared * CGU registers will be modified. */ @@ -1230,7 +1230,7 @@ void pullMISO(int high) /* Control MISO pull-up/down state Assume pull down by clearing: * - * EPD = Enable pull-down connect (bit + * EPD = Enable pull-down connect (bit */ pinconfig = PINCONF_SPIFI_MISO & ~(PINCONF_PULLUP | PINCONF_PULLDOWN); diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_ssp.c b/nuttx/arch/arm/src/lpc43xx/lpc43_ssp.c index a7efe8471..5edc03c06 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_ssp.c +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_ssp.c @@ -66,7 +66,7 @@ ****************************************************************************/ /* The following enable debug output from this file (needs CONFIG_DEBUG too). - * + * * CONFIG_SSP_DEBUG - Define to enable basic SSP debug * CONFIG_SSP_VERBOSE - Define to enable verbose SSP debug */ @@ -192,7 +192,7 @@ static struct lpc43_sspdev_s g_ssp0dev = #ifdef CONFIG_LPC43_SSP_INTERRUPTS .sspirq = LPC43_IRQ_SSP0, #endif -}; +}; #endif /* CONFIG_LPC43_SSP0 */ #ifdef CONFIG_LPC43_SSP1 @@ -226,7 +226,7 @@ static struct lpc43_sspdev_s g_ssp1dev = #ifdef CONFIG_LPC43_SSP_INTERRUPTS .sspirq = LPC43_IRQ_SSP1, #endif -}; +}; #endif /* CONFIG_LPC43_SSP1 */ /**************************************************************************** @@ -376,7 +376,7 @@ static uint32_t ssp_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) divisor = (divisor + 1) & ~1; /* Save the new divisor value */ - + ssp_putreg(priv, LPC43_SSP_CPSR_OFFSET, divisor); /* Calculate the new actual */ @@ -429,19 +429,19 @@ static void ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) { case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */ break; - + case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */ regval |= SSP_CR0_CPHA; break; - + case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */ regval |= SSP_CR0_CPOL; break; - + case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ regval |= (SSP_CR0_CPOL|SSP_CR0_CPHA); break; - + default: sspdbg("Bad mode: %d\n", mode); DEBUGASSERT(FALSE); diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_uart.c b/nuttx/arch/arm/src/lpc43xx/lpc43_uart.c index 4491830f9..f37387db5 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_uart.c +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_uart.c @@ -58,7 +58,7 @@ /************************************************************************** * Private Definitions **************************************************************************/ - + /* Select UART parameters for the selected console */ #if defined(CONFIG_USART0_SERIAL_CONSOLE) @@ -199,7 +199,7 @@ void up_lowputc(char ch) * PCLK_UART1; in the PCLKSEL1 register, select PCLK_USART2 and PCLK_USART3. * 3. Baud rate: In the LCR register, set bit DLAB = 1. This enables access * to registers DLL and DLM for setting the baud rate. Also, if needed, - * set the fractional baud rate in the fractional divider + * set the fractional baud rate in the fractional divider * 4. UART FIFO: Use bit FIFO enable (bit 0) in FCR register to * enable FIFO. * 5. Pins: Select UART pins through the PINSEL registers and pin modes @@ -496,7 +496,7 @@ void lpc43_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud) uint32_t errval; /* Error value associated with the candidate */ /* The U[S]ART buad is given by: - * + * * Fbaud = Fbase * mul / (mul + divadd) / (16 * dl) * dl = Fbase * mul / (mul + divadd) / Fbaud / 16 * = Fbase * mul / ((mul + divadd) * Fbaud * 16) @@ -507,7 +507,7 @@ void lpc43_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud) * 0 < mul < 16 * 0 <= divadd < mul */ - + best = UINT32_MAX; divadd = 0; mul = 0; diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_usb0dev.c b/nuttx/arch/arm/src/lpc43xx/lpc43_usb0dev.c index 379dbc435..c17f075b6 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_usb0dev.c +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_usb0dev.c @@ -638,7 +638,7 @@ static bool lpc43_rqenqueue(FAR struct lpc43_ep_s *privep, FAR struct lpc43_req_s *req) { bool is_empty = !privep->head; - + req->flink = NULL; if (is_empty) { @@ -692,7 +692,7 @@ static void lpc43_queuedtd(uint8_t epphy, struct lpc43_dtd_s *dtd) uint32_t bit = LPC43_ENDPTMASK(epphy); lpc43_setbits (bit, LPC43_USBDEV_ENDPTPRIME); - + while (lpc43_getreg (LPC43_USBDEV_ENDPTPRIME) & bit) ; } @@ -710,7 +710,7 @@ static inline void lpc43_ep0xfer(uint8_t epphy, uint8_t *buf, uint32_t nbytes) struct lpc43_dtd_s *dtd = &g_td[epphy]; lpc43_writedtd(dtd, buf, nbytes); - + lpc43_queuedtd(epphy, dtd); } @@ -733,9 +733,9 @@ static void lpc43_readsetup(uint8_t epphy, struct usb_ctrlreq_s *ctrl) /* copy the request... */ for (i = 0; i < 8; i++) ((uint8_t *) ctrl)[i] = ((uint8_t *) dqh->setup)[i]; - + } while (!(lpc43_getreg(LPC43_USBDEV_USBCMD) & USBDEV_USBCMD_SUTW)); - + /* Clear the trip wire */ lpc43_clrbits(USBDEV_USBCMD_SUTW, LPC43_USBDEV_USBCMD); @@ -756,7 +756,7 @@ static inline void lpc43_set_address(struct lpc43_usbdev_s *priv, uint16_t addre priv->paddr = address; priv->paddrset = address != 0; - lpc43_chgbits(USBDEV_DEVICEADDR_MASK, priv->paddr << USBDEV_DEVICEADDR_SHIFT, + lpc43_chgbits(USBDEV_DEVICEADDR_MASK, priv->paddr << USBDEV_DEVICEADDR_SHIFT, LPC43_USBDEV_DEVICEADDR); } @@ -807,7 +807,7 @@ static int lpc43_progressep(struct lpc43_ep_s *privep) if (privreq->req.len == 0) { - /* If the class driver is responding to a setup packet, then wait for the + /* If the class driver is responding to a setup packet, then wait for the * host to illicit thr response */ if (privep->epphy == LPC43_EP0_IN && privep->dev->ep0state == EP0STATE_SETUP_OUT) @@ -819,7 +819,7 @@ static int lpc43_progressep(struct lpc43_ep_s *privep) else usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_EPOUTNULLPACKET), 0); } - + lpc43_reqcomplete(privep, lpc43_rqdequeue(privep), OK); return OK; } @@ -1016,10 +1016,10 @@ static void lpc43_ep0configure(struct lpc43_usbdev_s *priv) g_qh[LPC43_EP0_IN ].capability = (DQH_CAPABILITY_MAX_PACKET(CONFIG_USBDEV_EP0_MAXSIZE) | DQH_CAPABILITY_IOS | DQH_CAPABILITY_ZLT); - + g_qh[LPC43_EP0_OUT].currdesc = DTD_NEXTDESC_INVALID; g_qh[LPC43_EP0_IN ].currdesc = DTD_NEXTDESC_INVALID; - + /* Enable EP0 */ lpc43_setbits (USBDEV_ENDPTCTRL0_RXE | USBDEV_ENDPTCTRL0_TXE, LPC43_USBDEV_ENDPTCTRL0); } @@ -1067,7 +1067,7 @@ static void lpc43_usbreset(struct lpc43_usbdev_s *priv) privep->stalled = false; } - /* Tell the class driver that we are disconnected. The class + /* Tell the class driver that we are disconnected. The class * driver should then accept any new configurations. */ if (priv->driver) @@ -1090,7 +1090,7 @@ static void lpc43_usbreset(struct lpc43_usbdev_s *priv) lpc43_ep0configure(priv); /* Enable Device interrupts */ - lpc43_putreg(USB_FRAME_INT | USB_ERROR_INT | + lpc43_putreg(USB_FRAME_INT | USB_ERROR_INT | USBDEV_USBINTR_NAKE | USBDEV_USBINTR_SLE | USBDEV_USBINTR_URE | USBDEV_USBINTR_PCE | USBDEV_USBINTR_UE, LPC43_USBDEV_USBINTR); } @@ -1106,7 +1106,7 @@ static void lpc43_usbreset(struct lpc43_usbdev_s *priv) static inline void lpc43_ep0state(struct lpc43_usbdev_s *priv, uint16_t state) { priv->ep0state = state; - + switch (state) { case EP0STATE_WAIT_NAK_IN: @@ -1138,7 +1138,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv) uint16_t index; uint16_t len; - /* Terminate any pending requests - since all DTDs will have been retired + /* Terminate any pending requests - since all DTDs will have been retired * because of the setup packet */ lpc43_cancelrequests(&priv->eplist[LPC43_EP0_OUT], -EPROTO); @@ -1180,7 +1180,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv) * index: zero interface endpoint * len: 2; data = status */ - + usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_GETSTATUS), 0); if (!priv->paddrset || len != 2 || (ctrl.type & USB_REQ_DIR_IN) == 0 || value != 0) @@ -1207,21 +1207,21 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv) else priv->ep0buf[0] = 0; /* Not stalled */ priv->ep0buf[1] = 0; - + lpc43_ep0xfer (LPC43_EP0_IN, priv->ep0buf, 2); lpc43_ep0state (priv, EP0STATE_SHORTWRITE); } } break; - + case USB_REQ_RECIPIENT_DEVICE: { if (index == 0) { usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_DEVGETSTATUS), 0); - + /* Features: Remote Wakeup=YES; selfpowered=? */ - + priv->ep0buf[0] = (priv->selfpowered << USB_FEATURE_SELFPOWERED) | (1 << USB_FEATURE_REMOTEWAKEUP); priv->ep0buf[1] = 0; @@ -1236,7 +1236,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv) } } break; - + case USB_REQ_RECIPIENT_INTERFACE: { usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_IFGETSTATUS), 0); @@ -1247,7 +1247,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv) lpc43_ep0state (priv, EP0STATE_SHORTWRITE); } break; - + default: { usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_BADGETSTATUS), 0); @@ -1258,7 +1258,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv) } } break; - + case USB_REQ_CLEARFEATURE: { /* type: host-to-device; recipient = device, interface or endpoint @@ -1266,7 +1266,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv) * index: zero interface endpoint; * len: zero, data = none */ - + usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_CLEARFEATURE), 0); if ((ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT) { @@ -1285,7 +1285,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv) } } break; - + case USB_REQ_SETFEATURE: { /* type: host-to-device; recipient = device, interface, endpoint @@ -1293,7 +1293,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv) * index: zero interface endpoint; * len: 0; data = none */ - + usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_SETFEATURE), 0); if (((ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) && value == USB_FEATURE_TESTMODE) @@ -1317,7 +1317,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv) } } break; - + case USB_REQ_SETADDRESS: { /* type: host-to-device; recipient = device @@ -1331,7 +1331,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv) { /* Save the address. We cannot actually change to the next address until * the completion of the status phase. */ - + priv->paddr = ctrl.value[0]; priv->paddrset = false; lpc43_ep0state (priv, EP0STATE_WAIT_NAK_IN); @@ -1343,7 +1343,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv) } } break; - + case USB_REQ_GETDESCRIPTOR: /* type: device-to-host; recipient = device * value: descriptor type and index @@ -1369,7 +1369,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv) } } break; - + case USB_REQ_GETCONFIGURATION: /* type: device-to-host; recipient = device * value: 0; @@ -1390,7 +1390,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv) } } break; - + case USB_REQ_SETCONFIGURATION: /* type: host-to-device; recipient = device * value: configuration value @@ -1411,7 +1411,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv) } } break; - + case USB_REQ_GETINTERFACE: /* type: device-to-host; recipient = interface * value: 0 @@ -1429,7 +1429,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv) lpc43_dispatchrequest(priv, &ctrl); } break; - + case USB_REQ_SYNCHFRAME: /* type: device-to-host; recipient = endpoint * value: 0 @@ -1440,7 +1440,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv) usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_SYNCHFRAME), 0); } break; - + default: { usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_INVALIDCTRLREQ), 0); @@ -1471,7 +1471,7 @@ static void lpc43_ep0complete(struct lpc43_usbdev_s *priv, uint8_t epphy) struct lpc43_ep_s *privep = &priv->eplist[epphy]; usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_EP0COMPLETE), (uint16_t)priv->ep0state); - + switch (priv->ep0state) { case EP0STATE_DATA_IN: @@ -1485,15 +1485,15 @@ static void lpc43_ep0complete(struct lpc43_usbdev_s *priv, uint8_t epphy) case EP0STATE_DATA_OUT: if (lpc43_rqempty(privep)) return; - + if (lpc43_epcomplete (priv, epphy)) lpc43_ep0state (priv, EP0STATE_WAIT_NAK_IN); break; - + case EP0STATE_SHORTWRITE: lpc43_ep0state (priv, EP0STATE_WAIT_NAK_OUT); break; - + case EP0STATE_WAIT_STATUS_IN: lpc43_ep0state (priv, EP0STATE_IDLE); @@ -1592,9 +1592,9 @@ bool lpc43_epcomplete(struct lpc43_usbdev_s *priv, uint8_t epphy) usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_EPOUTQEMPTY), 0); return true; } - + int xfrd = dtd->xfer_len - (dtd->config >> 16); - + privreq->req.xfrd += xfrd; bool complete = true; @@ -1621,7 +1621,7 @@ bool lpc43_epcomplete(struct lpc43_usbdev_s *priv, uint8_t epphy) { privreq = lpc43_rqdequeue (privep); } - + if (!lpc43_rqempty(privep)) { lpc43_progressep(privep); @@ -1667,11 +1667,11 @@ static int lpc43_usbinterrupt(int irq, FAR void *context) usbtrace(TRACE_INTEXIT(LPC43_TRACEINTID_USB), 0); return OK; } - + /* When the device controller enters a suspend state from an active state, * the SLI bit will be set to a one. */ - + if (!priv->suspended && (disr & USBDEV_USBSTS_SLI) != 0) { usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_SUSPENDED),0); @@ -1718,30 +1718,30 @@ static int lpc43_usbinterrupt(int irq, FAR void *context) if (portsc1 & USBDEV_PRTSC1_FPR) { /* FIXME: this occurs because of a J-to-K transition detected - * while the port is in SUSPEND state - presumambly this + * while the port is in SUSPEND state - presumambly this * is where the host is resuming the device? * * - but do we need to "ack" the interrupt */ } } - + #ifdef CONFIG_LPC43_USBDEV_FRAME_INTERRUPT if (disr & USBDEV_USBSTT_SRI) { usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_FRAME), 0); - - priv->sof = (int)lpc43_getreg(LPC43_USBDEV_FRINDEX_OFFSET); + + priv->sof = (int)lpc43_getreg(LPC43_USBDEV_FRINDEX_OFFSET); } #endif if (disr & USBDEV_USBSTS_UEI) { /* FIXME: these occur when a transfer results in an error condition - * it is set alongside USBINT if the DTD also had its IOC + * it is set alongside USBINT if the DTD also had its IOC * bit set. */ } - + if (disr & USBDEV_USBSTS_UI) { /* Handle completion interrupts */ @@ -1752,12 +1752,12 @@ static int lpc43_usbinterrupt(int irq, FAR void *context) /* Clear any NAK interrupt and completion interrupts */ lpc43_putreg (mask, LPC43_USBDEV_ENDPTNAK); lpc43_putreg (mask, LPC43_USBDEV_ENDPTCOMPLETE); - + if (mask & LPC43_ENDPTMASK(0)) lpc43_ep0complete(priv, 0); if (mask & LPC43_ENDPTMASK(1)) lpc43_ep0complete(priv, 1); - + for (n = 1; n < LPC43_NLOGENDPOINTS; n++) { if (mask & LPC43_ENDPTMASK((n<<1))) @@ -1772,9 +1772,9 @@ static int lpc43_usbinterrupt(int irq, FAR void *context) if (setupstat) { /* Clear the endpoint complete CTRL OUT and IN when a Setup is received */ - lpc43_putreg(LPC43_ENDPTMASK(LPC43_EP0_IN) | LPC43_ENDPTMASK(LPC43_EP0_OUT), + lpc43_putreg(LPC43_ENDPTMASK(LPC43_EP0_IN) | LPC43_ENDPTMASK(LPC43_EP0_OUT), LPC43_USBDEV_ENDPTCOMPLETE); - + if (setupstat & LPC43_ENDPTMASK(LPC43_EP0_OUT)) { usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_EP0SETUP), setupstat); @@ -1832,7 +1832,7 @@ static int lpc43_epconfigure(FAR struct usbdev_ep_s *ep, DEBUGASSERT(desc->addr == ep->eplog); /* Initialise EP capabilities */ - + uint16_t maxsize = GETUINT16(desc->mxpacketsize); if ((desc->attr & USB_EP_ATTR_XFERTYPE_MASK) == USB_EP_ATTR_XFER_ISOC) { @@ -1886,7 +1886,7 @@ static int lpc43_epconfigure(FAR struct usbdev_ep_s *ep, lpc43_setbits (USBDEV_ENDPTCTRL_TXE, LPC43_USBDEV_ENDPTCTRL(privep->epphy)); else lpc43_setbits (USBDEV_ENDPTCTRL_RXE, LPC43_USBDEV_ENDPTCTRL(privep->epphy)); - + return OK; } @@ -2076,7 +2076,7 @@ static int lpc43_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r { ret = -EBUSY; } - else + else { /* Add the new request to the request queue for the endpoint */ @@ -2121,7 +2121,7 @@ static int lpc43_epcancel(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r priv = privep->dev; flags = irqsave(); - + /* FIXME: if the request is the first, then we need to flush the EP * otherwise just remove it from the list * @@ -2379,7 +2379,7 @@ static int lpc43_wakeup(struct usbdev_s *dev) * Name: lpc43_selfpowered * * Description: - * Sets/clears the device selfpowered feature + * Sets/clears the device selfpowered feature * *******************************************************************************/ @@ -2449,7 +2449,7 @@ void up_usbinitialize(void) usbtrace(TRACE_DEVINIT, 0); /* Disable USB interrupts */ - + lpc43_putreg(0, LPC43_USBDEV_USBINTR); /* Initialize the device state structure */ @@ -2519,7 +2519,7 @@ void up_usbinitialize(void) /* Enable USB OTG PLL and wait for lock */ lpc43_putreg (0, LPC43_SYSCREG_USB_ATXPLLPDREG); - + uint32_t bank = EVNTRTR_BANK(EVENTRTR_USBATXPLLLOCK); uint32_t bit = EVNTRTR_BIT(EVENTRTR_USBATXPLLLOCK); @@ -2657,7 +2657,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) up_enable_irq(LPC43_IRQ_USBOTG); /* FIXME: nothing seems to call DEV_CONNECT(), but we need to set - * the RS bit to enable the controller. It kind of makes sense + * the RS bit to enable the controller. It kind of makes sense * to do this after the class has bound to us... * GEN: This bug is really in the class driver. It should make the * soft connect when it is ready to be enumerated. I have added diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_userspace.c b/nuttx/arch/arm/src/lpc43xx/lpc43_userspace.c index c5c62f716..7bc7f1c25 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_userspace.c +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_userspace.c @@ -98,7 +98,7 @@ void lpc43_userspace(void) /* Initialize all of user-space .data */ DEBUGASSERT(USERSPACE->us_datasource != 0 && - USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && + USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && USERSPACE->us_datastart <= USERSPACE->us_dataend); src = (uint8_t*)USERSPACE->us_datasource; diff --git a/nuttx/arch/arm/src/nuc1xx/Make.defs b/nuttx/arch/arm/src/nuc1xx/Make.defs index 669d0877e..dd5895148 100644 --- a/nuttx/arch/arm/src/nuc1xx/Make.defs +++ b/nuttx/arch/arm/src/nuc1xx/Make.defs @@ -33,7 +33,7 @@ # ############################################################################ -HEAD_ASRC = +HEAD_ASRC = CMN_ASRCS = up_exception.S up_saveusercontext.S up_fullcontextrestore.S CMN_ASRCS += up_switchcontext.S vfork.S @@ -67,7 +67,7 @@ ifeq ($(CONFIG_DEBUG),y) CMN_CSRCS += up_dumpnvic.c endif -CHIP_ASRCS = +CHIP_ASRCS = CHIP_CSRCS = nuc_clockconfig.c nuc_gpio.c nuc_idle.c nuc_irq.c nuc_lowputc.c CHIP_CSRCS += nuc_serial.c nuc_start.c nuc_timerisr.c diff --git a/nuttx/arch/arm/src/nuc1xx/chip/nuc_gcr.h b/nuttx/arch/arm/src/nuc1xx/chip/nuc_gcr.h index cf09cac81..c9ad2df98 100644 --- a/nuttx/arch/arm/src/nuc1xx/chip/nuc_gcr.h +++ b/nuttx/arch/arm/src/nuc1xx/chip/nuc_gcr.h @@ -158,167 +158,167 @@ /* Multiple function pin GPIOA control register */ #define GCR_GPA_MFP(n) (1 << (n)) /* Bits 0-15: PAn pin function selection */ -# define GCR_GPA_MFP0 (1 << 0) -# define GCR_GPA_MFP1 (1 << 1) -# define GCR_GPA_MFP2 (1 << 2) -# define GCR_GPA_MFP3 (1 << 3) -# define GCR_GPA_MFP4 (1 << 4) -# define GCR_GPA_MFP5 (1 << 5) -# define GCR_GPA_MFP6 (1 << 6) -# define GCR_GPA_MFP7 (1 << 7) -# define GCR_GPA_MFP8 (1 << 8) -# define GCR_GPA_MFP9 (1 << 9) -# define GCR_GPA_MFP10 (1 << 10) -# define GCR_GPA_MFP11 (1 << 11) -# define GCR_GPA_MFP12 (1 << 12) -# define GCR_GPA_MFP13 (1 << 13) -# define GCR_GPA_MFP14 (1 << 14) -# define GCR_GPA_MFP15 (1 << 15) +# define GCR_GPA_MFP0 (1 << 0) +# define GCR_GPA_MFP1 (1 << 1) +# define GCR_GPA_MFP2 (1 << 2) +# define GCR_GPA_MFP3 (1 << 3) +# define GCR_GPA_MFP4 (1 << 4) +# define GCR_GPA_MFP5 (1 << 5) +# define GCR_GPA_MFP6 (1 << 6) +# define GCR_GPA_MFP7 (1 << 7) +# define GCR_GPA_MFP8 (1 << 8) +# define GCR_GPA_MFP9 (1 << 9) +# define GCR_GPA_MFP10 (1 << 10) +# define GCR_GPA_MFP11 (1 << 11) +# define GCR_GPA_MFP12 (1 << 12) +# define GCR_GPA_MFP13 (1 << 13) +# define GCR_GPA_MFP14 (1 << 14) +# define GCR_GPA_MFP15 (1 << 15) #define GCR_GPA_TYPE(n) (1 << ((n)+16)) /* Bits 16-31: Enable Schmitt trigger function */ -# define GCR_GPA_TYPE0 (1 << 0) -# define GCR_GPA_TYPE1 (1 << 1) -# define GCR_GPA_TYPE2 (1 << 2) -# define GCR_GPA_TYPE3 (1 << 3) -# define GCR_GPA_TYPE4 (1 << 4) -# define GCR_GPA_TYPE5 (1 << 5) -# define GCR_GPA_TYPE6 (1 << 6) -# define GCR_GPA_TYPE7 (1 << 7) -# define GCR_GPA_TYPE8 (1 << 8) -# define GCR_GPA_TYPE9 (1 << 9) -# define GCR_GPA_TYPE10 (1 << 10) -# define GCR_GPA_TYPE11 (1 << 11) -# define GCR_GPA_TYPE12 (1 << 12) -# define GCR_GPA_TYPE13 (1 << 13) -# define GCR_GPA_TYPE14 (1 << 14) -# define GCR_GPA_TYPE15 (1 << 15) +# define GCR_GPA_TYPE0 (1 << 0) +# define GCR_GPA_TYPE1 (1 << 1) +# define GCR_GPA_TYPE2 (1 << 2) +# define GCR_GPA_TYPE3 (1 << 3) +# define GCR_GPA_TYPE4 (1 << 4) +# define GCR_GPA_TYPE5 (1 << 5) +# define GCR_GPA_TYPE6 (1 << 6) +# define GCR_GPA_TYPE7 (1 << 7) +# define GCR_GPA_TYPE8 (1 << 8) +# define GCR_GPA_TYPE9 (1 << 9) +# define GCR_GPA_TYPE10 (1 << 10) +# define GCR_GPA_TYPE11 (1 << 11) +# define GCR_GPA_TYPE12 (1 << 12) +# define GCR_GPA_TYPE13 (1 << 13) +# define GCR_GPA_TYPE14 (1 << 14) +# define GCR_GPA_TYPE15 (1 << 15) /* Multiple function pin GPIOB control register */ #define GCR_GPB_MFP(n) (1 << (n)) /* Bits 0-15: PBn pin function selection */ -# define GCR_GPB_MFP0 (1 << 0) -# define GCR_GPB_MFP1 (1 << 1) -# define GCR_GPB_MFP2 (1 << 2) -# define GCR_GPB_MFP3 (1 << 3) -# define GCR_GPB_MFP4 (1 << 4) -# define GCR_GPB_MFP5 (1 << 5) -# define GCR_GPB_MFP6 (1 << 6) -# define GCR_GPB_MFP7 (1 << 7) -# define GCR_GPB_MFP8 (1 << 8) -# define GCR_GPB_MFP9 (1 << 9) -# define GCR_GPB_MFP10 (1 << 10) -# define GCR_GPB_MFP11 (1 << 11) -# define GCR_GPB_MFP12 (1 << 12) -# define GCR_GPB_MFP13 (1 << 13) -# define GCR_GPB_MFP14 (1 << 14) -# define GCR_GPB_MFP15 (1 << 15) +# define GCR_GPB_MFP0 (1 << 0) +# define GCR_GPB_MFP1 (1 << 1) +# define GCR_GPB_MFP2 (1 << 2) +# define GCR_GPB_MFP3 (1 << 3) +# define GCR_GPB_MFP4 (1 << 4) +# define GCR_GPB_MFP5 (1 << 5) +# define GCR_GPB_MFP6 (1 << 6) +# define GCR_GPB_MFP7 (1 << 7) +# define GCR_GPB_MFP8 (1 << 8) +# define GCR_GPB_MFP9 (1 << 9) +# define GCR_GPB_MFP10 (1 << 10) +# define GCR_GPB_MFP11 (1 << 11) +# define GCR_GPB_MFP12 (1 << 12) +# define GCR_GPB_MFP13 (1 << 13) +# define GCR_GPB_MFP14 (1 << 14) +# define GCR_GPB_MFP15 (1 << 15) #define GCR_GPB_TYPE(n) (1 << ((n)+16)) /* Bits 16-31: Enable Schmitt trigger function */ -# define GCR_GPB_TYPE0 (1 << 0) -# define GCR_GPB_TYPE1 (1 << 1) -# define GCR_GPB_TYPE2 (1 << 2) -# define GCR_GPB_TYPE3 (1 << 3) -# define GCR_GPB_TYPE4 (1 << 4) -# define GCR_GPB_TYPE5 (1 << 5) -# define GCR_GPB_TYPE6 (1 << 6) -# define GCR_GPB_TYPE7 (1 << 7) -# define GCR_GPB_TYPE8 (1 << 8) -# define GCR_GPB_TYPE9 (1 << 9) -# define GCR_GPB_TYPE10 (1 << 10) -# define GCR_GPB_TYPE11 (1 << 11) -# define GCR_GPB_TYPE12 (1 << 12) -# define GCR_GPB_TYPE13 (1 << 13) -# define GCR_GPB_TYPE14 (1 << 14) -# define GCR_GPB_TYPE15 (1 << 15) +# define GCR_GPB_TYPE0 (1 << 0) +# define GCR_GPB_TYPE1 (1 << 1) +# define GCR_GPB_TYPE2 (1 << 2) +# define GCR_GPB_TYPE3 (1 << 3) +# define GCR_GPB_TYPE4 (1 << 4) +# define GCR_GPB_TYPE5 (1 << 5) +# define GCR_GPB_TYPE6 (1 << 6) +# define GCR_GPB_TYPE7 (1 << 7) +# define GCR_GPB_TYPE8 (1 << 8) +# define GCR_GPB_TYPE9 (1 << 9) +# define GCR_GPB_TYPE10 (1 << 10) +# define GCR_GPB_TYPE11 (1 << 11) +# define GCR_GPB_TYPE12 (1 << 12) +# define GCR_GPB_TYPE13 (1 << 13) +# define GCR_GPB_TYPE14 (1 << 14) +# define GCR_GPB_TYPE15 (1 << 15) /* Multiple function pin GPIOC control register */ #define GCR_GPC_MFP(n) (1 << (n)) /* Bits 0-15: PCn pin function selection */ -# define GCR_GPC_MFP0 (1 << 0) -# define GCR_GPC_MFP1 (1 << 1) -# define GCR_GPC_MFP2 (1 << 2) -# define GCR_GPC_MFP3 (1 << 3) -# define GCR_GPC_MFP4 (1 << 4) -# define GCR_GPC_MFP5 (1 << 5) -# define GCR_GPC_MFP6 (1 << 6) -# define GCR_GPC_MFP7 (1 << 7) -# define GCR_GPC_MFP8 (1 << 8) -# define GCR_GPC_MFP9 (1 << 9) -# define GCR_GPC_MFP10 (1 << 10) -# define GCR_GPC_MFP11 (1 << 11) -# define GCR_GPC_MFP12 (1 << 12) -# define GCR_GPC_MFP13 (1 << 13) -# define GCR_GPC_MFP14 (1 << 14) -# define GCR_GPC_MFP15 (1 << 15) +# define GCR_GPC_MFP0 (1 << 0) +# define GCR_GPC_MFP1 (1 << 1) +# define GCR_GPC_MFP2 (1 << 2) +# define GCR_GPC_MFP3 (1 << 3) +# define GCR_GPC_MFP4 (1 << 4) +# define GCR_GPC_MFP5 (1 << 5) +# define GCR_GPC_MFP6 (1 << 6) +# define GCR_GPC_MFP7 (1 << 7) +# define GCR_GPC_MFP8 (1 << 8) +# define GCR_GPC_MFP9 (1 << 9) +# define GCR_GPC_MFP10 (1 << 10) +# define GCR_GPC_MFP11 (1 << 11) +# define GCR_GPC_MFP12 (1 << 12) +# define GCR_GPC_MFP13 (1 << 13) +# define GCR_GPC_MFP14 (1 << 14) +# define GCR_GPC_MFP15 (1 << 15) #define GCR_GPC_TYPE(n) (1 << ((n)+16)) /* Bits 16-31: Enable Schmitt trigger function */ -# define GCR_GPC_TYPE0 (1 << 0) -# define GCR_GPC_TYPE1 (1 << 1) -# define GCR_GPC_TYPE2 (1 << 2) -# define GCR_GPC_TYPE3 (1 << 3) -# define GCR_GPC_TYPE4 (1 << 4) -# define GCR_GPC_TYPE5 (1 << 5) -# define GCR_GPC_TYPE6 (1 << 6) -# define GCR_GPC_TYPE7 (1 << 7) -# define GCR_GPC_TYPE8 (1 << 8) -# define GCR_GPC_TYPE9 (1 << 9) -# define GCR_GPC_TYPE10 (1 << 10) -# define GCR_GPC_TYPE11 (1 << 11) -# define GCR_GPC_TYPE12 (1 << 12) -# define GCR_GPC_TYPE13 (1 << 13) -# define GCR_GPC_TYPE14 (1 << 14) -# define GCR_GPC_TYPE15 (1 << 15) +# define GCR_GPC_TYPE0 (1 << 0) +# define GCR_GPC_TYPE1 (1 << 1) +# define GCR_GPC_TYPE2 (1 << 2) +# define GCR_GPC_TYPE3 (1 << 3) +# define GCR_GPC_TYPE4 (1 << 4) +# define GCR_GPC_TYPE5 (1 << 5) +# define GCR_GPC_TYPE6 (1 << 6) +# define GCR_GPC_TYPE7 (1 << 7) +# define GCR_GPC_TYPE8 (1 << 8) +# define GCR_GPC_TYPE9 (1 << 9) +# define GCR_GPC_TYPE10 (1 << 10) +# define GCR_GPC_TYPE11 (1 << 11) +# define GCR_GPC_TYPE12 (1 << 12) +# define GCR_GPC_TYPE13 (1 << 13) +# define GCR_GPC_TYPE14 (1 << 14) +# define GCR_GPC_TYPE15 (1 << 15) /* Multiple function pin GPIOD control register */ #define GCR_GPD_MFP(n) (1 << (n)) /* Bits 0-15: PDn pin function selection */ -# define GCR_GPD_MFP0 (1 << 0) -# define GCR_GPD_MFP1 (1 << 1) -# define GCR_GPD_MFP2 (1 << 2) -# define GCR_GPD_MFP3 (1 << 3) -# define GCR_GPD_MFP4 (1 << 4) -# define GCR_GPD_MFP5 (1 << 5) -# define GCR_GPD_MFP6 (1 << 6) -# define GCR_GPD_MFP7 (1 << 7) -# define GCR_GPD_MFP8 (1 << 8) -# define GCR_GPD_MFP9 (1 << 9) -# define GCR_GPD_MFP10 (1 << 10) -# define GCR_GPD_MFP11 (1 << 11) -# define GCR_GPD_MFP12 (1 << 12) -# define GCR_GPD_MFP13 (1 << 13) -# define GCR_GPD_MFP14 (1 << 14) -# define GCR_GPD_MFP15 (1 << 15) +# define GCR_GPD_MFP0 (1 << 0) +# define GCR_GPD_MFP1 (1 << 1) +# define GCR_GPD_MFP2 (1 << 2) +# define GCR_GPD_MFP3 (1 << 3) +# define GCR_GPD_MFP4 (1 << 4) +# define GCR_GPD_MFP5 (1 << 5) +# define GCR_GPD_MFP6 (1 << 6) +# define GCR_GPD_MFP7 (1 << 7) +# define GCR_GPD_MFP8 (1 << 8) +# define GCR_GPD_MFP9 (1 << 9) +# define GCR_GPD_MFP10 (1 << 10) +# define GCR_GPD_MFP11 (1 << 11) +# define GCR_GPD_MFP12 (1 << 12) +# define GCR_GPD_MFP13 (1 << 13) +# define GCR_GPD_MFP14 (1 << 14) +# define GCR_GPD_MFP15 (1 << 15) #define GCR_GPD_TYPE(n) (1 << ((n)+16)) /* Bits 16-31: Enable Schmitt trigger function */ -# define GCR_GPD_TYPE0 (1 << 0) -# define GCR_GPD_TYPE1 (1 << 1) -# define GCR_GPD_TYPE2 (1 << 2) -# define GCR_GPD_TYPE3 (1 << 3) -# define GCR_GPD_TYPE4 (1 << 4) -# define GCR_GPD_TYPE5 (1 << 5) -# define GCR_GPD_TYPE6 (1 << 6) -# define GCR_GPD_TYPE7 (1 << 7) -# define GCR_GPD_TYPE8 (1 << 8) -# define GCR_GPD_TYPE9 (1 << 9) -# define GCR_GPD_TYPE10 (1 << 10) -# define GCR_GPD_TYPE11 (1 << 11) -# define GCR_GPD_TYPE12 (1 << 12) -# define GCR_GPD_TYPE13 (1 << 13) -# define GCR_GPD_TYPE14 (1 << 14) -# define GCR_GPD_TYPE15 (1 << 15) +# define GCR_GPD_TYPE0 (1 << 0) +# define GCR_GPD_TYPE1 (1 << 1) +# define GCR_GPD_TYPE2 (1 << 2) +# define GCR_GPD_TYPE3 (1 << 3) +# define GCR_GPD_TYPE4 (1 << 4) +# define GCR_GPD_TYPE5 (1 << 5) +# define GCR_GPD_TYPE6 (1 << 6) +# define GCR_GPD_TYPE7 (1 << 7) +# define GCR_GPD_TYPE8 (1 << 8) +# define GCR_GPD_TYPE9 (1 << 9) +# define GCR_GPD_TYPE10 (1 << 10) +# define GCR_GPD_TYPE11 (1 << 11) +# define GCR_GPD_TYPE12 (1 << 12) +# define GCR_GPD_TYPE13 (1 << 13) +# define GCR_GPD_TYPE14 (1 << 14) +# define GCR_GPD_TYPE15 (1 << 15) /* Multiple function pin GPIOE control register */ #define GCR_GPE_MFP(n) (1 << (n)) /* Bits 0-15: PDn pin function selection */ -# define GCR_GPE_MFP0 (1 << 0) -# define GCR_GPE_MFP1 (1 << 1) -# define GCR_GPE_MFP2 (1 << 2) -# define GCR_GPE_MFP3 (1 << 3) -# define GCR_GPE_MFP4 (1 << 4) -# define GCR_GPE_MFP5 (1 << 5) +# define GCR_GPE_MFP0 (1 << 0) +# define GCR_GPE_MFP1 (1 << 1) +# define GCR_GPE_MFP2 (1 << 2) +# define GCR_GPE_MFP3 (1 << 3) +# define GCR_GPE_MFP4 (1 << 4) +# define GCR_GPE_MFP5 (1 << 5) #define GCR_GPE_TYPE(n) (1 << ((n)+16)) /* Bits 16-31: Enable Schmitt trigger function */ -# define GCR_GPE_TYPE0 (1 << 0) -# define GCR_GPE_TYPE1 (1 << 1) -# define GCR_GPE_TYPE2 (1 << 2) -# define GCR_GPE_TYPE3 (1 << 3) -# define GCR_GPE_TYPE4 (1 << 4) -# define GCR_GPE_TYPE5 (1 << 5) +# define GCR_GPE_TYPE0 (1 << 0) +# define GCR_GPE_TYPE1 (1 << 1) +# define GCR_GPE_TYPE2 (1 << 2) +# define GCR_GPE_TYPE3 (1 << 3) +# define GCR_GPE_TYPE4 (1 << 4) +# define GCR_GPE_TYPE5 (1 << 5) /* Alternative multiple function pin control register */ diff --git a/nuttx/arch/arm/src/nuc1xx/chip/nuc_gpio.h b/nuttx/arch/arm/src/nuc1xx/chip/nuc_gpio.h index aea16ab0c..7d99118e0 100644 --- a/nuttx/arch/arm/src/nuc1xx/chip/nuc_gpio.h +++ b/nuttx/arch/arm/src/nuc1xx/chip/nuc_gpio.h @@ -428,56 +428,56 @@ #define GPIO_PMD_OPENDRAIN 2 /* Open drain output */ #define GPIO_PMD_BIDI 3 /* Quasi bi-directional */ -#define GPIO_PMD_SHIFT(n) ((n) << 1) /* Bits 2n-2n+1: GPIOx Pin[n] mode control */ +#define GPIO_PMD_SHIFT(n) ((n) << 1) /* Bits 2n-2n+1: GPIOx Pin[n] mode control */ #define GPIO_PMD_MASK(n) (3 << GPIO_PMD_SHIFT(n)) # define GPIO_PMD(n,v) ((v) << GPIO_PMD_SHIFT(n)) -#define GPIO_PMD0_SHIFT (0) /* Bits 0-1: GPIOx Pin0 mode control */ +#define GPIO_PMD0_SHIFT (0) /* Bits 0-1: GPIOx Pin0 mode control */ #define GPIO_PMD0_MASK (3 << GPIO_PMD0_SHIFT) # define GPIO_PMD0(v) ((v) << GPIO_PMD0_SHIFT) -#define GPIO_PMD1_SHIFT (2) /* Bits 2-3: GPIOx Pin1 mode control */ +#define GPIO_PMD1_SHIFT (2) /* Bits 2-3: GPIOx Pin1 mode control */ #define GPIO_PMD1_MASK (3 << GPIO_PMD1_SHIFT) # define GPIO_PMD1(v) ((v) << GPIO_PMD1_SHIFT) -#define GPIO_PMD2_SHIFT (4) /* Bits 4-5: GPIOx Pin2 mode control */ +#define GPIO_PMD2_SHIFT (4) /* Bits 4-5: GPIOx Pin2 mode control */ #define GPIO_PMD2_MASK (3 << GPIO_PMD2_SHIFT) # define GPIO_PMD2(v) ((v) << GPIO_PMD2_SHIFT) -#define GPIO_PMD3_SHIFT (6) /* Bits 6-7: GPIOx Pin3 mode control */ +#define GPIO_PMD3_SHIFT (6) /* Bits 6-7: GPIOx Pin3 mode control */ #define GPIO_PMD3_MASK (3 << GPIO_PMD3_SHIFT) # define GPIO_PMD3(v) ((v) << GPIO_PMD3_SHIFT) -#define GPIO_PMD4_SHIFT (8) /* Bits 8-9: GPIOx Pin4 mode control */ +#define GPIO_PMD4_SHIFT (8) /* Bits 8-9: GPIOx Pin4 mode control */ #define GPIO_PMD4_MASK (3 << GPIO_PMD4_SHIFT) # define GPIO_PMD4(v) ((v) << GPIO_PMD4_SHIFT) -#define GPIO_PMD5_SHIFT (10) /* Bits 10-11: GPIOx Pin5 mode control */ +#define GPIO_PMD5_SHIFT (10) /* Bits 10-11: GPIOx Pin5 mode control */ #define GPIO_PMD5_MASK (3 << GPIO_PMD5_SHIFT) # define GPIO_PMD5(v) ((v) << GPIO_PMD5_SHIFT) -#define GPIO_PMD6_SHIFT (12) /* Bits 12-13: GPIOx Pin6 mode control */ +#define GPIO_PMD6_SHIFT (12) /* Bits 12-13: GPIOx Pin6 mode control */ #define GPIO_PMD6_MASK (3 << GPIO_PMD6_SHIFT) # define GPIO_PMD6(v) ((v) << GPIO_PMD6_SHIFT) -#define GPIO_PMD7_SHIFT (14) /* Bits 14-15: GPIOx Pin7 mode control */ +#define GPIO_PMD7_SHIFT (14) /* Bits 14-15: GPIOx Pin7 mode control */ #define GPIO_PMD7_MASK (3 << GPIO_PMD7_SHIFT) # define GPIO_PMD7(v) ((v) << GPIO_PMD7_SHIFT) -#define GPIO_PMD8_SHIFT (16) /* Bits 16-17: GPIOx Pin8 mode control */ +#define GPIO_PMD8_SHIFT (16) /* Bits 16-17: GPIOx Pin8 mode control */ #define GPIO_PMD8_MASK (3 << GPIO_PMD8_SHIFT) # define GPIO_PMD8(v) ((v) << GPIO_PMD8_SHIFT) -#define GPIO_PMD9_SHIFT (18) /* Bits 18-19: GPIOx Pin9 mode control */ +#define GPIO_PMD9_SHIFT (18) /* Bits 18-19: GPIOx Pin9 mode control */ #define GPIO_PMD9_MASK (3 << GPIO_PMD9_SHIFT) # define GPIO_PMD9(v) ((v) << GPIO_PMD9_SHIFT) -#define GPIO_PMD10_SHIFT (20) /* Bits 20-21: GPIOx Pin0 mode control */ +#define GPIO_PMD10_SHIFT (20) /* Bits 20-21: GPIOx Pin0 mode control */ #define GPIO_PMD10_MASK (3 << GPIO_PMD10_SHIFT) # define GPIO_PMD10(v) ((v) << GPIO_PMD10_SHIFT) -#define GPIO_PMD11_SHIFT (22) /* Bits 22-23: GPIOx Pin1 mode control */ +#define GPIO_PMD11_SHIFT (22) /* Bits 22-23: GPIOx Pin1 mode control */ #define GPIO_PMD11_MASK (3 << GPIO_PMD11_SHIFT) # define GPIO_PMD11(v) ((v) << GPIO_PMD11_SHIFT) -#define GPIO_PMD12_SHIFT (24) /* Bits 24-25: GPIOx Pin2 mode control */ +#define GPIO_PMD12_SHIFT (24) /* Bits 24-25: GPIOx Pin2 mode control */ #define GPIO_PMD12_MASK (3 << GPIO_PMD12_SHIFT) # define GPIO_PMD12(v) ((v) << GPIO_PMD12_SHIFT) -#define GPIO_PMD13_SHIFT (26) /* Bits 26-27: GPIOx Pin3 mode control */ +#define GPIO_PMD13_SHIFT (26) /* Bits 26-27: GPIOx Pin3 mode control */ #define GPIO_PMD13_MASK (3 << GPIO_PMD13_SHIFT) # define GPIO_PMD13(v) ((v) << GPIO_PMD13_SHIFT) -#define GPIO_PMD14_SHIFT (28) /* Bits 28-29: GPIOx Pin4 mode control */ +#define GPIO_PMD14_SHIFT (28) /* Bits 28-29: GPIOx Pin4 mode control */ #define GPIO_PMD14_MASK (3 << GPIO_PMD14_SHIFT) # define GPIO_PMD14(v) ((v) << GPIO_PMD14_SHIFT) -#define GPIO_PMD15_SHIFT (30) /* Bits 30-31: GPIOx Pin5 mode control */ +#define GPIO_PMD15_SHIFT (30) /* Bits 30-31: GPIOx Pin5 mode control */ #define GPIO_PMD15_MASK (3 << GPIO_PMD15_SHIFT) # define GPIO_PMD15(v) ((v) << GPIO_PMD15_SHIFT) diff --git a/nuttx/arch/arm/src/nuc1xx/nuc_gpio.c b/nuttx/arch/arm/src/nuc1xx/nuc_gpio.c index 95f1ff143..9c4c79a90 100644 --- a/nuttx/arch/arm/src/nuc1xx/nuc_gpio.c +++ b/nuttx/arch/arm/src/nuc1xx/nuc_gpio.c @@ -140,7 +140,7 @@ int nuc_configgpio(gpio_cfgset_t cfgset) { regval |= GPIO_OFFD(pin); } - + putreg32(regval, regaddr); /* Check if we need to enable debouncing */ @@ -153,7 +153,7 @@ int nuc_configgpio(gpio_cfgset_t cfgset) { regval |= GPIO_DBEN(pin); } - + putreg32(regval, regaddr); /* Configure interrupting pins */ diff --git a/nuttx/arch/arm/src/nuc1xx/nuc_idle.c b/nuttx/arch/arm/src/nuc1xx/nuc_idle.c index 7daa5ca95..bc9fe7c6b 100644 --- a/nuttx/arch/arm/src/nuc1xx/nuc_idle.c +++ b/nuttx/arch/arm/src/nuc1xx/nuc_idle.c @@ -87,7 +87,7 @@ static void up_idlepm(void) enum pm_state_e newstate; irqstate_t flags; int ret; - + /* Decide, which power saving level can be obtained */ newstate = pm_checkstate(); diff --git a/nuttx/arch/arm/src/nuc1xx/nuc_lowputc.c b/nuttx/arch/arm/src/nuc1xx/nuc_lowputc.c index f8fe44145..c66a20d87 100644 --- a/nuttx/arch/arm/src/nuc1xx/nuc_lowputc.c +++ b/nuttx/arch/arm/src/nuc1xx/nuc_lowputc.c @@ -174,7 +174,7 @@ void nuc_lowsetup(void) #ifdef CONFIG_NUC_UART1 #ifdef CONFIG_UART1_FLOW_CONTROL - regval |= (GCR_GPB_MFP4 | GCR_GPB_MFP5 | GCR_GPB_MFP6| GCR_GPB_MFP7) + regval |= (GCR_GPB_MFP4 | GCR_GPB_MFP5 | GCR_GPB_MFP6| GCR_GPB_MFP7) #else regval |= (GCR_GPB_MFP4 | GCR_GPB_MFP5); #endif @@ -364,11 +364,11 @@ void nuc_setbaud(uintptr_t base, uint32_t baud) uint32_t divx; regval = getreg32(base + NUC_UART_BAUD_OFFSET); - + /* Mode 0: Source Clock mod 16 < 3 => Using Divider X = 16 */ clksperbit = (NUC_UART_CLK + (baud >> 1)) / baud; - if ((clksperbit & 15) < 3) + if ((clksperbit & 15) < 3) { regval &= ~(UART_BAUD_DIV_X_ONE | UART_BAUD_DIV_X_EN); brd = (clksperbit >> 4) - 2; @@ -390,7 +390,7 @@ void nuc_setbaud(uintptr_t base, uint32_t baud) /* Mode 1: Try to Set Divider X up 10 */ regval &= ~UART_BAUD_DIV_X_ONE; - + for (divx = 8; divx < 16; divx++) { brd = clksperbit % (divx + 1); diff --git a/nuttx/arch/arm/src/nuc1xx/nuc_serial.c b/nuttx/arch/arm/src/nuc1xx/nuc_serial.c index 10acca0b1..ee774b9ae 100644 --- a/nuttx/arch/arm/src/nuc1xx/nuc_serial.c +++ b/nuttx/arch/arm/src/nuc1xx/nuc_serial.c @@ -705,7 +705,7 @@ static int up_interrupt(int irq, void *context) * generated after several bytes have been recevied and enable * the RX timout. */ - + up_rxto_enable(priv); } @@ -727,7 +727,7 @@ static int up_interrupt(int irq, void *context) regval = up_serialin(priv, NUC_UART_MCR_OFFSET); up_serialout(priv, NUC_UART_MCR_OFFSET, regval | UART_MSR_DCTSF); } - + /* Check for line status or buffer errors*/ if ((isr & UART_ISR_RLS_INT) != 0 || diff --git a/nuttx/arch/arm/src/nuc1xx/nuc_userspace.c b/nuttx/arch/arm/src/nuc1xx/nuc_userspace.c index 0a60059ba..88a50695c 100644 --- a/nuttx/arch/arm/src/nuc1xx/nuc_userspace.c +++ b/nuttx/arch/arm/src/nuc1xx/nuc_userspace.c @@ -97,7 +97,7 @@ void nuc_userspace(void) /* Initialize all of user-space .data */ DEBUGASSERT(USERSPACE->us_datasource != 0 && - USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && + USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && USERSPACE->us_datastart <= USERSPACE->us_dataend); src = (uint8_t*)USERSPACE->us_datasource; diff --git a/nuttx/arch/arm/src/sam34/chip/sam_acc.h b/nuttx/arch/arm/src/sam34/chip/sam_acc.h index 7747a5ac0..1e546ac14 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_acc.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_acc.h @@ -134,7 +134,7 @@ #define ACC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ #define ACC_WPMR_WPKEY_MASK (0x00ffffff << ACC_WPMR_WPKEY_SHIFT) # define ACC_WPMR_WPKEY (0x00414343 << ACC_WPMR_WPKEY_SHIFT) - + /* Write Protect Status Register */ #define ACC_WPSR_WPROTERR (1 << 0) /* Bit 0: Write protection error */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_can.h b/nuttx/arch/arm/src/sam34/chip/sam_can.h index c6c140bf0..22548314e 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_can.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_can.h @@ -63,7 +63,7 @@ /* CAN register offsets *****************************************************************/ -#define SAM_CAN_MR_OFFSET 0x0000 /* Mode Register */ +#define SAM_CAN_MR_OFFSET 0x0000 /* Mode Register */ #define SAM_CAN_IER_OFFSET 0x0004 /* Interrupt Enable Register */ #define SAM_CAN_IDR_OFFSET 0x0008 /* Interrupt Disable Register */ #define SAM_CAN_IMR_OFFSET 0x000c /* Interrupt Mask Register */ @@ -146,7 +146,7 @@ /* CAN register bit definitions *********************************************************/ -/* Mode Register */ +/* Mode Register */ #define CAN_MR_CANEN (1 << 0) /* Bit 0: CAN controller enable */ #define CAN_MR_LPM (1 << 1) /* Bit 1: Disable/enable low power mode */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_dacc.h b/nuttx/arch/arm/src/sam34/chip/sam_dacc.h index 86768fc30..4581289ed 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_dacc.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_dacc.h @@ -210,7 +210,7 @@ #define DACC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ #define DACC_WPMR_WPKEY_MASK (0x00ffffff << DACC_WPMR_WPKEY_SHIFT) # define DACC_WPMR_WPKEY_MASK (0x00444143 << DACC_WPMR_WPKEY_SHIFT) - + /* Write Protect Status register */ #define DACC_WPSR_WPROTERR (1 << 0) /* Bit 0: Write protection error */ diff --git a/nuttx/arch/arm/src/sam34/sam4l_gpio.h b/nuttx/arch/arm/src/sam34/sam4l_gpio.h index e4aa8e8f1..49860adae 100644 --- a/nuttx/arch/arm/src/sam34/sam4l_gpio.h +++ b/nuttx/arch/arm/src/sam34/sam4l_gpio.h @@ -218,7 +218,7 @@ * GPIO Input: .... .... .... II.. .... .... * GPIO Output: .... .... .... .... .... .... * Peripheral: .... .... .... II.. .... .... - */ + */ #define GPIO_INT_SHIFT (10) /* Bits 10-11: Interrupting input control */ #define GPIO_INT_MASK (3 << GPIO_INT_SHIFT) diff --git a/nuttx/arch/arm/src/sam34/sam_userspace.c b/nuttx/arch/arm/src/sam34/sam_userspace.c index 7fd274be3..fc266fe8f 100644 --- a/nuttx/arch/arm/src/sam34/sam_userspace.c +++ b/nuttx/arch/arm/src/sam34/sam_userspace.c @@ -98,7 +98,7 @@ void sam_userspace(void) /* Initialize all of user-space .data */ DEBUGASSERT(USERSPACE->us_datasource != 0 && - USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && + USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && USERSPACE->us_datastart <= USERSPACE->us_dataend); src = (uint8_t*)USERSPACE->us_datasource; diff --git a/nuttx/arch/arm/src/sama5/chip/sam_pwm.h b/nuttx/arch/arm/src/sama5/chip/sam_pwm.h index 308ef1e4f..f967043da 100644 --- a/nuttx/arch/arm/src/sama5/chip/sam_pwm.h +++ b/nuttx/arch/arm/src/sama5/chip/sam_pwm.h @@ -92,7 +92,7 @@ #define SAM_PWM_CMPV_OFFSET(n) (0x0130 + ((int)(n) << 4)) /* n=0..7 */ #define SAM_PWM_CMPVUPD_OFFSET(n) (0x0134 + ((int)(n) << 4)) /* n=0-7 */ #define SAM_PWM_CMPM_OFFSET(n) (0x0138 + ((int)(n) << 4)) /* n=0-7 */ -#define SAM_PWM_CMPMUPD_OFFSET(n) (0x013c + ((int)(n) << 4)) /* n=0-7 */ +#define SAM_PWM_CMPMUPD_OFFSET(n) (0x013c + ((int)(n) << 4)) /* n=0-7 */ #define SAM_PWM_CMPV0_OFFSET 0x0130 /* PWM Comparison 0 Value Register */ #define SAM_PWM_CMPVUPD0_OFFSET 0x0134 /* PWM Comparison 0 Value Update Register */ diff --git a/nuttx/arch/arm/src/sama5/sam_gf512.c b/nuttx/arch/arm/src/sama5/sam_gf512.c index 55ca77bdf..bdbbc6780 100644 --- a/nuttx/arch/arm/src/sama5/sam_gf512.c +++ b/nuttx/arch/arm/src/sama5/sam_gf512.c @@ -56,7 +56,7 @@ /* Gallois Field tables for 512 bytes sectors. First raw is "index_of" and second one is "alpha_to" */ -const uint16_t pmecc_gf512[2][PMECC_GF_SIZEOF_512] = +const uint16_t pmecc_gf512[2][PMECC_GF_SIZEOF_512] = { /* "index_of" table */ { diff --git a/nuttx/arch/arm/src/sama5/sam_pck.c b/nuttx/arch/arm/src/sama5/sam_pck.c index 06ddd29a1..a77480853 100644 --- a/nuttx/arch/arm/src/sama5/sam_pck.c +++ b/nuttx/arch/arm/src/sama5/sam_pck.c @@ -122,7 +122,7 @@ uint32_t sam_pck_configure(enum pckid_e pckid, uint32_t frequency) regval = PMC_PCK_CSS_PLLA; clkin = BOARD_PLLA_FREQUENCY; } - + /* The the larger smallest divisor that does not exceed the requested * frequency. */ diff --git a/nuttx/arch/arm/src/sama5/sam_pwm.c b/nuttx/arch/arm/src/sama5/sam_pwm.c index 5d389a221..377d704b7 100644 --- a/nuttx/arch/arm/src/sama5/sam_pwm.c +++ b/nuttx/arch/arm/src/sama5/sam_pwm.c @@ -1132,7 +1132,7 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev, pwm_chan_putreg(chan, SAM_PWM_CMR_OFFSET, PWM_CMR_CPRE_CLKA); - /* Set the PWM period. + /* Set the PWM period. * * If the waveform is left-aligned, then the output waveform period * depends on the channel counter source clock and can be calculated @@ -1368,7 +1368,7 @@ FAR struct pwm_lowerhalf_s *sam_pwminitialize(int channel) { pwmdbg("ERROR: Failed to attach IRQ%d\n", channel); return NULL; - + } #endif diff --git a/nuttx/arch/arm/src/sama5/sam_tc.h b/nuttx/arch/arm/src/sama5/sam_tc.h index ba5657503..50585f7a1 100644 --- a/nuttx/arch/arm/src/sama5/sam_tc.h +++ b/nuttx/arch/arm/src/sama5/sam_tc.h @@ -107,7 +107,7 @@ extern "C" * On success, a non-NULL handle value is returned. This handle may be * used with subsequent timer/counter interfaces to manage the timer. A * NULL handle value is returned on a failure. - * + * ****************************************************************************/ TC_HANDLE sam_tc_allocate(int channel, int mode); @@ -123,7 +123,7 @@ TC_HANDLE sam_tc_allocate(int channel, int mode); * * Returned Value: * None - * + * ****************************************************************************/ void sam_tc_free(TC_HANDLE handle); @@ -139,7 +139,7 @@ void sam_tc_free(TC_HANDLE handle); * handle Channel handle previously allocated by sam_tc_allocate() * * Returned Value: - * + * ****************************************************************************/ void sam_tc_start(TC_HANDLE handle); @@ -154,7 +154,7 @@ void sam_tc_start(TC_HANDLE handle); * handle Channel handle previously allocated by sam_tc_allocate() * * Returned Value: - * + * ****************************************************************************/ void sam_tc_stop(TC_HANDLE handle); @@ -167,7 +167,7 @@ void sam_tc_stop(TC_HANDLE handle); * setting in the register will be the TC input frequency divided by * the provided divider (which should derive from the divider returned * by sam_tc_divider). - * + * * * Input Parameters: * handle Channel handle previously allocated by sam_tc_allocate() diff --git a/nuttx/arch/arm/src/sama5/sam_trng.c b/nuttx/arch/arm/src/sama5/sam_trng.c index c93393bbe..3f0d701fd 100644 --- a/nuttx/arch/arm/src/sama5/sam_trng.c +++ b/nuttx/arch/arm/src/sama5/sam_trng.c @@ -172,7 +172,7 @@ static int sam_interrupt(int irq, void *context) /* This is not the first sample. Check if the new sample differs from * the preceding sample. */ - + else if (odata == g_trngdev.samples[g_trngdev.nsamples - 1]) { /* Two samples with the same value. Discard this one and try again. */ diff --git a/nuttx/arch/arm/src/sama5/sam_tsd.c b/nuttx/arch/arm/src/sama5/sam_tsd.c index 915e082b2..c3d45307f 100644 --- a/nuttx/arch/arm/src/sama5/sam_tsd.c +++ b/nuttx/arch/arm/src/sama5/sam_tsd.c @@ -434,7 +434,7 @@ errout: * Input Parameters * priv - The touchscreen private data structure * tsav - The new (shifted) value of the TSAV field of the ADC TSMR regsiter. - * + * * Returned Value: * None * @@ -495,7 +495,7 @@ static void sam_tsd_setaverage(struct sam_tsd_s *priv, uint32_t tsav) * * Input Parameters * arg - The touchscreen private data structure cast to (void *) - * + * * Returned Value: * None * diff --git a/nuttx/arch/arm/src/samd/Make.defs b/nuttx/arch/arm/src/samd/Make.defs index 602a0fbed..d1630b414 100644 --- a/nuttx/arch/arm/src/samd/Make.defs +++ b/nuttx/arch/arm/src/samd/Make.defs @@ -33,7 +33,7 @@ # ############################################################################ -HEAD_ASRC = +HEAD_ASRC = CMN_ASRCS = up_exception.S up_saveusercontext.S up_fullcontextrestore.S CMN_ASRCS += up_switchcontext.S vfork.S @@ -67,7 +67,7 @@ ifeq ($(CONFIG_DEBUG),y) CMN_CSRCS += up_dumpnvic.c endif -CHIP_ASRCS = +CHIP_ASRCS = CHIP_CSRCS = sam_clockconfig.c sam_idle.c sam_irq.c sam_lowputc.c CHIP_CSRCS += sam_port.c sam_sercom.c sam_serial.c sam_start.c CHIP_CSRCS += sam_timerisr.c sam_usart.c diff --git a/nuttx/arch/arm/src/samd/sam_clockconfig.c b/nuttx/arch/arm/src/samd/sam_clockconfig.c index 7556d3b79..0fef4a3b3 100644 --- a/nuttx/arch/arm/src/samd/sam_clockconfig.c +++ b/nuttx/arch/arm/src/samd/sam_clockconfig.c @@ -821,7 +821,7 @@ static inline void sam_gclk_config(FAR const struct sam_gclkconfig_s *config) /* Wait for synchronization */ sam_gclck_waitsyncbusy(); - + /* Select the generator */ putreg32(((uint32_t)config->gclk << GCLK_GENDIV_ID_SHIFT), @@ -897,7 +897,7 @@ static inline void sam_config_gclks(void) /* Wait for the reset to complete */ while ((getreg8(SAM_GCLK_CTRL) & GCLK_CTRL_SWRST) != 0); - + /* Configure all GCLK generators, skipping GLCK_MAIN which is configured * below. */ diff --git a/nuttx/arch/arm/src/samd/sam_idle.c b/nuttx/arch/arm/src/samd/sam_idle.c index ea18904bf..8b8d3565b 100644 --- a/nuttx/arch/arm/src/samd/sam_idle.c +++ b/nuttx/arch/arm/src/samd/sam_idle.c @@ -87,7 +87,7 @@ static void up_idlepm(void) enum pm_state_e newstate; irqstate_t flags; int ret; - + /* Decide, which power saving level can be obtained */ newstate = pm_checkstate(); diff --git a/nuttx/arch/arm/src/samd/sam_port.c b/nuttx/arch/arm/src/samd/sam_port.c index 42a732227..8614383ee 100644 --- a/nuttx/arch/arm/src/samd/sam_port.c +++ b/nuttx/arch/arm/src/samd/sam_port.c @@ -177,8 +177,8 @@ static inline void sam_configinput(uintptr_t base, port_pinset_t pinset) break; } - /* Configure the pin as an input */ - + /* Configure the pin as an input */ + putreg32(regval, base + SAM_PORT_WRCONFIG_OFFSET); } @@ -281,8 +281,8 @@ static inline void sam_configoutput(uintptr_t base, port_pinset_t pinset) regval |= PORT_WRCONFIG_DRVSTR; } - /* Configure the pin as an output */ - + /* Configure the pin as an output */ + putreg32(regval, base + SAM_PORT_WRCONFIG_OFFSET); } @@ -356,8 +356,8 @@ static inline void sam_configperiph(uintptr_t base, port_pinset_t pinset) break; } - /* Configure the pin for the peripheral function */ - + /* Configure the pin for the peripheral function */ + putreg32(regval, base + SAM_PORT_WRCONFIG_OFFSET); } @@ -410,7 +410,7 @@ static inline void sam_configreset(uintptr_t base, port_pinset_t pinset) /* Disable the peripheral multiplexor, disable the input, disable * pull-up/down, reset driver strength, etc. */ - + putreg32(regval, base + SAM_PORT_WRCONFIG_OFFSET); } diff --git a/nuttx/arch/arm/src/samd/sam_userspace.c b/nuttx/arch/arm/src/samd/sam_userspace.c index 71bbb1ba3..0f40d617e 100644 --- a/nuttx/arch/arm/src/samd/sam_userspace.c +++ b/nuttx/arch/arm/src/samd/sam_userspace.c @@ -97,7 +97,7 @@ void sam_userspace(void) /* Initialize all of user-space .data */ DEBUGASSERT(USERSPACE->us_datasource != 0 && - USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && + USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && USERSPACE->us_datastart <= USERSPACE->us_dataend); src = (uint8_t*)USERSPACE->us_datasource; diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_eth.h b/nuttx/arch/arm/src/stm32/chip/stm32_eth.h index 92a229ccc..e074c520c 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32_eth.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32_eth.h @@ -754,7 +754,7 @@ #define ETH_RDES4_IPPT_SHIFT (0) /* Bits 0-2: IP payload type */ #define ETH_RDES4_IPPT_MASK (7 << ETH_RDES4_IPPT_SHIFT) # define ETH_RDES4_IPPT_UDP (1 << ETH_RDES4_IPPT_SHIFT) /* UDP payload in IP datagram */ -# define ETH_RDES4_IPPT_TCP (2 << ETH_RDES4_IPPT_SHIFT) /* TCP payload in IP datagram */ +# define ETH_RDES4_IPPT_TCP (2 << ETH_RDES4_IPPT_SHIFT) /* TCP payload in IP datagram */ # define ETH_RDES4_IPPT_ICMP (3 << ETH_RDES4_IPPT_SHIFT) /* ICMP payload in IP datagram */ #define ETH_RDES4_IPHE (1 << 3) /* Bit 3: IP header error */ #define ETH_RDES4_IPPE (1 << 4) /* Bit 4: IP payload error */ @@ -791,7 +791,7 @@ #ifndef __ASSEMBLY__ -/* Ethernet TX DMA Descriptor */ +/* Ethernet TX DMA Descriptor */ struct eth_txdesc_s { @@ -812,7 +812,7 @@ struct eth_txdesc_s #endif }; -/* Ethernet RX DMA Descriptor */ +/* Ethernet RX DMA Descriptor */ struct eth_rxdesc_s { diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_otgfs.h b/nuttx/arch/arm/src/stm32/chip/stm32_otgfs.h index 7c574f3b0..b9ec9cfa8 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32_otgfs.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32_otgfs.h @@ -160,7 +160,7 @@ #define STM32_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */ #define STM32_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */ -#define STM32_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5)) +#define STM32_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5)) #define STM32_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */ #define STM32_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */ #define STM32_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */ diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_rtc.h b/nuttx/arch/arm/src/stm32/chip/stm32_rtc.h index f96f704b1..e5004c5ab 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32_rtc.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32_rtc.h @@ -44,7 +44,7 @@ #define STM32_RTC_CRH_OFFSET 0x0000 /* RTC control register High (16-bit) */ #define STM32_RTC_CRL_OFFSET 0x0004 /* RTC control register low (16-bit) */ -#define STM32_RTC_PRLH_OFFSET 0x0008 /* RTC prescaler load register high (16-bit) */ +#define STM32_RTC_PRLH_OFFSET 0x0008 /* RTC prescaler load register high (16-bit) */ #define STM32_RTC_PRLL_OFFSET 0x000c /* RTC prescaler load register low (16-bit) */ #define STM32_RTC_DIVH_OFFSET 0x0010 /* RTC prescaler divider register high (16-bit) */ #define STM32_RTC_DIVL_OFFSET 0x0014 /* RTC prescaler divider register low (16-bit) */ diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_gpio.h b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_gpio.h index d339fc15e..11c333434 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_gpio.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_gpio.h @@ -271,12 +271,12 @@ #define AFIO_MAPR_USART1_REMAP (1 << 2) /* Bit 2: USART1 remapping */ #define AFIO_MAPR_USART2_REMAP (1 << 3) /* Bit 3: USART2 remapping */ #define AFIO_MAPR_USART3_REMAP_SHIFT (4) /* Bits 5-4: USART3 remapping */ -#define AFIO_MAPR_USART3_REMAP_MASK (3 << AFIO_MAPR_USART3_REMAP_SHIFT) +#define AFIO_MAPR_USART3_REMAP_MASK (3 << AFIO_MAPR_USART3_REMAP_SHIFT) # define AFIO_MAPR_USART3_NOREMAP (0 << AFIO_MAPR_USART3_REMAP_SHIFT) /* 00: No remap */ # define AFIO_MAPR_USART3_PARTREMAP (1 << AFIO_MAPR_USART3_REMAP_SHIFT) /* 01: Partial remap */ # define AFIO_MAPR_USART3_FULLREMAP (3 << AFIO_MAPR_USART3_REMAP_SHIFT) /* 11: Full remap */ #define AFIO_MAPR_TIM1_REMAP_SHIFT (6) /* Bits 7-6: TIM1 remapping */ -#define AFIO_MAPR_TIM1_REMAP_MASK (3 << AFIO_MAPR_TIM1_REMAP_SHIFT) +#define AFIO_MAPR_TIM1_REMAP_MASK (3 << AFIO_MAPR_TIM1_REMAP_SHIFT) # define AFIO_MAPR_TIM1_NOREMAP (0 << AFIO_MAPR_TIM1_REMAP_SHIFT) /* 00: No remap */ # define AFIO_MAPR_TIM1_PARTREMAP (1 << AFIO_MAPR_TIM1_REMAP_SHIFT) /* 01: Partial remap */ # define AFIO_MAPR_TIM1_FULLREMAP (3 << AFIO_MAPR_TIM1_REMAP_SHIFT) /* 11: Full remap */ diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f20xxx_dma.h b/nuttx/arch/arm/src/stm32/chip/stm32f20xxx_dma.h index af4b361c2..1389c0eef 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f20xxx_dma.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f20xxx_dma.h @@ -89,7 +89,7 @@ #define STM32_DMA_S4CR_OFFSET 0x0070 /* DMA stream 4 configuration register */ #define STM32_DMA_S5CR_OFFSET 0x0088 /* DMA stream 5 configuration register */ #define STM32_DMA_S6CR_OFFSET 0x00a0 /* DMA stream 6 configuration register */ -#define STM32_DMA_S7CR_OFFSET 0x00b8 /* DMA stream 7 configuration register */ +#define STM32_DMA_S7CR_OFFSET 0x00b8 /* DMA stream 7 configuration register */ #define STM32_DMA_S0NDTR_OFFSET 0x0014 /* DMA stream 0 number of data register */ #define STM32_DMA_S1NDTR_OFFSET 0x002c /* DMA stream 1 number of data register */ diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h b/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h index 5fd8288bb..dc291ad29 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h @@ -39,7 +39,7 @@ /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ - + /* STM32F40XXX Address Blocks *******************************************************/ #define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_dma.h b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_dma.h index 6ba868b96..b7bf7b1a8 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_dma.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_dma.h @@ -89,7 +89,7 @@ #define STM32_DMA_S4CR_OFFSET 0x0070 /* DMA stream 4 configuration register */ #define STM32_DMA_S5CR_OFFSET 0x0088 /* DMA stream 5 configuration register */ #define STM32_DMA_S6CR_OFFSET 0x00a0 /* DMA stream 6 configuration register */ -#define STM32_DMA_S7CR_OFFSET 0x00b8 /* DMA stream 7 configuration register */ +#define STM32_DMA_S7CR_OFFSET 0x00b8 /* DMA stream 7 configuration register */ #define STM32_DMA_S0NDTR_OFFSET 0x0014 /* DMA stream 0 number of data register */ #define STM32_DMA_S1NDTR_OFFSET 0x002c /* DMA stream 1 number of data register */ diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h index 6647c8851..3e4c9f6a0 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h @@ -39,7 +39,7 @@ /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ - + /* STM32F40XXX Address Blocks *******************************************************/ #define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ diff --git a/nuttx/arch/arm/src/stm32/chip/stm32l15xxx_memorymap.h b/nuttx/arch/arm/src/stm32/chip/stm32l15xxx_memorymap.h index cb37a16f6..4ada87f0d 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32l15xxx_memorymap.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32l15xxx_memorymap.h @@ -41,7 +41,7 @@ /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ - + /* STM32F40XXX Address Blocks *******************************************************/ #define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ diff --git a/nuttx/arch/arm/src/stm32/chip/stm32l15xxx_pinmap.h b/nuttx/arch/arm/src/stm32/chip/stm32l15xxx_pinmap.h index f0547c9ef..1a9264c38 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32l15xxx_pinmap.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32l15xxx_pinmap.h @@ -45,7 +45,7 @@ /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* Alternate Pin Functions. +/* Alternate Pin Functions. * * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. * Drivers, however, will use the pin selection without the numeric suffix. diff --git a/nuttx/arch/arm/src/stm32/stm32_allocateheap.c b/nuttx/arch/arm/src/stm32/stm32_allocateheap.c index 7ffa2e042..50fb9037e 100644 --- a/nuttx/arch/arm/src/stm32/stm32_allocateheap.c +++ b/nuttx/arch/arm/src/stm32/stm32_allocateheap.c @@ -112,7 +112,7 @@ # define CONFIG_STM32_CCMEXCLUDE 1 /* Only one memory region can be support (internal SRAM) */ - + # if CONFIG_MM_REGIONS > 1 # error "CONFIG_MM_REGIONS > 1. The STM32L15X has only one memory region." # endif @@ -239,7 +239,7 @@ * regions are contiguous and treated as one in this logic that extends to * 0x2002:0000 (or 0x2003:0000 for the F427/F437/F429/F439). * - * As a complication, CCM SRAM cannot be used for DMA. So, if STM32 DMA is enabled, + * As a complication, CCM SRAM cannot be used for DMA. So, if STM32 DMA is enabled, * CCM SRAM should probably be excluded from the heap or the application must take * extra care to ensure that DMA buffers are not allocated in CCM SRAM. * @@ -347,7 +347,7 @@ # undef CONFIG_STM32_CCMEXCLUDE # define CONFIG_STM32_CCMEXCLUDE 1 # endif - + # elif !defined(CONFIG_STM32_CCMEXCLUDE) /* Configuration 2: FSMC SRAM is not used, but CCM SRAM is requested. DMA diff --git a/nuttx/arch/arm/src/stm32/stm32_dac.h b/nuttx/arch/arm/src/stm32/stm32_dac.h index 44404e6fb..0be2b6b37 100644 --- a/nuttx/arch/arm/src/stm32/stm32_dac.h +++ b/nuttx/arch/arm/src/stm32/stm32_dac.h @@ -52,7 +52,7 @@ ************************************************************************************/ /* Configuration ********************************************************************/ /* Timer devices may be used for different purposes. One special purpose is to - * control periodic DAC outputs. If CONFIG_STM32_TIMn is defined then + * control periodic DAC outputs. If CONFIG_STM32_TIMn is defined then * CONFIG_STM32_TIMn_DAC must also be defined to indicate that timer "n" is intended * to be used for that purpose. */ diff --git a/nuttx/arch/arm/src/stm32/stm32_idle.c b/nuttx/arch/arm/src/stm32/stm32_idle.c index e8b51caa5..54e18101e 100644 --- a/nuttx/arch/arm/src/stm32/stm32_idle.c +++ b/nuttx/arch/arm/src/stm32/stm32_idle.c @@ -88,7 +88,7 @@ static void up_idlepm(void) enum pm_state_e newstate; irqstate_t flags; int ret; - + /* Decide, which power saving level can be obtained */ newstate = pm_checkstate(); @@ -192,7 +192,7 @@ void up_idle(void) * perform any AHB master accesses during sleep mode." * * Workaround - * Enable DMA1 or DMA2 clocks in the RCC_AHBENR register before + * Enable DMA1 or DMA2 clocks in the RCC_AHBENR register before * executing the WFI/WFE instruction." * * Here the workaround is just to avoid SLEEP mode for the connectivity diff --git a/nuttx/arch/arm/src/stm32/stm32_iwdg.c b/nuttx/arch/arm/src/stm32/stm32_iwdg.c index e81f93949..e72165018 100644 --- a/nuttx/arch/arm/src/stm32/stm32_iwdg.c +++ b/nuttx/arch/arm/src/stm32/stm32_iwdg.c @@ -418,7 +418,7 @@ static int stm32_keepalive(FAR struct watchdog_lowerhalf_s *lower) irqstate_t flags; wdvdbg("Entry\n"); - + /* Reload the IWDG timer */ flags = irqsave(); @@ -600,7 +600,7 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower, * So we want: * timeout = 1000 * reload / Fiwdg */ - + priv->timeout = (1000 * (uint32_t)reload) / fiwdg; /* Save setup values for later use */ @@ -619,7 +619,7 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower, /* If CONFIG_STM32_IWDG_DEFERREDSETUP is selected, then perform the register * configuration only if the timer has been started. */ - + #ifdef CONFIG_STM32_IWDG_DEFERREDSETUP if (priv->started) #endif diff --git a/nuttx/arch/arm/src/stm32/stm32_ltdc.c b/nuttx/arch/arm/src/stm32/stm32_ltdc.c index d9cf1f7f4..bd27ee1f0 100644 --- a/nuttx/arch/arm/src/stm32/stm32_ltdc.c +++ b/nuttx/arch/arm/src/stm32/stm32_ltdc.c @@ -219,7 +219,7 @@ #define STM32_LTDC_BUFFER_L1 STM32_LTDC_BUFFER_START #define STM32_LTDC_ENDBUF_L1 (STM32_LTDC_BUFFER_L1 + STM32_L1_FBSIZE) -#ifdef CONFIG_STM32_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 # define STM32_LTDC_BUFFER_L2 STM32_LTDC_ENDBUF_L1 # define STM32_LTDC_ENDBUF_L2 (STM32_LTDC_BUFFER_L2 + STM32_L2_FBSIZE) #else @@ -728,7 +728,7 @@ static void stm32_config_lcd_clock(void) * Name: stm32_show_layer * * Description: - * Show the given layer with the specified window + * Show the given layer with the specified window * ****************************************************************************/ diff --git a/nuttx/arch/arm/src/stm32/stm32_pm.h b/nuttx/arch/arm/src/stm32/stm32_pm.h index be040d296..d6dbe5245 100644 --- a/nuttx/arch/arm/src/stm32/stm32_pm.h +++ b/nuttx/arch/arm/src/stm32/stm32_pm.h @@ -75,7 +75,7 @@ extern "C" { * Name: stm32_pmstop * * Description: - * Enter STOP mode. + * Enter STOP mode. * * Input Parameters: * lpds - true: To further reduce power consumption in Stop mode, put the @@ -115,11 +115,11 @@ EXTERN int stm32_pmstandby(void); * Name: stm32_pmsleep * * Description: - * Enter SLEEP mode. + * Enter SLEEP mode. * * Input Parameters: * sleeponexit - true: SLEEPONEXIT bit is set when the WFI instruction is - * executed, the MCU enters Sleep mode as soon as it + * executed, the MCU enters Sleep mode as soon as it * exits the lowest priority ISR. * - false: SLEEPONEXIT bit is cleared, the MCU enters Sleep mode * as soon as WFI or WFE instruction is executed. diff --git a/nuttx/arch/arm/src/stm32/stm32_pmsleep.c b/nuttx/arch/arm/src/stm32/stm32_pmsleep.c index 3027b99a7..49ebf1ce7 100644 --- a/nuttx/arch/arm/src/stm32/stm32_pmsleep.c +++ b/nuttx/arch/arm/src/stm32/stm32_pmsleep.c @@ -68,11 +68,11 @@ * Name: stm32_pmsleep * * Description: - * Enter SLEEP mode. + * Enter SLEEP mode. * * Input Parameters: * sleeponexit - true: SLEEPONEXIT bit is set when the WFI instruction is - * executed, the MCU enters Sleep mode as soon as it + * executed, the MCU enters Sleep mode as soon as it * exits the lowest priority ISR. * - false: SLEEPONEXIT bit is cleared, the MCU enters Sleep mode * as soon as WFI or WFE instruction is executed. diff --git a/nuttx/arch/arm/src/stm32/stm32_pmstandby.c b/nuttx/arch/arm/src/stm32/stm32_pmstandby.c index 467edaec2..2b4de6a6f 100644 --- a/nuttx/arch/arm/src/stm32/stm32_pmstandby.c +++ b/nuttx/arch/arm/src/stm32/stm32_pmstandby.c @@ -101,7 +101,7 @@ int stm32_pmstandby(void) regval = getreg32(NVIC_SYSCON); regval |= NVIC_SYSCON_SLEEPDEEP; putreg32(regval, NVIC_SYSCON); - + /* Sleep until the wakeup reset occurs */ asm("wfi"); diff --git a/nuttx/arch/arm/src/stm32/stm32_pmstop.c b/nuttx/arch/arm/src/stm32/stm32_pmstop.c index 14ce63b55..bde0334ec 100644 --- a/nuttx/arch/arm/src/stm32/stm32_pmstop.c +++ b/nuttx/arch/arm/src/stm32/stm32_pmstop.c @@ -66,7 +66,7 @@ * Name: stm32_pmstop * * Description: - * Enter STOP mode. + * Enter STOP mode. * * Input Parameters: * lpds - true: To further reduce power consumption in Stop mode, put the @@ -98,7 +98,7 @@ int stm32_pmstop(bool lpds) { regval |= PWR_CR_LPDS; } - + putreg32(regval, STM32_PWR_CR); /* Set SLEEPDEEP bit of Cortex System Control Register */ @@ -106,7 +106,7 @@ int stm32_pmstop(bool lpds) regval = getreg32(NVIC_SYSCON); regval |= NVIC_SYSCON_SLEEPDEEP; putreg32(regval, NVIC_SYSCON); - + /* Sleep until the wakeup interrupt or event occurs */ #ifdef CONFIG_PM_WFE @@ -116,7 +116,7 @@ int stm32_pmstop(bool lpds) #else /* Mode: SLEEP + Entry with WFI */ - asm("wfi"); + asm("wfi"); #endif return OK; } diff --git a/nuttx/arch/arm/src/stm32/stm32_pwr.h b/nuttx/arch/arm/src/stm32/stm32_pwr.h index 63ae14429..2ec3de6dc 100644 --- a/nuttx/arch/arm/src/stm32/stm32_pwr.h +++ b/nuttx/arch/arm/src/stm32/stm32_pwr.h @@ -62,7 +62,7 @@ extern "C" { /************************************************************************************ * Public Functions ************************************************************************************/ - + /************************************************************************************ * Name: stm32_pwr_enablebkp * diff --git a/nuttx/arch/arm/src/stm32/stm32_qencoder.c b/nuttx/arch/arm/src/stm32/stm32_qencoder.c index 5e99b05a8..4e19d4c2e 100644 --- a/nuttx/arch/arm/src/stm32/stm32_qencoder.c +++ b/nuttx/arch/arm/src/stm32/stm32_qencoder.c @@ -589,7 +589,7 @@ static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, FAR const char *msg) * Name: stm32_tim2lower * * Description: - * Map a timer number to a device structure + * Map a timer number to a device structure * ************************************************************************************/ @@ -671,7 +671,7 @@ static int stm32_interrupt(FAR struct stm32_lowerhalf_s *priv) * Name: stm32_intNinterrupt * * Description: - * TIMN interrupt handler + * TIMN interrupt handler * ************************************************************************************/ @@ -723,7 +723,7 @@ static int stm32_tim8interrupt(int irq, FAR void *context) * Description: * This method is called when the driver is opened. The lower half driver * should configure and initialize the device so that it is ready for use. - * The initial position value should be zero. * + * The initial position value should be zero. * * ************************************************************************************/ @@ -779,7 +779,7 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower) stm32_putreg16(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); #if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) - if (priv->config->timid == 1 || priv->config->timid == 8) + if (priv->config->timid == 1 || priv->config->timid == 8) { /* Clear the Repetition Counter value */ @@ -797,7 +797,7 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower) stm32_configgpio(priv->config->ti1cfg); stm32_configgpio(priv->config->ti2cfg); - + /* Set the encoder Mode 3 */ smcr = stm32_getreg16(priv, STM32_GTIM_SMCR_OFFSET); @@ -830,7 +830,7 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower) stm32_putreg16(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - + /* Set the Input Capture Prescaler value: Capture performed each time an * edge is detected on the capture input. */ @@ -896,7 +896,7 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower) stm32_shutdown(lower); return ret; } - + /* Enable the update/global interrupt at the NVIC */ up_enable_irq(priv->config->irq); @@ -908,7 +908,7 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower) cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); cr1 &= ~GTIM_CR1_UDIS; stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - + /* Reset the URS Bit */ cr1 &= ~GTIM_CR1_URS; @@ -949,7 +949,7 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower) * Description: * This method is called when the driver is closed. The lower half driver * should stop data collection, free any resources, disable timer hardware, and - * put the system into the lowest possible power usage state * + * put the system into the lowest possible power usage state * * ************************************************************************************/ @@ -964,9 +964,9 @@ static int stm32_shutdown(FAR struct qe_lowerhalf_s *lower) /* Disable the update/global interrupt at the NVIC */ - flags = irqsave(); + flags = irqsave(); up_disable_irq(priv->config->irq); - + /* Detach the interrupt handler */ (void)irq_detach(priv->config->irq); diff --git a/nuttx/arch/arm/src/stm32/stm32_rtcounter.c b/nuttx/arch/arm/src/stm32/stm32_rtcounter.c index 0238582e4..5ffb1a313 100644 --- a/nuttx/arch/arm/src/stm32/stm32_rtcounter.c +++ b/nuttx/arch/arm/src/stm32/stm32_rtcounter.c @@ -41,16 +41,16 @@ /* The STM32 RTC Driver offers standard precision of 1 Hz or High Resolution * operating at rate up to 16384 Hz. It provides UTC time and alarm interface * with external output pin (for wake-up). - * - * RTC is based on hardware RTC module which is located in a separate power - * domain. The 32-bit counter is extended by 16-bit registers in BKP domain + * + * RTC is based on hardware RTC module which is located in a separate power + * domain. The 32-bit counter is extended by 16-bit registers in BKP domain * STM32_BKP_DR1 to provide system equiv. function to the: time_t time(time_t *). - * - * Notation: + * + * Notation: * - clock refers to 32-bit hardware counter * - time is a combination of clock and upper bits stored in backuped domain * with unit of 1 [s] - * + * * TODO: Error Handling in case LSE fails during start-up or during operation. */ @@ -164,7 +164,7 @@ static alarmcb_t g_alarmcb; * Public Data ************************************************************************************/ -/* Variable determines the state of the LSE oscilator. +/* Variable determines the state of the LSE oscilator. * Possible errors: * - on start-up * - during operation, reported by LSE interrupt @@ -267,7 +267,7 @@ static void up_rtc_breakout(FAR const struct timespec *tp, uint64_t frac; uint32_t cnt; uint16_t ovf; - + /* Break up the time in seconds + milleconds into the correct values for our use */ frac = ((uint64_t)tp->tv_nsec * CONFIG_RTC_FREQUENCY) / 1000000000; @@ -331,8 +331,8 @@ static int stm32_rtc_interrupt(int irq, void *context) #endif /* Clear pending flags, leave RSF high */ - - putreg16(RTC_CRL_RSF, STM32_RTC_CRL); + + putreg16(RTC_CRL_RSF, STM32_RTC_CRL); return 0; } #endif @@ -365,8 +365,8 @@ int up_rtcinitialize(void) stm32_pwr_enablebkp(); stm32_rcc_enablelse(); - - /* TODO: Get state from this function, if everything is + + /* TODO: Get state from this function, if everything is * okay and whether it is already enabled (if it was disabled * reset upper time register) */ @@ -541,7 +541,7 @@ int up_rtc_gettime(FAR struct timespec *tp) ls = (uint32_t)cnth << 16 | (uint32_t)cntl; ms = (uint32_t)ovf << 16 | (uint32_t)cnth; - + /* Then we can save the time in seconds and fractional seconds. */ tp->tv_sec = (ms << (32-RTC_CLOCKS_SHIFT-16)) | (ls >> (RTC_CLOCKS_SHIFT+16)); @@ -623,11 +623,11 @@ int up_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback) g_alarmcb = callback; /* Break out the time values */ - + up_rtc_breakout(tp, ®vals); /* Enable RTC alarm */ - + cr = getreg16(STM32_RTC_CRH); cr |= RTC_CRH_ALRIE; putreg16(cr, STM32_RTC_CRH); @@ -651,7 +651,7 @@ int up_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback) * Name: up_rtc_cancelalarm * * Description: - * Cancel a pending alarm alarm + * Cancel a pending alarm alarm * * Input Parameters: * none @@ -682,7 +682,7 @@ int up_rtc_cancelalarm(void) stm32_rtc_endwr(); irqrestore(flags); - ret = OK; + ret = OK; } return ret; } diff --git a/nuttx/arch/arm/src/stm32/stm32_sdio.h b/nuttx/arch/arm/src/stm32/stm32_sdio.h index ceeb56f0d..61046dad0 100644 --- a/nuttx/arch/arm/src/stm32/stm32_sdio.h +++ b/nuttx/arch/arm/src/stm32/stm32_sdio.h @@ -88,7 +88,7 @@ EXTERN FAR struct sdio_dev_s *sdio_initialize(int slotno); * * Input Parameters: * dev - An instance of the SDIO driver device state structure. - * cardinslot - true is a card has been detected in the slot; false if a + * cardinslot - true is a card has been detected in the slot; false if a * card has been removed from the slot. Only transitions * (inserted->removed or removed->inserted should be reported) * diff --git a/nuttx/arch/arm/src/stm32/stm32_spi.h b/nuttx/arch/arm/src/stm32/stm32_spi.h index 62f304dfb..2ee090958 100644 --- a/nuttx/arch/arm/src/stm32/stm32_spi.h +++ b/nuttx/arch/arm/src/stm32/stm32_spi.h @@ -88,13 +88,13 @@ enum spi_dev_e; * board-specific logic. These functions will perform chip selection and * status operations using GPIOs in the way your board is configured. * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, then - * provide stm32_spi1/2/...cmddata() functions in your board-specific logic. + * provide stm32_spi1/2/...cmddata() functions in your board-specific logic. * These functions will perform cmd/data selection operations using GPIOs in the * way your board is configured. * 4. Add a calls to up_spiinitialize() in your low level application * initialization logic * 5. The handle returned by up_spiinitialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * diff --git a/nuttx/arch/arm/src/stm32/stm32_userspace.c b/nuttx/arch/arm/src/stm32/stm32_userspace.c index c51e9e725..b68705dce 100644 --- a/nuttx/arch/arm/src/stm32/stm32_userspace.c +++ b/nuttx/arch/arm/src/stm32/stm32_userspace.c @@ -98,7 +98,7 @@ void stm32_userspace(void) /* Initialize all of user-space .data */ DEBUGASSERT(USERSPACE->us_datasource != 0 && - USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && + USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && USERSPACE->us_datastart <= USERSPACE->us_dataend); src = (uint8_t*)USERSPACE->us_datasource; diff --git a/nuttx/arch/arm/src/stm32/stm32_waste.h b/nuttx/arch/arm/src/stm32/stm32_waste.h index fa734f432..6906c7aa4 100644 --- a/nuttx/arch/arm/src/stm32/stm32_waste.h +++ b/nuttx/arch/arm/src/stm32/stm32_waste.h @@ -57,7 +57,7 @@ extern "C" { ****************************************************************************/ /** Waste CPU Time - * + * * up_waste() is the logic that will be executed when portions of kernel * or user-app is polling some register or similar, waiting for desired * status. This time is wasted away. This function offers a measure of diff --git a/nuttx/arch/arm/src/stm32/stm32_wwdg.c b/nuttx/arch/arm/src/stm32/stm32_wwdg.c index dc6967215..2b4f54868 100644 --- a/nuttx/arch/arm/src/stm32/stm32_wwdg.c +++ b/nuttx/arch/arm/src/stm32/stm32_wwdg.c @@ -456,7 +456,7 @@ static int stm32_getstatus(FAR struct watchdog_lowerhalf_s *lower, { status->flags |= WDFLAGS_ACTIVE; } - + if (priv->handler) { status->flags |= WDFLAGS_CAPTURE; @@ -595,7 +595,7 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower, wdvdbg("wdgtb=%d fwwdg=%d reload=%d timout=%d\n", wdgtb, fwwdg, reload, priv->timeout); - + /* Set WDGTB[1:0] bits according to calculated value */ regval = stm32_getreg(STM32_WWDG_CFR); @@ -662,7 +662,7 @@ static xcpt_t stm32_capture(FAR struct watchdog_lowerhalf_s *lower, regval |= WWDG_CFR_EWI; stm32_putreg(regval, STM32_WWDG_CFR); - + up_enable_irq(STM32_IRQ_WWDG); } else @@ -716,7 +716,7 @@ static int stm32_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd, if (cmd == WDIOC_MINTIME) { uint32_t mintime = (uint32_t)arg; - + /* The minimum time should be strictly less than the total delay * which, in turn, will be less than or equal to WWDG_CR_T_MAX */ diff --git a/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c b/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c index 4c74fa912..46e847e54 100644 --- a/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c +++ b/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c @@ -86,7 +86,7 @@ static inline void rcc_reset(void) regval = getreg32(STM32_RCC_CR); regval &= ~(RCC_CR_HSEON|RCC_CR_CSSON|RCC_CR_PLLON); putreg32(regval, STM32_RCC_CR); - + /* Reset PLLCFGR register to reset default */ putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG); @@ -586,7 +586,7 @@ static inline void rcc_enableapb2(void) * * Description: * Called to change to new clock based on settings in board.h - * + * * NOTE: This logic would need to be extended if you need to select low- * power clocking modes! ****************************************************************************/ @@ -598,7 +598,7 @@ static void stm32_stdclockconfig(void) volatile int32_t timeout; /* Enable External High-Speed Clock (HSE) */ - + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEON; /* Enable HSE */ putreg32(regval, STM32_RCC_CR); @@ -642,7 +642,7 @@ static void stm32_stdclockconfig(void) putreg32(regval, STM32_PWR_CR); /* Set the HCLK source/divider */ - + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; regval |= STM32_RCC_CFGR_HPRE; @@ -654,7 +654,7 @@ static void stm32_stdclockconfig(void) regval &= ~RCC_CFGR_PPRE2_MASK; regval |= STM32_RCC_CFGR_PPRE2; putreg32(regval, STM32_RCC_CFGR); - + /* Set the PCLK1 divider */ regval = getreg32(STM32_RCC_CFGR); @@ -673,13 +673,13 @@ static void stm32_stdclockconfig(void) regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; putreg32(regval, STM32_RCC_CR); - + /* Wait until the PLL is ready */ - + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } - + #if defined(CONFIG_STM32_STM32F429) /* Enable the Over-drive to extend the clock frequency to 180 Mhz */ @@ -716,7 +716,7 @@ static void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } diff --git a/nuttx/arch/arm/src/str71x/Make.defs b/nuttx/arch/arm/src/str71x/Make.defs index 5da6fd5b7..1978c2dff 100644 --- a/nuttx/arch/arm/src/str71x/Make.defs +++ b/nuttx/arch/arm/src/str71x/Make.defs @@ -56,7 +56,7 @@ ifeq ($(CONFIG_DEBUG_STACK),y) CMN_CSRCS += up_checkstack.c endif -CHIP_ASRCS = +CHIP_ASRCS = CHIP_CSRCS = str71x_prccu.c str71x_lowputc.c str71x_decodeirq.c str71x_irq.c \ str71x_timerisr.c str71x_serial.c diff --git a/nuttx/arch/arm/src/str71x/str71x_head.S b/nuttx/arch/arm/src/str71x/str71x_head.S index d5b40de3d..098d238ff 100644 --- a/nuttx/arch/arm/src/str71x/str71x_head.S +++ b/nuttx/arch/arm/src/str71x/str71x_head.S @@ -265,7 +265,7 @@ * * IRQs and FIQs are disabled * IVR set to zero - * All channels are disabled + * All channels are disabled * Channels set to priority 0 * All SIR[n] registers contain the NuttX IRQ number in the MS 16-bits * diff --git a/nuttx/arch/arm/src/str71x/str71x_lowputc.c b/nuttx/arch/arm/src/str71x/str71x_lowputc.c index fde33adb4..6473e60be 100644 --- a/nuttx/arch/arm/src/str71x/str71x_lowputc.c +++ b/nuttx/arch/arm/src/str71x/str71x_lowputc.c @@ -295,7 +295,7 @@ void up_lowsetup(void) #endif /* Configure GPIO0 pins to enable all UARTs in the configuration - * (the serial driver later depends on this configuration) + * (the serial driver later depends on this configuration) */ #if HAVE_UART diff --git a/nuttx/arch/arm/src/str71x/str71x_serial.c b/nuttx/arch/arm/src/str71x/str71x_serial.c index 2f4e56ff0..a3351eb5f 100644 --- a/nuttx/arch/arm/src/str71x/str71x_serial.c +++ b/nuttx/arch/arm/src/str71x/str71x_serial.c @@ -925,7 +925,7 @@ static bool up_txempty(struct uart_dev_s *dev) * Name: up_serialinit * * Description: - * Performs the low level UART initialization early in + * Performs the low level UART initialization early in * debug so that the serial console will be available * during bootup. This must be called before up_serialinit. * diff --git a/nuttx/arch/arm/src/str71x/str71x_xti.c b/nuttx/arch/arm/src/str71x/str71x_xti.c index 3ef0a803d..118b0448b 100644 --- a/nuttx/arch/arm/src/str71x/str71x_xti.c +++ b/nuttx/arch/arm/src/str71x/str71x_xti.c @@ -205,9 +205,9 @@ int str71x_xticonfig(int irq, bool rising) /* Make sure that the interrupt is disabled */ str71x_disable_xtiirq(irq); - + /* Decide if we use the lower or upper regiser */ - + bit = irq - STR71X_IRQ_FIRSTXTI; ndx = 0; if (bit > 7) @@ -257,7 +257,7 @@ void str71x_enable_xtiirq(int irq) if (irq >= STR71X_IRQ_FIRSTXTI && irq <= NR_IRQS) { /* Decide if we use the lower or upper regiser */ - + bit = irq - STR71X_IRQ_FIRSTXTI; ndx = 0; if (bit > 7) @@ -297,7 +297,7 @@ void str71x_disable_xtiirq(int irq) if (irq >= STR71X_IRQ_FIRSTXTI && irq <= NR_IRQS) { /* Decide if we use the lower or upper regiser */ - + bit = irq - STR71X_IRQ_FIRSTXTI; ndx = 0; if (bit > 7) diff --git a/nuttx/arch/arm/src/tiva/chip/lm3s_memorymap.h b/nuttx/arch/arm/src/tiva/chip/lm3s_memorymap.h index b70b3a8aa..36dee7215 100644 --- a/nuttx/arch/arm/src/tiva/chip/lm3s_memorymap.h +++ b/nuttx/arch/arm/src/tiva/chip/lm3s_memorymap.h @@ -47,7 +47,7 @@ ************************************************************************************/ /* Memory map ***********************************************************************/ - + #if defined(CONFIG_ARCH_CHIP_LM3S6918) || defined(CONFIG_ARCH_CHIP_LM3S6432) || \ defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM3S8962) # define TIVA_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */ @@ -272,7 +272,7 @@ # define TIVA_FLASHCON_BASE (TIVA_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ # define TIVA_SYSCON_BASE (TIVA_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ /* -0x1ffffff: Reserved */ -#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) /* FiRM Peripheral Base Addresses */ # define TIVA_WDOG_BASE (TIVA_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ diff --git a/nuttx/arch/arm/src/tiva/chip/lm3s_pinmap.h b/nuttx/arch/arm/src/tiva/chip/lm3s_pinmap.h index 8c8da05ba..6f170ad19 100644 --- a/nuttx/arch/arm/src/tiva/chip/lm3s_pinmap.h +++ b/nuttx/arch/arm/src/tiva/chip/lm3s_pinmap.h @@ -169,7 +169,7 @@ # define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ # define GPIO_UART2_RX (GPIO_FUNC_PFINPUT | GPIO_PORTG | 0) /* PA0: UART 0 receive (UGRx) */ # define GPIO_UART2_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PA1: UART 0 transmit (UGTx) */ -#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) # define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ # define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ # define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ diff --git a/nuttx/arch/arm/src/tiva/tiva_ethernet.c b/nuttx/arch/arm/src/tiva/tiva_ethernet.c index 6afd0a2f9..070236827 100644 --- a/nuttx/arch/arm/src/tiva/tiva_ethernet.c +++ b/nuttx/arch/arm/src/tiva/tiva_ethernet.c @@ -71,7 +71,7 @@ #ifdef CONFIG_TIVA_ETHHDUPLEX # define TIVA_DUPLEX_SETBITS 0 # define TIVA_DUPLEX_CLRBITS MAC_TCTL_DUPLEX -#else +#else # define TIVA_DUPLEX_SETBITS MAC_TCTL_DUPLEX # define TIVA_DUPLEX_CLRBITS 0 #endif @@ -81,7 +81,7 @@ #ifdef CONFIG_TIVA_ETHNOAUTOCRC # define TIVA_CRC_SETBITS 0 # define TIVA_CRC_CLRBITS MAC_TCTL_CRC -#else +#else # define TIVA_CRC_SETBITS MAC_TCTL_CRC # define TIVA_CRC_CLRBITS 0 #endif @@ -91,7 +91,7 @@ #ifdef CONFIG_TIVA_ETHNOPAD # define TIVA_PADEN_SETBITS 0 # define TIVA_PADEN_CLRBITS MAC_TCTL_PADEN -#else +#else # define TIVA_PADEN_SETBITS MAC_TCTL_PADEN # define TIVA_PADEN_CLRBITS 0 #endif @@ -104,7 +104,7 @@ #ifdef CONFIG_TIVA_MULTICAST # define TIVA_AMUL_SETBITS MAC_RCTL_AMUL # define TIVA_AMUL_CLRBITS 0 -#else +#else # define TIVA_AMUL_SETBITS 0 # define TIVA_AMUL_CLRBITS MAC_RCTL_AMUL #endif @@ -114,7 +114,7 @@ #ifdef CONFIG_TIVA_PROMISCUOUS # define TIVA_PRMS_SETBITS MAC_RCTL_PRMS # define TIVA_PRMS_CLRBITS 0 -#else +#else # define TIVA_PRMS_SETBITS 0 # define TIVA_PRMS_CLRBITS MAC_RCTL_PRMS #endif @@ -124,7 +124,7 @@ #ifdef CONFIG_TIVA_BADCRC # define TIVA_BADCRC_SETBITS MAC_RCTL_BADCRC # define TIVA_BADCRC_CLRBITS 0 -#else +#else # define TIVA_BADCRC_SETBITS 0 # define TIVA_BADCRC_CLRBITS MAC_RCTL_BADCRC #endif @@ -921,7 +921,7 @@ static int tiva_interrupt(int irq, FAR void *context) tiva_txdone(priv); } - /* Enable Ethernet interrupts (perhaps excluding the TX done interrupt if + /* Enable Ethernet interrupts (perhaps excluding the TX done interrupt if * there are no pending transmissions). */ @@ -1012,7 +1012,7 @@ static void tiva_polltimer(int argc, uint32_t arg, ...) * * Description: * NuttX Callback: Bring up the Ethernet interface when an IP address is - * provided + * provided * * Parameters: * dev - Reference to the NuttX driver state structure @@ -1055,7 +1055,7 @@ static int tiva_ifup(struct uip_driver_s *dev) tiva_ethout(priv, TIVA_MAC_MDV_OFFSET, div); nllvdbg("MDV: %08x\n", div); - /* Then configure the Ethernet Controller for normal operation + /* Then configure the Ethernet Controller for normal operation * * Setup the transmit control register (Full duplex, TX CRC Auto Generation, * TX Padding Enabled). @@ -1250,7 +1250,7 @@ static int tiva_ifdown(struct uip_driver_s *dev) * Function: tiva_txavail * * Description: - * Driver callback invoked when new TX data is available. This is a + * Driver callback invoked when new TX data is available. This is a * stimulus perform an out-of-cycle poll and, thereby, reduce the TX * latency. * @@ -1301,7 +1301,7 @@ static int tiva_txavail(struct uip_driver_s *dev) * * Parameters: * dev - Reference to the NuttX driver state structure - * mac - The MAC address to be added + * mac - The MAC address to be added * * Returned Value: * None @@ -1331,7 +1331,7 @@ static int tiva_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac) * * Parameters: * dev - Reference to the NuttX driver state structure - * mac - The MAC address to be removed + * mac - The MAC address to be removed * * Returned Value: * None @@ -1416,7 +1416,7 @@ static inline int tiva_ethinitialize(int intf) /* If the board can provide us with a MAC address, get the address * from the board now. The MAC will not be applied until tiva_ifup() - * is caleld (and the MAC can be overwritten with a netdev ioctl call). + * is caleld (and the MAC can be overwritten with a netdev ioctl call). */ #ifdef CONFIG_TIVA_BOARDMAC diff --git a/nuttx/arch/arm/src/tiva/tiva_gpio.c b/nuttx/arch/arm/src/tiva/tiva_gpio.c index 335142ae9..e61d9f1b1 100644 --- a/nuttx/arch/arm/src/tiva/tiva_gpio.c +++ b/nuttx/arch/arm/src/tiva/tiva_gpio.c @@ -903,7 +903,7 @@ void tiva_gpiowrite(uint32_t pinset, bool value) * * "In order to write to GPIO DATA, the corresponding bits in the mask, * resulting from the address bus bits [9:2], must be High. Otherwise, the - * bit values remain unchanged by the write. + * bit values remain unchanged by the write. * * "... All bits are cleared by a reset." */ diff --git a/nuttx/arch/arm/src/tiva/tiva_serial.c b/nuttx/arch/arm/src/tiva/tiva_serial.c index 81b50f05e..c14edfad0 100644 --- a/nuttx/arch/arm/src/tiva/tiva_serial.c +++ b/nuttx/arch/arm/src/tiva/tiva_serial.c @@ -1250,7 +1250,7 @@ static bool up_txempty(struct uart_dev_s *dev) * Name: up_serialinit * * Description: - * Performs the low level UART initialization early in + * Performs the low level UART initialization early in * debug so that the serial console will be available * during bootup. This must be called before up_serialinit. * diff --git a/nuttx/arch/arm/src/tiva/tiva_ssi.c b/nuttx/arch/arm/src/tiva/tiva_ssi.c index d77a2edd6..8f1c0c79d 100644 --- a/nuttx/arch/arm/src/tiva/tiva_ssi.c +++ b/nuttx/arch/arm/src/tiva/tiva_ssi.c @@ -735,7 +735,7 @@ static inline void ssi_performrx(struct tiva_ssidev_s *priv) { /* There are no more outgoing words to send, but there are * additional incoming words expected (I would think that this - * a real corner case, be we will handle it with an extra + * a real corner case, be we will handle it with an extra * interrupt, probably an Rx timeout). */ @@ -1092,7 +1092,7 @@ static uint32_t ssi_setfrequencyinternal(struct tiva_ssidev_s *priv, * (FSysClk). The clock is first divided by an even prescale value * CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale * (SSI_CPSR) register ... The clock is further divided by a value - * from 1 to 256, which is 1 + SCR, where SCR is the value programmed + * from 1 to 256, which is 1 + SCR, where SCR is the value programmed * i n the SSI Control0 (SSICR0) register ... * * "The frequency of the output clock SSIClk is defined by: @@ -1462,7 +1462,7 @@ FAR struct spi_dev_s *up_spiinitialize(int port) uint8_t regval; ssidbg("port: %d\n", port); - + /* Set up for the selected port */ flags = irqsave(); diff --git a/nuttx/arch/arm/src/tiva/tiva_ssi.h b/nuttx/arch/arm/src/tiva/tiva_ssi.h index 7f8f87bb7..cac0f6cdc 100644 --- a/nuttx/arch/arm/src/tiva/tiva_ssi.h +++ b/nuttx/arch/arm/src/tiva/tiva_ssi.h @@ -92,7 +92,7 @@ extern "C" * 4. Add a call to up_spiinitialize() in your low level application * initialization logic * 5. The handle returned by up_spiinitialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * diff --git a/nuttx/arch/arm/src/tiva/tiva_userspace.c b/nuttx/arch/arm/src/tiva/tiva_userspace.c index 973fe44d8..e2b278024 100644 --- a/nuttx/arch/arm/src/tiva/tiva_userspace.c +++ b/nuttx/arch/arm/src/tiva/tiva_userspace.c @@ -98,7 +98,7 @@ void tiva_userspace(void) /* Initialize all of user-space .data */ DEBUGASSERT(USERSPACE->us_datasource != 0 && - USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && + USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && USERSPACE->us_datastart <= USERSPACE->us_dataend); src = (uint8_t*)USERSPACE->us_datasource; diff --git a/nuttx/arch/avr/include/at32uc3/irq.h b/nuttx/arch/avr/include/at32uc3/irq.h index 00802ebab..64861001e 100644 --- a/nuttx/arch/avr/include/at32uc3/irq.h +++ b/nuttx/arch/avr/include/at32uc3/irq.h @@ -63,7 +63,7 @@ # undef CONFIG_AVR32_GPIOIRQSETA # undef CONFIG_AVR32_GPIOIRQSETB #endif - + /* IRQ numbers **************************************************************/ /* Events. These exclude: * @@ -287,7 +287,7 @@ #if (CONFIG_AVR32_GPIOIRQSETA & 0x00000001) != 0 # define AVR32_IRQ_GPIO_PA0 __IRQ_GPPIO_PA0 # define __IRQ_GPIO_PA1 (__IRQ_GPPIO_PA0+1) -#else +#else # define __IRQ_GPIO_PA1 __IRQ_GPPIO_PA0 #endif diff --git a/nuttx/arch/avr/include/avr/irq.h b/nuttx/arch/avr/include/avr/irq.h index 9a84d1aa7..c237ded68 100644 --- a/nuttx/arch/avr/include/avr/irq.h +++ b/nuttx/arch/avr/include/avr/irq.h @@ -168,7 +168,7 @@ static inline irqstate_t irqsave(void) ( "\tin %0, __SREG__\n" "\tcli\n" - : "=&r" (sreg) :: + : "=&r" (sreg) :: ); return sreg; } diff --git a/nuttx/arch/avr/include/avr32/irq.h b/nuttx/arch/avr/include/avr32/irq.h index 09ee0296a..13326f0b7 100644 --- a/nuttx/arch/avr/include/avr32/irq.h +++ b/nuttx/arch/avr/include/avr32/irq.h @@ -66,7 +66,7 @@ * this makes it easier to following the ordering of pushing on a push-down * stack. */ - + #define REG_R8 16 #define REG_R9 15 #define REG_R10 14 diff --git a/nuttx/arch/avr/src/at32uc3/at32uc3_gpio.c b/nuttx/arch/avr/src/at32uc3/at32uc3_gpio.c index a0e39e19d..2a2996740 100644 --- a/nuttx/arch/avr/src/at32uc3/at32uc3_gpio.c +++ b/nuttx/arch/avr/src/at32uc3/at32uc3_gpio.c @@ -151,13 +151,13 @@ int at32uc3_configgpio(uint16_t cfgset) if ((cfgset & GPIO_ENABLE) != 0) { /* Its a GPIO. Input or output? */ - + if ((cfgset & GPIO_OUTPUT) != 0) { /* Its a GPIO output. Set up the initial output value and enable * the output driver. */ - + if ((cfgset & GPIO_VALUE) != 0) { putreg32(pinmask, base + AVR32_GPIO_OVRS_OFFSET); @@ -222,7 +222,7 @@ int at32uc3_configgpio(uint16_t cfgset) putreg32(pinmask, base + AVR32_GPIO_IERS_OFFSET); } - + return OK; } diff --git a/nuttx/arch/avr/src/at32uc3/at32uc3_gpioirq.c b/nuttx/arch/avr/src/at32uc3/at32uc3_gpioirq.c index c55ba3d13..d0442babc 100644 --- a/nuttx/arch/avr/src/at32uc3/at32uc3_gpioirq.c +++ b/nuttx/arch/avr/src/at32uc3/at32uc3_gpioirq.c @@ -177,7 +177,7 @@ static inline int gpio_pin(unsigned int irq) pinset >>= 1; } - + return -EINVAL; } @@ -309,7 +309,7 @@ void gpio_irqinitialize(void) } /* Then attach the GPIO interrupt handlers */ - + #if CONFIG_AVR32_GPIOIRQSETA != 0 irq_attach(AVR32_IRQ_GPIO0, gpio0_interrupt); #endif diff --git a/nuttx/arch/avr/src/at32uc3/at32uc3_lowconsole.c b/nuttx/arch/avr/src/at32uc3/at32uc3_lowconsole.c index 509d389af..d58558852 100644 --- a/nuttx/arch/avr/src/at32uc3/at32uc3_lowconsole.c +++ b/nuttx/arch/avr/src/at32uc3/at32uc3_lowconsole.c @@ -164,7 +164,7 @@ static void usart_setbaudrate(uintptr_t usart_base, uint32_t baudrate) mr &= ~USART_MR_SYNC; mr |= USART_MR_OVER; - + /* Calculate the clock divider assuming 16x oversampling */ cd = (AVR32_PBA_CLOCK + (baudrate << 2)) / (baudrate << 3); @@ -177,7 +177,7 @@ static void usart_setbaudrate(uintptr_t usart_base, uint32_t baudrate) /* Use the undivided PBA clock */ - cd = AVR32_PBA_CLOCK / baudrate; + cd = AVR32_PBA_CLOCK / baudrate; } DEBUGASSERT(cd > 0 && cd < 65536); @@ -202,7 +202,7 @@ static void usart_setbaudrate(uintptr_t usart_base, uint32_t baudrate) void usart_reset(uintptr_t usart_base) { irqstate_t flags; - + /* Disable all USART interrupts */ flags = irqsave(); @@ -275,7 +275,7 @@ void usart_configure(uintptr_t usart_base, uint32_t baud, unsigned int parity, { regval |= USART_MR_CHRL_BITS(nbits); } - + usart_putreg(usart_base, AVR32_USART_MR_OFFSET, regval); /* Set the baud rate generation register */ diff --git a/nuttx/arch/avr/src/at32uc3/at32uc3_tc.h b/nuttx/arch/avr/src/at32uc3/at32uc3_tc.h index 821b35b33..f3773c161 100644 --- a/nuttx/arch/avr/src/at32uc3/at32uc3_tc.h +++ b/nuttx/arch/avr/src/at32uc3/at32uc3_tc.h @@ -355,7 +355,7 @@ # define TC_BMR_TC2XC2S_NONE (1 << TC_BMR_TC2XC2S_SHIFT) /* None */ # define TC_BMR_TC2XC2S_TIOA0 (2 << TC_BMR_TC2XC2S_SHIFT) /* TIOA0 */ # define TC_BMR_TC2XC2S_TIOA1 (3 << TC_BMR_TC2XC2S_SHIFT) /* TIOA1 */ - + /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/nuttx/arch/avr/src/at32uc3/at32uc3_timerisr.c b/nuttx/arch/avr/src/at32uc3/at32uc3_timerisr.c index 711cef3c9..361fb8ec2 100644 --- a/nuttx/arch/avr/src/at32uc3/at32uc3_timerisr.c +++ b/nuttx/arch/avr/src/at32uc3/at32uc3_timerisr.c @@ -121,7 +121,7 @@ * Therefore, the TOP interrupt should occur after 143+1=144 counts * at a rate of 69.57us x 144 = 10.02 ms */ - + #ifdef AVR32_CLOCK_OSC32 # define AV32_PSEL 1 # define AV32_TOP (82-1) @@ -168,7 +168,7 @@ static void rtc_waitnotbusy(void) int up_timerisr(int irq, uint32_t *regs) { /* Clear the pending timer interrupt */ - + putreg32(RTC_INT_TOPI, AVR32_RTC_ICR); /* Process timer interrupt */ @@ -228,7 +228,7 @@ void up_timerinit(void) /* Enable RTC interrupts */ putreg32(RTC_INT_TOPI, AVR32_RTC_IER); - + /* Enable the RTC */ rtc_waitnotbusy(); diff --git a/nuttx/arch/avr/src/at90usb/at90usb_head.S b/nuttx/arch/avr/src/at90usb/at90usb_head.S index 1e705ba71..6d850b7f2 100755 --- a/nuttx/arch/avr/src/at90usb/at90usb_head.S +++ b/nuttx/arch/avr/src/at90usb/at90usb_head.S @@ -227,7 +227,7 @@ __do_copy_data: .Lcopyloop: lpm r0, Z+ st X+, r0 - + .Lcopystart: cpi r26, lo8(_edata) cpc r27, r17 @@ -246,7 +246,7 @@ __do_clear_bss: .Lclearloop: st X+, r1 - + .Lclearstart: cpi r26, lo8(_ebss) cpc r27, r17 diff --git a/nuttx/arch/avr/src/at90usb/at90usb_lowconsole.c b/nuttx/arch/avr/src/at90usb/at90usb_lowconsole.c index 64fd50fe1..b45f119d9 100644 --- a/nuttx/arch/avr/src/at90usb/at90usb_lowconsole.c +++ b/nuttx/arch/avr/src/at90usb/at90usb_lowconsole.c @@ -77,7 +77,7 @@ * AVR_NORMAL_UBRR1 = 52 (rounded), actual baud = 9615 * AVR_DBLSPEED_UBRR1 = 104 (rounded), actual baud = 9615 */ - + #undef UART1_DOUBLE_SPEED #if BOARD_CPU_CLOCK <= 4000000 # if CONFIG_USART1_BAUD <= 9600 @@ -194,7 +194,7 @@ void usart1_configure(void) ucsr1b = ((1 << TXEN1) | (1 << RXEN1)); ucsr1c = 0; - + /* Select parity */ #if CONFIG_USART1_PARITY == 1 diff --git a/nuttx/arch/avr/src/at90usb/at90usb_lowinit.c b/nuttx/arch/avr/src/at90usb/at90usb_lowinit.c index 5f8964f6c..89de8b8ca 100644 --- a/nuttx/arch/avr/src/at90usb/at90usb_lowinit.c +++ b/nuttx/arch/avr/src/at90usb/at90usb_lowinit.c @@ -50,7 +50,7 @@ **************************************************************************/ #if defined(CONFIG_WDTO_15MS) -# define WDTO_VALUE WDTO_15MS +# define WDTO_VALUE WDTO_15MS #elif defined(CONFIG_WDTO_30MS) # define WDTO_VALUE WDTO_30MS #elif defined(CONFIG_WDTO_60MS) diff --git a/nuttx/arch/avr/src/at90usb/at90usb_usbdev.c b/nuttx/arch/avr/src/at90usb/at90usb_usbdev.c index a5fb64c36..57741250a 100644 --- a/nuttx/arch/avr/src/at90usb/at90usb_usbdev.c +++ b/nuttx/arch/avr/src/at90usb/at90usb_usbdev.c @@ -624,7 +624,7 @@ static inline int avr_epNsend(FAR struct avr_ep_s *privep, } /* Send the USB data. The outer loop handles for each packet of data - * (including zero-length packets) + * (including zero-length packets) */ do @@ -1531,7 +1531,7 @@ static inline void avr_ep0setup(void) case USB_REQ_RECIPIENT_ENDPOINT: if (g_usbdev.paddrset != 0 && value == USB_FEATURE_ENDPOINTHALT && - len == 0 && + len == 0 && (privep = avr_epfindbyaddr(index)) != NULL) { avr_epstall(&privep->ep, false); @@ -1579,7 +1579,7 @@ static inline void avr_ep0setup(void) case USB_REQ_RECIPIENT_ENDPOINT: if (g_usbdev.paddrset != 0 && value == USB_FEATURE_ENDPOINTHALT && - len == 0 && + len == 0 && (privep = avr_epfindbyaddr(index)) != NULL) { avr_epstall(&privep->ep, true); @@ -2493,8 +2493,8 @@ static int avr_epcancel(FAR struct usbdev_ep_s *ep, usbtrace(TRACE_EPCANCEL, privep->ep.eplog); - /* FIXME: if the request is the first, then we need to flush the EP otherwise - * just remove it from the list but ... all other implementations cancel all + /* FIXME: if the request is the first, then we need to flush the EP otherwise + * just remove it from the list but ... all other implementations cancel all * requests ... */ flags = irqsave(); @@ -2716,7 +2716,7 @@ static int avr_wakeup(struct usbdev_s *dev) * Name: avr_selfpowered * * Description: - * Sets/clears the device selfpowered feature + * Sets/clears the device selfpowered feature * *******************************************************************************/ @@ -2949,7 +2949,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) * * Description: * Sample VBUS to see if there are changes in our connection status. There - * is actually an interrupt to signal this case so it should not be necessary + * is actually an interrupt to signal this case so it should not be necessary * to poll our connection status. However, on certain "noisy" systems, VBUS * may bounce and provide inaccurate information in the interrupt handler * (especially if a relay is used to switch VBUS!). This poll is, then, diff --git a/nuttx/arch/avr/src/atmega/Make.defs b/nuttx/arch/avr/src/atmega/Make.defs index a7d3a881b..826d372a1 100644 --- a/nuttx/arch/avr/src/atmega/Make.defs +++ b/nuttx/arch/avr/src/atmega/Make.defs @@ -74,7 +74,7 @@ CHIP_CSRCS = atmega_lowconsole.c atmega_lowinit.c atmega_serial.c atmega_timeris # Configuration-dependent ATMEGA files ifeq ($(CONFIG_AVR_GPIOIRQ),y) -CHIP_CSRCS += +CHIP_CSRCS += endif diff --git a/nuttx/arch/avr/src/atmega/atmega_head.S b/nuttx/arch/avr/src/atmega/atmega_head.S index dc35cd879..b272e54c3 100755 --- a/nuttx/arch/avr/src/atmega/atmega_head.S +++ b/nuttx/arch/avr/src/atmega/atmega_head.S @@ -240,7 +240,7 @@ __do_clear_bss: .Lclearloop: st X+, r1 - + .Lclearstart: cpi r26, lo8(_ebss) cpc r27, r17 diff --git a/nuttx/arch/avr/src/atmega/atmega_lowconsole.c b/nuttx/arch/avr/src/atmega/atmega_lowconsole.c index ccf56dc33..ba3255741 100644 --- a/nuttx/arch/avr/src/atmega/atmega_lowconsole.c +++ b/nuttx/arch/avr/src/atmega/atmega_lowconsole.c @@ -76,7 +76,7 @@ * AVR_NORMAL_UBRR1 = 52 (rounded), actual baud = 9615 * AVR_DBLSPEED_UBRR1 = 104 (rounded), actual baud = 9615 */ - + #undef UART0_DOUBLE_SPEED #if BOARD_CPU_CLOCK <= 4000000 # if CONFIG_USART0_BAUD <= 9600 @@ -136,7 +136,7 @@ * AVR_NORMAL_UBRR1 = 52 (rounded), actual baud = 9615 * AVR_DBLSPEED_UBRR1 = 104 (rounded), actual baud = 9615 */ - + #undef UART1_DOUBLE_SPEED #if BOARD_CPU_CLOCK <= 4000000 # if CONFIG_USART1_BAUD <= 9600 @@ -275,7 +275,7 @@ void usart0_configure(void) ucsr0b = ((1 << TXEN0) | (1 << RXEN0)); ucsr0c = 0; - + /* Select parity */ #if CONFIG_USART0_PARITY == 1 @@ -352,7 +352,7 @@ void usart1_configure(void) ucsr1b = ((1 << TXEN1) | (1 << RXEN1)); ucsr1c = 0; - + /* Select parity */ #if CONFIG_USART1_PARITY == 1 diff --git a/nuttx/arch/avr/src/atmega/atmega_lowinit.c b/nuttx/arch/avr/src/atmega/atmega_lowinit.c index 075a6413a..1ac5661f6 100644 --- a/nuttx/arch/avr/src/atmega/atmega_lowinit.c +++ b/nuttx/arch/avr/src/atmega/atmega_lowinit.c @@ -50,7 +50,7 @@ **************************************************************************/ #if defined(CONFIG_WDTO_15MS) -# define WDTO_VALUE WDTO_15MS +# define WDTO_VALUE WDTO_15MS #elif defined(CONFIG_WDTO_30MS) # define WDTO_VALUE WDTO_30MS #elif defined(CONFIG_WDTO_60MS) diff --git a/nuttx/arch/avr/src/avr/avr_internal.h b/nuttx/arch/avr/src/avr/avr_internal.h index 8fb3fae28..f74d682e5 100644 --- a/nuttx/arch/avr/src/avr/avr_internal.h +++ b/nuttx/arch/avr/src/avr/avr_internal.h @@ -54,7 +54,7 @@ ****************************************************************************/ /* Macros to handle saving and restore interrupt state. The state is copied - * from the stack to the TCB, but only a referenced is passed to get the + * from the stack to the TCB, but only a referenced is passed to get the * state from the TCB. */ @@ -142,7 +142,7 @@ uint8_t *up_doirq(uint8_t irq, uint8_t *regs); * Description: * These external functions must be provided by board-specific logic. They are * implementations of the select, status, and cmddata methods of the SPI interface - * defined by struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * defined by struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods * including up_spiinitialize()) are provided by common LPC17xx logic. To use * this common SPI logic on your board: * diff --git a/nuttx/arch/avr/src/avr/excptmacros.h b/nuttx/arch/avr/src/avr/excptmacros.h index 730f02acc..c46e0024a 100644 --- a/nuttx/arch/avr/src/avr/excptmacros.h +++ b/nuttx/arch/avr/src/avr/excptmacros.h @@ -92,7 +92,7 @@ * * Description: * This macro provides the exception entry logic. It is called with the PC already on the - * stack. It simply saves one register on the stack (r24) and passes the IRQ number to + * stack. It simply saves one register on the stack (r24) and passes the IRQ number to * common logic (see EXCPT_PROLOGUE). * * On Entry: @@ -437,7 +437,7 @@ out _SFR_IO_ADDR(SPH), r25 /* (SPH then SPL) */ ld r24, x+ out _SFR_IO_ADDR(SPL), r24 - + /* Fetch the return address and save it at the bottom of the new stack so * that we can iret to switch contexts. The new stack is now: * diff --git a/nuttx/arch/avr/src/avr/up_blocktask.c b/nuttx/arch/avr/src/avr/up_blocktask.c index 82fcd65db..004bf6e44 100644 --- a/nuttx/arch/avr/src/avr/up_blocktask.c +++ b/nuttx/arch/avr/src/avr/up_blocktask.c @@ -130,7 +130,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/avr/src/avr/up_createstack.c b/nuttx/arch/avr/src/avr/up_createstack.c index 521213126..1dd7e5006 100644 --- a/nuttx/arch/avr/src/avr/up_createstack.c +++ b/nuttx/arch/avr/src/avr/up_createstack.c @@ -118,7 +118,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) } /* Do we need to allocate a new stack? */ - + if (!tcb->stack_alloc_ptr) { /* Allocate the stack. If DEBUG is enabled (but not stack debug), diff --git a/nuttx/arch/avr/src/avr/up_releasepending.c b/nuttx/arch/avr/src/avr/up_releasepending.c index 0a63189fe..a3646f6f9 100644 --- a/nuttx/arch/avr/src/avr/up_releasepending.c +++ b/nuttx/arch/avr/src/avr/up_releasepending.c @@ -97,7 +97,7 @@ void up_release_pending(void) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/avr/src/avr/up_reprioritizertr.c b/nuttx/arch/avr/src/avr/up_reprioritizertr.c index 4c510f4ea..773b0ede8 100644 --- a/nuttx/arch/avr/src/avr/up_reprioritizertr.c +++ b/nuttx/arch/avr/src/avr/up_reprioritizertr.c @@ -69,7 +69,7 @@ * * Description: * Called when the priority of a running or - * ready-to-run task changes and the reprioritization will + * ready-to-run task changes and the reprioritization will * cause a context switch. Two cases: * * 1) The priority of the currently running task drops and the next @@ -152,7 +152,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/avr/src/avr/up_spi.c b/nuttx/arch/avr/src/avr/up_spi.c index 8a243c2d9..78a4fa9ba 100644 --- a/nuttx/arch/avr/src/avr/up_spi.c +++ b/nuttx/arch/avr/src/avr/up_spi.c @@ -140,7 +140,7 @@ static const struct spi_ops_s g_spiops = static struct avr_spidev_s g_spidev = { .spidev = { &g_spiops }, -}; +}; /**************************************************************************** * Public Data @@ -319,19 +319,19 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) { case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */ break; - + case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */ regval |= (1 << CPHA); break; - + case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */ regval |= (1 << CPOL); break; - + case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ regval |= ((1 << CPOL) | (1 << CPHA)); break; - + default: DEBUGASSERT(FALSE); return; diff --git a/nuttx/arch/avr/src/avr/up_unblocktask.c b/nuttx/arch/avr/src/avr/up_unblocktask.c index 970deedd6..305e057a8 100644 --- a/nuttx/arch/avr/src/avr/up_unblocktask.c +++ b/nuttx/arch/avr/src/avr/up_unblocktask.c @@ -109,7 +109,7 @@ void up_unblock_task(struct tcb_s *tcb) /* The currently active task has changed! We need to do * a context switch to the new task. * - * Are we in an interrupt handler? + * Are we in an interrupt handler? */ if (current_regs) @@ -120,7 +120,7 @@ void up_unblock_task(struct tcb_s *tcb) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/avr/src/avr32/Toolchain.defs b/nuttx/arch/avr/src/avr32/Toolchain.defs index 9c3bed04c..51fe4fbba 100644 --- a/nuttx/arch/avr/src/avr32/Toolchain.defs +++ b/nuttx/arch/avr/src/avr32/Toolchain.defs @@ -44,7 +44,7 @@ # that we are operating on a Windows platform. But in the case where we # have an AVR32 toolchain built under Cygwin, the correct setting would be # GNU, not AVRTOOLSW. -# +# CROSSDEV = avr32- ARCHCPUFLAGS = -mpart=uc3b0256 diff --git a/nuttx/arch/avr/src/avr32/avr32_internal.h b/nuttx/arch/avr/src/avr32/avr32_internal.h index 906cffc78..c98f0b5cc 100644 --- a/nuttx/arch/avr/src/avr32/avr32_internal.h +++ b/nuttx/arch/avr/src/avr32/avr32_internal.h @@ -52,7 +52,7 @@ ****************************************************************************/ /* Macros to handle saving and restore interrupt state. The state is copied - * from the stack to the TCB, but only a referenced is passed to get the + * from the stack to the TCB, but only a referenced is passed to get the * state from the TCB. */ diff --git a/nuttx/arch/avr/src/avr32/up_blocktask.c b/nuttx/arch/avr/src/avr32/up_blocktask.c index 1da4eb573..955d3b1d2 100644 --- a/nuttx/arch/avr/src/avr32/up_blocktask.c +++ b/nuttx/arch/avr/src/avr32/up_blocktask.c @@ -130,7 +130,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/avr/src/avr32/up_createstack.c b/nuttx/arch/avr/src/avr32/up_createstack.c index f9968d555..fd1af6782 100644 --- a/nuttx/arch/avr/src/avr32/up_createstack.c +++ b/nuttx/arch/avr/src/avr32/up_createstack.c @@ -117,7 +117,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) } /* Do we need to allocate a new stack? */ - + if (!tcb->stack_alloc_ptr) { /* Allocate the stack. If DEBUG is enabled (but not stack debug), diff --git a/nuttx/arch/avr/src/avr32/up_exceptions.S b/nuttx/arch/avr/src/avr32/up_exceptions.S index 53a5b9c4f..b4d399cdb 100755 --- a/nuttx/arch/avr/src/avr32/up_exceptions.S +++ b/nuttx/arch/avr/src/avr32/up_exceptions.S @@ -179,7 +179,7 @@ avr32_intcommon: /* On entry to each, the context save area looks like this: */ /* xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx SR PC */ /* ^ ^+2*4 */ - + HANDLER avr32_unrec, AVR32_IRQ_UNREC /* Unrecoverable xcptn */ HANDLER avr32_tlbmult, AVR32_IRQ_TLBMULT /* TLB multiple hit */ HANDLER avr32_busdata, AVR32_IRQ_BUSDATA /* Bus error data fetch */ @@ -240,7 +240,7 @@ avr32_xcptcommon: /* Save r8 and r8: */ /* xx xx xx xx xx xx xx xx xx SR PC LI 12 11 10 SR PC */ /* ^ ^+6*4 ^+8*4 */ - + st.w sp[6*4], r9 st.w sp[7*4], r8 diff --git a/nuttx/arch/avr/src/avr32/up_initialstate.c b/nuttx/arch/avr/src/avr32/up_initialstate.c index adfc95596..86138b616 100644 --- a/nuttx/arch/avr/src/avr32/up_initialstate.c +++ b/nuttx/arch/avr/src/avr32/up_initialstate.c @@ -91,7 +91,7 @@ void up_initial_state(struct tcb_s *tcb) /* No pending signal delivery */ xcp->sigdeliver = NULL; - + /* Clear the frame pointer and link register since this is the outermost * frame. */ diff --git a/nuttx/arch/avr/src/avr32/up_releasepending.c b/nuttx/arch/avr/src/avr32/up_releasepending.c index 00956e442..e144ca904 100644 --- a/nuttx/arch/avr/src/avr32/up_releasepending.c +++ b/nuttx/arch/avr/src/avr32/up_releasepending.c @@ -97,7 +97,7 @@ void up_release_pending(void) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/avr/src/avr32/up_reprioritizertr.c b/nuttx/arch/avr/src/avr32/up_reprioritizertr.c index 621f08613..07ee9c6a4 100644 --- a/nuttx/arch/avr/src/avr32/up_reprioritizertr.c +++ b/nuttx/arch/avr/src/avr32/up_reprioritizertr.c @@ -69,7 +69,7 @@ * * Description: * Called when the priority of a running or - * ready-to-run task changes and the reprioritization will + * ready-to-run task changes and the reprioritization will * cause a context switch. Two cases: * * 1) The priority of the currently running task drops and the next @@ -152,7 +152,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/avr/src/avr32/up_stackframe.c b/nuttx/arch/avr/src/avr32/up_stackframe.c index a38370801..e53eee5ae 100644 --- a/nuttx/arch/avr/src/avr32/up_stackframe.c +++ b/nuttx/arch/avr/src/avr32/up_stackframe.c @@ -53,7 +53,7 @@ * Pre-processor Macros ****************************************************************************/ -/* The AVR32 stack must be aligned at word (4 byte) boundaries. If necessary +/* The AVR32 stack must be aligned at word (4 byte) boundaries. If necessary * frame_size must be rounded up to the next boundary */ @@ -116,7 +116,7 @@ FAR void *up_stack_frame(FAR struct tcb_s *tcb, size_t frame_size) /* Align the frame_size */ frame_size = STACK_ALIGN_UP(frame_size); - + /* Is there already a stack allocated? Is it big enough? */ if (!tcb->stack_alloc_ptr || tcb->adj_stack_size <= frame_size) diff --git a/nuttx/arch/avr/src/avr32/up_unblocktask.c b/nuttx/arch/avr/src/avr32/up_unblocktask.c index 1fcfa1dd7..42dc3d52a 100644 --- a/nuttx/arch/avr/src/avr32/up_unblocktask.c +++ b/nuttx/arch/avr/src/avr32/up_unblocktask.c @@ -109,7 +109,7 @@ void up_unblock_task(struct tcb_s *tcb) /* The currently active task has changed! We need to do * a context switch to the new task. * - * Are we in an interrupt handler? + * Are we in an interrupt handler? */ if (current_regs) @@ -120,7 +120,7 @@ void up_unblock_task(struct tcb_s *tcb) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/hc/src/common/up_blocktask.c b/nuttx/arch/hc/src/common/up_blocktask.c index 5a2986291..58dd3360c 100644 --- a/nuttx/arch/hc/src/common/up_blocktask.c +++ b/nuttx/arch/hc/src/common/up_blocktask.c @@ -130,7 +130,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -148,7 +148,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state) else if (!up_saveusercontext(rtcb->xcp.regs)) { - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/hc/src/common/up_createstack.c b/nuttx/arch/hc/src/common/up_createstack.c index 3272fda13..aad1557fc 100644 --- a/nuttx/arch/hc/src/common/up_createstack.c +++ b/nuttx/arch/hc/src/common/up_createstack.c @@ -114,7 +114,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) } /* Do we need to allocate a new stack? */ - + if (!tcb->stack_alloc_ptr) { /* Allocate the stack. If DEBUG is enabled (but not stack debug), diff --git a/nuttx/arch/hc/src/common/up_releasepending.c b/nuttx/arch/hc/src/common/up_releasepending.c index b8da18d60..7a55254e7 100644 --- a/nuttx/arch/hc/src/common/up_releasepending.c +++ b/nuttx/arch/hc/src/common/up_releasepending.c @@ -96,7 +96,7 @@ void up_release_pending(void) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -110,13 +110,13 @@ void up_release_pending(void) /* Copy the exception context into the TCB of the task that * was currently active. if up_saveusercontext returns a non-zero - * value, then this is really the previously running task + * value, then this is really the previously running task * restarting! */ else if (!up_saveusercontext(rtcb->xcp.regs)) { - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/hc/src/common/up_reprioritizertr.c b/nuttx/arch/hc/src/common/up_reprioritizertr.c index d9689a0f3..ee8ed4e3c 100644 --- a/nuttx/arch/hc/src/common/up_reprioritizertr.c +++ b/nuttx/arch/hc/src/common/up_reprioritizertr.c @@ -69,7 +69,7 @@ * * Description: * Called when the priority of a running or - * ready-to-run task changes and the reprioritization will + * ready-to-run task changes and the reprioritization will * cause a context switch. Two cases: * * 1) The priority of the currently running task drops and the next @@ -152,7 +152,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -171,7 +171,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) else if (!up_saveusercontext(rtcb->xcp.regs)) { - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/hc/src/common/up_stackframe.c b/nuttx/arch/hc/src/common/up_stackframe.c index bc3f996b2..4ced22c4a 100644 --- a/nuttx/arch/hc/src/common/up_stackframe.c +++ b/nuttx/arch/hc/src/common/up_stackframe.c @@ -116,7 +116,7 @@ FAR void *up_stack_frame(FAR struct tcb_s *tcb, size_t frame_size) /* Align the frame_size */ frame_size = STACK_ALIGN_UP(frame_size); - + /* Is there already a stack allocated? Is it big enough? */ if (!tcb->stack_alloc_ptr || tcb->adj_stack_size <= frame_size) diff --git a/nuttx/arch/hc/src/common/up_unblocktask.c b/nuttx/arch/hc/src/common/up_unblocktask.c index de787418a..08cefc1d4 100644 --- a/nuttx/arch/hc/src/common/up_unblocktask.c +++ b/nuttx/arch/hc/src/common/up_unblocktask.c @@ -109,7 +109,7 @@ void up_unblock_task(struct tcb_s *tcb) /* The currently active task has changed! We need to do * a context switch to the new task. * - * Are we in an interrupt handler? + * Are we in an interrupt handler? */ if (current_regs) @@ -120,7 +120,7 @@ void up_unblock_task(struct tcb_s *tcb) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -132,7 +132,7 @@ void up_unblock_task(struct tcb_s *tcb) } /* We are not in an interrupt handler. Copy the user C context - * into the TCB of the task that was previously active. if + * into the TCB of the task that was previously active. if * up_saveusercontext returns a non-zero value, then this is really the * previously running task restarting! */ diff --git a/nuttx/arch/hc/src/m9s12/Make.defs b/nuttx/arch/hc/src/m9s12/Make.defs index 0f70c42ab..7ca06b436 100644 --- a/nuttx/arch/hc/src/m9s12/Make.defs +++ b/nuttx/arch/hc/src/m9s12/Make.defs @@ -35,7 +35,7 @@ HEAD_ASRC = m9s12_vectors.S -CMN_ASRCS = +CMN_ASRCS = CMN_CSRCS = up_allocateheap.c up_blocktask.c up_copystate.c up_createstack.c \ up_doirq.c up_exit.c up_idle.c up_initialize.c up_interruptcontext.c \ up_mdelay.c up_modifyreg16.c up_modifyreg32.c up_modifyreg8.c \ diff --git a/nuttx/arch/hc/src/m9s12/m9s12_assert.c b/nuttx/arch/hc/src/m9s12/m9s12_assert.c index b977f8822..7834d9800 100644 --- a/nuttx/arch/hc/src/m9s12/m9s12_assert.c +++ b/nuttx/arch/hc/src/m9s12/m9s12_assert.c @@ -63,7 +63,7 @@ # undef CONFIG_ARCH_USBDUMP #endif -/* Output debug info if stack dump is selected -- even if +/* Output debug info if stack dump is selected -- even if * debug is not selected. */ diff --git a/nuttx/arch/hc/src/m9s12/m9s12_dumpgpio.c b/nuttx/arch/hc/src/m9s12/m9s12_dumpgpio.c index c43d4439e..b958092b8 100644 --- a/nuttx/arch/hc/src/m9s12/m9s12_dumpgpio.c +++ b/nuttx/arch/hc/src/m9s12/m9s12_dumpgpio.c @@ -143,7 +143,7 @@ static const struct gpio_mebiinfo_s mebiinfo[HCS12_MEBI_NPORTS] = {HCS12_MEBI_PORTE, HCS12_MEBI_DDRE, 'E', MEBIPORT_E}, /* Port E */ {HCS12_MEBI_PORTK, HCS12_MEBI_DDRK, 'K', MEBIPORT_K} /* Port K */ }; - + /**************************************************************************** * Private Data ****************************************************************************/ @@ -223,7 +223,7 @@ static inline void hcs12_mebidump(uint8_t portndx) lldbg(" Illegal MEBI port index: %d\n", portndx); return; } - + ptr = &mebiinfo[portndx]; lldbg(" MEBI Port%c:\n", ptr->name); diff --git a/nuttx/arch/hc/src/m9s12/m9s12_ethernet.c b/nuttx/arch/hc/src/m9s12/m9s12_ethernet.c index d380f7757..b01bc1284 100644 --- a/nuttx/arch/hc/src/m9s12/m9s12_ethernet.c +++ b/nuttx/arch/hc/src/m9s12/m9s12_ethernet.c @@ -440,7 +440,7 @@ static void emac_polltimer(int argc, uint32_t arg, ...) * * Description: * NuttX Callback: Bring up the Ethernet interface when an IP address is - * provided + * provided * * Parameters: * dev - Reference to the NuttX driver state structure @@ -520,7 +520,7 @@ static int emac_ifdown(struct uip_driver_s *dev) * Function: emac_txavail * * Description: - * Driver callback invoked when new TX data is available. This is a + * Driver callback invoked when new TX data is available. This is a * stimulus perform an out-of-cycle poll and, thereby, reduce the TX * latency. * @@ -570,7 +570,7 @@ static int emac_txavail(struct uip_driver_s *dev) * * Parameters: * dev - Reference to the NuttX driver state structure - * mac - The MAC address to be added + * mac - The MAC address to be added * * Returned Value: * None @@ -599,7 +599,7 @@ static int emac_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac) * * Parameters: * dev - Reference to the NuttX driver state structure - * mac - The MAC address to be removed + * mac - The MAC address to be removed * * Returned Value: * None diff --git a/nuttx/arch/hc/src/m9s12/m9s12_gpio.c b/nuttx/arch/hc/src/m9s12/m9s12_gpio.c index 280202da5..464169ed7 100644 --- a/nuttx/arch/hc/src/m9s12/m9s12_gpio.c +++ b/nuttx/arch/hc/src/m9s12/m9s12_gpio.c @@ -286,7 +286,7 @@ static inline void pim_interrupt(uint8_t portndx, unsigned pin, uint8_t type) { gpio_writebit(HCS12_PIM_PORT_IE(portndx), pin, false); } -} +} /**************************************************************************** * Name: pim_configgpio @@ -308,7 +308,7 @@ static inline void pim_configgpio(uint16_t cfgset, uint8_t portndx, uint8_t pin) if ((cfgset & GPIO_INT_ENABLE) != 0) { /* Yes.. then it must not be tagged as an output */ - + ASSERT((cfgset & GPIO_DIRECTION) != GPIO_OUTPUT); /* If the pull-driver is also enabled, it must be enabled with a diff --git a/nuttx/arch/hc/src/m9s12/m9s12_gpioirq.c b/nuttx/arch/hc/src/m9s12/m9s12_gpioirq.c index 017292a26..02b8146c0 100644 --- a/nuttx/arch/hc/src/m9s12/m9s12_gpioirq.c +++ b/nuttx/arch/hc/src/m9s12/m9s12_gpioirq.c @@ -164,7 +164,7 @@ static int hcs12_interrupt(uint16_t base, int irq0, uint8_t valid, void *context */ putreg8(bit, base+HCS12_PIM_IF_OFFSET); - + /* Re-deliver the IRQ (recurses! We got here from irq_dispatch!) */ irq_dispatch(irq, context); diff --git a/nuttx/arch/hc/src/m9s12/m9s12_initialstate.c b/nuttx/arch/hc/src/m9s12/m9s12_initialstate.c index 3259cbb9a..678b26c90 100644 --- a/nuttx/arch/hc/src/m9s12/m9s12_initialstate.c +++ b/nuttx/arch/hc/src/m9s12/m9s12_initialstate.c @@ -115,7 +115,7 @@ void up_initial_state(struct tcb_s *tcb) # ifdef CONFIG_SUPPRESS_INTERRUPTS /* Disable STOP, Mask I- and Z- interrupts */ - xcp->regs[REG_CCR] = HCS12_CCR_S|HCS12_CCR_X|HCS12_CCR_I; + xcp->regs[REG_CCR] = HCS12_CCR_S|HCS12_CCR_X|HCS12_CCR_I; # else /* Disable STOP, Enable I- and Z-interrupts */ diff --git a/nuttx/arch/hc/src/m9s12/m9s12_internal.h b/nuttx/arch/hc/src/m9s12/m9s12_internal.h index 9076e490d..104dfd362 100644 --- a/nuttx/arch/hc/src/m9s12/m9s12_internal.h +++ b/nuttx/arch/hc/src/m9s12/m9s12_internal.h @@ -163,7 +163,7 @@ * Ports A, B, E, and K reside in the MEBI block * Ports T,S,G,H,J, and L reside in the PIM block. */ - + #define GPIO_PORT_SHIFT 3 #define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT) # define GPIO_PORT_A (0 << GPIO_PORT_SHIFT) @@ -341,7 +341,7 @@ EXTERN int hcs12_ethinitialize(int intf); * 3. Add a calls to up_spiinitialize() in your low level application * initialization logic * 4. The handle returned by up_spiinitialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * diff --git a/nuttx/arch/hc/src/m9s12/m9s12_irq.c b/nuttx/arch/hc/src/m9s12/m9s12_irq.c index 56e357a2e..ad859dc51 100644 --- a/nuttx/arch/hc/src/m9s12/m9s12_irq.c +++ b/nuttx/arch/hc/src/m9s12/m9s12_irq.c @@ -87,7 +87,7 @@ void up_irqinitialize(void) /* Initialize logic to support a second level of interrupt decoding for * GPIO pins. */ - + #ifdef CONFIG_GPIO_IRQ hcs12_gpioirqinitialize(); #endif diff --git a/nuttx/arch/hc/src/m9s12/m9s12_mebi.h b/nuttx/arch/hc/src/m9s12/m9s12_mebi.h index f7426a3e5..99bd23510 100644 --- a/nuttx/arch/hc/src/m9s12/m9s12_mebi.h +++ b/nuttx/arch/hc/src/m9s12/m9s12_mebi.h @@ -99,7 +99,7 @@ /* Port K Data Register Bit-Field Definitions */ /* Data Direction Register K Bit-Field Definitions */ -#define MEBI_PIN(n) (1 << (n)) +#define MEBI_PIN(n) (1 << (n)) #define MEBI_PIN0 (1 << 0) #define MEBI_PIN1 (1 << 1) #define MEBI_PIN2 (1 << 2) diff --git a/nuttx/arch/hc/src/m9s12/m9s12_serial.c b/nuttx/arch/hc/src/m9s12/m9s12_serial.c index bb61d7dbc..b83659f3f 100644 --- a/nuttx/arch/hc/src/m9s12/m9s12_serial.c +++ b/nuttx/arch/hc/src/m9s12/m9s12_serial.c @@ -250,7 +250,7 @@ static inline void up_serialout(struct up_dev_s *priv, int offset, uint8_t value static inline void up_setsciint(struct up_dev_s *priv) { uint8_t regval; - + regval = up_serialin(priv, HCS12_SCI_CR2_OFFSET); regval &= ~SCI_CR2_ALLINTS; regval |= priv->im; @@ -264,7 +264,7 @@ static inline void up_setsciint(struct up_dev_s *priv) static inline void up_disablesciint(struct up_dev_s *priv, uint8_t *im) { uint8_t regval; - + /* Return the current interrupt mask value */ if (im) @@ -348,7 +348,7 @@ static int up_setup(struct uart_dev_s *dev) up_serialout(priv, HCS12_SCI_BDH_OFFSET, (uint8_t)(tmp >> 8)); up_serialout(priv, HCS12_SCI_BDL_OFFSET, (uint8_t)(tmp & 0xff)); - + /* Set up the SCICR1 register */ cr1 = 0; @@ -422,7 +422,7 @@ static int up_attach(struct uart_dev_s *dev) if (ret == OK) { /* Enable the Rx interrupt (the TX interrupt is still disabled - * until we have something to send). + * until we have something to send). */ priv->im = SCI_CR2_RIE; @@ -567,7 +567,7 @@ static int up_receive(struct uart_dev_s *dev, uint32_t *status) /* Return the error indications */ *status = (uint32_t)(priv->sr1 & ~SCI_CR2_ALLINTS); - + /* Get the Rx data */ rxd = (int)up_serialin(priv, HCS12_SCI_DRL_OFFSET); diff --git a/nuttx/arch/hc/src/m9s12/m9s12_serial.h b/nuttx/arch/hc/src/m9s12/m9s12_serial.h index f38377982..0c5f70041 100644 --- a/nuttx/arch/hc/src/m9s12/m9s12_serial.h +++ b/nuttx/arch/hc/src/m9s12/m9s12_serial.h @@ -77,7 +77,7 @@ #ifndef CONFIG_SCI0_DISABLE # ifndef CONFIG_SCI0_PARITY # warning "CONFIG_SCI0_PARITY not defined -- Assuming none" -# define CONFIG_SCI0_PARITY 0 +# define CONFIG_SCI0_PARITY 0 # elif CONFIG_SCI0_PARITY != 0 && CONFIG_SCI0_PARITY != 2 && CONFIG_SCI0_PARITY != 2 # error "CONFIG_SCI0_PARITY value not recognized" # endif @@ -95,7 +95,7 @@ #ifndef CONFIG_SCI1_DISABLE # ifndef CONFIG_SCI1_PARITY # warning "CONFIG_SCI1_PARITY not defined -- Assuming none" -# define CONFIG_SCI1_PARITY 0 +# define CONFIG_SCI1_PARITY 0 # elif CONFIG_SCI1_PARITY != 0 && CONFIG_SCI1_PARITY != 2 && CONFIG_SCI1_PARITY != 2 # error "CONFIG_SCI1_PARITY value not recognized" # endif diff --git a/nuttx/arch/hc/src/m9s12/m9s12_spi.h b/nuttx/arch/hc/src/m9s12/m9s12_spi.h index 931e0efcf..b3d6f3cef 100644 --- a/nuttx/arch/hc/src/m9s12/m9s12_spi.h +++ b/nuttx/arch/hc/src/m9s12/m9s12_spi.h @@ -52,7 +52,7 @@ #define HCS12_SPI_CR1_OFFSET 0x00 /* SPI Control Register 1 */ #define HCS12_SPI_CR2_OFFSET 0x01 /* SPI Control Register 2 */ #define HCS12_SPI_BR_OFFSET 0x02 /* SPI Baud Rate Register */ -#define HCS12_SPI_SR_OFFSET 0x03 /* SPI Status Register */ +#define HCS12_SPI_SR_OFFSET 0x03 /* SPI Status Register */ #define HCS12_SPI_DR_OFFSET 0x05 /* SPI Data Register */ /* Register Addresses ***************************************************************/ @@ -90,7 +90,7 @@ #define SPI_BR_SPPR_SHIFT (4) /* Bits 4-6: SPI Baud Rate Preselection */ #define SPI_BR_SPPR_MASK (7 << SPI_BR_SPPR_SHIFT) -/* SPI Status Register Bit-Field Definitions */ +/* SPI Status Register Bit-Field Definitions */ #define SPI_SR_MODF (1 << 4) /* Bit 4: Mode Fault */ #define SPI_SR_SPTEF (1 << 5) /* Bit 5: SPI Transmit Empty Interrupt */ diff --git a/nuttx/arch/hc/src/m9s12/m9s12_start.S b/nuttx/arch/hc/src/m9s12/m9s12_start.S index c79388030..890786270 100755 --- a/nuttx/arch/hc/src/m9s12/m9s12_start.S +++ b/nuttx/arch/hc/src/m9s12/m9s12_start.S @@ -96,7 +96,7 @@ * * The MC9S12NE64 has 64K bytes of FLASH EEPROM and 8K bytes of RAM. */ - + .macro MMCINIT /* Registers are always positioned at address 0x0000 */ @@ -126,7 +126,7 @@ * already been configured at 24 MHz */ - .macro PLLINIT + .macro PLLINIT #ifndef CONFIG_HCS12_SERIALMON /* Select the clock source from crystal */ @@ -137,7 +137,7 @@ bclr *HCS12_CRG_PLLCTL #CRG_PLLCTL_PLLON ldab #HCS12_SYNR_VALUE stab HCS12_CRG_SYNR - ldab #HCS12_REFDV_VALUE + ldab #HCS12_REFDV_VALUE stab HCS12_CRG_REFDV bset *HCS12_CRG_PLLCTL #CRG_PLLCTL_PLLON diff --git a/nuttx/arch/hc/src/m9s12/m9s12_timerisr.c b/nuttx/arch/hc/src/m9s12/m9s12_timerisr.c index dcefa1dc6..46733da01 100644 --- a/nuttx/arch/hc/src/m9s12/m9s12_timerisr.c +++ b/nuttx/arch/hc/src/m9s12/m9s12_timerisr.c @@ -75,7 +75,7 @@ #define MIN_PRER 1024 /* 2**10, B=1 */ #define MAX_PRER 65536 /* 2**16, B=7 */ - + #define MIN_MODCNT 1 /* A=0 */ #define MAX_MODCNT 16 /* A=15 */ diff --git a/nuttx/arch/hc/src/m9s12/m9s12_vectors.S b/nuttx/arch/hc/src/m9s12/m9s12_vectors.S index 4b10ed62a..d7d929b65 100755 --- a/nuttx/arch/hc/src/m9s12/m9s12_vectors.S +++ b/nuttx/arch/hc/src/m9s12/m9s12_vectors.S @@ -80,7 +80,7 @@ * PCH * High Address PCL <-- SP before interrupt */ - + .macro HANDLER, label, irqno \label: ldab #\irqno /* Load B=IRQ number */ @@ -293,7 +293,7 @@ vcommon: #endif /* Save the PPAGE register */ - + #ifndef CONFIG_HCS12_NONBANKED movb HCS12_MMC_PPAGE, 1, -sp #endif @@ -318,7 +318,7 @@ vcommon: bne up_fullcontextrestore /* Restore registers and return */ - + /* Restore the PPAGE register */ #ifndef CONFIG_HCS12_NONBANKED diff --git a/nuttx/arch/mips/include/mips32/irq.h b/nuttx/arch/mips/include/mips32/irq.h index 8a3a71352..d42dbcfd2 100644 --- a/nuttx/arch/mips/include/mips32/irq.h +++ b/nuttx/arch/mips/include/mips32/irq.h @@ -430,7 +430,7 @@ static inline void cp0_putstatus(irqstate_t status) "\tnop\n" "\tnop\n" /* Plus one for good measure */ "\t.set pop\n" - : + : : "r" (status) : "memory" ); @@ -490,7 +490,7 @@ static inline void cp0_putcause(uint32_t cause) "\t.set noreorder\n" "\tmtc0 %0, $13, 0\n" /* Set the cause to the provided value */ "\t.set pop\n" - : + : : "r" (cause) : "memory" ); diff --git a/nuttx/arch/mips/include/mips32/registers.h b/nuttx/arch/mips/include/mips32/registers.h index 70279cb6f..659cd3397 100644 --- a/nuttx/arch/mips/include/mips32/registers.h +++ b/nuttx/arch/mips/include/mips32/registers.h @@ -83,7 +83,7 @@ #define t9 $25 /* Static registers: Registers that must be saved and restored if used */ - + #define s0 $16 #define s1 $17 #define s2 $18 diff --git a/nuttx/arch/mips/include/mips32/syscall.h b/nuttx/arch/mips/include/mips32/syscall.h index 349fba9bd..bf2a7847f 100644 --- a/nuttx/arch/mips/include/mips32/syscall.h +++ b/nuttx/arch/mips/include/mips32/syscall.h @@ -62,7 +62,7 @@ * a SYS call in kernel mode. The first four syscall values must, therefore, be * reserved (0 is not used). */ - + #ifdef CONFIG_NUTTX_KERNEL # ifndef CONFIG_SYS_RESERVED # error "CONFIG_SYS_RESERVED must be defined to the value 4" diff --git a/nuttx/arch/mips/include/pic32mx/irq.h b/nuttx/arch/mips/include/pic32mx/irq.h index 91fde196d..7c9da7099 100644 --- a/nuttx/arch/mips/include/pic32mx/irq.h +++ b/nuttx/arch/mips/include/pic32mx/irq.h @@ -123,7 +123,7 @@ static inline void cp0_putintctl(uint32_t intctl) "\t.set noreorder\n" "\tmtc0 %0, $12, 1\n" /* Set the IntCtl to the provided value */ "\t.set pop\n" - : + : : "r" (intctl) : "memory" ); @@ -183,7 +183,7 @@ static inline void cp0_putebase(uint32_t ebase) "\t.set noreorder\n" "\tmtc0 %0, $15, 1\n" /* Set the EBASE to the provided value */ "\t.set pop\n" - : + : : "r" (ebase) : "memory" ); diff --git a/nuttx/arch/mips/src/common/up_createstack.c b/nuttx/arch/mips/src/common/up_createstack.c index 7961ef3d9..506ece44d 100644 --- a/nuttx/arch/mips/src/common/up_createstack.c +++ b/nuttx/arch/mips/src/common/up_createstack.c @@ -55,7 +55,7 @@ * Pre-processor Macros ****************************************************************************/ -/* MIPS requires at least a 4-byte stack alignment. For floating point use, +/* MIPS requires at least a 4-byte stack alignment. For floating point use, * however, the stack must be aligned to 8-byte addresses. */ @@ -135,7 +135,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) } /* Do we need to allocate a new stack? */ - + if (!tcb->stack_alloc_ptr) { /* Allocate the stack. If DEBUG is enabled (but not stack debug), @@ -202,7 +202,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) /* The MIPS stack must be aligned at word (4 byte) boundaries; for * floating point use, the stack must be aligned to 8-byte addresses. * If necessary top_of_stack must be rounded down to the next - * boundary to meet these alignment requirements. + * boundary to meet these alignment requirements. */ top_of_stack = STACK_ALIGN_DOWN(top_of_stack); diff --git a/nuttx/arch/mips/src/common/up_stackframe.c b/nuttx/arch/mips/src/common/up_stackframe.c index 8f0fa66cd..87f13bc42 100644 --- a/nuttx/arch/mips/src/common/up_stackframe.c +++ b/nuttx/arch/mips/src/common/up_stackframe.c @@ -51,7 +51,7 @@ /**************************************************************************** * Pre-processor Macros ****************************************************************************/ -/* MIPS requires at least a 4-byte stack alignment. For floating point use, +/* MIPS requires at least a 4-byte stack alignment. For floating point use, * however, the stack must be aligned to 8-byte addresses. */ @@ -118,7 +118,7 @@ FAR void *up_stack_frame(FAR struct tcb_s *tcb, size_t frame_size) /* Align the frame_size */ frame_size = STACK_ALIGN_UP(frame_size); - + /* Is there already a stack allocated? Is it big enough? */ if (!tcb->stack_alloc_ptr || tcb->adj_stack_size <= frame_size) diff --git a/nuttx/arch/mips/src/common/up_usestack.c b/nuttx/arch/mips/src/common/up_usestack.c index 934ac8ed1..89cff7ff9 100644 --- a/nuttx/arch/mips/src/common/up_usestack.c +++ b/nuttx/arch/mips/src/common/up_usestack.c @@ -53,7 +53,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* MIPS requires at least a 4-byte stack alignment. For floating point use, +/* MIPS requires at least a 4-byte stack alignment. For floating point use, * however, the stack must be aligned to 8-byte addresses. */ diff --git a/nuttx/arch/mips/src/mips32/Toolchain.defs b/nuttx/arch/mips/src/mips32/Toolchain.defs index dc34b8c76..4f031f3e0 100644 --- a/nuttx/arch/mips/src/mips32/Toolchain.defs +++ b/nuttx/arch/mips/src/mips32/Toolchain.defs @@ -91,7 +91,7 @@ endif # Each toolchain definition should set: # # CROSSDEV The GNU toolchain triple (command prefix) -# ARCROSSDEV If required, an alternative prefix used when +# ARCROSSDEV If required, an alternative prefix used when # invoking ar and nm. # ARCHCPUFLAGS CPU-specific flags selecting the instruction set # FPU options, etc. diff --git a/nuttx/arch/mips/src/mips32/up_blocktask.c b/nuttx/arch/mips/src/mips32/up_blocktask.c index e0d1cf247..62c0c126e 100644 --- a/nuttx/arch/mips/src/mips32/up_blocktask.c +++ b/nuttx/arch/mips/src/mips32/up_blocktask.c @@ -131,7 +131,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/mips/src/mips32/up_initialstate.c b/nuttx/arch/mips/src/mips32/up_initialstate.c index a4d204b30..ca981ffaf 100644 --- a/nuttx/arch/mips/src/mips32/up_initialstate.c +++ b/nuttx/arch/mips/src/mips32/up_initialstate.c @@ -100,7 +100,7 @@ void up_initial_state(struct tcb_s *tcb) /* Save the task entry point */ xcp->regs[REG_EPC] = (uint32_t)tcb->start; - + /* If this task is running PIC, then set the PIC base register to the * address of the allocated D-Space region. */ diff --git a/nuttx/arch/mips/src/mips32/up_releasepending.c b/nuttx/arch/mips/src/mips32/up_releasepending.c index 7999bffeb..1c2ac638d 100644 --- a/nuttx/arch/mips/src/mips32/up_releasepending.c +++ b/nuttx/arch/mips/src/mips32/up_releasepending.c @@ -99,7 +99,7 @@ void up_release_pending(void) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/mips/src/mips32/up_reprioritizertr.c b/nuttx/arch/mips/src/mips32/up_reprioritizertr.c index a8f0158b9..71a082fd8 100644 --- a/nuttx/arch/mips/src/mips32/up_reprioritizertr.c +++ b/nuttx/arch/mips/src/mips32/up_reprioritizertr.c @@ -71,7 +71,7 @@ * * Description: * Called when the priority of a running or - * ready-to-run task changes and the reprioritization will + * ready-to-run task changes and the reprioritization will * cause a context switch. Two cases: * * 1) The priority of the currently running task drops and the next @@ -154,7 +154,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/mips/src/mips32/up_swint0.c b/nuttx/arch/mips/src/mips32/up_swint0.c index 34a8a1dde..0f9bde459 100644 --- a/nuttx/arch/mips/src/mips32/up_swint0.c +++ b/nuttx/arch/mips/src/mips32/up_swint0.c @@ -310,7 +310,7 @@ int up_swint0(int irq, FAR void *context) #endif /* Clear the pending software interrupt 0 in the PIC32 interrupt block */ - + up_clrpend_irq(PIC32MX_IRQSRC_CS0); /* And reset the software interrupt bit in the MIPS CAUSE register */ diff --git a/nuttx/arch/mips/src/mips32/up_unblocktask.c b/nuttx/arch/mips/src/mips32/up_unblocktask.c index 99cd25052..277ec79cf 100644 --- a/nuttx/arch/mips/src/mips32/up_unblocktask.c +++ b/nuttx/arch/mips/src/mips32/up_unblocktask.c @@ -111,7 +111,7 @@ void up_unblock_task(struct tcb_s *tcb) /* The currently active task has changed! We need to do * a context switch to the new task. * - * Are we in an interrupt handler? + * Are we in an interrupt handler? */ if (current_regs) @@ -122,7 +122,7 @@ void up_unblock_task(struct tcb_s *tcb) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/mips/src/mips32/up_vfork.c b/nuttx/arch/mips/src/mips32/up_vfork.c index 82b097a26..af76c0779 100644 --- a/nuttx/arch/mips/src/mips32/up_vfork.c +++ b/nuttx/arch/mips/src/mips32/up_vfork.c @@ -77,7 +77,7 @@ * any data other than a variable of type pid_t used to store the return * value from vfork(), or returns from the function in which vfork() was * called, or calls any other function before successfully calling _exit() - * or one of the exec family of functions. + * or one of the exec family of functions. * * The overall sequence is: * @@ -107,7 +107,7 @@ * Upon successful completion, vfork() returns 0 to the child process and * returns the process ID of the child process to the parent process. * Otherwise, -1 is returned to the parent, no child process is created, - * and errno is set to indicate the error. + * and errno is set to indicate the error. * ****************************************************************************/ @@ -185,7 +185,7 @@ pid_t up_vfork(const struct vfork_s *context) DEBUGASSERT((uint32_t)parent->adj_stack_ptr > context->sp); stackutil = (uint32_t)parent->adj_stack_ptr - context->sp; - svdbg("stacksize:%d stackutil:%d\n", stacksize, stackutil); + svdbg("stacksize:%d stackutil:%d\n", stacksize, stackutil); /* Make some feeble effort to perserve the stack contents. This is * feeble because the stack surely contains invalid pointers and other diff --git a/nuttx/arch/mips/src/mips32/up_vfork.h b/nuttx/arch/mips/src/mips32/up_vfork.h index 556633072..079a744c8 100644 --- a/nuttx/arch/mips/src/mips32/up_vfork.h +++ b/nuttx/arch/mips/src/mips32/up_vfork.h @@ -72,7 +72,7 @@ * then this is the frame pointer. * r31 ra Return address. */ - + #define VFORK_S0_OFFSET (0*4) /* Saved register s0 */ #define VFORK_S1_OFFSET (1*4) /* Saved register s1 */ #define VFORK_S2_OFFSET (2*4) /* Saved register s2 */ diff --git a/nuttx/arch/mips/src/mips32/vfork.S b/nuttx/arch/mips/src/mips32/vfork.S index 2b7d180d3..8aba77326 100644 --- a/nuttx/arch/mips/src/mips32/vfork.S +++ b/nuttx/arch/mips/src/mips32/vfork.S @@ -64,7 +64,7 @@ * undefined if the process created by vfork() either modifies any data other than * a variable of type pid_t used to store the return value from vfork(), or returns * from the function in which vfork() was called, or calls any other function before - * successfully calling _exit() or one of the exec family of functions. + * successfully calling _exit() or one of the exec family of functions. * * This thin layer implements vfork by simply calling up_vfork() with the vfork() * context as an argument. The overall sequence is: @@ -93,7 +93,7 @@ * Upon successful completion, vfork() returns 0 to the child process and returns * the process ID of the child process to the parent process. Otherwise, -1 is * returned to the parent, no child process is created, and errno is set to - * indicate the error. + * indicate the error. * ************************************************************************************/ diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-config.h b/nuttx/arch/mips/src/pic32mx/pic32mx-config.h index d64caf5fb..058b02f68 100644 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-config.h +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-config.h @@ -806,7 +806,7 @@ #undef CONFIG_PIC32MX_FCKSM #if defined(BOARD_POSC_SWITCH) -# if defined(BOARD_POSC_FSCM) +# if defined(BOARD_POSC_FSCM) # define CONFIG_PIC32MX_FCKSM DEVCFG1_FCKSM_BOTH # else # define CONFIG_PIC32MX_FCKSM DEVCFG1_FCKSM_CSONLY diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-ethernet.c b/nuttx/arch/mips/src/pic32mx/pic32mx-ethernet.c index 81ace7b9b..fedf20b04 100644 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-ethernet.c +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-ethernet.c @@ -651,7 +651,7 @@ static void pic32mx_dumprxdesc(struct pic32mx_rxdesc_s *rxdesc, const char *msg) * Initialize the buffers by placing them all in a free list * * Parameters: - * priv - Pointer to EMAC device driver structure + * priv - Pointer to EMAC device driver structure * * Returned Value: * None @@ -670,7 +670,7 @@ static inline void pic32mx_bufferinit(struct pic32mx_driver_s *priv) sq_addlast((sq_entry_t*)buffer, &priv->pd_freebuffers); /* Get the address of the next buffer */ - + buffer += PIC32MX_ALIGNED_BUFSIZE; } } @@ -682,7 +682,7 @@ static inline void pic32mx_bufferinit(struct pic32mx_driver_s *priv) * Allocate one buffer by removing it from the free list * * Parameters: - * priv - Pointer to EMAC device driver structure + * priv - Pointer to EMAC device driver structure * * Returned Value: * Pointer to the allocated buffer (or NULL on failure) @@ -703,7 +703,7 @@ static uint8_t *pic32mx_allocbuffer(struct pic32mx_driver_s *priv) * Free one buffer by returning it to the free list * * Parameters: - * priv - Pointer to EMAC device driver structure + * priv - Pointer to EMAC device driver structure * * Returned Value: * Pointer to the allocated buffer (or NULL on failure) @@ -724,7 +724,7 @@ static void pic32mx_freebuffer(struct pic32mx_driver_s *priv, uint8_t *buffer) * Initialize the EMAC Tx descriptor table * * Parameters: - * priv - Pointer to EMAC device driver structure + * priv - Pointer to EMAC device driver structure * * Returned Value: * None @@ -792,7 +792,7 @@ static inline void pic32mx_txdescinit(struct pic32mx_driver_s *priv) * Initialize the EMAC Rx descriptor table * * Parameters: - * priv - Pointer to EMAC device driver structure + * priv - Pointer to EMAC device driver structure * * Returned Value: * None @@ -885,7 +885,7 @@ static inline struct pic32mx_txdesc_s *pic32mx_txdesc(struct pic32mx_driver_s *p * done condition has been processed when the buffer has been freed and * reset to zero. */ - + if ((txdesc->status & TXDESC_STATUS_EOWN) == 0 && txdesc->address == 0) { /* Yes.. return a pointer to the descriptor */ @@ -1280,10 +1280,10 @@ static void pic32mx_timerpoll(struct pic32mx_driver_s *priv) * possibly a response to the incoming packet (but probably not, in reality). * However, since the Rx and Tx operations are decoupled, there is no * guarantee that there will be a Tx descriptor available at that time. - * This function will perform that check and, if no Tx descriptor is + * This function will perform that check and, if no Tx descriptor is * available, this function will (1) stop incoming Rx processing (bad), and * (2) hold the outgoing packet in a pending state until the next Tx - * interrupt occurs. + * interrupt occurs. * * Parameters: * priv - Reference to the driver state structure @@ -1314,7 +1314,7 @@ static void pic32mx_response(struct pic32mx_driver_s *priv) /* No.. mark the Tx as pending and halt further Rx interrupts */ DEBUGASSERT((priv->pd_inten & ETH_INT_TXDONE) != 0); - + priv->pd_txpending = true; priv->pd_inten &= ~ETH_RXINTS; pic32mx_putreg(priv->pd_inten, PIC32MX_ETH_IEN); @@ -1351,7 +1351,7 @@ static void pic32mx_rxdone(struct pic32mx_driver_s *priv) { /* Check if any RX descriptor has the EOWN bit cleared meaning that the * this descriptor is now under software control and a message was - * received. + * received. */ rxdesc = pic32mx_rxdesc(priv); @@ -1387,7 +1387,7 @@ static void pic32mx_rxdone(struct pic32mx_driver_s *priv) * be the same size as our max packet size, any fragments also * imply that the packet is too big. */ - + else if (priv->pd_dev.d_len > CONFIG_NET_BUFSIZE) { nlldbg("Too big. packet length: %d rxdesc: %08x\n", priv->pd_dev.d_len, rxdesc->status); @@ -1408,7 +1408,7 @@ static void pic32mx_rxdone(struct pic32mx_driver_s *priv) uint8_t *rxbuffer; /* Get the Rx buffer address from the Rx descriptor */ - + priv->pd_dev.d_buf = (uint8_t*)VIRT_ADDR(rxdesc->address); DEBUGASSERT(priv->pd_dev.d_buf != NULL); @@ -1744,7 +1744,7 @@ static int pic32mx_interrupt(int irq, void *context) * has no effect. */ - /* FWMARK: Full Watermark Interrupt. This bit is set when the RX + /* FWMARK: Full Watermark Interrupt. This bit is set when the RX * escriptor Buffer Count is greater than or equal to the value in the * RXFWM bit (ETHRXWM:16-23) field. It is cleared by writing the BUFCDEC * (ETHCON1:0) bit to decrement the BUFCNT counter. Writing a ‘0’ or a @@ -1852,7 +1852,7 @@ static void pic32mx_polltimer(int argc, uint32_t arg, ...) * * Description: * NuttX Callback: Bring up the Ethernet interface when an IP address is - * provided + * provided * * Parameters: * dev - Reference to the NuttX driver state structure @@ -2197,7 +2197,7 @@ static int pic32mx_ifdown(struct uip_driver_s *dev) * Function: pic32mx_txavail * * Description: - * Driver callback invoked when new TX data is available. This is a + * Driver callback invoked when new TX data is available. This is a * stimulus perform an out-of-cycle poll and, thereby, reduce the TX * latency. * @@ -2252,7 +2252,7 @@ static int pic32mx_txavail(struct uip_driver_s *dev) * * Parameters: * dev - Reference to the NuttX driver state structure - * mac - The MAC address to be added + * mac - The MAC address to be added * * Returned Value: * None @@ -2282,7 +2282,7 @@ static int pic32mx_addmac(struct uip_driver_s *dev, const uint8_t *mac) * * Parameters: * dev - Reference to the NuttX driver state structure - * mac - The MAC address to be removed + * mac - The MAC address to be removed * * Returned Value: * None @@ -2364,7 +2364,7 @@ static void pic32mx_phybusywait(void) * Parameters: * phyaddr - The device address where the PHY was discovered * regaddr - The address of the PHY register to be written - * phydata - The data to write to the PHY register + * phydata - The data to write to the PHY register * * Returned Value: * None @@ -2630,7 +2630,7 @@ static int pic32mx_phymode(uint8_t phyaddr, uint8_t mode) * Initialize the PHY * * Parameters: - * priv - Pointer to EMAC device driver structure + * priv - Pointer to EMAC device driver structure * * Returned Value: * None directly. As a side-effect, it will initialize priv->pd_phyaddr @@ -2761,7 +2761,7 @@ static inline int pic32mx_phyinit(struct pic32mx_driver_s *priv) } /* Are we configured to do auto-negotiation? - * + * * Preferably the auto-negotiation should be selected if the PHY supports * it. Expose the supported capabilities: Half/Full Duplex, 10BaseT/100Base * TX, etc. (Extended Register 4). Start the negotiation (Control Register @@ -2773,7 +2773,7 @@ static inline int pic32mx_phyinit(struct pic32mx_driver_s *priv) #ifdef CONFIG_PHY_AUTONEG /* Setup the Auto-negotiation advertisement: 100 or 10, and HD or FD */ - pic32mx_phywrite(phyaddr, MII_ADVERTISE, + pic32mx_phywrite(phyaddr, MII_ADVERTISE, (MII_ADVERTISE_100BASETXFULL | MII_ADVERTISE_100BASETXHALF | MII_ADVERTISE_10BASETXFULL | MII_ADVERTISE_10BASETXHALF | MII_ADVERTISE_CSMA)); @@ -2944,7 +2944,7 @@ static void pic32mx_macmode(uint8_t mode) if ((mode & PIC32MX_DUPLEX_MASK) == PIC32MX_DUPLEX_FULL) { /* Set the back-to-back inter-packet gap */ - + pic32mx_putreg(21, PIC32MX_EMAC1_IPGT); /* Set MAC to operate in full duplex mode with CRC and Pad enabled */ @@ -2955,7 +2955,7 @@ static void pic32mx_macmode(uint8_t mode) else { /* Set the back-to-back inter-packet gap */ - + pic32mx_putreg(18, PIC32MX_EMAC1_IPGT); /* Set MAC to operate in half duplex mode with CRC and Pad enabled */ diff --git a/nuttx/arch/rgmp/include/arm/arch/subarch/arch.h b/nuttx/arch/rgmp/include/arm/arch/subarch/arch.h index 8b92c6bfe..e5f3fff10 100644 --- a/nuttx/arch/rgmp/include/arm/arch/subarch/arch.h +++ b/nuttx/arch/rgmp/include/arm/arch/subarch/arch.h @@ -45,12 +45,12 @@ static inline void up_mdelay(uint32_t msec) { - + } static inline void up_udelay(uint32_t usec) { - + } #endif /* !__ASSEMBLY__ */ diff --git a/nuttx/arch/rgmp/include/limits.h b/nuttx/arch/rgmp/include/limits.h index a4458e301..51a17a330 100644 --- a/nuttx/arch/rgmp/include/limits.h +++ b/nuttx/arch/rgmp/include/limits.h @@ -33,8 +33,8 @@ * ************************************************************/ -#ifndef __ARCH_RGMP_INCLUDE_LIMITS_H -#define __ARCH_RGMP_INCLUDE_LIMITS_H +#ifndef __ARCH_RGMP_INCLUDE_LIMITS_H +#define __ARCH_RGMP_INCLUDE_LIMITS_H /************************************************************ * Included Files diff --git a/nuttx/arch/rgmp/src/arm/Make.defs b/nuttx/arch/rgmp/src/arm/Make.defs index 8185980c6..e21b046e8 100644 --- a/nuttx/arch/rgmp/src/arm/Make.defs +++ b/nuttx/arch/rgmp/src/arm/Make.defs @@ -5,7 +5,7 @@ # Author: Yu Qiang <yuq825@gmail.com> # # This file is a part of NuttX: -# +# # Copyright (C) 2011 Gregory Nutt. All rights reserved. # # diff --git a/nuttx/arch/rgmp/src/arm/arch_nuttx.c b/nuttx/arch/rgmp/src/arm/arch_nuttx.c index e916c5520..93d4e447a 100644 --- a/nuttx/arch/rgmp/src/arm/arch_nuttx.c +++ b/nuttx/arch/rgmp/src/arm/arch_nuttx.c @@ -47,7 +47,7 @@ void nuttx_arch_init(void) { - + } void nuttx_arch_exit(void) diff --git a/nuttx/arch/rgmp/src/nuttx.c b/nuttx/arch/rgmp/src/nuttx.c index a154ea34a..e6fee5de1 100644 --- a/nuttx/arch/rgmp/src/nuttx.c +++ b/nuttx/arch/rgmp/src/nuttx.c @@ -176,7 +176,7 @@ FAR void *up_stack_frame(FAR struct tcb_s *tcb, size_t frame_size) /* Align the frame_size */ frame_size = (frame_size + 3) & ~3; - + /* Is there already a stack allocated? Is it big enough? */ if (!tcb->stack_alloc_ptr || tcb->adj_stack_size <= frame_size) { @@ -280,7 +280,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state) } // If there are any pending tasks, then add them to the g_readytorun // task list now. It should be the up_realease_pending() called from - // sched_unlock() to do this for disable preemption. But it block + // sched_unlock() to do this for disable preemption. But it block // itself, so it's OK. if (g_pendingtasks.head) { warn("Disable preemption failed for task block itself\n"); @@ -328,7 +328,7 @@ void up_unblock_task(struct tcb_s *tcb) #if CONFIG_RR_INTERVAL > 0 tcb->timeslice = CONFIG_RR_INTERVAL / MSEC_PER_TICK; #endif - + // Add the task in the correct location in the prioritized // g_readytorun task list. if (sched_addreadytorun(tcb) && !up_interrupt_context()) { @@ -402,7 +402,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) struct tcb_s *nexttcb; // If there are any pending tasks, then add them to the g_readytorun // task list now. It should be the up_realease_pending() called from - // sched_unlock() to do this for disable preemption. But it block + // sched_unlock() to do this for disable preemption. But it block // itself, so it's OK. if (g_pendingtasks.head) { warn("Disable preemption failed for reprioritize task\n"); @@ -439,7 +439,7 @@ void up_assert(const uint8_t *filename, int line) { fprintf(stderr, "Assertion failed at file:%s line: %d\n", filename, line); - // in interrupt context or idle task means kernel error + // in interrupt context or idle task means kernel error // which will stop the OS // if in user space just terminate the task if (up_interrupt_context() || current_task->pid == 0) { @@ -523,7 +523,7 @@ int up_prioritize_irq(int irq, int priority) void up_sigdeliver(struct Trapframe *tf) { sig_deliver_t sigdeliver; - + pop_xcptcontext(¤t_task->xcp); sigdeliver = current_task->xcp.sigdeliver; current_task->xcp.sigdeliver = NULL; diff --git a/nuttx/arch/rgmp/src/rgmp.c b/nuttx/arch/rgmp/src/rgmp.c index e71782112..495c5e05c 100644 --- a/nuttx/arch/rgmp/src/rgmp.c +++ b/nuttx/arch/rgmp/src/rgmp.c @@ -88,7 +88,7 @@ void rtos_kfree(void *addr) /** * The interrupt can be nested. The pair of rtos_enter_interrupt() - * and rtos_exit_interrupt() make sure the context switch is + * and rtos_exit_interrupt() make sure the context switch is * performed only in the last IRQ exit. */ void rtos_enter_interrupt(void) diff --git a/nuttx/arch/rgmp/src/x86/Make.defs b/nuttx/arch/rgmp/src/x86/Make.defs index 5fb40006e..fcf3180d8 100644 --- a/nuttx/arch/rgmp/src/x86/Make.defs +++ b/nuttx/arch/rgmp/src/x86/Make.defs @@ -5,7 +5,7 @@ # Author: Yu Qiang <yuq825@gmail.com> # # This file is a part of NuttX: -# +# # Copyright (C) 2011 Gregory Nutt. All rights reserved. # # diff --git a/nuttx/arch/rgmp/src/x86/com.c b/nuttx/arch/rgmp/src/x86/com.c index 7983bb1bc..5a946db52 100644 --- a/nuttx/arch/rgmp/src/x86/com.c +++ b/nuttx/arch/rgmp/src/x86/com.c @@ -310,7 +310,7 @@ static int up_attach(struct uart_dev_s *dev) int err; err = rgmp_request_irq(priv->irq, &priv->action, 0); - + return err; } @@ -374,7 +374,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) struct inode *inode = filep->f_inode; struct uart_dev_s *dev = inode->i_private; struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - + switch (cmd) { case COM_SET_BAUD: priv->baud = arg; @@ -546,7 +546,7 @@ static bool up_txempty(struct uart_dev_s *dev) * Name: up_serialinit * * Description: - * Performs the low level UART initialization early in + * Performs the low level UART initialization early in * debug so that the serial console will be available * during bootup. This must be called before up_serialinit. * @@ -554,7 +554,7 @@ static bool up_txempty(struct uart_dev_s *dev) void up_earlyserialinit(void) { - + } /**************************************************************************** diff --git a/nuttx/arch/sh/include/m16c/irq.h b/nuttx/arch/sh/include/m16c/irq.h index b134428a7..b24a62443 100644 --- a/nuttx/arch/sh/include/m16c/irq.h +++ b/nuttx/arch/sh/include/m16c/irq.h @@ -208,7 +208,7 @@ * - Save FLG register * - Clear I, D, and U flags in FLG register * - Builds stack frame like: - * + * * sp -> PC bits 0-7 * sp+1 -> PC bits 8-15 * sp+2 -> FLG bits 0-7 diff --git a/nuttx/arch/sh/include/m16c/types.h b/nuttx/arch/sh/include/m16c/types.h index bd23a9a5f..4c68391b0 100644 --- a/nuttx/arch/sh/include/m16c/types.h +++ b/nuttx/arch/sh/include/m16c/types.h @@ -62,7 +62,7 @@ * the user prefers to use the definitions provided by their toolchain header * files * - * int is 16-bits and long is 32-bits + * int is 16-bits and long is 32-bits */ typedef signed char _int8_t; diff --git a/nuttx/arch/sh/src/common/up_assert.c b/nuttx/arch/sh/src/common/up_assert.c index 1c4016665..77dfae286 100644 --- a/nuttx/arch/sh/src/common/up_assert.c +++ b/nuttx/arch/sh/src/common/up_assert.c @@ -63,7 +63,7 @@ # undef CONFIG_ARCH_USBDUMP #endif -/* Output debug info if stack dump is selected -- even if +/* Output debug info if stack dump is selected -- even if * debug is not selected. */ diff --git a/nuttx/arch/sh/src/common/up_blocktask.c b/nuttx/arch/sh/src/common/up_blocktask.c index 9959e71df..81e1789fc 100644 --- a/nuttx/arch/sh/src/common/up_blocktask.c +++ b/nuttx/arch/sh/src/common/up_blocktask.c @@ -129,7 +129,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state) up_copystate(rtcb->xcp.regs, current_regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -147,7 +147,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state) else if (!up_saveusercontext(rtcb->xcp.regs)) { - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/sh/src/common/up_createstack.c b/nuttx/arch/sh/src/common/up_createstack.c index 280b5a6b9..4c2d36ae9 100644 --- a/nuttx/arch/sh/src/common/up_createstack.c +++ b/nuttx/arch/sh/src/common/up_createstack.c @@ -114,7 +114,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) } /* Do we need to allocate a new stack? */ - + if (!tcb->stack_alloc_ptr) { /* Allocate the stack. If DEBUG is enabled (but not stack debug), diff --git a/nuttx/arch/sh/src/common/up_releasepending.c b/nuttx/arch/sh/src/common/up_releasepending.c index b3960972d..f1cde5075 100644 --- a/nuttx/arch/sh/src/common/up_releasepending.c +++ b/nuttx/arch/sh/src/common/up_releasepending.c @@ -97,7 +97,7 @@ void up_release_pending(void) up_copystate(rtcb->xcp.regs, current_regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -111,13 +111,13 @@ void up_release_pending(void) /* Copy the exception context into the TCB of the task that * was currently active. if up_saveusercontext returns a non-zero - * value, then this is really the previously running task + * value, then this is really the previously running task * restarting! */ else if (!up_saveusercontext(rtcb->xcp.regs)) { - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/sh/src/common/up_reprioritizertr.c b/nuttx/arch/sh/src/common/up_reprioritizertr.c index 64f5d9969..8ef6c06c4 100644 --- a/nuttx/arch/sh/src/common/up_reprioritizertr.c +++ b/nuttx/arch/sh/src/common/up_reprioritizertr.c @@ -69,7 +69,7 @@ * * Description: * Called when the priority of a running or - * ready-to-run task changes and the reprioritization will + * ready-to-run task changes and the reprioritization will * cause a context switch. Two cases: * * 1) The priority of the currently running task drops and the next @@ -152,7 +152,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) up_copystate(rtcb->xcp.regs, current_regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -171,7 +171,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) else if (!up_saveusercontext(rtcb->xcp.regs)) { - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/sh/src/common/up_stackframe.c b/nuttx/arch/sh/src/common/up_stackframe.c index 16837f62f..736402b81 100644 --- a/nuttx/arch/sh/src/common/up_stackframe.c +++ b/nuttx/arch/sh/src/common/up_stackframe.c @@ -114,7 +114,7 @@ FAR void *up_stack_frame(FAR struct tcb_s *tcb, size_t frame_size) /* Align the frame_size */ frame_size = STACK_ALIGN_UP(frame_size); - + /* Is there already a stack allocated? Is it big enough? */ if (!tcb->stack_alloc_ptr || tcb->adj_stack_size <= frame_size) diff --git a/nuttx/arch/sh/src/common/up_unblocktask.c b/nuttx/arch/sh/src/common/up_unblocktask.c index 455c50ce2..5ba0173fb 100644 --- a/nuttx/arch/sh/src/common/up_unblocktask.c +++ b/nuttx/arch/sh/src/common/up_unblocktask.c @@ -109,7 +109,7 @@ void up_unblock_task(struct tcb_s *tcb) /* The currently active task has changed! We need to do * a context switch to the new task. * - * Are we in an interrupt handler? + * Are we in an interrupt handler? */ if (current_regs) @@ -120,7 +120,7 @@ void up_unblock_task(struct tcb_s *tcb) up_copystate(rtcb->xcp.regs, current_regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -132,7 +132,7 @@ void up_unblock_task(struct tcb_s *tcb) } /* We are not in an interrupt handler. Copy the user C context - * into the TCB of the task that was previously active. if + * into the TCB of the task that was previously active. if * up_saveusercontext returns a non-zero value, then this is really the * previously running task restarting! */ diff --git a/nuttx/arch/sh/src/common/up_usestack.c b/nuttx/arch/sh/src/common/up_usestack.c index e0f348045..b489762b6 100644 --- a/nuttx/arch/sh/src/common/up_usestack.c +++ b/nuttx/arch/sh/src/common/up_usestack.c @@ -104,7 +104,7 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size) } /* Save the new stack allocation */ - + tcb->stack_alloc_ptr = stack; /* The SH family uses a push-down stack: the stack grows toward lower diff --git a/nuttx/arch/sh/src/m16c/Make.defs b/nuttx/arch/sh/src/m16c/Make.defs index 6d5877b8b..be8f160ea 100644 --- a/nuttx/arch/sh/src/m16c/Make.defs +++ b/nuttx/arch/sh/src/m16c/Make.defs @@ -35,7 +35,7 @@ HEAD_ASRC = m16c_head.S -CMN_ASRCS = +CMN_ASRCS = CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c \ up_createstack.c up_doirq.c up_exit.c up_idle.c up_initialize.c \ up_interruptcontext.c up_lowputs.c up_mdelay.c up_puts.c \ diff --git a/nuttx/arch/sh/src/m16c/m16c_dumpstate.c b/nuttx/arch/sh/src/m16c/m16c_dumpstate.c index 8083f62bd..d0ee37b04 100644 --- a/nuttx/arch/sh/src/m16c/m16c_dumpstate.c +++ b/nuttx/arch/sh/src/m16c/m16c_dumpstate.c @@ -181,7 +181,7 @@ void up_dumpstate(void) } /* Get the limits on the interrupt stack memory. The near RAM memory map is as follows: - * + * * 0x00400 - DATA Size: Determined by linker * BSS Size: Determined by linker * Interrupt stack Size: CONFIG_ARCH_INTERRUPTSTACK diff --git a/nuttx/arch/sh/src/m16c/m16c_head.S b/nuttx/arch/sh/src/m16c/m16c_head.S index e1eca90f1..cd1a3aa7d 100644 --- a/nuttx/arch/sh/src/m16c/m16c_head.S +++ b/nuttx/arch/sh/src/m16c/m16c_head.S @@ -70,7 +70,7 @@ ************************************************************************************/ /* The near RAM memory map is as follows: - * + * * 0x00400 - DATA Size: Determined by linker * BSS Size: Determined by linker * Interrupt stack Size: CONFIG_ARCH_INTERRUPTSTACK diff --git a/nuttx/arch/sh/src/m16c/m16c_irq.c b/nuttx/arch/sh/src/m16c/m16c_irq.c index b62f55b54..5c4645053 100644 --- a/nuttx/arch/sh/src/m16c/m16c_irq.c +++ b/nuttx/arch/sh/src/m16c/m16c_irq.c @@ -78,7 +78,7 @@ volatile uint32_t *current_regs; /* Actually a pointer to the beginning of a uin void up_irqinitialize(void) { current_regs = NULL; - + /* And finally, enable interrupts */ #ifndef CONFIG_SUPPRESS_INTERRUPTS diff --git a/nuttx/arch/sh/src/m16c/m16c_serial.c b/nuttx/arch/sh/src/m16c/m16c_serial.c index a936dd922..b0afc22fe 100644 --- a/nuttx/arch/sh/src/m16c/m16c_serial.c +++ b/nuttx/arch/sh/src/m16c/m16c_serial.c @@ -613,7 +613,7 @@ static int up_setup(struct uart_dev_s *dev) { dbg("Invalid bits=%d\n", priv->bits); } - + if (priv->parity != 0) { regval |= UART_MR_PRYE; @@ -1075,7 +1075,7 @@ static bool up_txready(struct uart_dev_s *dev) * Name: up_earlyconsoleinit * * Description: - * Performs the low level UART initialization early in + * Performs the low level UART initialization early in * debug so that the serial console will be available * during bootup. This must be called before up_consoleinit. * diff --git a/nuttx/arch/sh/src/m16c/m16c_timerisr.c b/nuttx/arch/sh/src/m16c/m16c_timerisr.c index ee61d7601..dfc7f4d91 100644 --- a/nuttx/arch/sh/src/m16c/m16c_timerisr.c +++ b/nuttx/arch/sh/src/m16c/m16c_timerisr.c @@ -161,13 +161,13 @@ void up_timerinit(void) putreg8(0, M16C_TB2IC); /* Set up timer 0 mode register for timer mode with the calculated prescaler value */ - + putreg8(M16C_TA0MODE_CONFIG, M16C_TA0MR); /* Set the calculated reload value */ putreg16(M16C_RELOAD_VALUE, M16C_TA0); - + /* Attach the interrupt handler */ irq_attach(M16C_SYSTIMER_IRQ, (xcpt_t)up_timerisr); @@ -175,7 +175,7 @@ void up_timerinit(void) /* Enable timer interrupts */ putreg8(1, M16C_TA0IC); - + /* Set the interrupt priority */ putreg8(M16C_TA0_PRIO, M16C_TA0IC); diff --git a/nuttx/arch/sh/src/m16c/m16c_vectors.S b/nuttx/arch/sh/src/m16c/m16c_vectors.S index 8a99148e4..f0f151fc3 100644 --- a/nuttx/arch/sh/src/m16c/m16c_vectors.S +++ b/nuttx/arch/sh/src/m16c/m16c_vectors.S @@ -228,7 +228,7 @@ * - Save FLG register * - Clear I, D, and U flags in FLG register * - Builds stack frame like (on the push-down, interrupt stack): - * + * * sp -> PC bits 0-7 * sp+1 -> PC bits 8-15 * sp+2 -> FLG bits 0-7 @@ -245,7 +245,7 @@ m16c_vector _m16c_unexpected_isr, NR_IRQS /* Variable vectors */ - + m16c_vector _m16c_brk_isr, M16C_BRK_IRQ m16c_vector _m16c_int3_isr, M16C_INT3_IRQ m16c_vector _m16c_int5_isr, M16C_INT5_IRQ @@ -372,11 +372,11 @@ _m16c_commonvector: * * Of the ISP to the end of the context array: */ - + ldc r0, isp /* ISP = address of base of new context info */ - + /* Restore the user stack pointer */ - + pop.w r0 /* R0 = saved user stack pointer */ fset u /* Switch to User stack */ ldc r0, sp /* Restore the user stack pointer */ @@ -416,7 +416,7 @@ _up_saveusercontext: * - Save FLG register * - Clear I, D, and U flags in FLG register * - Builds stack frame like (on the push-down, interrupt stack): - * + * * sp -> PC bits 0-7 * sp+1 -> PC bits 8-15 * sp+2 -> FLG bits 0-7 @@ -482,7 +482,7 @@ _up_fullcontextrestore: * - Save FLG register * - Clear I and D flags in FLG register (U is preserved) * - Builds stack frame like (on the push-down, interrupt stack): - * + * * sp -> PC bits 0-7 * sp+1 -> PC bits 8-15 * sp+2 -> FLG bits 0-7 @@ -497,9 +497,9 @@ _m16c_contextrestore: /* Set the USP to the beginning of the context save area */ ldc r1, sp /* USP = address of base of new context info */ - + /* Restore the user stack pointer */ - + fset b /* Switch to bank 1 */ pop.w r0 /* R0 = saved user stack pointer */ fclr b /* Back to bank 0 */ diff --git a/nuttx/arch/sh/src/sh1/Make.defs b/nuttx/arch/sh/src/sh1/Make.defs index d75fdf70d..ab96a3657 100644 --- a/nuttx/arch/sh/src/sh1/Make.defs +++ b/nuttx/arch/sh/src/sh1/Make.defs @@ -35,7 +35,7 @@ HEAD_ASRC = sh1_head.S -CMN_ASRCS = +CMN_ASRCS = CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c \ up_createstack.c up_doirq.c up_exit.c up_idle.c up_initialize.c \ up_initialstate.c up_interruptcontext.c up_lowputs.c \ @@ -51,6 +51,6 @@ CMN_CSRCS += sh1_schedulesigaction.c sh1_sigdeliver.c endif ifeq ($(CONFIG_USBDEV),y) -CHIP_CSRCS += +CHIP_CSRCS += endif diff --git a/nuttx/arch/sh/src/sh1/sh1_dumpstate.c b/nuttx/arch/sh/src/sh1/sh1_dumpstate.c index e9ffc4caa..849c406df 100644 --- a/nuttx/arch/sh/src/sh1/sh1_dumpstate.c +++ b/nuttx/arch/sh/src/sh1/sh1_dumpstate.c @@ -55,7 +55,7 @@ * Definitions ****************************************************************************/ -/* Output debug info if stack dump is selected -- even if +/* Output debug info if stack dump is selected -- even if * debug is not selected. */ diff --git a/nuttx/arch/sh/src/sh1/sh1_head.S b/nuttx/arch/sh/src/sh1/sh1_head.S index 89d6bf288..3654d0c60 100644 --- a/nuttx/arch/sh/src/sh1/sh1_head.S +++ b/nuttx/arch/sh/src/sh1/sh1_head.S @@ -477,7 +477,7 @@ __start0: .Ledata: .long _edata #endif -.Lsbss: +.Lsbss: .long _sbss .Lebss: .long _ebss diff --git a/nuttx/arch/sh/src/sh1/sh1_saveusercontext.S b/nuttx/arch/sh/src/sh1/sh1_saveusercontext.S index 56a43a2fb..a1b6bfff9 100644 --- a/nuttx/arch/sh/src/sh1/sh1_saveusercontext.S +++ b/nuttx/arch/sh/src/sh1/sh1_saveusercontext.S @@ -81,7 +81,7 @@ _up_saveusercontext: * to populate. * * Re-position to the end of the structure (+4_ so that we can use - * auto decrement + * auto decrement */ add #(XCPTCONTEXT_SIZE), r4 /* R4: Address of last entry + 4 */ diff --git a/nuttx/arch/sh/src/sh1/sh1_serial.c b/nuttx/arch/sh/src/sh1/sh1_serial.c index 5f521fa5a..3719e0d5f 100644 --- a/nuttx/arch/sh/src/sh1/sh1_serial.c +++ b/nuttx/arch/sh/src/sh1/sh1_serial.c @@ -568,7 +568,7 @@ static int up_interrupt(int irq, void *context) struct up_dev_s *priv; #ifdef CONFIG_SH1_SCI0 - if ((irq >= g_sci0priv.irq) && + if ((irq >= g_sci0priv.irq) && (irq <= g_sci0priv.irq + SH1_SCI_NIRQS)) { dev = &g_sci0port; @@ -576,7 +576,7 @@ static int up_interrupt(int irq, void *context) else #endif #ifdef CONFIG_SH1_SCI1 - if ((irq >= g_sci1priv.irq) && + if ((irq >= g_sci1priv.irq) && (irq <= g_sci1priv.irq + SH1_SCI_NIRQS)) { dev = &g_sci1port; @@ -616,7 +616,7 @@ static int up_interrupt(int irq, void *context) /* Handle outgoing, transmit bytes (TDRE: Transmit Data Register Empty) * when TIE is enabled. TIE is only enabled when the driver is waiting with - * buffered data. Since TDRE is usually true, + * buffered data. Since TDRE is usually true, */ if ((priv->ssr & SH1_SCISSR_TDRE) != 0 && (priv->scr & SH1_SCISCR_TIE) != 0) @@ -836,7 +836,7 @@ static bool up_txready(struct uart_dev_s *dev) * Name: up_earlyconsoleinit * * Description: - * Performs the low level SCI initialization early in + * Performs the low level SCI initialization early in * debug so that the serial console will be available * during bootup. This must be called before up_consoleinit. * diff --git a/nuttx/arch/sim/include/limits.h b/nuttx/arch/sim/include/limits.h index 9288cb585..5a8d7c54e 100644 --- a/nuttx/arch/sim/include/limits.h +++ b/nuttx/arch/sim/include/limits.h @@ -33,8 +33,8 @@ * ************************************************************/ -#ifndef __ARCH_SIM_INCLUDE_LIMITS_H -#define __ARCH_SIM_INCLUDE_LIMITS_H +#ifndef __ARCH_SIM_INCLUDE_LIMITS_H +#define __ARCH_SIM_INCLUDE_LIMITS_H /************************************************************ * Included Files diff --git a/nuttx/arch/sim/src/Makefile b/nuttx/arch/sim/src/Makefile index 29eadb395..02eda68bd 100644 --- a/nuttx/arch/sim/src/Makefile +++ b/nuttx/arch/sim/src/Makefile @@ -111,7 +111,7 @@ STDLIBS += -lc # Determine which objects are required in the link. The # up_head object normally draws in all that is needed, but -# there are a fews that must be included because they +# there are a fews that must be included because they # are called only from the host OS-specific logic (HOSTOBJS) LINKOBJS = up_head$(OBJEXT) @@ -132,7 +132,7 @@ RELPATHS += -L"$(TOPDIR)/lib" # Add the board-specific library and directory -LIBPATHS += -L board +LIBPATHS += -L board RELPATHS += -L board RELLIBS += -lboard @@ -207,7 +207,7 @@ export_head: board/libboard$(LIBEXT) up_head.o $(HOSTOBJS) depend: .depend -cleanrel: +cleanrel: $(Q) rm -f nuttx.rel GNU/Linux-names.dat Cygwin-names.dat clean: cleanrel diff --git a/nuttx/arch/sim/src/up_blocktask.c b/nuttx/arch/sim/src/up_blocktask.c index db9701434..6e0f94015 100644 --- a/nuttx/arch/sim/src/up_blocktask.c +++ b/nuttx/arch/sim/src/up_blocktask.c @@ -129,7 +129,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state) if (!up_setjmp(rtcb->xcp.regs)) { - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/sim/src/up_framebuffer.c b/nuttx/arch/sim/src/up_framebuffer.c index bf80e99a1..e20dd92e3 100644 --- a/nuttx/arch/sim/src/up_framebuffer.c +++ b/nuttx/arch/sim/src/up_framebuffer.c @@ -303,7 +303,7 @@ static int up_getcursor(FAR struct fb_vtable_s *vtable, #endif /**************************************************************************** - * Name: + * Name: ****************************************************************************/ #ifdef CONFIG_FB_HWCURSOR diff --git a/nuttx/arch/sim/src/up_lcd.c b/nuttx/arch/sim/src/up_lcd.c index 4c2031dd2..abbb2a8e0 100644 --- a/nuttx/arch/sim/src/up_lcd.c +++ b/nuttx/arch/sim/src/up_lcd.c @@ -32,7 +32,7 @@ * POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************/ - + /**************************************************************************** * Included Files ****************************************************************************/ @@ -203,7 +203,7 @@ static const struct fb_videoinfo_s g_videoinfo = /* This is the standard, NuttX Plane information object */ -static const struct lcd_planeinfo_s g_planeinfo = +static const struct lcd_planeinfo_s g_planeinfo = { .putrun = sim_putrun, /* Put a run into LCD memory */ .getrun = sim_getrun, /* Get a run from LCD memory */ @@ -213,12 +213,12 @@ static const struct lcd_planeinfo_s g_planeinfo = /* This is the standard, NuttX LCD driver object */ -static struct sim_dev_s g_lcddev = +static struct sim_dev_s g_lcddev = { .dev = { /* LCD Configuration */ - + .getvideoinfo = sim_getvideoinfo, .getplaneinfo = sim_getplaneinfo, diff --git a/nuttx/arch/sim/src/up_releasepending.c b/nuttx/arch/sim/src/up_releasepending.c index 036c65299..a1c2eb544 100644 --- a/nuttx/arch/sim/src/up_releasepending.c +++ b/nuttx/arch/sim/src/up_releasepending.c @@ -92,7 +92,7 @@ void up_release_pending(void) if (!up_setjmp(rtcb->xcp.regs)) { - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/sim/src/up_reprioritizertr.c b/nuttx/arch/sim/src/up_reprioritizertr.c index 7423a7112..578fd5a97 100644 --- a/nuttx/arch/sim/src/up_reprioritizertr.c +++ b/nuttx/arch/sim/src/up_reprioritizertr.c @@ -70,7 +70,7 @@ * * Description: * Called when the priority of a running or - * ready-to-run task changes and the reprioritization will + * ready-to-run task changes and the reprioritization will * cause a context switch. Two cases: * * 1) The priority of the currently running task drops and the next @@ -150,7 +150,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) if (!up_setjmp(rtcb->xcp.regs)) { - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/sim/src/up_setjmp.S b/nuttx/arch/sim/src/up_setjmp.S index a65317c65..c40884352 100644 --- a/nuttx/arch/sim/src/up_setjmp.S +++ b/nuttx/arch/sim/src/up_setjmp.S @@ -46,7 +46,7 @@ /************************************************************************** * Private Definitions **************************************************************************/ - + #ifdef __CYGWIN__ # define SYMBOL(s) _##s #else diff --git a/nuttx/arch/sim/src/up_stackframe.c b/nuttx/arch/sim/src/up_stackframe.c index 3fc481fca..542403c9a 100644 --- a/nuttx/arch/sim/src/up_stackframe.c +++ b/nuttx/arch/sim/src/up_stackframe.c @@ -116,7 +116,7 @@ FAR void *up_stack_frame(FAR struct tcb_s *tcb, size_t frame_size) /* Align the frame_size */ frame_size = STACK_ALIGN_UP(frame_size); - + /* Is there already a stack allocated? Is it big enough? */ if (!tcb->stack_alloc_ptr || tcb->adj_stack_size <= frame_size) diff --git a/nuttx/arch/sim/src/up_touchscreen.c b/nuttx/arch/sim/src/up_touchscreen.c index c65013738..9ee99cbe9 100644 --- a/nuttx/arch/sim/src/up_touchscreen.c +++ b/nuttx/arch/sim/src/up_touchscreen.c @@ -199,7 +199,7 @@ static void up_notify(FAR struct up_dev_s *priv) * is no longer avaialable. */ - sem_post(&priv->waitsem); + sem_post(&priv->waitsem); } /* If there are threads waiting on poll() for touchscreen data to become availabe, diff --git a/nuttx/arch/sim/src/up_unblocktask.c b/nuttx/arch/sim/src/up_unblocktask.c index 35961c5f8..04c2349e4 100644 --- a/nuttx/arch/sim/src/up_unblocktask.c +++ b/nuttx/arch/sim/src/up_unblocktask.c @@ -109,7 +109,7 @@ void up_unblock_task(struct tcb_s *tcb) if (sched_addreadytorun(tcb)) { /* The currently active task has changed! Copy the exception context - * into the TCB of the task that was previously active. if + * into the TCB of the task that was previously active. if * up_setjmp returns a non-zero value, then this is really the * previously running task restarting! */ diff --git a/nuttx/arch/sim/src/up_x11framebuffer.c b/nuttx/arch/sim/src/up_x11framebuffer.c index a035e2f3a..f59320a46 100644 --- a/nuttx/arch/sim/src/up_x11framebuffer.c +++ b/nuttx/arch/sim/src/up_x11framebuffer.c @@ -276,7 +276,7 @@ static inline int up_x11mapsharedmem(int depth, unsigned int fblen) printf("Using shared memory.\n"); up_x11traperrors(); - g_image = XShmCreateImage(g_display, DefaultVisual(g_display, g_screen), + g_image = XShmCreateImage(g_display, DefaultVisual(g_display, g_screen), depth, ZPixmap, NULL, &g_xshminfo, g_fbpixelwidth, g_fbpixelheight); if (up_x11untraperrors()) diff --git a/nuttx/arch/x86/include/i486/arch.h b/nuttx/arch/x86/include/i486/arch.h index 6bb2418d7..adb457f82 100644 --- a/nuttx/arch/x86/include/i486/arch.h +++ b/nuttx/arch/x86/include/i486/arch.h @@ -160,7 +160,7 @@ * For example if we wanted to read the In-Service Register (ISR), then we * would set both bits 1 and 0 to 1. The next read to the base register, * (0x20 for PIC1 or 0xa0 for PIC2) will return the status of the In-Service - * Register. + * Register. */ #define PIC1_OCW3 0x20 @@ -179,7 +179,7 @@ /* If the PIC has been reset, it must be initialized with 2 to 4 Initialization * Command Words (ICW) before it will accept and process Interrupt Requests. The - * following outlines the four possible Initialization Command Words. + * following outlines the four possible Initialization Command Words. */ #define PIC1_ICW1 0x20 @@ -197,7 +197,7 @@ * released onto the bus, during the 2nd INTA Pulse. Using the 8086 mode, * only bits 7:3 need to be used. This will be 00001000 (0x08) for PIC1 and * 01110000 (0x70) for PIC2. If you wish to relocate the IRQ Vector Table, - * then you can use this register. + * then you can use this register. */ #define PIC1_ICW2 0x21 @@ -309,7 +309,7 @@ * * The Global Descriptor Table or GDT is a data structure used by Intel x86- * family processors starting with the 80286 in order to define the - * characteristics of the various memory areas used during program execution, + * characteristics of the various memory areas used during program execution, * for example the base address, the size and access privileges like * executability and writability. These memory areas are called segments in * Intel terminology. diff --git a/nuttx/arch/x86/include/i486/limits.h b/nuttx/arch/x86/include/i486/limits.h index aa167a0af..8bcc4c42d 100644 --- a/nuttx/arch/x86/include/i486/limits.h +++ b/nuttx/arch/x86/include/i486/limits.h @@ -33,8 +33,8 @@ * ****************************************************************************/ -#ifndef __ARCH_X86_INCLUDE_I486_LIMITS_H -#define __ARCH_X86_INCLUDE_I486_LIMITS_H +#ifndef __ARCH_X86_INCLUDE_I486_LIMITS_H +#define __ARCH_X86_INCLUDE_I486_LIMITS_H /**************************************************************************** * Included Files diff --git a/nuttx/arch/x86/src/common/up_assert.c b/nuttx/arch/x86/src/common/up_assert.c index 8f4f53b9a..ed9b0cdb2 100644 --- a/nuttx/arch/x86/src/common/up_assert.c +++ b/nuttx/arch/x86/src/common/up_assert.c @@ -64,7 +64,7 @@ # undef CONFIG_ARCH_USBDUMP #endif -/* Output debug info if stack dump is selected -- even if +/* Output debug info if stack dump is selected -- even if * debug is not selected. */ diff --git a/nuttx/arch/x86/src/common/up_blocktask.c b/nuttx/arch/x86/src/common/up_blocktask.c index dba388cb0..f436c006f 100644 --- a/nuttx/arch/x86/src/common/up_blocktask.c +++ b/nuttx/arch/x86/src/common/up_blocktask.c @@ -129,7 +129,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -147,7 +147,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state) else if (!up_saveusercontext(rtcb->xcp.regs)) { - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/x86/src/common/up_releasepending.c b/nuttx/arch/x86/src/common/up_releasepending.c index 3f9f9fc0b..9507ff898 100644 --- a/nuttx/arch/x86/src/common/up_releasepending.c +++ b/nuttx/arch/x86/src/common/up_releasepending.c @@ -97,7 +97,7 @@ void up_release_pending(void) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -111,13 +111,13 @@ void up_release_pending(void) /* Copy the exception context into the TCB of the task that * was currently active. if up_saveusercontext returns a non-zero - * value, then this is really the previously running task + * value, then this is really the previously running task * restarting! */ else if (!up_saveusercontext(rtcb->xcp.regs)) { - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/x86/src/common/up_reprioritizertr.c b/nuttx/arch/x86/src/common/up_reprioritizertr.c index 8c83b0790..3c5115b72 100644 --- a/nuttx/arch/x86/src/common/up_reprioritizertr.c +++ b/nuttx/arch/x86/src/common/up_reprioritizertr.c @@ -69,7 +69,7 @@ * * Description: * Called when the priority of a running or - * ready-to-run task changes and the reprioritization will + * ready-to-run task changes and the reprioritization will * cause a context switch. Two cases: * * 1) The priority of the currently running task drops and the next @@ -152,7 +152,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -171,7 +171,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) else if (!up_saveusercontext(rtcb->xcp.regs)) { - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/x86/src/common/up_unblocktask.c b/nuttx/arch/x86/src/common/up_unblocktask.c index 873ff1420..43b93c4e6 100644 --- a/nuttx/arch/x86/src/common/up_unblocktask.c +++ b/nuttx/arch/x86/src/common/up_unblocktask.c @@ -108,7 +108,7 @@ void up_unblock_task(struct tcb_s *tcb) /* The currently active task has changed! We need to do * a context switch to the new task. * - * Are we in an interrupt handler? + * Are we in an interrupt handler? */ if (current_regs) @@ -119,7 +119,7 @@ void up_unblock_task(struct tcb_s *tcb) up_savestate(rtcb->xcp.regs); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -131,7 +131,7 @@ void up_unblock_task(struct tcb_s *tcb) } /* We are not in an interrupt handler. Copy the user C context - * into the TCB of the task that was previously active. if + * into the TCB of the task that was previously active. if * up_saveusercontext returns a non-zero value, then this is really the * previously running task restarting! */ diff --git a/nuttx/arch/x86/src/i486/up_createstack.c b/nuttx/arch/x86/src/i486/up_createstack.c index a619ed19b..cdd7fec7c 100644 --- a/nuttx/arch/x86/src/i486/up_createstack.c +++ b/nuttx/arch/x86/src/i486/up_createstack.c @@ -116,7 +116,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) } /* Do we need to allocate a new stack? */ - + if (!tcb->stack_alloc_ptr) { /* Allocate the stack. If DEBUG is enabled (but not stack debug), diff --git a/nuttx/arch/x86/src/i486/up_irq.c b/nuttx/arch/x86/src/i486/up_irq.c index a160379e2..6a56c361a 100644 --- a/nuttx/arch/x86/src/i486/up_irq.c +++ b/nuttx/arch/x86/src/i486/up_irq.c @@ -106,7 +106,7 @@ static void idt_outb(uint8_t val, uint16_t addr) * combine several sources of interrupt onto one or more CPU lines, while * allowing priority levels to be assigned to its interrupt outputs. When * the device has multiple interrupt outputs to assert, it will assert them - * in the order of their relative priority. + * in the order of their relative priority. * ****************************************************************************/ @@ -119,7 +119,7 @@ static void up_remappic(void) /* If the PIC has been reset, it must be initialized with 2 to 4 Initialization * Command Words (ICW) before it will accept and process Interrupt Requests. The - * following outlines the four possible Initialization Command Words. + * following outlines the four possible Initialization Command Words. */ /* Remap the irq table for primary: @@ -150,7 +150,7 @@ static void up_remappic(void) * Name up_idtentry * * Description: - * Initialize one IDT entry. + * Initialize one IDT entry. * ****************************************************************************/ @@ -293,7 +293,7 @@ void up_disable_irq(int irq) { unsigned int regaddr; uint8_t regbit; - + if (irq >= IRQ0) { /* Map the IRQ IMR regiser to a PIC and a bit number */ @@ -331,7 +331,7 @@ void up_enable_irq(int irq) { unsigned int regaddr; uint8_t regbit; - + if (irq >= IRQ0) { /* Map the IRQ IMR regiser to a PIC and a bit number */ diff --git a/nuttx/arch/x86/src/i486/up_savestate.c b/nuttx/arch/x86/src/i486/up_savestate.c index ce237efac..ad280e4fd 100644 --- a/nuttx/arch/x86/src/i486/up_savestate.c +++ b/nuttx/arch/x86/src/i486/up_savestate.c @@ -77,7 +77,7 @@ void up_savestate(uint32_t *regs) { uint8_t cpl; uint8_t rpl; - + /* First, just copy all of the registers */ up_copystate(regs, (uint32_t*)current_regs); diff --git a/nuttx/arch/x86/src/i486/up_stackframe.c b/nuttx/arch/x86/src/i486/up_stackframe.c index d8884b790..fd93ac48f 100644 --- a/nuttx/arch/x86/src/i486/up_stackframe.c +++ b/nuttx/arch/x86/src/i486/up_stackframe.c @@ -117,7 +117,7 @@ FAR void *up_stack_frame(FAR struct tcb_s *tcb, size_t frame_size) /* Align the frame_size */ frame_size = STACK_ALIGN_UP(frame_size); - + /* Is there already a stack allocated? Is it big enough? */ if (!tcb->stack_alloc_ptr || tcb->adj_stack_size <= frame_size) diff --git a/nuttx/arch/x86/src/qemu/qemu_head.S b/nuttx/arch/x86/src/qemu/qemu_head.S index 8e9c8a1db..8c49b5fcd 100755 --- a/nuttx/arch/x86/src/qemu/qemu_head.S +++ b/nuttx/arch/x86/src/qemu/qemu_head.S @@ -44,7 +44,7 @@ /**************************************************************************** * Pre-processor definitions ****************************************************************************/ - + /* Memory Map: _sbss is the start of the BSS region (see ld.script) _ebss is * the end of the BSS regsion (see ld.script). The idle task stack starts at * the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE thread diff --git a/nuttx/arch/x86/src/qemu/qemu_lowputc.c b/nuttx/arch/x86/src/qemu/qemu_lowputc.c index 9bfee18d0..9260884a3 100644 --- a/nuttx/arch/x86/src/qemu/qemu_lowputc.c +++ b/nuttx/arch/x86/src/qemu/qemu_lowputc.c @@ -46,7 +46,7 @@ ****************************************************************************/ /* COM1 port addresses */ - + #define COM1_PORT 0x3f8 /* COM1: I/O port 0x3f8, IRQ 4 */ #define COM2_PORT 0x2f8 /* COM2: I/O port 0x2f8, IRQ 3 */ #define COM3_PORT 0x3e8 /* COM3: I/O port 0x3e8, IRQ 4 */ diff --git a/nuttx/arch/x86/src/qemu/qemu_lowsetup.c b/nuttx/arch/x86/src/qemu/qemu_lowsetup.c index 3b58f696c..db2b01ef5 100644 --- a/nuttx/arch/x86/src/qemu/qemu_lowsetup.c +++ b/nuttx/arch/x86/src/qemu/qemu_lowsetup.c @@ -75,7 +75,7 @@ static void up_gdtentry(struct gdt_entry_s *entry, uint32_t base, entry->lowlimit = (limit & 0xffff); entry->granularity = (limit >> 16) & 0x0f; - + entry->granularity |= gran & 0xf0; entry->access = access; } diff --git a/nuttx/arch/x86/src/qemu/qemu_saveusercontext.S b/nuttx/arch/x86/src/qemu/qemu_saveusercontext.S index ab1244798..4ef68a383 100644 --- a/nuttx/arch/x86/src/qemu/qemu_saveusercontext.S +++ b/nuttx/arch/x86/src/qemu/qemu_saveusercontext.S @@ -161,7 +161,7 @@ up_saveusercontext: * function when context is switch back to this thread. The non-zero * return value is the indication that we have been resumed. */ - + movl $1, (4*REG_EAX)(%eax) /* Get and save the interrupt state */ diff --git a/nuttx/arch/z16/include/limits.h b/nuttx/arch/z16/include/limits.h index 6601c4737..0abbd6b29 100644 --- a/nuttx/arch/z16/include/limits.h +++ b/nuttx/arch/z16/include/limits.h @@ -33,8 +33,8 @@ * ****************************************************************************/ -#ifndef __ARCH_Z16_INCLUDE_LIMITS_H -#define __ARCH_Z16_INCLUDE_LIMITS_H +#ifndef __ARCH_Z16_INCLUDE_LIMITS_H +#define __ARCH_Z16_INCLUDE_LIMITS_H /**************************************************************************** * Included Files diff --git a/nuttx/arch/z16/include/types.h b/nuttx/arch/z16/include/types.h index e58a93ba1..a1d7c9eff 100644 --- a/nuttx/arch/z16/include/types.h +++ b/nuttx/arch/z16/include/types.h @@ -37,8 +37,8 @@ * only indirectly through sys/types.h */ -#ifndef __ARCH_Z16_INCLUDE_TYPES_H -#define __ARCH_Z16_INCLUDE_TYPES_H +#ifndef __ARCH_Z16_INCLUDE_TYPES_H +#define __ARCH_Z16_INCLUDE_TYPES_H /**************************************************************************** * Included Files diff --git a/nuttx/arch/z16/src/common/up_assert.c b/nuttx/arch/z16/src/common/up_assert.c index d2b64026e..051d8ca01 100644 --- a/nuttx/arch/z16/src/common/up_assert.c +++ b/nuttx/arch/z16/src/common/up_assert.c @@ -63,7 +63,7 @@ # undef CONFIG_ARCH_USBDUMP #endif -/* Output debug info if stack dump is selected -- even if +/* Output debug info if stack dump is selected -- even if * debug is not selected. */ diff --git a/nuttx/arch/z16/src/common/up_blocktask.c b/nuttx/arch/z16/src/common/up_blocktask.c index 56618ab3d..c8a8fae99 100644 --- a/nuttx/arch/z16/src/common/up_blocktask.c +++ b/nuttx/arch/z16/src/common/up_blocktask.c @@ -132,7 +132,7 @@ void up_block_task(FAR struct tcb_s *tcb, tstate_t task_state) SAVE_IRQCONTEXT(rtcb); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -153,7 +153,7 @@ void up_block_task(FAR struct tcb_s *tcb, tstate_t task_state) else if (!SAVE_USERCONTEXT(rtcb)) { - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/z16/src/common/up_createstack.c b/nuttx/arch/z16/src/common/up_createstack.c index bdb6d2647..0a7fecd3b 100644 --- a/nuttx/arch/z16/src/common/up_createstack.c +++ b/nuttx/arch/z16/src/common/up_createstack.c @@ -115,7 +115,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) } /* Do we need to allocate a new stack? */ - + if (!tcb->stack_alloc_ptr) { /* Allocate the stack. If DEBUG is enabled (but not stack debug), diff --git a/nuttx/arch/z16/src/common/up_doirq.c b/nuttx/arch/z16/src/common/up_doirq.c index 1009814ce..ffe15a114 100644 --- a/nuttx/arch/z16/src/common/up_doirq.c +++ b/nuttx/arch/z16/src/common/up_doirq.c @@ -81,7 +81,7 @@ FAR chipreg_t *up_doirq(int irq, FAR chipreg_t *regs) { FAR chipreg_t *ret = regs; - + board_led_on(LED_INIRQ); #ifdef CONFIG_SUPPRESS_INTERRUPTS PANIC(); diff --git a/nuttx/arch/z16/src/common/up_registerdump.c b/nuttx/arch/z16/src/common/up_registerdump.c index 178320dd2..c56658f16 100644 --- a/nuttx/arch/z16/src/common/up_registerdump.c +++ b/nuttx/arch/z16/src/common/up_registerdump.c @@ -52,7 +52,7 @@ * Definitions ****************************************************************************/ -/* Output debug info if stack dump is selected -- even if +/* Output debug info if stack dump is selected -- even if * debug is not selected. */ diff --git a/nuttx/arch/z16/src/common/up_releasepending.c b/nuttx/arch/z16/src/common/up_releasepending.c index a25459730..7db0cd614 100644 --- a/nuttx/arch/z16/src/common/up_releasepending.c +++ b/nuttx/arch/z16/src/common/up_releasepending.c @@ -99,7 +99,7 @@ void up_release_pending(void) SAVE_IRQCONTEXT(rtcb); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -115,13 +115,13 @@ void up_release_pending(void) /* Copy the exception context into the TCB of the task that * was currently active. if SAVE_USERCONTEXT returns a non-zero - * value, then this is really the previously running task + * value, then this is really the previously running task * restarting! */ else if (!SAVE_USERCONTEXT(rtcb)) { - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/z16/src/common/up_reprioritizertr.c b/nuttx/arch/z16/src/common/up_reprioritizertr.c index bbfee7845..456d39010 100644 --- a/nuttx/arch/z16/src/common/up_reprioritizertr.c +++ b/nuttx/arch/z16/src/common/up_reprioritizertr.c @@ -71,7 +71,7 @@ * * Description: * Called when the priority of a running or - * ready-to-run task changes and the reprioritization will + * ready-to-run task changes and the reprioritization will * cause a context switch. Two cases: * * 1) The priority of the currently running task drops and the next @@ -154,7 +154,7 @@ void up_reprioritize_rtr(FAR struct tcb_s *tcb, uint8_t priority) SAVE_IRQCONTEXT(rtcb); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -175,7 +175,7 @@ void up_reprioritize_rtr(FAR struct tcb_s *tcb, uint8_t priority) else if (!SAVE_USERCONTEXT(rtcb)) { - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/z16/src/common/up_stackdump.c b/nuttx/arch/z16/src/common/up_stackdump.c index ef9eebb23..fd16cf238 100644 --- a/nuttx/arch/z16/src/common/up_stackdump.c +++ b/nuttx/arch/z16/src/common/up_stackdump.c @@ -49,7 +49,7 @@ * Definitions ****************************************************************************/ -/* Output debug info if stack dump is selected -- even if +/* Output debug info if stack dump is selected -- even if * debug is not selected. */ diff --git a/nuttx/arch/z16/src/common/up_stackframe.c b/nuttx/arch/z16/src/common/up_stackframe.c index ea2d696c8..feb5c8578 100644 --- a/nuttx/arch/z16/src/common/up_stackframe.c +++ b/nuttx/arch/z16/src/common/up_stackframe.c @@ -115,7 +115,7 @@ FAR void *up_stack_frame(FAR struct tcb_s *tcb, size_t frame_size) /* Align the frame_size */ frame_size = STACK_ALIGN_UP(frame_size); - + /* Is there already a stack allocated? Is it big enough? */ if (!tcb->stack_alloc_ptr || tcb->adj_stack_size <= frame_size) diff --git a/nuttx/arch/z16/src/common/up_unblocktask.c b/nuttx/arch/z16/src/common/up_unblocktask.c index a629b5066..984e514ad 100644 --- a/nuttx/arch/z16/src/common/up_unblocktask.c +++ b/nuttx/arch/z16/src/common/up_unblocktask.c @@ -113,7 +113,7 @@ void up_unblock_task(FAR struct tcb_s *tcb) /* The currently active task has changed! We need to do * a context switch to the new task. * - * Are we in an interrupt handler? + * Are we in an interrupt handler? */ if (IN_INTERRUPT) @@ -124,7 +124,7 @@ void up_unblock_task(FAR struct tcb_s *tcb) SAVE_IRQCONTEXT(rtcb); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -139,7 +139,7 @@ void up_unblock_task(FAR struct tcb_s *tcb) } /* We are not in an interrupt handler. Copy the user C context - * into the TCB of the task that was previously active. if + * into the TCB of the task that was previously active. if * SAVE_USERCONTEXT returns a non-zero value, then this is really the * previously running task restarting! */ diff --git a/nuttx/arch/z16/src/z16f/Make.defs b/nuttx/arch/z16/src/z16f/Make.defs index 4c47cf41b..4146c1221 100644 --- a/nuttx/arch/z16/src/z16f/Make.defs +++ b/nuttx/arch/z16/src/z16f/Make.defs @@ -35,7 +35,7 @@ HEAD_SSRC = z16f_head.S -CMN_SSRCS = +CMN_SSRCS = CMN_CSRCS = up_allocateheap.c up_initialize.c up_schedulesigaction.c \ up_assert.c up_initialstate.c up_sigdeliver.c up_blocktask.c \ up_interruptcontext.c up_stackdump.c up_copystate.c \ diff --git a/nuttx/arch/z16/src/z16f/chip.h b/nuttx/arch/z16/src/z16f/chip.h index f684652cb..05ce812c0 100644 --- a/nuttx/arch/z16/src/z16f/chip.h +++ b/nuttx/arch/z16/src/z16f/chip.h @@ -62,7 +62,7 @@ #endif /* Z16F Chip Variants ***************************************************************/ - + #if defined(CONFIG_ARCH_CHIP_Z16F2810) # define Z16F_INVMEM_SIZE (128*1024) # define Z16F_IRAM_SIZE (4*1024) @@ -122,7 +122,7 @@ * Internal non-volatile memory starts at address zero. The size * of the internal non-volatile memory is chip-dependent. */ - + #define Z16F_INVMEM_BASE _HX32(00000000) /* Most chip variants support external memory */ @@ -141,7 +141,7 @@ /* Internal RAM always ends at 0xffbfff. The IRAM base address depends * on the size of the IRAM supported by the chip. */ - + #define Z16F_IRAM_BASE (_HX32(ffffc000) - Z16F_IRAM_SIZE) /* External memory mapped peripherals, internal I/O memory and SFRS */ diff --git a/nuttx/arch/z16/src/z16f/z16f_clkinit.c b/nuttx/arch/z16/src/z16f/z16f_clkinit.c index d125d6143..4e6b80e80 100644 --- a/nuttx/arch/z16/src/z16f/z16f_clkinit.c +++ b/nuttx/arch/z16/src/z16f/z16f_clkinit.c @@ -77,7 +77,7 @@ extern _Erom unsigned long SYS_CLK_FREQ; * and the clock source is _DEFSRC. * * NOTE: The UART output is designed to work with 5.56 MHz internal and 20 MHz - * External clock frequencies at the Default Baud rate of 57.6K Baud. + * External clock frequencies at the Default Baud rate of 57.6K Baud. * Entering different clock frequencies may cause the UART to stop transmitting * unless the user makes changes to the UART routines. * diff --git a/nuttx/arch/z16/src/z16f/z16f_head.S b/nuttx/arch/z16/src/z16f/z16f_head.S index c1a69a18e..2a45095c5 100755 --- a/nuttx/arch/z16/src/z16f/z16f_head.S +++ b/nuttx/arch/z16/src/z16f/z16f_head.S @@ -121,7 +121,7 @@ vector C2=_c3_isr vector C1=_c2_isr vector C0=_c0_isr - + /************************************************************************** * Equates **************************************************************************/ @@ -129,7 +129,7 @@ /************************************************************************** * Data Allocation **************************************************************************/ - + /************************************************************************** * Code **************************************************************************/ diff --git a/nuttx/arch/z16/src/z16f/z16f_sysexec.c b/nuttx/arch/z16/src/z16f/z16f_sysexec.c index bd922237f..eb3c4065c 100644 --- a/nuttx/arch/z16/src/z16f/z16f_sysexec.c +++ b/nuttx/arch/z16/src/z16f/z16f_sysexec.c @@ -81,13 +81,13 @@ void z16f_sysexec(FAR chipreg_t *regs) { uint16_t excp; - + /* Save that register reference so that it can be used for built-in * diagnostics. */ current_regs = regs; - + /* The cause of the system exception is indicated in the SYSEXCPH&L * registers */ diff --git a/nuttx/arch/z80/include/ez80/limits.h b/nuttx/arch/z80/include/ez80/limits.h index 9e27b14e6..a049d37db 100644 --- a/nuttx/arch/z80/include/ez80/limits.h +++ b/nuttx/arch/z80/include/ez80/limits.h @@ -33,8 +33,8 @@ * ****************************************************************************/ -#ifndef __ARCH_Z80_INCLUDE_EZ80_LIMITS_H -#define __ARCH_Z80_INCLUDE_EZ80_LIMITS_H +#ifndef __ARCH_Z80_INCLUDE_EZ80_LIMITS_H +#define __ARCH_Z80_INCLUDE_EZ80_LIMITS_H /**************************************************************************** * Included Files diff --git a/nuttx/arch/z80/include/z180/chip.h b/nuttx/arch/z80/include/z180/chip.h index 1127e4e00..9a1ba8098 100644 --- a/nuttx/arch/z80/include/z180/chip.h +++ b/nuttx/arch/z80/include/z180/chip.h @@ -270,7 +270,7 @@ * 32 K ROM (185) * 1 Ch ESCC * IEEE 1284 Bi-Directional Centronics Parallel Port - * 7 or 24 Bits of I/O + * 7 or 24 Bits of I/O */ #elif defined(CONFIG_ARCH_CHIP_Z8019520FSG) || /* 100-pin QFP 20MHz 5V */ \ diff --git a/nuttx/arch/z80/include/z180/limits.h b/nuttx/arch/z80/include/z180/limits.h index a70118448..283c10e33 100644 --- a/nuttx/arch/z80/include/z180/limits.h +++ b/nuttx/arch/z80/include/z180/limits.h @@ -33,8 +33,8 @@ * ****************************************************************************/ -#ifndef __ARCH_Z80_INCLUDE_Z180_LIMITS_H -#define __ARCH_Z80_INCLUDE_Z180_LIMITS_H +#ifndef __ARCH_Z80_INCLUDE_Z180_LIMITS_H +#define __ARCH_Z80_INCLUDE_Z180_LIMITS_H /**************************************************************************** * Included Files diff --git a/nuttx/arch/z80/include/z8/irq.h b/nuttx/arch/z80/include/z8/irq.h index 3a0c75900..d1ceef7fd 100644 --- a/nuttx/arch/z80/include/z8/irq.h +++ b/nuttx/arch/z80/include/z8/irq.h @@ -198,7 +198,7 @@ # define NR_IRQS (29) -#endif +#endif #define Z8_IRQ_SYSTIMER Z8_TIMER0_IRQ diff --git a/nuttx/arch/z80/include/z8/limits.h b/nuttx/arch/z80/include/z8/limits.h index 724d8c98d..d71360bac 100644 --- a/nuttx/arch/z80/include/z8/limits.h +++ b/nuttx/arch/z80/include/z8/limits.h @@ -33,8 +33,8 @@ * ****************************************************************************/ -#ifndef __ARCH_Z80_INCLUDE_Z8_LIMITS_H -#define __ARCH_Z80_INCLUDE_Z8_LIMITS_H +#ifndef __ARCH_Z80_INCLUDE_Z8_LIMITS_H +#define __ARCH_Z80_INCLUDE_Z8_LIMITS_H /**************************************************************************** * Included Files diff --git a/nuttx/arch/z80/include/z80/limits.h b/nuttx/arch/z80/include/z80/limits.h index f1a1c1e17..dc9e0a70c 100644 --- a/nuttx/arch/z80/include/z80/limits.h +++ b/nuttx/arch/z80/include/z80/limits.h @@ -33,8 +33,8 @@ * ****************************************************************************/ -#ifndef __ARCH_Z80_INCLUDE_Z80_LIMITS_H -#define __ARCH_Z80_INCLUDE_Z80_LIMITS_H +#ifndef __ARCH_Z80_INCLUDE_Z80_LIMITS_H +#define __ARCH_Z80_INCLUDE_Z80_LIMITS_H /**************************************************************************** * Included Files diff --git a/nuttx/arch/z80/src/Makefile.sdccl b/nuttx/arch/z80/src/Makefile.sdccl index 44c3376c8..c444690e7 100644 --- a/nuttx/arch/z80/src/Makefile.sdccl +++ b/nuttx/arch/z80/src/Makefile.sdccl @@ -130,7 +130,7 @@ asm_mem.h: libarch$(LIBEXT): asm_mem.h $(OBJS) $(call ARCHIVE, $@, $(OBJS)) -# This builds the libboard library in the board/ subdirectory +# This builds the libboard library in the board/ subdirectory board/libboard$(LIBEXT): $(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" libboard$(LIBEXT) EXTRADEFINES=$(EXTRADEFINES) diff --git a/nuttx/arch/z80/src/Makefile.sdccw b/nuttx/arch/z80/src/Makefile.sdccw index dbf437b48..79e1b002e 100644 --- a/nuttx/arch/z80/src/Makefile.sdccw +++ b/nuttx/arch/z80/src/Makefile.sdccw @@ -130,7 +130,7 @@ asm_mem.h: libarch$(LIBEXT): asm_mem.h $(OBJS) $(call ARCHIVE, $@, $(OBJS)) -# This builds the libboard library in the board\ subdirectory +# This builds the libboard library in the board\ subdirectory board\libboard$(LIBEXT): $(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" libboard$(LIBEXT) EXTRADEFINES=$(EXTRADEFINES) diff --git a/nuttx/arch/z80/src/common/up_assert.c b/nuttx/arch/z80/src/common/up_assert.c index 9bdd5cdf5..55561db33 100644 --- a/nuttx/arch/z80/src/common/up_assert.c +++ b/nuttx/arch/z80/src/common/up_assert.c @@ -62,7 +62,7 @@ # undef CONFIG_ARCH_USBDUMP #endif -/* Output debug info if stack dump is selected -- even if +/* Output debug info if stack dump is selected -- even if * debug is not selected. */ diff --git a/nuttx/arch/z80/src/common/up_blocktask.c b/nuttx/arch/z80/src/common/up_blocktask.c index 875c0602c..418a09cc0 100644 --- a/nuttx/arch/z80/src/common/up_blocktask.c +++ b/nuttx/arch/z80/src/common/up_blocktask.c @@ -133,7 +133,7 @@ void up_block_task(FAR struct tcb_s *tcb, tstate_t task_state) SAVE_IRQCONTEXT(rtcb); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -154,7 +154,7 @@ void up_block_task(FAR struct tcb_s *tcb, tstate_t task_state) else if (!SAVE_USERCONTEXT(rtcb)) { - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/z80/src/common/up_createstack.c b/nuttx/arch/z80/src/common/up_createstack.c index 4e4c458e8..1a058ec50 100644 --- a/nuttx/arch/z80/src/common/up_createstack.c +++ b/nuttx/arch/z80/src/common/up_createstack.c @@ -114,7 +114,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) } /* Do we need to allocate a new stack? */ - + if (!tcb->stack_alloc_ptr) { /* Allocate the stack. If DEBUG is enabled (but not stack debug), diff --git a/nuttx/arch/z80/src/common/up_releasepending.c b/nuttx/arch/z80/src/common/up_releasepending.c index 7e9eb9f18..81a2f2413 100644 --- a/nuttx/arch/z80/src/common/up_releasepending.c +++ b/nuttx/arch/z80/src/common/up_releasepending.c @@ -100,7 +100,7 @@ void up_release_pending(void) SAVE_IRQCONTEXT(rtcb); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -116,13 +116,13 @@ void up_release_pending(void) /* Copy the exception context into the TCB of the task that * was currently active. if SAVE_USERCONTEXT returns a non-zero - * value, then this is really the previously running task + * value, then this is really the previously running task * restarting! */ else if (!SAVE_USERCONTEXT(rtcb)) { - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/z80/src/common/up_reprioritizertr.c b/nuttx/arch/z80/src/common/up_reprioritizertr.c index a5b3a18c8..0f0ca2fb6 100644 --- a/nuttx/arch/z80/src/common/up_reprioritizertr.c +++ b/nuttx/arch/z80/src/common/up_reprioritizertr.c @@ -72,7 +72,7 @@ * * Description: * Called when the priority of a running or - * ready-to-run task changes and the reprioritization will + * ready-to-run task changes and the reprioritization will * cause a context switch. Two cases: * * 1) The priority of the currently running task drops and the next @@ -155,7 +155,7 @@ void up_reprioritize_rtr(FAR struct tcb_s *tcb, uint8_t priority) SAVE_IRQCONTEXT(rtcb); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -176,7 +176,7 @@ void up_reprioritize_rtr(FAR struct tcb_s *tcb, uint8_t priority) else if (!SAVE_USERCONTEXT(rtcb)) { - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ diff --git a/nuttx/arch/z80/src/common/up_stackdump.c b/nuttx/arch/z80/src/common/up_stackdump.c index 6cb85dd38..21707889b 100644 --- a/nuttx/arch/z80/src/common/up_stackdump.c +++ b/nuttx/arch/z80/src/common/up_stackdump.c @@ -50,7 +50,7 @@ * Definitions ****************************************************************************/ -/* Output debug info if stack dump is selected -- even if +/* Output debug info if stack dump is selected -- even if * debug is not selected. */ diff --git a/nuttx/arch/z80/src/common/up_stackframe.c b/nuttx/arch/z80/src/common/up_stackframe.c index fdc43a850..1db0bf470 100644 --- a/nuttx/arch/z80/src/common/up_stackframe.c +++ b/nuttx/arch/z80/src/common/up_stackframe.c @@ -114,7 +114,7 @@ FAR void *up_stack_frame(FAR struct tcb_s *tcb, size_t frame_size) /* Align the frame_size */ frame_size = STACK_ALIGN_UP(frame_size); - + /* Is there already a stack allocated? Is it big enough? */ if (!tcb->stack_alloc_ptr || tcb->adj_stack_size <= frame_size) diff --git a/nuttx/arch/z80/src/common/up_unblocktask.c b/nuttx/arch/z80/src/common/up_unblocktask.c index e6141d4fc..6c46b0a14 100644 --- a/nuttx/arch/z80/src/common/up_unblocktask.c +++ b/nuttx/arch/z80/src/common/up_unblocktask.c @@ -114,7 +114,7 @@ void up_unblock_task(FAR struct tcb_s *tcb) /* The currently active task has changed! We need to do * a context switch to the new task. * - * Are we in an interrupt handler? + * Are we in an interrupt handler? */ if (IN_INTERRUPT()) @@ -125,7 +125,7 @@ void up_unblock_task(FAR struct tcb_s *tcb) SAVE_IRQCONTEXT(rtcb); - /* Restore the exception context of the rtcb at the (new) head + /* Restore the exception context of the rtcb at the (new) head * of the g_readytorun task list. */ @@ -140,7 +140,7 @@ void up_unblock_task(FAR struct tcb_s *tcb) } /* We are not in an interrupt handler. Copy the user C context - * into the TCB of the task that was previously active. if + * into the TCB of the task that was previously active. if * SAVE_USERCONTEXT returns a non-zero value, then this is really the * previously running task restarting! */ diff --git a/nuttx/arch/z80/src/ez80/Make.defs b/nuttx/arch/z80/src/ez80/Make.defs index fb2b3d48f..271ff0f9d 100644 --- a/nuttx/arch/z80/src/ez80/Make.defs +++ b/nuttx/arch/z80/src/ez80/Make.defs @@ -36,7 +36,7 @@ HEAD_ASRC = ez80_vectors.asm HEAD_SSRC = -CMN_SSRCS = +CMN_SSRCS = CMN_CSRCS = up_initialize.c up_allocateheap.c up_createstack.c \ up_releasestack.c up_interruptcontext.c up_blocktask.c \ up_unblocktask.c up_exit.c up_releasepending.c \ @@ -49,7 +49,7 @@ ifeq ($(CONFIG_ARCH_CHIP_EZ80F91),y) CHIP_ASRCS += ez80f91_init.asm endif -CHIP_SSRCS = +CHIP_SSRCS = CHIP_CSRCS = ez80_clock.c ez80_initialstate.c ez80_irq.c ez80_copystate.c \ ez80_schedulesigaction.c ez80_sigdeliver.c ez80_timerisr.c \ ez80_lowuart.c ez80_serial.c ez80_spi.c ez80_i2c.c \ diff --git a/nuttx/arch/z80/src/ez80/ez80_emac.c b/nuttx/arch/z80/src/ez80/ez80_emac.c index 727003677..4957a5bd8 100644 --- a/nuttx/arch/z80/src/ez80/ez80_emac.c +++ b/nuttx/arch/z80/src/ez80/ez80_emac.c @@ -470,7 +470,7 @@ static void ez80emac_miiwrite(FAR struct ez80emac_driver_s *priv, uint8_t offset static uint16_t ez80emac_miiread(FAR struct ez80emac_driver_s *priv, uint32_t offset) { uint8_t regval; - + /* Wait for any preceding MII management operation to complete */ ez80emac_waitmiibusy(); @@ -613,7 +613,7 @@ static int ez80emac_miiconfigure(FAR struct ez80emac_driver_s *priv) ndbg("Configure autonegotiation\n"); if (bauto) { - ez80emac_miiwrite(priv, MII_ADVERTISE, + ez80emac_miiwrite(priv, MII_ADVERTISE, MII_ADVERTISE_100BASETXFULL|MII_ADVERTISE_100BASETXHALF| MII_ADVERTISE_10BASETXFULL|MII_ADVERTISE_10BASETXHALF| MII_ADVERTISE_CSMA); @@ -1177,7 +1177,7 @@ static int ez80emac_receive(struct ez80emac_driver_s *priv) * RxDMA reads the next two bytes from the RxFIFO and writes them into * the Rx descriptor status LSB and MSB. The packet length counter is * stored into the descriptor table packet length field, the descriptor - * table next pointer is written into the Rx descriptor table and finally + * table next pointer is written into the Rx descriptor table and finally * the Rx_DONE_STAT bit in the EMAC Interrupt Status Register register is * set to 1. */ @@ -1223,7 +1223,7 @@ static int ez80emac_receive(struct ez80emac_driver_s *priv) { int nbytes = (int)((FAR uint8_t*)priv->rxendp1 - (FAR uint8_t*)psrc); nvdbg("RX wraps after %d bytes\n", nbytes + SIZEOF_EMACSDESC); - + memcpy(pdest, psrc, nbytes); memcpy(&pdest[nbytes], priv->rxstart, pktlen - nbytes); } @@ -1383,7 +1383,7 @@ static int ez80emac_txinterrupt(int irq, FAR void *context) } } - /* Save the new head. If it is NULL, then we have read all the way to + /* Save the new head. If it is NULL, then we have read all the way to * the terminating description with np==NULL. */ @@ -1616,7 +1616,7 @@ static void ez80emac_polltimer(int argc, uint32_t arg, ...) * * Description: * NuttX Callback: Bring up the Ethernet interface when an IP address is - * provided + * provided * * Parameters: * dev - Reference to the NuttX driver state structure @@ -1760,7 +1760,7 @@ static int ez80emac_ifdown(struct uip_driver_s *dev) * Function: ez80emac_txavail * * Description: - * Driver callback invoked when new TX data is available. This is a + * Driver callback invoked when new TX data is available. This is a * stimulus perform an out-of-cycle poll and, thereby, reduce the TX * latency. * @@ -1807,7 +1807,7 @@ static int ez80emac_txavail(struct uip_driver_s *dev) * * Parameters: * dev - Reference to the NuttX driver state structure - * mac - The MAC address to be added + * mac - The MAC address to be added * * Returned Value: * None @@ -1837,7 +1837,7 @@ static int ez80emac_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac) * * Parameters: * dev - Reference to the NuttX driver state structure - * mac - The MAC address to be removed + * mac - The MAC address to be removed * * Returned Value: * None @@ -1885,12 +1885,12 @@ static int ez80_emacinitialize(void) outp(EZ80_EMAC_RST, 0); /* Reset everything */ outp(EZ80_EMAC_RST, 0xff); outp(EZ80_EMAC_RST, 0); - + /* The ez80 has a fixed 8kb of EMAC SRAM memory (+ 8kb of * general purpose SRAM) located in the high address space. * Configure the GP and EMAC SRAM */ - + outp(EZ80_RAM_CTL, (RAMCTL_ERAMEN|RAMCTL_GPRAMEN)); outp(EZ80_RAM_ADDR_U, (CONFIG_EZ80_RAMADDR >> 16)); outp(EZ80_EMAC_BP_U, (CONFIG_EZ80_RAMADDR >> 16)); @@ -2014,7 +2014,7 @@ static int ez80_emacinitialize(void) outp(EZ80_EMAC_CFG3, EMAC_RETRY); /* EMAC_CFG4_TXFC - Pause control frames are allowed to be transmitted - * EMAC_CFG4_RXFC - Act on received pause control frames + * EMAC_CFG4_RXFC - Act on received pause control frames */ outp(EZ80_EMAC_CFG4, EMAC_CFG4_TXFC|EMAC_CFG4_RXFC); diff --git a/nuttx/arch/z80/src/ez80/ez80_i2c.c b/nuttx/arch/z80/src/ez80/ez80_i2c.c index 83942a542..329892d16 100644 --- a/nuttx/arch/z80/src/ez80/ez80_i2c.c +++ b/nuttx/arch/z80/src/ez80/ez80_i2c.c @@ -261,7 +261,7 @@ static uint16_t i2c_getccr(uint32_t fscl) fscl = ftmp; n = 7; } - + /* Finally, get M: * * M = (fsamp / 10) / fscl - 1 = ftmp / fscl - 1 @@ -340,7 +340,7 @@ static void i2c_clriflg(void) * None * ****************************************************************************/ - + static void i2c_start(void) { uint8_t regval = inp(EZ80_I2C_CTL); @@ -362,7 +362,7 @@ static void i2c_start(void) * None * ****************************************************************************/ - + static void i2c_stop(void) { uint8_t regval = inp(EZ80_I2C_CTL); @@ -382,11 +382,11 @@ static void i2c_stop(void) * * Returned Value: * 0: Success, IFLG is set and DATA can be sent or received. - + * Or <0: Negated error value. IFLG is cleared. * * -EIO: Irrecoverable (or unexpected) error occured - * -EAGAIN: And + * -EAGAIN: And * ****************************************************************************/ @@ -420,7 +420,7 @@ static int i2c_sendaddr(struct ez80_i2cdev_s *priv, uint8_t readbit) outp(EZ80_I2C_DR, (uint8_t)I2C_ADDR8(priv->addr) | readbit); i2c_clriflg(); - + /* And wait for the address transfer to complete */ sr = i2c_waitiflg(); @@ -659,7 +659,7 @@ static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int bufle if (sr == I2C_SR_ARBLOST1) { /* Arbitration lost, break out of the inner loop and - * try sending the message again + * try sending the message again */ break; @@ -745,7 +745,7 @@ static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen) /* Retry as necessary to receive the whole message */ - for (retry = 0; retry < 100; retry++) + for (retry = 0; retry < 100; retry++) { /* Enter MASTER TRANSMIT mode by setting the STA bit in the I2C_CTL * register to 1. The I2C then tests the I2C bus and transmits a START @@ -784,7 +784,7 @@ static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen) /* If the AAK bit is cleared to 0 during a transfer, the I2C * transmits a NACK bit after the next byte is received. */ - + regval &= ~I2C_CTL_AAK; } else @@ -798,7 +798,7 @@ static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen) } outp(EZ80_I2C_CTL, regval); - /* Wait for IFLG to be set meaning that incoming data is + /* Wait for IFLG to be set meaning that incoming data is * available in the I2C_DR registers. */ @@ -851,7 +851,7 @@ static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen) i2c_clriflg(); break; } - + /* Unexpected status response */ else @@ -881,7 +881,7 @@ failure: * Description: * Initialize the selected I2C port. And return a unique instance of struct * struct i2c_dev_s. This function may be called to obtain multiple - * instances of the interface, each of which may be set up with a + * instances of the interface, each of which may be set up with a * different frequency and slave address. * * Input Parameter: @@ -897,7 +897,7 @@ FAR struct i2c_dev_s *up_i2cinitialize(int port) FAR struct ez80_i2cdev_s *i2c; uint16_t ccr; uint8_t regval; - + if (!g_initialized) { /* Set up some initial BRG value */ @@ -906,7 +906,7 @@ FAR struct i2c_dev_s *up_i2cinitialize(int port) i2c_setccr(ccr); /* No GPIO setup is required -- I2C pints, SCL/SDA are not multiplexed */ - + /* This semaphore enforces serialized access for I2C transfers */ sem_init(&g_i2csem, 0, 1); @@ -929,4 +929,4 @@ FAR struct i2c_dev_s *up_i2cinitialize(int port) i2c->ccr = g_currccr; } return (FAR struct i2c_dev_s *)i2c; -} +} diff --git a/nuttx/arch/z80/src/ez80/ez80_irq.c b/nuttx/arch/z80/src/ez80/ez80_irq.c index 604e5c5b3..19c29b45d 100644 --- a/nuttx/arch/z80/src/ez80/ez80_irq.c +++ b/nuttx/arch/z80/src/ez80/ez80_irq.c @@ -78,7 +78,7 @@ volatile chipreg_t *current_regs; void up_irqinitialize(void) { current_regs = NULL; - + /* And finally, enable interrupts */ #ifndef CONFIG_SUPPRESS_INTERRUPTS diff --git a/nuttx/arch/z80/src/ez80/ez80_registerdump.c b/nuttx/arch/z80/src/ez80/ez80_registerdump.c index bf53f81f7..82c8cc8ad 100644 --- a/nuttx/arch/z80/src/ez80/ez80_registerdump.c +++ b/nuttx/arch/z80/src/ez80/ez80_registerdump.c @@ -52,7 +52,7 @@ * Definitions ****************************************************************************/ -/* Output debug info if stack dump is selected -- even if +/* Output debug info if stack dump is selected -- even if * debug is not selected. */ diff --git a/nuttx/arch/z80/src/ez80/ez80_serial.c b/nuttx/arch/z80/src/ez80/ez80_serial.c index a178ecb19..06ca2753e 100644 --- a/nuttx/arch/z80/src/ez80/ez80_serial.c +++ b/nuttx/arch/z80/src/ez80/ez80_serial.c @@ -560,7 +560,7 @@ static void ez80_rxint(struct uart_dev_s *dev, bool enable) { struct ez80_dev_s *priv = (struct ez80_dev_s*)dev->priv; uint8_t ier = ez80_serialin(priv, EZ80_UART_IER); - + if (enable) { #ifndef CONFIG_SUPPRESS_SERIAL_INTS @@ -766,7 +766,7 @@ int up_putc(int ch) ez80_serialout(priv, EZ80_UART_THR, (uint8_t)ch); /* Wait for the character to be sent before re-enabling interrupts */ - + ez80_waittxready(priv); ez80_restoreuartint(priv, ier); return ch; diff --git a/nuttx/arch/z80/src/ez80/ez80_sigdeliver.c b/nuttx/arch/z80/src/ez80/ez80_sigdeliver.c index 7280835d1..0f2409b9c 100644 --- a/nuttx/arch/z80/src/ez80/ez80_sigdeliver.c +++ b/nuttx/arch/z80/src/ez80/ez80_sigdeliver.c @@ -105,7 +105,7 @@ void up_sigdeliver(void) regs[XCPT_I] = rtcb->xcp.saved_i; /* Get a local copy of the sigdeliver function pointer. We do this so - * that we can nullify the sigdeliver function pointer in the TCB and + * that we can nullify the sigdeliver function pointer in the TCB and * accept more signal deliveries while processing the current pending * signals. */ diff --git a/nuttx/arch/z80/src/ez80/ez80_spi.c b/nuttx/arch/z80/src/ez80/ez80_spi.c index 260bdc777..8a6eab663 100644 --- a/nuttx/arch/z80/src/ez80/ez80_spi.c +++ b/nuttx/arch/z80/src/ez80/ez80_spi.c @@ -174,7 +174,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) * * BRG >= System Clock Frequency / (2 * SPIR) */ - + uint32_t brg = ((EZ80_SYS_CLK_FREQ+1)/2 + frequency - 1) / frequency; /* "When configured as a Master, the 16-bit divisor value must be between diff --git a/nuttx/arch/z80/src/ez80/ez80_timerisr.c b/nuttx/arch/z80/src/ez80/ez80_timerisr.c index d29237e54..3cb3d029d 100644 --- a/nuttx/arch/z80/src/ez80/ez80_timerisr.c +++ b/nuttx/arch/z80/src/ez80/ez80_timerisr.c @@ -79,7 +79,7 @@ int up_timerisr(int irq, chipreg_t *regs) volatile uint8_t reg; /* Read the appropropriate timer0 registr to clear the interrupt */ - + #ifdef _EZ80F91 reg = inp(EZ80_TMR0_IIR); #else @@ -91,7 +91,7 @@ int up_timerisr(int irq, chipreg_t *regs) /* Process timer interrupt */ sched_process_timer(); - + /* Architecture specific hook into the timer interrupt handler */ #ifdef CONFIG_ARCH_TIMERHOOK @@ -147,7 +147,7 @@ void up_timerinit(void) outp(EZ80_TMR0_RRL, (uint8_t)(reload)); /* Clear any pending timer interrupts */ - + #if defined(_EZ80F91) reg = inp(EZ80_TMR0_IIR); #elif defined(_EZ80L92) || defined(_EZ80F92) ||defined(_EZ80F93) diff --git a/nuttx/arch/z80/src/ez80/ez80_vectors.asm b/nuttx/arch/z80/src/ez80/ez80_vectors.asm index eaec4b36f..107b570c4 100644 --- a/nuttx/arch/z80/src/ez80/ez80_vectors.asm +++ b/nuttx/arch/z80/src/ez80/ez80_vectors.asm @@ -137,71 +137,71 @@ _nmi: ; Symbol Val VecNo Addr ;----------------- --- ----- ----- _ez80_handlers: - irqhandler 0 ; EZ80_EMACRX_IRQ 0 0 0x040 + irqhandler 0 ; EZ80_EMACRX_IRQ 0 0 0x040 handlersize equ $-_ez80handlers - irqhandler 1 ; EZ80_EMACTX_IRQ 1 1 0x044 - irqhandler 2 ; EZ80_EMACSYS_IRQ 2 2 0x048 - irqhandler 3 ; EZ80_PLL_IRQ 3 3 0x04c - irqhandler 4 ; EZ80_FLASH_IRQ 4 4 0x050 - irqhandler 5 ; EZ80_TIMER0_IRQ 5 5 0x054 - irqhandler 6 ; EZ80_TIMER1_IRQ 6 6 0x058 - irqhandler 7 ; EZ80_TIMER2_IRQ 7 7 0x05c - irqhandler 8 ; EZ80_TIMER3_IRQ 8 8 0x060 - irqhandler EZ80_UNUSED ; 9 0x064 - irqhandler EZ80_UNUSED+1 ; 10 0x068 - irqhandler 9 ; EZ80_RTC_IRQ 9 11 0x06C - irqhandler 10 ; EZ80_UART0_IRQ 10 12 0x070 - irqhandler 11 ; EZ80_UART1_IRQ 11 13 0x074 - irqhandler 12 ; EZ80_I2C_IRQ 12 14 0x078 - irqhandler 13 ; EZ80_SPI_IRQ 13 15 0x07c - irqhandler 14 ; EZ80_PORTA0_IRQ 14 16 0x080 - irqhandler 15 ; EZ80_PORTA1_IRQ 15 17 0x084 - irqhandler 16 ; EZ80_PORTA2_IRQ 16 18 0x088 - irqhandler 17 ; EZ80_PORTA3_IRQ 17 19 0x08c - irqhandler 18 ; EZ80_PORTA4_IRQ 18 20 0x090 - irqhandler 19 ; EZ80_PORTA5_IRQ 19 21 0x094 - irqhandler 20 ; EZ80_PORTA6_IRQ 20 22 0x098 - irqhandler 21 ; EZ80_PORTA7_IRQ 21 23 0x09c - irqhandler 22 ; EZ80_PORTB0_IRQ 22 24 0x0a0 - irqhandler 23 ; EZ80_PORTB1_IRQ 23 25 0x0a4 - irqhandler 24 ; EZ80_PORTB2_IRQ 24 26 0x0a8 - irqhandler 25 ; EZ80_PORTB3_IRQ 25 27 0x0ac - irqhandler 26 ; EZ80_PORTB4_IRQ 26 28 0x0b0 - irqhandler 27 ; EZ80_PORTB5_IRQ 27 29 0x0b4 - irqhandler 28 ; EZ80_PORTB6_IRQ 28 20 0x0b8 - irqhandler 29 ; EZ80_PORTB7_IRQ 29 21 0x0bc - irqhandler 30 ; EZ80_PORTC0_IRQ 30 22 0x0c0 - irqhandler 31 ; EZ80_PORTC1_IRQ 31 23 0x0c4 - irqhandler 32 ; EZ80_PORTC2_IRQ 32 24 0x0c8 - irqhandler 33 ; EZ80_PORTC3_IRQ 33 25 0x0cc - irqhandler 34 ; EZ80_PORTC4_IRQ 34 26 0x0d0 - irqhandler 35 ; EZ80_PORTC5_IRQ 35 27 0x0d4 - irqhandler 36 ; EZ80_PORTC6_IRQ 36 28 0x0d8 - irqhandler 37 ; EZ80_PORTC7_IRQ 37 29 0x0dc - irqhandler 38 ; EZ80_PORTD0_IRQ 38 40 0x0e0 - irqhandler 39 ; EZ80_PORTD1_IRQ 39 41 0x0e4 - irqhandler 40 ; EZ80_PORTD2_IRQ 40 42 0x0e8 - irqhandler 41 ; EZ80_PORTD3_IRQ 41 43 0x0ec - irqhandler 42 ; EZ80_PORTD4_IRQ 42 44 0x0f0 - irqhandler 43 ; EZ80_PORTD5_IRQ 43 45 0x0f4 - irqhandler 44 ; EZ80_PORTD6_IRQ 44 46 0x0f8 - irqhandler 45 ; EZ80_PORTD7_IRQ 45 47 0x0fc - irqhandler EZ80_UNUSED+1 ; 48 0x100 - irqhandler EZ80_UNUSED+2 ; 49 0x104 - irqhandler EZ80_UNUSED+3 ; 50 0x108 - irqhandler EZ80_UNUSED+4 ; 51 0x10c - irqhandler EZ80_UNUSED+5 ; 52 0x110 - irqhandler EZ80_UNUSED+6 ; 53 0x114 - irqhandler EZ80_UNUSED+7 ; 54 0x118 - irqhandler EZ80_UNUSED+8 ; 55 0x11c - irqhandler EZ80_UNUSED+9 ; 56 0x120 - irqhandler EZ80_UNUSED+10 ; 57 0x124 - irqhandler EZ80_UNUSED+11 ; 58 0x128 - irqhandler EZ80_UNUSED+12 ; 59 0x12c - irqhandler EZ80_UNUSED+13 ; 60 0x130 - irqhandler EZ80_UNUSED+14 ; 61 0x134 - irqhandler EZ80_UNUSED+15 ; 62 0x138 - irqhandler EZ80_UNUSED+16 ; 63 0x13c + irqhandler 1 ; EZ80_EMACTX_IRQ 1 1 0x044 + irqhandler 2 ; EZ80_EMACSYS_IRQ 2 2 0x048 + irqhandler 3 ; EZ80_PLL_IRQ 3 3 0x04c + irqhandler 4 ; EZ80_FLASH_IRQ 4 4 0x050 + irqhandler 5 ; EZ80_TIMER0_IRQ 5 5 0x054 + irqhandler 6 ; EZ80_TIMER1_IRQ 6 6 0x058 + irqhandler 7 ; EZ80_TIMER2_IRQ 7 7 0x05c + irqhandler 8 ; EZ80_TIMER3_IRQ 8 8 0x060 + irqhandler EZ80_UNUSED ; 9 0x064 + irqhandler EZ80_UNUSED+1 ; 10 0x068 + irqhandler 9 ; EZ80_RTC_IRQ 9 11 0x06C + irqhandler 10 ; EZ80_UART0_IRQ 10 12 0x070 + irqhandler 11 ; EZ80_UART1_IRQ 11 13 0x074 + irqhandler 12 ; EZ80_I2C_IRQ 12 14 0x078 + irqhandler 13 ; EZ80_SPI_IRQ 13 15 0x07c + irqhandler 14 ; EZ80_PORTA0_IRQ 14 16 0x080 + irqhandler 15 ; EZ80_PORTA1_IRQ 15 17 0x084 + irqhandler 16 ; EZ80_PORTA2_IRQ 16 18 0x088 + irqhandler 17 ; EZ80_PORTA3_IRQ 17 19 0x08c + irqhandler 18 ; EZ80_PORTA4_IRQ 18 20 0x090 + irqhandler 19 ; EZ80_PORTA5_IRQ 19 21 0x094 + irqhandler 20 ; EZ80_PORTA6_IRQ 20 22 0x098 + irqhandler 21 ; EZ80_PORTA7_IRQ 21 23 0x09c + irqhandler 22 ; EZ80_PORTB0_IRQ 22 24 0x0a0 + irqhandler 23 ; EZ80_PORTB1_IRQ 23 25 0x0a4 + irqhandler 24 ; EZ80_PORTB2_IRQ 24 26 0x0a8 + irqhandler 25 ; EZ80_PORTB3_IRQ 25 27 0x0ac + irqhandler 26 ; EZ80_PORTB4_IRQ 26 28 0x0b0 + irqhandler 27 ; EZ80_PORTB5_IRQ 27 29 0x0b4 + irqhandler 28 ; EZ80_PORTB6_IRQ 28 20 0x0b8 + irqhandler 29 ; EZ80_PORTB7_IRQ 29 21 0x0bc + irqhandler 30 ; EZ80_PORTC0_IRQ 30 22 0x0c0 + irqhandler 31 ; EZ80_PORTC1_IRQ 31 23 0x0c4 + irqhandler 32 ; EZ80_PORTC2_IRQ 32 24 0x0c8 + irqhandler 33 ; EZ80_PORTC3_IRQ 33 25 0x0cc + irqhandler 34 ; EZ80_PORTC4_IRQ 34 26 0x0d0 + irqhandler 35 ; EZ80_PORTC5_IRQ 35 27 0x0d4 + irqhandler 36 ; EZ80_PORTC6_IRQ 36 28 0x0d8 + irqhandler 37 ; EZ80_PORTC7_IRQ 37 29 0x0dc + irqhandler 38 ; EZ80_PORTD0_IRQ 38 40 0x0e0 + irqhandler 39 ; EZ80_PORTD1_IRQ 39 41 0x0e4 + irqhandler 40 ; EZ80_PORTD2_IRQ 40 42 0x0e8 + irqhandler 41 ; EZ80_PORTD3_IRQ 41 43 0x0ec + irqhandler 42 ; EZ80_PORTD4_IRQ 42 44 0x0f0 + irqhandler 43 ; EZ80_PORTD5_IRQ 43 45 0x0f4 + irqhandler 44 ; EZ80_PORTD6_IRQ 44 46 0x0f8 + irqhandler 45 ; EZ80_PORTD7_IRQ 45 47 0x0fc + irqhandler EZ80_UNUSED+1 ; 48 0x100 + irqhandler EZ80_UNUSED+2 ; 49 0x104 + irqhandler EZ80_UNUSED+3 ; 50 0x108 + irqhandler EZ80_UNUSED+4 ; 51 0x10c + irqhandler EZ80_UNUSED+5 ; 52 0x110 + irqhandler EZ80_UNUSED+6 ; 53 0x114 + irqhandler EZ80_UNUSED+7 ; 54 0x118 + irqhandler EZ80_UNUSED+8 ; 55 0x11c + irqhandler EZ80_UNUSED+9 ; 56 0x120 + irqhandler EZ80_UNUSED+10 ; 57 0x124 + irqhandler EZ80_UNUSED+11 ; 58 0x128 + irqhandler EZ80_UNUSED+12 ; 59 0x12c + irqhandler EZ80_UNUSED+13 ; 60 0x130 + irqhandler EZ80_UNUSED+14 ; 61 0x134 + irqhandler EZ80_UNUSED+15 ; 62 0x138 + irqhandler EZ80_UNUSED+16 ; 63 0x13c ;************************************************************************** ; Common Interrupt handler diff --git a/nuttx/arch/z80/src/ez80/ez80f91_spi.h b/nuttx/arch/z80/src/ez80/ez80f91_spi.h index 1ef3a755d..16bc4648b 100644 --- a/nuttx/arch/z80/src/ez80/ez80f91_spi.h +++ b/nuttx/arch/z80/src/ez80/ez80f91_spi.h @@ -105,7 +105,7 @@ extern "C" { * include/nuttx/spi/spi.h). All other methods (including up_spiinitialize()) are * provided by common logic. To use this common SPI logic on your board: * - * 1. Provide ez80_spiselect() and ez80_spistatus() functions in your board-specific + * 1. Provide ez80_spiselect() and ez80_spistatus() functions in your board-specific * logic. This function will perform chip selection and status operations using * GPIOs in the way your board is configured. * 2. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration, provide the diff --git a/nuttx/arch/z80/src/z180/Make.defs b/nuttx/arch/z80/src/z180/Make.defs index 24d2cb64a..ad658094b 100644 --- a/nuttx/arch/z80/src/z180/Make.defs +++ b/nuttx/arch/z80/src/z180/Make.defs @@ -41,8 +41,8 @@ HEAD_ASRC = z180_head.asm endif endif -CMN_ASRCS = -CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_createstack.c +CMN_ASRCS = +CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_createstack.c CMN_CSRCS += up_doirq.c up_exit.c up_idle.c up_initialize.c CMN_CSRCS += up_interruptcontext.c up_mdelay.c up_releasepending.c CMN_CSRCS += up_releasestack.c up_reprioritizertr.c up_unblocktask.c diff --git a/nuttx/arch/z80/src/z180/README.txt b/nuttx/arch/z80/src/z180/README.txt index c06164cdd..b088470b6 100644 --- a/nuttx/arch/z80/src/z180/README.txt +++ b/nuttx/arch/z80/src/z180/README.txt @@ -46,4 +46,4 @@ z180_saveusercontext.asm, switch z180_schedulesigaction.c and z180_sigdeliver.c These files implement Z180 signal handling. - + diff --git a/nuttx/arch/z80/src/z180/z180_mmu.c b/nuttx/arch/z80/src/z180/z180_mmu.c index d6ed1ebcf..4306eaf5f 100644 --- a/nuttx/arch/z80/src/z180/z180_mmu.c +++ b/nuttx/arch/z80/src/z180/z180_mmu.c @@ -241,7 +241,7 @@ int up_addrenv_create(size_t envsize, FAR task_addrenv_t *addrenv) sdbg("ERROR: npages is zero\n"); return OK; } - + /* Allocate a structure in the common .bss to hold information about the * task's address environment. NOTE that this is not a part of the TCB, * but rather a break-away structure that can be shared by the task as @@ -287,7 +287,7 @@ int up_addrenv_create(size_t envsize, FAR task_addrenv_t *addrenv) errout_with_cbr: z180_mmu_freecbr(cbr); - + errout_with_irq: irqrestore(flags); return ret; diff --git a/nuttx/arch/z80/src/z180/z180_registerdump.c b/nuttx/arch/z80/src/z180/z180_registerdump.c index 17a44b059..ad67f12a3 100644 --- a/nuttx/arch/z80/src/z180/z180_registerdump.c +++ b/nuttx/arch/z80/src/z180/z180_registerdump.c @@ -52,7 +52,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Output debug info if stack dump is selected -- even if +/* Output debug info if stack dump is selected -- even if * debug is not selected. */ diff --git a/nuttx/arch/z80/src/z180/z180_scc.c b/nuttx/arch/z80/src/z180/z180_scc.c index a2f0d4561..29d0c5239 100644 --- a/nuttx/arch/z80/src/z180/z180_scc.c +++ b/nuttx/arch/z80/src/z180/z180_scc.c @@ -278,7 +278,7 @@ static uart_dev_t g_escca_port = */ #undef CONSOLE_DEV -#undef TTYS0_DEV +#undef TTYS0_DEV #undef TTYS1_DEV #if defined(CONFIG_Z180_SCC_SERIAL_CONSOLE) diff --git a/nuttx/arch/z80/src/z180/z180_timerisr.c b/nuttx/arch/z80/src/z180/z180_timerisr.c index ceb7efb5f..bf041519e 100644 --- a/nuttx/arch/z80/src/z180/z180_timerisr.c +++ b/nuttx/arch/z80/src/z180/z180_timerisr.c @@ -98,7 +98,7 @@ int up_timerisr(int irq, chipreg_t *regs) /* "When TMDR0 decrements to 0, TIF0 is set to 1. This generates an interrupt * request if enabled by TIE0 = 1. TIF0 is reset to 0 when TCR is read and - * the higher or lower byte of TMDR0 is read." + * the higher or lower byte of TMDR0 is read." */ regval = inp(Z180_PRT_TCR); diff --git a/nuttx/arch/z80/src/z8/Make.defs b/nuttx/arch/z80/src/z8/Make.defs index 5d7a338be..781c82182 100644 --- a/nuttx/arch/z80/src/z8/Make.defs +++ b/nuttx/arch/z80/src/z8/Make.defs @@ -35,7 +35,7 @@ HEAD_SSRC = z8_head.S -CMN_SSRCS = +CMN_SSRCS = CMN_CSRCS = up_initialize.c up_allocateheap.c up_createstack.c \ up_releasestack.c up_interruptcontext.c up_blocktask.c \ up_unblocktask.c up_exit.c up_releasepending.c \ diff --git a/nuttx/arch/z80/src/z8/z8_head.S b/nuttx/arch/z80/src/z8/z8_head.S index bdd6593e0..9316c7f64 100755 --- a/nuttx/arch/z80/src/z8/z8_head.S +++ b/nuttx/arch/z80/src/z8/z8_head.S @@ -49,7 +49,7 @@ /* Assume the large model */ -#if !defined(CONFIG_Z8_MODEL_LARGE) && !defined(CONFIG_Z8_MODEL_SMALL) +#if !defined(CONFIG_Z8_MODEL_LARGE) && !defined(CONFIG_Z8_MODEL_SMALL) # define CONFIG_Z8_MODEL_LARGE 1 # undef CONFIG_Z8_MODEL_SMALL #endif @@ -96,7 +96,7 @@ **************************************************************************/ segment CODE - + /************************************************************************** * Interrupt Vectors **************************************************************************/ @@ -222,7 +222,7 @@ _z8_reset10: /* Start NuttX */ - ldx __intrp,#0 + ldx __intrp,#0 xor r15, r15 xor r14, r14 call _os_start diff --git a/nuttx/arch/z80/src/z8/z8_i2c.c b/nuttx/arch/z80/src/z8/z8_i2c.c index 59cd2fc2b..6239ad25b 100644 --- a/nuttx/arch/z80/src/z8/z8_i2c.c +++ b/nuttx/arch/z80/src/z8/z8_i2c.c @@ -160,7 +160,7 @@ static void i2c_semtake(void) static void i2c_waittxempty(void) { - int i; + int i; for (i = 0; i < 10000 && (I2CSTAT & I2C_STAT_TDRE) == 0; i++); } @@ -178,7 +178,7 @@ static void i2c_waittxempty(void) * ****************************************************************************/ -static void i2c_waitrxavail(void) +static void i2c_waitrxavail(void) { int i; for (i = 0; i <= 10000 && (I2CSTAT & (I2C_STAT_RDRF | I2C_STAT_NCKI)) == 0; i++); @@ -365,7 +365,7 @@ static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int bufle I2CD = I2C_WRITEADDR8(priv->addr); I2CCTL |= I2C_CTL_START; - + /* Wait for the xmt buffer to become empty */ i2c_waittxempty(); @@ -385,7 +385,7 @@ static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int bufle * the last bit.. Hmmm. If this true then we will never be * able to send more than one data byte??? */ - + if (count == 1) { I2CCTL |= I2C_CTL_STOP; @@ -470,7 +470,7 @@ static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen) /* Retry as necessary to receive the whole message */ - for (retry = 0; retry < 100; retry++) + for (retry = 0; retry < 100; retry++) { /* Load the address into the transmit register. It is not sent * until the START bit is set. @@ -481,7 +481,7 @@ static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen) /* If we want only a single byte of data, then set the NACK * bit now. */ - + I2CCTL |= I2C_CTL_NAK; /* The START bit begins the transaction */ @@ -553,7 +553,7 @@ static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen) * Description: * Initialize the selected I2C port. And return a unique instance of struct * struct i2c_dev_s. This function may be called to obtain multiple - * instances of the interface, each of which may be set up with a + * instances of the interface, each of which may be set up with a * different frequency and slave address. * * Input Parameter: @@ -567,7 +567,7 @@ static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen) FAR struct i2c_dev_s *up_i2cinitialize(int port) { FAR struct z8_i2cdev_s *i2c; - + if (!g_initialized) { /* Set up some initial BRG value */ @@ -578,7 +578,7 @@ FAR struct i2c_dev_s *up_i2cinitialize(int port) /* Make sure that GPIOs are configured for the alternate function (this * varies with silicon revisions). */ - + PAADDR = 0x02; PACTL |= 0xc0; @@ -603,4 +603,4 @@ FAR struct i2c_dev_s *up_i2cinitialize(int port) } return (FAR struct i2c_dev_s *)i2c; -} +} diff --git a/nuttx/arch/z80/src/z8/z8_lowuart.c b/nuttx/arch/z80/src/z8/z8_lowuart.c index 730ed1b4c..ad4acb6e9 100644 --- a/nuttx/arch/z80/src/z8/z8_lowuart.c +++ b/nuttx/arch/z80/src/z8/z8_lowuart.c @@ -112,7 +112,7 @@ void up_lowserialinit(void) putreg8(brg & 0xff, U1BRL); /* Configure GPIO Port D pins 4 & 5 for alternate function */ - + putreg8(0x02, PAADDR); val = getreg8(PDCTL) | 0x30; /* Set bits in alternate function register */ putreg8(val, PDCTL); diff --git a/nuttx/arch/z80/src/z8/z8_registerdump.c b/nuttx/arch/z80/src/z8/z8_registerdump.c index f1ce13a24..d1319f93b 100644 --- a/nuttx/arch/z80/src/z8/z8_registerdump.c +++ b/nuttx/arch/z80/src/z8/z8_registerdump.c @@ -53,7 +53,7 @@ * Definitions ****************************************************************************/ -/* Output debug info if stack dump is selected -- even if +/* Output debug info if stack dump is selected -- even if * debug is not selected. */ diff --git a/nuttx/arch/z80/src/z8/z8_serial.c b/nuttx/arch/z80/src/z8/z8_serial.c index 8e809988c..7dcf2f258 100644 --- a/nuttx/arch/z80/src/z8/z8_serial.c +++ b/nuttx/arch/z80/src/z8/z8_serial.c @@ -244,7 +244,7 @@ static uart_dev_t g_uart1port = /**************************************************************************** * Name: z8_putuart ****************************************************************************/ - + static inline void z8_putuart(FAR struct z8_uart_s *priv, uint8_t value, uint8_t offset) { @@ -254,7 +254,7 @@ static inline void z8_putuart(FAR struct z8_uart_s *priv, uint8_t value, /**************************************************************************** * Name: z8_getuart ****************************************************************************/ - + static inline uint8_t z8_getuart(FAR struct z8_uart_s *priv, uint8_t offset) { return getreg8(*(priv->uartbase + offset)); @@ -338,7 +338,7 @@ void z8_uartconfigure(void) #ifdef EZ8_UART1 /* Configure GPIO Port D pins 4 & 5 for alternate function */ - + putreg8(0x02, PAADDR); val = getreg8(PDCTL) | 0x30; /* Set bits in alternate function register */ putreg8(val, PDCTL); @@ -759,7 +759,7 @@ int up_putc(int ch) uint8_t state; /* Keep interrupts disabled so that we do not interfere with normal - * driver operation + * driver operation */ state = z8_disableuartirq(&CONSOLE_DEV); diff --git a/nuttx/arch/z80/src/z8/z8_timerisr.c b/nuttx/arch/z80/src/z8/z8_timerisr.c index 0ed61e283..14009fe2e 100644 --- a/nuttx/arch/z80/src/z8/z8_timerisr.c +++ b/nuttx/arch/z80/src/z8/z8_timerisr.c @@ -98,7 +98,7 @@ int up_timerisr(int irq, uint32_t *regs) void up_timerinit(void) { uint32_t reload; - + up_disable_irq(Z8_IRQ_SYSTIMER); /* Write to the timer control register to disable the timer, configure diff --git a/nuttx/arch/z80/src/z8/z8_vector.S b/nuttx/arch/z80/src/z8/z8_vector.S index 180241521..7c4761d04 100755 --- a/nuttx/arch/z80/src/z8/z8_vector.S +++ b/nuttx/arch/z80/src/z8/z8_vector.S @@ -228,7 +228,7 @@ endif xdef _z8_p4ap0a_handler xdef _z8_potrap_handler xdef _z8_wotrap_handler -#endif +#endif /************************************************************************** * Macros @@ -430,7 +430,7 @@ endif vector P4A = _z8_p4ap0a_handler vector POTRAP = _z8_potrap_handler vector WOTRAP = _z8_wotrap_handler -#endif +#endif /************************************************************************** * Name: _z16f_*_handler @@ -724,7 +724,7 @@ _z8_potrap_handler: ENTER(Z8_POTRAP_IRQ) _z8_wotrap_handler: ENTER(Z8_WOTRAP_IRQ) -#endif +#endif /************************************************************************** * Name: _z16f_common_handler diff --git a/nuttx/arch/z80/src/z80/Make.defs b/nuttx/arch/z80/src/z80/Make.defs index 4f8c291c4..c60e88be6 100644 --- a/nuttx/arch/z80/src/z80/Make.defs +++ b/nuttx/arch/z80/src/z80/Make.defs @@ -41,7 +41,7 @@ HEAD_ASRC = z80_head.asm endif endif -CMN_ASRCS = +CMN_ASRCS = CMN_CSRCS = up_initialize.c up_allocateheap.c up_createstack.c \ up_releasestack.c up_interruptcontext.c up_blocktask.c \ up_unblocktask.c up_exit.c up_releasepending.c \ diff --git a/nuttx/arch/z80/src/z80/README.txt b/nuttx/arch/z80/src/z80/README.txt index df8b36de9..f81605475 100644 --- a/nuttx/arch/z80/src/z80/README.txt +++ b/nuttx/arch/z80/src/z80/README.txt @@ -8,42 +8,41 @@ sub-directory contains logic unique to the classic Z80 chip. Files in this directory include: z80_head.asm - This is the main entry point into the Z80 program. This includes the - handler for the RESET, power-up interrupt vector and address zero and all - RST interrupts. + This is the main entry point into the Z80 program. This includes the + handler for the RESET, power-up interrupt vector and address zero and all + RST interrupts. z80_rom.asm - Some architectures may have ROM located at address zero. In this case, a - special version of the "head" logic must be used. This special "head" - file is probably board-specific and, hence, belongs in the board-specific - configs/<board-name>/src directory. This file may, however, be used as - a model for such a board-specific file. - - z80_rom.S is enabled by specifying CONFIG_LINKER_ROM_AT_0000 in the - configuration file. - - A board specific version in the configs/<board-name>/src directory can be - used by: - - 1. Define CONFIG_ARCH_HAVEHEAD - 2. Add the board-specific head file, say <filename>.asm, to - configs/<board-name>/src - 3. Add a file called Make.defs in the configs/<board-name>/src directory - containing the line: HEAD_ASRC = <file-name>.asm + Some architectures may have ROM located at address zero. In this case, a + special version of the "head" logic must be used. This special "head" + file is probably board-specific and, hence, belongs in the board-specific + configs/<board-name>/src directory. This file may, however, be used as + a model for such a board-specific file. + + z80_rom.S is enabled by specifying CONFIG_LINKER_ROM_AT_0000 in the + configuration file. + + A board specific version in the configs/<board-name>/src directory can be + used by: + + 1. Define CONFIG_ARCH_HAVEHEAD + 2. Add the board-specific head file, say <filename>.asm, to + configs/<board-name>/src + 3. Add a file called Make.defs in the configs/<board-name>/src directory + containing the line: HEAD_ASRC = <file-name>.asm Make.defs - This is the standard makefile fragment that must be provided in all - chip directories. This fragment identifies the chip-specific file to - be used in building libarch. + This is the standard makefile fragment that must be provided in all + chip directories. This fragment identifies the chip-specific file to + be used in building libarch. chip.h - This is the standard header file that must be provided in all chip - directories. + This is the standard header file that must be provided in all chip + directories. z80_initialstate.c, z80_copystate.c, z80_restoreusercontext.asm, and z80_saveusercontext.asm, switch - These files implement the Z80 context switching logic + These files implement the Z80 context switching logic z80_schedulesigaction.c and z80_sigdeliver.c - These files implement Z80 signal handling. -
\ No newline at end of file + These files implement Z80 signal handling. diff --git a/nuttx/arch/z80/src/z80/z80_head.asm b/nuttx/arch/z80/src/z80/z80_head.asm index 7074461c2..4dadc5ba4 100644 --- a/nuttx/arch/z80/src/z80/z80_head.asm +++ b/nuttx/arch/z80/src/z80/z80_head.asm @@ -78,7 +78,7 @@ ; Other reset handlers ; ; Interrupt mode 1 behavior: -; +; ; 1. M1 cycle: 7 ticks ; Acknowledge interrupt and decrements SP ; 2. M2 cycle: 3 ticks diff --git a/nuttx/arch/z80/src/z80/z80_registerdump.c b/nuttx/arch/z80/src/z80/z80_registerdump.c index 7bf21a26f..a3271e61e 100644 --- a/nuttx/arch/z80/src/z80/z80_registerdump.c +++ b/nuttx/arch/z80/src/z80/z80_registerdump.c @@ -52,7 +52,7 @@ * Definitions ****************************************************************************/ -/* Output debug info if stack dump is selected -- even if +/* Output debug info if stack dump is selected -- even if * debug is not selected. */ diff --git a/nuttx/arch/z80/src/z80/z80_rom.asm b/nuttx/arch/z80/src/z80/z80_rom.asm index 70e698bf0..abc450bcd 100644 --- a/nuttx/arch/z80/src/z80/z80_rom.asm +++ b/nuttx/arch/z80/src/z80/z80_rom.asm @@ -109,7 +109,7 @@ _up_rstvectors: ; Other reset handlers ; ; Interrupt mode 1 behavior: -; +; ; 1. M1 cycle: 7 ticks ; Acknowledge interrupt and decrements SP ; 2. M2 cycle: 3 ticks |