Add timer and aitc headers

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1682 42af7a65-404d-4744-a932-0658087f49c3

1 files changed, 51 insertions, 40 deletions

diff --git a/nuttx/arch/arm/src/imx/imx_memorymap.h b/nuttx/arch/arm/src/imx/imx_memorymap.h
index 403906eda..44cfc7092 100644
--- a/nuttx/arch/arm/src/imx/imx_memorymap.h
+++ b/nuttx/arch/arm/src/imx/imx_memorymap.h
@@ -49,64 +49,75 @@
                                              /* -0x000fffff Double Map Image    1Mb */
                                              /* -0x001fffff Bootstrap ROM       1Mb */
 #define IMX_PERIPHERALS_PSECTION  0x00200000 /* -0x002fffff Peripherals         1Mb */
-#define IMX_SDRAM0_PSECTION       0x08000000 /* -0x08ffff00 SDRAM0             16Mb */
-#define IMX_SDRAM1_PSECTION       0x0c000000 /* -0x0cffff00 SDRAM1             16Mb */
-#define IMX_FLASH_PSECTION        0x10000000 /* -0x12000000 FLASH              32Mb */
+#define IMX_SDRAM0_PSECTION       0x08000000 /* -0x0bffffff SDRAM0 (CSD0)      64Mb */
+#define IMX_SDRAM1_PSECTION       0x0c000000 /* -0x0fffffff SDRAM1 (CSD1)      64Mb */
+#define IMX_FLASH_PSECTION        0x10000000 /* -0x11ffffff FLASH  (CS0)       32Mb */
+#define IMX_CS1_PSECTION          0x12000000 /* -0x12ffffff CS1                32Mb */
+#define IMX_CS2_PSECTION          0x13000000 /* -0x13ffffff CS2                32Mb */
+#define IMX_CS3_PSECTION          0x14000000 /* -0x14ffffff CS3                32Mb */
+#define IMX_CS4_PSECTION          0x15000000 /* -0x15ffffff CS4                32Mb */
+#define IMX_CS5_PSECTION          0x16000000 /* -0x16ffffff CS5                32Mb */
 
 /* Sizes of Address Sections ********************************************************/
 
+/* Mapped sections */
 #define IMX_PERIPHERALS_NSECTIONS 1          /*  1Mb  1 section                     */
-#define IMX_SDRAM0_NSECTIONS      16         /* 16Mb 16 sections                    */
-#define IMX_SDRAM1_NSECTIONS      16         /* 16Mb 16 sections                    */
-#define IMX_FLASH_NSECTIONS       32         /* 32Mb 32 sections                    */
+#define IMX_SDRAM0_NSECTIONS      16         /* 16Mb Based on CONFIG_DRAM_SIZE      */
+#define IMX_SDRAM1_NSECTIONS      0          /* 64Mb (Not mapped)                   */
+#define IMX_FLASH_NSECTIONS       32         /* 64Mb Based on CONFIG_FLASH_SIZE     */
+#define IMX_CS1_NSECTIONS         0          /* 32Mb (Not mapped)                   */
+#define IMX_CS2_NSECTIONS         0          /* 32Mb (Not mapped)                   */
+#define IMX_CS3_NSECTIONS         0          /* 32Mb (Not mapped)                   */
+#define IMX_CS4_NSECTIONS         0          /* 32Mb (Not mapped)                   */
+#define IMX_CS5_NSECTIONS         0          /* 32Mb (Not mapped)                   */
 
 /* Virtual Memory Map ***************************************************************/
 
-#define IMX_SDRAM_VSECTION        0x00000000 /* -0x01ffff00                    32Mb */
-#define IMX_FLASH_VSECTION        0x80000000 /* -0x81ffffff                    32Mb */
+#define IMX_SDRAM_VSECTION        0x00000000 /* -(+CONFIG_DRAM_SIZE)                */
+#define IMX_FLASH_VSECTION        0x80000000 /* -(+CONFIG_FLASH_SIZE)               */
 #define IMX_PERIPHERALS_VSECTION  0xe0000000 /* -0xe00fffff                     1Mb */
 
 /* Peripheral Register Offsets ******************************************************/
 
-#define IMX_AIPI1_OFFSET          0x00000000 /* -0x00000fff AIPI1            4Kb */
-#define IMX_WDOG_OFFSET           0x00001000 /* -0x00001fff WatchDog         4Kb */          
-#define IMX_TIMER1_OFFSET         0x00002000 /* -0x00002fff Timer1           4Kb */
-#define IMX_TIMER2_OFFSET         0x00003000 /* -0x00003fff Timer2           4Kb */
-#define IMX_RTC_OFFSET            0x00004000 /* -0x00004fff RTC              4Kb */
-#define IMX_LCDC_OFFSET           0x00005000 /* -0x00005fff LCD              4Kb */
+#define IMX_AIPI1_OFFSET          0x00000000 /* -0x00000fff AIPI1               4Kb */
+#define IMX_WDOG_OFFSET           0x00001000 /* -0x00001fff WatchDog            4Kb */          
+#define IMX_TIMER1_OFFSET         0x00002000 /* -0x00002fff Timer1              4Kb */
+#define IMX_TIMER2_OFFSET         0x00003000 /* -0x00003fff Timer2              4Kb */
+#define IMX_RTC_OFFSET            0x00004000 /* -0x00004fff RTC                 4Kb */
+#define IMX_LCDC_OFFSET           0x00005000 /* -0x00005fff LCD                 4Kb */
 #define   IMX_LCDC_COLORMAP       0x00005800
-#define IMX_UART1_OFFSET          0x00006000 /* -0x00006fff UART1            4Kb */
-#define IMX_UART2_OFFSET          0x00007000 /* -0x00007fff UART2            4Kb */
-#define IMX_PWM1_OFFSET           0x00008000 /* -0x00008fff PWM              4Kb */
-#define IMX_DMA_OFFSET            0x00009000 /* -0x00009fff DMA              4Kb */
-#define IMX_UART3_OFFSET          0x0000a000 /* -0x0000afff UART3            4Kb */
-                                             /* -0x0000ffff Reserved        20Kb */
-#define IMX_AIPI2_OFFSET          0x00010000 /* -0x00010fff AIPI2            4Kb */
-#define IMX_SIM_OFFSET            0x00011000 /* -0x00011fff SIM              4Kb */
-#define IMX_USBD_OFFSET           0x00012000 /* -0x00012fff USBD             4Kb */
-#define IMX_CSPI1_OFFSET          0x00013000 /* -0x00013fff CSPI1            4Kb */
-#define IMX_MMC_OFFSET            0x00014000 /* -0x00014fff MMC              4Kb */
-#define IMX_ASP_OFFSET            0x00015000 /* -0x00015fff ASP              4Kb */
-#define IMX_BTA_OFFSET            0x00016000 /* -0x00016fff BTA              4Kb */
-#define IMX_I2C_OFFSET            0x00017000 /* -0x00017fff I2C              4Kb */
-#define IMX_SSI_OFFSET            0x00018000 /* -0x00018fff SSI              4Kb */
-#define IMX_CSPI2_OFFSET          0x00019000 /* -0x00019fff CSPI2            4Kb */
-#define IMX_MSHC_OFFSET           0x0001a000 /* -0x0001afff Memory Stick     4Kb */
-#define IMX_CRM_OFFSET            0x0001b000 /* -0x0001bfff CRM              4Kb */
+#define IMX_UART1_OFFSET          0x00006000 /* -0x00006fff UART1               4Kb */
+#define IMX_UART2_OFFSET          0x00007000 /* -0x00007fff UART2               4Kb */
+#define IMX_PWM1_OFFSET           0x00008000 /* -0x00008fff PWM                 4Kb */
+#define IMX_DMA_OFFSET            0x00009000 /* -0x00009fff DMA                 4Kb */
+#define IMX_UART3_OFFSET          0x0000a000 /* -0x0000afff UART3               4Kb */
+                                             /* -0x0000ffff Reserved           20Kb */
+#define IMX_AIPI2_OFFSET          0x00010000 /* -0x00010fff AIPI2               4Kb */
+#define IMX_SIM_OFFSET            0x00011000 /* -0x00011fff SIM                 4Kb */
+#define IMX_USBD_OFFSET           0x00012000 /* -0x00012fff USBD                4Kb */
+#define IMX_CSPI1_OFFSET          0x00013000 /* -0x00013fff CSPI1               4Kb */
+#define IMX_MMC_OFFSET            0x00014000 /* -0x00014fff MMC                 4Kb */
+#define IMX_ASP_OFFSET            0x00015000 /* -0x00015fff ASP                 4Kb */
+#define IMX_BTA_OFFSET            0x00016000 /* -0x00016fff BTA                 4Kb */
+#define IMX_I2C_OFFSET            0x00017000 /* -0x00017fff I2C                 4Kb */
+#define IMX_SSI_OFFSET            0x00018000 /* -0x00018fff SSI                 4Kb */
+#define IMX_CSPI2_OFFSET          0x00019000 /* -0x00019fff CSPI2               4Kb */
+#define IMX_MSHC_OFFSET           0x0001a000 /* -0x0001afff Memory Stick        4Kb */
+#define IMX_CRM_OFFSET            0x0001b000 /* -0x0001bfff CRM                 4Kb */
 #define   IMX_PLL_OFFSET          0x0001b000
 #define   IMX_SC_OFFSET           0x0001b800
-#define IMX_GPIO_OFFSET           0x0001c000 /* -0x0001cfff GPIO             4Kb */
+#define IMX_GPIO_OFFSET           0x0001c000 /* -0x0001cfff GPIO                4Kb */
 #define   IMX_PTA_OFFSET          0x0001c000
 #define   IMX_PTB_OFFSET          0x0001c100
 #define   IMX_PTC_OFFSET          0x0001c200
 #define   IMX_PTD_OFFSET          0x0001c300
-                                             /* -0x0001ffff Reserved        12Kb */
-#define IMX_EIM_OFFSET            0x00020000 /* -0x00020fff WEIM             4Kb */
-#define IMX_SDRAMC_OFFSET         0x00021000 /* -0x00021fff SDRAMC           4Kb */
-#define IMX_DSPA_OFFSET           0x00022000 /* -0x00022fff DSPA             4Kb */
-#define IMX_AITC_OFFSET           0x00023000 /* -0x00023fff AITC             4Kb */
-#define IMX_CSI_OFFSET            0x00024000 /* -0x00024fff CSI              4Kb */
-                                             /* -0x000fffff Reserved       876Kb */
+                                             /* -0x0001ffff Reserved           12Kb */
+#define IMX_EIM_OFFSET            0x00020000 /* -0x00020fff WEIM                4Kb */
+#define IMX_SDRAMC_OFFSET         0x00021000 /* -0x00021fff SDRAMC              4Kb */
+#define IMX_DSPA_OFFSET           0x00022000 /* -0x00022fff DSPA                4Kb */
+#define IMX_AITC_OFFSET           0x00023000 /* -0x00023fff AITC                4Kb */
+#define IMX_CSI_OFFSET            0x00024000 /* -0x00024fff CSI                 4Kb */
+                                             /* -0x000fffff Reserved          876Kb */
 
 /* Peripheral Register Offsets ******************************************************/