diff options
| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-07-01 19:39:30 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-07-01 19:39:30 +0000 |
| commit | d75bdf9300533c94711466eaf3d9213a30d68a7f (patch) | |
| tree | cac68c90bfe9c7cdc5d20b518278a45e21875908 /nuttx/arch/arm/src/lpc17xx | |
| parent | 9ecbcf45e00a366d02da0d82066763627dd0d589 (diff) | |
| download | px4-nuttx-d75bdf9300533c94711466eaf3d9213a30d68a7f.tar.gz px4-nuttx-d75bdf9300533c94711466eaf3d9213a30d68a7f.tar.bz2 px4-nuttx-d75bdf9300533c94711466eaf3d9213a30d68a7f.zip | |
Add LPC43 USB0 and timer header files
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4895 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/lpc17xx')
| -rw-r--r-- | nuttx/arch/arm/src/lpc17xx/lpc17_timer.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_timer.h b/nuttx/arch/arm/src/lpc17xx/lpc17_timer.h index 03a85e32d..207c6d5cc 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_timer.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_timer.h @@ -1,8 +1,8 @@ /************************************************************************************
* arch/arm/src/lpc17xx/lpc17_timer.h
*
- * Copyright (C) 2010 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ * Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -179,10 +179,10 @@ /* Capture Control Register */
#define TMR_CCR_CAP0RE (1 << 0) /* Bit 0: Capture on CAPn.0 rising edge */
-#define TMR_CCR_CAP0FE (1 << 1) /* Bit 1: Capture on CAPn.0 falling edg */
+#define TMR_CCR_CAP0FE (1 << 1) /* Bit 1: Capture on CAPn.0 falling edge */
#define TMR_CCR_CAP0I (1 << 2) /* Bit 2: Interrupt on CAPn.0 */
#define TMR_CCR_CAP1RE (1 << 3) /* Bit 3: Capture on CAPn.1 rising edge */
-#define TMR_CCR_CAP1FE (1 << 4) /* Bit 4: Capture on CAPn.1 falling edg */
+#define TMR_CCR_CAP1FE (1 << 4) /* Bit 4: Capture on CAPn.1 falling edge */
#define TMR_CCR_CAP1I (1 << 5) /* Bit 5: Interrupt on CAPn.1 */
/* Bits 6-31: Reserved */
/* External Match Register */
@@ -225,14 +225,14 @@ #define TMR_CTCR_MODE_SHIFT (0) /* Bits 0-1: Counter/Timer Mode */
#define TMR_CTCR_MODE_MASK (3 << TMR_CTCR_MODE_SHIFT)
-# define TMR_CTCR_MODE_TIMER (0 << TMR_CTCR_MODE_SHIFT) /* Timer Mode, prescal match */
+# define TMR_CTCR_MODE_TIMER (0 << TMR_CTCR_MODE_SHIFT) /* Timer Mode, prescale match */
# define TMR_CTCR_MODE_CNTRRE (1 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP rising edge */
# define TMR_CTCR_MODE_CNTRFE (2 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP falling edge */
# define TMR_CTCR_MODE_CNTRBE (3 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP both edges */
#define TMR_CTCR_INPSEL_SHIFT (2) /* Bits 2-3: Count Input Select */
#define TMR_CTCR_INPSEL_MASK (3 << TMR_CTCR_INPSEL_SHIFT)
# define TMR_CTCR_INPSEL_CAPNp0 (0 << TMR_CTCR_INPSEL_SHIFT) /* CAPn.0 for TIMERn */
-# define TMR_CTCR_INPSEL_CAPNp1 (1 << TMR_CTCR_INPSEL_SHIFT) /* CAPn.0 for TIMERn */
+# define TMR_CTCR_INPSEL_CAPNp1 (1 << TMR_CTCR_INPSEL_SHIFT) /* CAPn.1 for TIMERn */
/* Bits 4-31: Reserved */
/************************************************************************************
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