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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-12-09 17:03:16 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-12-09 17:03:16 +0000 |
| commit | 88f3c3ba8d3161537032f2390936047c0535dce9 (patch) | |
| tree | d13d6f30d8434fcb973fe397ebe500632dd7e314 /nuttx/arch/arm/src/stm32/chip/stm32_eth.h | |
| parent | 1a79f640a822bd01d8ef8149c5f0d3e793d65b88 (diff) | |
| download | px4-nuttx-88f3c3ba8d3161537032f2390936047c0535dce9.tar.gz px4-nuttx-88f3c3ba8d3161537032f2390936047c0535dce9.tar.bz2 px4-nuttx-88f3c3ba8d3161537032f2390936047c0535dce9.zip | |
Add PHY setup for STM3240G-EVAL Ethernet driver
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4151 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/stm32/chip/stm32_eth.h')
| -rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32_eth.h | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_eth.h b/nuttx/arch/arm/src/stm32/chip/stm32_eth.h index b757992a6..6237521fe 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32_eth.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32_eth.h @@ -245,10 +245,18 @@ #define ETH_MACMIIAR_MW (1 << 1) /* Bit 1: MII write */ #define ETH_MACMIIAR_CR_SHIFT (2) /* Bits 2-4: Clock range */ #define ETH_MACMIIAR_CR_MASK (7 << ETH_MACMIIAR_CR_SHIFT) -# define ETH_MACMIIAR_CR_60_100 (0 << ETH_MACMIIAR_CR_SHIFT) /* 000 60-100 MHz HCLK/42 */ +#if 0 /* Per the reference manual */ +# define ETH_MACMIIAR_CR_60_100 (0 << ETH_MACMIIAR_CR_SHIFT) /* 000 60-100 MHzHCLK/42 */ # define ETH_MACMIIAR_CR_100_168 (1 << ETH_MACMIIAR_CR_SHIFT) /* 001 100-168 MHz HCLK/62 */ -# define ETH_MACMIIAR_CR_20_35 (2 << ETH_MACMIIAR_CR_SHIFT) /* 010 20-35 MHz HCLK/16 */ -# define ETH_MACMIIAR_CR_35_60 (3 << ETH_MACMIIAR_CR_SHIFT) /* 011 35-60 MHz HCLK/26 */ +# define ETH_MACMIIAR_CR_20_35 (2 << ETH_MACMIIAR_CR_SHIFT) /* 010 20-35 MHz HCLK/16 */ +# define ETH_MACMIIAR_CR_35_60 (3 << ETH_MACMIIAR_CR_SHIFT) /* 011 35-60 MHz HCLK/26 */ +#else /* Per the driver example */ +# define ETH_MACMIIAR_CR_60_100 (0 << ETH_MACMIIAR_CR_SHIFT) /* 000 60-100 MHz HCLK/42 */ +# define ETH_MACMIIAR_CR_100_150 (1 << ETH_MACMIIAR_CR_SHIFT) /* 001 100-150 MHz HCLK/62 */ +# define ETH_MACMIIAR_CR_20_35 (2 << ETH_MACMIIAR_CR_SHIFT) /* 010 20-35 MHz HCLK/16 */ +# define ETH_MACMIIAR_CR_35_60 (3 << ETH_MACMIIAR_CR_SHIFT) /* 011 35-60 MHz HCLK/26 */ +# define ETH_MACMIIAR_CR_150_168 (4 << ETH_MACMIIAR_CR_SHIFT) /* 100 150-168 MHz HCLK/102 */ +#endif #define ETH_MACMIIAR_MR_SHIFT (6) /* Bits 6-10: MII register */ #define ETH_MACMIIAR_MR_MASK (31 << ETH_MACMIIAR_MR_SHIFT) #define ETH_MACMIIAR_PA_SHIFT (11) /* Bits 11-15: PHY address */ |