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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-02-22 18:14:18 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-02-22 18:14:18 +0000 |
| commit | dfb6261f45bb4a34b3fdfc10047c908534e0bee5 (patch) | |
| tree | 73105f0c26928d4c6992417ea780daa36c439549 /nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h | |
| parent | 6e7deb2a77bcd3159a47328699e2c489238931b0 (diff) | |
| download | px4-nuttx-dfb6261f45bb4a34b3fdfc10047c908534e0bee5.tar.gz px4-nuttx-dfb6261f45bb4a34b3fdfc10047c908534e0bee5.tar.bz2 px4-nuttx-dfb6261f45bb4a34b3fdfc10047c908534e0bee5.zip | |
Incoporate new ARMv7-M exception handling logic contributed by Mike Smith
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4413 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h')
| -rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h | 30 |
1 files changed, 28 insertions, 2 deletions
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h index 0d6b965d2..8ce98c988 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h @@ -36,7 +36,6 @@ /************************************************************************************ * Pre-processor definitions ************************************************************************************/ - /* This file is included by stm32_vectors.S. It provides the macro VECTOR that * supplies ach STM32F10xxx vector in terms of a (lower-case) ISR label and an * (upper-case) IRQ number as defined in arch/arm/include/stm32/stm32f10xxx_irq.h. @@ -46,6 +45,18 @@ #ifdef CONFIG_STM32_CONNECTIVITY_LINE +/* If the common ARMv7-M vector handling is used, then all it needs is the following + * definition that provides the number of supported vectors. + */ + +#ifdef CONFIG_ARMV7M_CMNVECTOR + +/* Reserve 68 interrupt table entries for I/O interrupts. */ + +# define ARMV7M_PERIPHERAL_INTERRUPTS 68 + +#else + VECTOR(stm32_wwdg, STM32_IRQ_WWDG) /* Vector 16+0: Window Watchdog interrupt */ VECTOR(stm32_pvd, STM32_IRQ_PVD) /* Vector 16+1: PVD through EXTI Line detection interrupt */ VECTOR(stm32_tamper, STM32_IRQ_TAMPER) /* Vector 16+2: Tamper interrupt */ @@ -107,6 +118,19 @@ VECTOR(stm32_can2rx1, STM32_IRQ_CAN2RX1) /* Vector 16+65: CAN2 RX1 inter VECTOR(stm32_can2sce, STM32_IRQ_CAN2SCE) /* Vector 16+66: CAN2 SCE interrupt */ VECTOR(stm32_otgfs, STM32_IRQ_OTGFS) /* Vector 16+67: USB On The Go FS global interrupt */ +#endif /* CONFIG_ARMV7M_CMNVECTOR */ +#else /* CONFIG_STM32_CONNECTIVITY_LINE */ + +/* If the common ARMv7-M vector handling is used, then all it needs is the following + * definition that provides the number of supported vectors. + */ + +#ifdef CONFIG_ARMV7M_CMNVECTOR + +/* Reserve 60 interrupt table entries for I/O interrupts. */ + +# define ARMV7M_PERIPHERAL_INTERRUPTS 60 + #else VECTOR(stm32_wwdg, STM32_IRQ_WWDG) /* Vector 16+0: Window Watchdog interrupt */ @@ -169,4 +193,6 @@ VECTOR(stm32_dma2ch1, STM32_IRQ_DMA2CH1) /* Vector 16+56: DMA2 Channel 1 VECTOR(stm32_dma2ch2, STM32_IRQ_DMA2CH2) /* Vector 16+57: DMA2 Channel 2 global interrupt */ VECTOR(stm32_dma2ch3, STM32_IRQ_DMA2CH3) /* Vector 16+58: DMA2 Channel 3 global interrupt */ VECTOR(stm32_dma2ch45, STM32_IRQ_DMA2CH45) /* Vector 16+59: DMA2 Channel 4&5 global interrupt */ -#endif + +#endif /* CONFIG_ARMV7M_CMNVECTOR */ +#endif /* CONFIG_STM32_CONNECTIVITY_LINE */ |