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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-12-14 21:59:08 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-12-14 21:59:08 +0000 |
| commit | f13e02c9981253413fe0a0bef4e1223901dbf724 (patch) | |
| tree | 6f767fd6c7ed93a0fa794bd982e64fbe08164f65 /nuttx/arch/arm/src/stm32/chip | |
| parent | 0b08eb3243a52370912409affeec4ca87dabc85d (diff) | |
| download | px4-nuttx-f13e02c9981253413fe0a0bef4e1223901dbf724.tar.gz px4-nuttx-f13e02c9981253413fe0a0bef4e1223901dbf724.tar.bz2 px4-nuttx-f13e02c9981253413fe0a0bef4e1223901dbf724.zip | |
STM32 F4 RTC is functional
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4178 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/stm32/chip')
| -rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32f40xxx_rtc.h | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_rtc.h b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_rtc.h index c12698f7f..fdfa9b323 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_rtc.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_rtc.h @@ -55,6 +55,7 @@ #define STM32_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */ #define STM32_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */ #define STM32_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */ +#define STM32_RTC_TSDR_OFFSET 0x0030 /* RTC time stamp date register */ #define STM32_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */ #define STM32_RTC_CALR_OFFSET 0x003c /* RTC calibration register */ #define STM32_RTC_TAFCR_OFFSET 0x0040 /* RTC tamper and alternate function configuration register */ @@ -98,6 +99,7 @@ #define STM32_RTC_SSR (STM32_RTC_BASE+STM32_RTC_SSR_OFFSET) #define STM32_RTC_SHIFTR (STM32_RTC_BASE+STM32_RTC_SHIFTR_OFFSET) #define STM32_RTC_TSTR (STM32_RTC_BASE+STM32_RTC_TSTR_OFFSET) +#define STM32_RTC_TSDR (STM32_RTC_BASE+STM32_RTC_TSDR_OFFSET) #define STM32_RTC_TSSSR (STM32_RTC_BASE+STM32_RTC_TSSSR_OFFSET) #define STM32_RTC_CALR (STM32_RTC_BASE+STM32_RTC_CALR_OFFSET) #define STM32_RTC_TAFCR (STM32_RTC_BASE+STM32_RTC_TAFCR_OFFSET) @@ -151,7 +153,7 @@ #define RTC_DR_DU_MASK (15 << RTC_DR_DU_SHIFT) #define RTC_DR_DT_SHIFT (4) /* Bits 4-5: Date tens in BCD format */ #define RTC_DR_DT_MASK (3 << RTC_DR_DT_SHIFT) -#define RTC_DR_MU_SHIFT (20) /* Bits 8-11: Month units in BCD format */ +#define RTC_DR_MU_SHIFT (8) /* Bits 8-11: Month units in BCD format */ #define RTC_DR_MU_MASK (15 << RTC_DR_MU_SHIFT) #define RTC_DR_MT (1 << 12) /* Bit 12: Month tens in BCD format */ #define RTC_DR_WDU_SHIFT (13) /* Bits 13-15: Week day units */ @@ -298,6 +300,18 @@ #define RTC_TSTR_HT_MASK (3 << RTC_TSTR_HT_SHIFT) #define RTC_TSTR_PM (1 << 22) /* Bit 22: AM/PM notation */ +/* RTC time stamp date register */ + +#define RTC_TSDR_DU_SHIFT (0) /* Bit 0-3: Date units in BCD format */ +#define RTC_TSDR_DU_MASK (15 << RTC_TSDR_DU_SHIFT) */ +#define RTC_TSDR_DT_SHIFT (4) /* Bits 4-5: Date tens in BCD format */ +#define RTC_TSDR_DT_MASK (3 << RTC_TSDR_DT_SHIFT) +#define RTC_TSDR_MU_SHIFT (8) /* Bits 8-11: Month units in BCD format */ +#define RTC_TSDR_MU_MASK (xx << RTC_TSDR_MU_SHIFT) +#define RTC_TSDR_MT (1 << 12) /* Bit 12: Month tens in BCD format */ +#define RTC_TSDR_WDU_SHIFT (13) /* Bits 13-15: Week day units */ +#define RTC_TSDR_WDU_MASK (7 << RTC_TSDR_WDU_SHIFT) + /* RTC timestamp sub second register */ #define RTC_TSSSR_MASK (0xffff) /* Bits 0-15: Sub second value */ |