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author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2007-02-19 22:51:18 +0000 |
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committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2007-02-19 22:51:18 +0000 |
commit | 0924f81f32294abaae83d0fd9f4ff7a6257065ac (patch) | |
tree | bc6c6bc6997a73744ef28aa82f8e5738d1173e3d /nuttx/arch/c5471/src/up_irq.c | |
parent | 71989f8323da84187bb4b06ef9d4435d037d7a27 (diff) | |
download | px4-nuttx-0924f81f32294abaae83d0fd9f4ff7a6257065ac.tar.gz px4-nuttx-0924f81f32294abaae83d0fd9f4ff7a6257065ac.tar.bz2 px4-nuttx-0924f81f32294abaae83d0fd9f4ff7a6257065ac.zip |
Fix ARM IRQ handling problem + ARM context restore problem
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@9 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/c5471/src/up_irq.c')
-rw-r--r-- | nuttx/arch/c5471/src/up_irq.c | 44 |
1 files changed, 20 insertions, 24 deletions
diff --git a/nuttx/arch/c5471/src/up_irq.c b/nuttx/arch/c5471/src/up_irq.c index d388f6446..3c8a17371 100644 --- a/nuttx/arch/c5471/src/up_irq.c +++ b/nuttx/arch/c5471/src/up_irq.c @@ -48,8 +48,8 @@ * Definitions ************************************************************/ -#define EdgeSensitive 0x00000020 -#define Priority 0x0000001E +#define ILR_EDGESENSITIVE 0x00000020 +#define ILR_PRIORITY 0x0000001E /************************************************************ * Public Data @@ -164,10 +164,10 @@ void up_irqinitialize(void) /* Override hardware defaults */ - putreg32(EdgeSensitive | Priority, ILR_IRQ2_REG); - putreg32(EdgeSensitive | Priority, ILR_IRQ4_REG); - putreg32(Priority, ILR_IRQ6_REG); - putreg32(EdgeSensitive | Priority, ILR_IRQ15_REG); + putreg32(ILR_EDGESENSITIVE | ILR_PRIORITY, ILR_IRQ2_REG); + putreg32(ILR_EDGESENSITIVE | ILR_PRIORITY, ILR_IRQ4_REG); + putreg32(ILR_PRIORITY, ILR_IRQ6_REG); + putreg32(ILR_EDGESENSITIVE | ILR_PRIORITY, ILR_IRQ15_REG); /* Initialize hardware interrupt vectors */ @@ -214,30 +214,26 @@ void up_enable_irq(int irq) } /************************************************************ - * Name: up_acknowledge_irq + * Name: up_maskack_irq * * Description: - * Disable the IRQ specified by 'irq' + * Mask the IRQ and acknowledge it * ************************************************************/ -/* Bit 0 of the Interrupt Control Rigster == New IRQ - * agreement (NEW_IRQ_AGR). Reset IRQ output. Clear source - * IRQ register. Enables a new IRQ generation. Reset by - * internal logic. - * - * IRQ (FIQ) output and SRC_IRQ_REG and SRC_IRQ_BIN_REG - * (SRC_FIQ_REG) registers are reset only if the bit in the - * Interrupt register (IT_REG) corresponding to the interrupt - * having requested MCU action is already cleared or masked. - * - * For an edge-sensitive interrupt, the Interrupt register bit is - * deactivated when reading the SRC_IRQ_REG or SRC_IRQ_BIN_REG - * (SRC_FIQ_REG) registers. - */ - -void up_acknowledge_irq(int irq) +void up_maskack_irq(int irq) { uint32 reg = getreg32(INT_CTRL_REG); + + /* Mask the interrupt */ + + reg = getreg32(MASK_IT_REG); + putreg32(reg | (1 << irq), MASK_IT_REG); + + /* Set the NEW_IRQ_AGR bit. This clears the IRQ src register + * enables generation of a new IRQ. + */ + + reg = getreg32(INT_CTRL_REG); putreg32(reg | 0x00000001, INT_CTRL_REG); /* write the NEW_IRQ_AGR bit. */ } |